Repair circuit, control method, memory and electronic equipment

Abstract

The embodiment of the invention provides a repair circuit, a control method, a memory and electronic equipment, and relates to the technical field of semiconductors. The repair circuit comprises an address storage module and a plurality of repair control modules, each repair control module corresponds to a row of redundant storage units, and each repair control module is electrically connected with the address storage module; the repair control module is configured to compare a received target row address with each invalid row address in a first comparison stage, and if the target row address is matched with any invalid row address, a word line of a row of redundant storage units corresponding to the invalid row address is activated; and in a second comparison stage, matching the received target column address with the at least two groups of redundant column addresses, and controlling the column selection switch devices corresponding to the matched group of redundant column addresses to be turned on. According to the embodiment of the invention, the repairing capability of the redundant storage units can be enhanced, and the number of the redundant storage units needing to be set is reduced, so that the size of a chip is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a repair circuit and control method, a memory, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] This application provides a repair circuit and control method, a memory, and an electronic device to solve the technical problem that the repair circuit in the prior art requires a large number of redundant memory units, resulting in a large chip size.

[0005] In the first aspect, embodiments of this application provide a repair circuit, including: an address storage module and a plurality of repair control modules, each repair control module corresponding to a row of redundant storage units, and each repair control module being electrically connected to the address storage module. Each row of redundant storage units corresponds to at least one failed row address and at least two sets of redundant column addresses. The failed row address is used to represent the row address corresponding to the failed storage unit, and each set of redundant column addresses is used to represent the column addresses corresponding to at least two redundant storage units. The address storage module is configured to store at least one failed row address and each set of redundant column addresses, and provide them to each repair control module accordingly. The repair control module is configured to, in the first comparison phase, compare the received target row address with each failed row address. If the target row address matches any failed row address, the word line of the corresponding row of redundant memory cells is activated. In the second comparison phase, the received target column address is matched with at least two sets of redundant column addresses. If the target column address matches any set of redundant column addresses, the column selection switches corresponding to the matched set of redundant column addresses are all turned on, so that the corresponding redundant memory cells can transmit data with the port. The target row address and target column address are the row address and column address of the memory cell that needs to read data, respectively.

[0006] In one possible implementation, the repair control module is also configured to be any of the following: If the target row address does not match any of the failed row addresses, then activate the word line of the memory cell corresponding to the target row address; If the target column address does not match any of the redundant column addresses, the column selection switch device corresponding to the target column address is turned on so that the corresponding memory cell and port can transmit data.

[0007] In one possible implementation, the repair control module includes: The row address comparison module, which is electrically connected to the address storage module, is configured to compare the received target row address with each failed row address. If the target row address matches any failed row address, the first matching information is generated. The first control module, electrically connected to the row address comparison module, is configured to generate a first control signal based on the first matching information output by the row address comparison module and output it to the word line of a row of redundant memory cells corresponding to the failed row address, so as to control the switching device electrically connected to the word line to be turned on. The column address comparison module, electrically connected to the address storage module, is configured to match the received target column address with at least two sets of redundant column addresses. If the target column address matches any set of redundant column addresses, a second matching information is generated. The second matching information is used to indicate the set of redundant column addresses that are matched. The second control module, electrically connected to the column address comparison module, is configured to generate a second control signal based on the second matching information output by the column address comparison module and output it to the control line of the column selection switch device corresponding to a set of matched redundant column addresses, so as to control the column selection switch device to be turned on.

[0008] In one possible implementation, the row address comparison module is also configured to generate a third matching message if the target row address does not match any of the failed row addresses. The first control module is also configured to generate a third control signal based on the third matching information output by the row address comparison module and output it to the word line of the memory cell corresponding to the target row address, so as to control the switching device electrically connected to the word line to turn on.

[0009] In one possible implementation, the column address comparison module is also configured to generate a fourth matching message if the target column address does not match any of the redundant column addresses. The second control module is configured to generate a fourth control signal based on the fourth matching information output by the column address comparison module and output it to the control line of the column selection switch device corresponding to the target column address, so as to control the column selection switch device to be turned on.

[0010] In one possible implementation, the first control module includes: The redundant row decoding unit is electrically connected to the row address comparison module and is configured to generate a redundant row address based on the first matching information output by the row address comparison module, and generate a first enable signal based on the redundant row address; the redundant row address is used to represent the row address of a row of redundant memory cells; The first voltage control unit, electrically connected to the redundant row decoding unit, is configured to generate a first control signal based on the first enable signal output by the redundant row decoding unit, and output it to the word line of a row of redundant memory cells corresponding to the failed row address, so as to control the switching device electrically connected to the word line to be turned on. The row address decoding unit is electrically connected to the row address comparison module and is configured to generate a second enable signal based on the third matching information output by the row address comparison module and the target row address. The second voltage control unit, electrically connected to the row address decoding unit, is configured to generate a third control signal based on the second enable signal output by the row address decoding unit, and output it to the word line of the memory cell corresponding to the target row address to control the switching device electrically connected to the word line to turn on.

[0011] In one possible implementation, the second control module includes: The redundant column decoding unit is electrically connected to the column address comparison module and is configured to generate a set of matching redundant column addresses based on the second matching information output by the column address comparison module, and generate a third enable signal based on the set of matching redundant column addresses. The third voltage control unit, electrically connected to the redundant column decoding unit, is configured to generate a second control signal based on the third enable signal output by the redundant column decoding unit and output it to the control line of the column selection switching device corresponding to a set of matched redundant column addresses, so as to control the column selection switching device to be turned on. The column address decoding unit, electrically connected to the column address comparison module, is configured to generate a fourth enable signal based on the fourth matching information output by the column address comparison module and the target column address; The fourth voltage control unit, electrically connected to the column address decoding unit, is configured to generate a fourth control signal based on the fourth enable signal output by the column address decoding unit, and output it to the control line of the column selection switch device corresponding to the target column address to control the column selection switch device to be turned on.

[0012] In one possible implementation, the circuit repair also includes: The repair mode selection module is electrically connected to both the address storage module and the repair control module. It is configured to determine the repair mode based on at least one of the number of failed row addresses output by the address storage module and the number of rows of redundant storage units. The repair modes include a first repair mode and a second repair mode. If the repair mode is the first repair mode, the repair control module is controlled to perform a first comparison stage. If the repair mode is the second repair mode, the repair control module is controlled to perform a first comparison stage and a second comparison stage.

[0013] In one possible implementation, the repair mode selection module is also configured to be at least one of the following: If the number of invalid line addresses is one, then the repair mode is determined to be the first repair mode; If the number of invalid line addresses is greater than one, then the repair mode is determined to be the second repair mode; If the difference between the number of rows in the redundant storage unit and the number of failed row addresses is greater than the first preset value, then the repair mode is determined to be the first repair mode. If the difference between the number of rows in the redundant storage unit and the number of failed row addresses is not greater than the first preset value, then the repair mode is determined to be the second repair mode. If the number of rows of redundant storage units is greater than the second preset value, then the repair mode is determined to be the first repair mode.

[0014] In one possible implementation, the repair mode selection module is electrically connected to both the row address comparison module and the column address comparison module; The repair mode selection module is also configured to at least one of the following: If the repair mode is determined to be the first repair mode, then the first flag signal is output to the row address comparison module corresponding to each failed row address to start the row address comparison module, and the second flag signal is output to the column address comparison module corresponding to each failed row address to stop the column address comparison module. If the repair mode is determined to be the second repair mode, then the first flag signal is output to the row address comparison module corresponding to each failed row address to start the row address comparison module, and the third flag signal is output to the column address comparison module corresponding to each failed row address to start the column address comparison module.

[0015] In one possible implementation, the redundant column address corresponding to a row of redundant storage units is divided into 2ⁿ groups of redundant column addresses, where 1≤n≤13 and n is a positive integer.

[0016] Secondly, embodiments of this application provide a memory, including: multiple bit lines, multiple word lines, multiple array-distributed memory cells, multiple array-distributed redundant memory cells, multiple sensitive amplifiers, and multiple repair circuits of the first aspect; One bit line corresponds to one column of memory cells and is electrically connected to one column of redundant memory cells. One word line corresponds to one row of memory cells and is electrically connected to one row of redundant memory cells; Each sensitive amplifier includes two column select switching devices, each column select switching device being electrically connected to a port; Each repair control module is electrically connected to a row of redundant storage cells, and each repair control module is electrically connected to the column selection switching devices of multiple sensitive amplifiers.

[0017] In one possible implementation, the memory includes a plurality of first memory blocks and at least one second memory block, with memory cells located within the first memory blocks and redundant memory cells located within the second memory blocks; The second storage block containing each row of redundant storage units is not adjacent to the first storage block containing the storage unit corresponding to the repair of each row of redundant storage units.

[0018] Thirdly, embodiments of this application provide an electronic device, including: a repair circuit as described in the first aspect or a memory as described in the second aspect.

[0019] Fourthly, embodiments of this application provide a control method applied to the repair circuit of the first aspect, the control method comprising: In the first comparison phase, the received target row address is compared with each failed row address. If the target row address matches any failed row address, the word line of the row of redundant memory cells corresponding to the failed row address is activated. In the second comparison phase, the received target column address is matched with at least two sets of redundant column addresses. If the target column address matches any set of redundant column addresses, the column selection switches corresponding to the matched set of redundant column addresses are turned on so that the corresponding redundant storage units and ports can transmit data.

[0020] In one possible implementation, prior to the first comparison phase, the following is also included: The repair mode is determined based on at least one of the number of failed row addresses and the number of rows of redundant memory cells; the repair mode includes a first repair mode and a second repair mode. If the repair mode is the first repair mode, then the first comparison phase is executed; If the repair mode is the second repair mode, then the first comparison phase and the second comparison phase are executed.

[0021] In one possible implementation, the repair mode is determined based on at least one of the number of failed row addresses and the number of rows of redundant storage cells, including any of the following: If the number of invalid line addresses is one, then the repair mode is determined to be the first repair mode; If the number of invalid line addresses is greater than one, then the repair mode is determined to be the second repair mode; If the difference between the number of rows in the redundant storage unit and the number of failed row addresses is greater than the first preset value, then the repair mode is determined to be the first repair mode. If the difference between the number of rows in the redundant storage unit and the number of failed row addresses is not greater than the first preset value, then the repair mode is determined to be the second repair mode. If the number of rows of redundant storage units is greater than the second preset value, then the repair mode is determined to be the first repair mode.

[0022] In one possible implementation, if the repair mode is the first repair mode, then a first comparison phase is performed, including: If the repair mode is the first repair mode, then a first flag signal is output to the row address comparison module of the repair circuit corresponding to each failed row address to start the row address comparison module, and a second flag signal is output to the column address comparison module of the repair circuit corresponding to the failed row address to stop the column address comparison module; and / or, If the repair mode is the second repair mode, then the first comparison phase and the second comparison phase are executed, including: If the repair mode is the second repair mode, then the first flag signal is output to the row address comparison module corresponding to each failed row address to start the row address comparison module, and the third flag signal is output to the column address comparison module corresponding to each failed row address to start the column address comparison module.

[0023] The beneficial technical effects of the technical solutions provided in this application include: The address storage module of this application embodiment can output at least one failed row address and at least two sets of redundant column addresses corresponding to each row of redundant storage units to the corresponding repair control module. This allows the repair control module to compare the received target row address with each failed row address in the first comparison stage. If the target row address matches any failed row address, the word line of the row of redundant storage units corresponding to the failed row address is activated. In the second comparison stage, the received target column address is matched with at least two sets of redundant column addresses. If the target column address matches any set of redundant column addresses, the column selection switches corresponding to the matched set of redundant column addresses are all turned on, so that the corresponding redundant storage units can transmit data with the port. After two comparison stages, the redundant storage units can replace the failed storage units, thereby repairing the faulty storage units.

[0024] Meanwhile, each row of redundant storage units corresponds to at least two sets of redundant column addresses, and each set of redundant column addresses corresponds to the column addresses of at least two redundant storage units. That is, in this embodiment, each row of redundant storage units is divided, and the row addresses of the storage units used for repair by the redundant storage units corresponding to the redundant column addresses of different sets of redundant storage units in a row of redundant storage units can be different. This allows storage units in different rows to be repaired through the same row of redundant storage units, that is, the same row of redundant storage units can be split for repair. This allows the same row of redundant storage units to not be limited to repairing only one faulty storage unit, thereby enhancing the repair capability of redundant storage units. In other words, it can greatly increase the reliability of the memory, and the reliability determination of the chip can be completed with fewer redundant arrays, and the size of the chip can be reduced.

[0025] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0026] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic diagram of the framework of the first repair circuit 10 provided in the embodiments of this application; Figure 2 A schematic diagram of the frame connecting the first address storage module 110 and the repair control module 120 in an embodiment of this application; Figure 3 A schematic diagram of the frame connecting the second address storage module 110 and the repair control module 120 in an embodiment of this application; Figure 4 A schematic diagram of the framework of the second repair circuit 10 provided in the embodiments of this application; Figure 5 A schematic diagram of a structure for repairing a failed memory cell using a first repair mode, provided in an embodiment of this application; Figure 6 A schematic diagram of a structure for repairing a failed memory cell using a second repair mode, provided in an embodiment of this application; Figure 7 A schematic diagram of the framework for fine-grained repair settings of a repair circuit 10 provided in an embodiment of this application; Figure 8 A schematic diagram of the arrangement structure of the first type of storage block provided in an embodiment of this application; Figure 9 A schematic diagram of the arrangement structure of the second type of storage block provided in an embodiment of this application; Figure 10 This is a flowchart illustrating a control method provided in an embodiment of this application.

[0027] Figure label: 10-Repair the circuit; 110 - Address storage module; 120-Repair control module, 121-Row address comparison module, 122-First control module, 1221-Redundant row decoding unit, 1222-First voltage control unit, 1223-Row address decoding unit, 1224-Second voltage control unit, 123-Column address comparison module, 124-Second control module, 1241-Redundant column decoding unit, 1242-Third voltage control unit, 1243-Column address decoding unit, 1244-Fourth voltage control unit; 130 - Repair Mode Selection Module; 210 - First storage block; 220 - Second storage block. Detailed Implementation

[0028] This application is described in detail below. Examples of embodiments of this application are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. Furthermore, detailed descriptions of known technologies that are unnecessary for the features of this application are omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0029] Those skilled in the art will understand that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0030] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0031] In related technologies, most existing memory repair circuits currently use redundant memory cells to replace faulty memory cells for repair. However, considering the large number of memory cells and their array arrangement (row-column distribution and shared mode), the repair process is usually not a simple replacement of individual memory cells, but rather the replacement of entire rows and columns. Since the number of memory cells in a single row is much smaller than the number of memory cells in a column, row replacement is the most commonly used mode in memory repair. However, this row-by-row repair mode works well if the faulty memory cells are concentrated in one row, but if the errors are scattered, it leads to a significant waste of repair resources. Therefore, this application proposes a refined row repair mode, which allows for more flexible repair. If the errors are not concentrated in one row, only a redundant row can be used for repair.

[0032] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments.

[0033] See Figure 1 As shown in the schematic diagram, this application embodiment provides a first type of repair circuit 10. The repair circuit 10 includes an address storage module 110 and a plurality of repair control modules 120. Each repair control module 120 corresponds to a row of redundant storage units, and each repair control module 120 is electrically connected to the address storage module 110. Each row of redundant storage units corresponds to at least one failed row address and at least two sets of redundant column addresses. The failed row address is used to represent the row address corresponding to the failed storage unit, and each set of redundant column addresses is used to represent the column addresses corresponding to at least two redundant storage units. The address storage module 110 is configured to store at least one failed row address and each set of redundant column addresses, and provide them to each repair control module 120 accordingly. The repair control module 120 is configured to, in the first comparison phase, compare the received target row address with each failed row address. If the target row address matches any failed row address, the word line of the corresponding row of redundant memory cell is activated. In the second comparison phase, the received target column address is matched with at least two sets of redundant column addresses. If the target column address matches any set of redundant column addresses, the column selection switches corresponding to the matched set of redundant column addresses are all turned on, so that the corresponding redundant memory cell can transmit data with the port. The target row address and the target column address are the row address and column address of the memory cell that needs to read data, respectively.

[0034] Optionally, the target row address and target column address can be output to the repair control module 120 in real time by the memory processing unit. The row address corresponding to each memory cell is used to indicate the address of the word line of the memory cell, and is used to activate the word line of the memory cell; the row address corresponding to each redundant memory cell is used to indicate the address of the word line of the redundant memory cell, and is used to activate the word line of the redundant memory cell.

[0035] Activating the word line of the redundant memory cell means outputting a first control signal to the word line of the redundant memory cell so that the switching device connected to the word line is turned on.

[0036] The redundant column address of each redundant memory cell is used to indicate the address of the control line of the column select switch device of the corresponding sensitive amplifier, and is used to activate the control line of the column select switch device.

[0037] In this embodiment of the application, a single row of redundant storage units can be used to repair multiple failed storage units that are not in the same row. A single row of redundant storage units may correspond to multiple failed row addresses. Each group of redundant column addresses can directly include multiple redundant column addresses, or it can be a total redundant column address used to represent multiple redundant column addresses.

[0038] Optionally, the target column address is matched with the set of redundant column addresses when the target column address matches one of the redundant column addresses in a set of redundant column addresses; the target column address is matched with the set of redundant column addresses when a portion of the address number of the target column address matches a portion of the address number in a set of redundant column addresses.

[0039] The address storage module 110 of this application embodiment can output at least one failed row address and at least two sets of redundant column addresses corresponding to each row of redundant storage units to the corresponding repair control module 120. This allows the repair control module 120 to compare the received target row address with each failed row address in the first comparison stage. If the target row address matches any failed row address, the word line of the row of redundant storage units corresponding to the failed row address is activated. In the second comparison stage, the received target column address is matched with at least two sets of redundant column addresses. If the target column address matches any set of redundant column addresses, the column selection switch devices corresponding to the matched set of redundant column addresses are all turned on, so that the corresponding redundant storage units can transmit data with the port. After two comparison stages, the redundant storage units can replace the failed storage units, thereby repairing the faulty storage units.

[0040] Meanwhile, each row of redundant storage units corresponds to at least two sets of redundant column addresses, and each set of redundant column addresses corresponds to the column addresses of at least two redundant storage units. That is, in this embodiment, each row of redundant storage units is divided, and the row addresses of the storage units used for repair by the redundant storage units corresponding to the redundant column addresses of different sets of redundant storage units in a row of redundant storage units can be different. This allows storage units in different rows to be repaired through the same row of redundant storage units, that is, the same row of redundant storage units can be split for repair. This allows the same row of redundant storage units to not be limited to repairing only one faulty storage unit, thereby enhancing the repair capability of redundant storage units. In other words, it can greatly increase the reliability of the memory, and the reliability determination of the chip can be completed with fewer redundant arrays, and the size of the chip can be reduced.

[0041] The repair circuit 10 of this application embodiment can automatically perform repairs within the memory chip after leaving the factory, exhibiting strong reliability. Similarly, the redundant memory cells in the same column of this application embodiment can also be divided to repair memory cells in different columns, not limited to repairing only one faulty memory cell in a column of redundant memory cells, thus enhancing the repair capability of redundant memory cells. This application embodiment relates to the array structure of memory such as DRAM, and particularly to the repair process and repair circuit design for faulty memory cells in a DRAM memory array.

[0042] In some embodiments, the repair control module 120 is further configured to: activate the word line of the memory cell corresponding to the target row address if the target row address does not match any of the failed row addresses; and control the column selection switch device corresponding to the target column address to open if the target column address does not match any of the redundant column addresses, so that the corresponding memory cell can transmit data with the port. That is, when the target row address and target column address do not match the failed row address and redundant column address, it indicates that the target memory cell is not a failed cell, and data access to the target memory cell can be directly performed according to the address of the target memory cell without switching to a redundant memory cell.

[0043] See Figure 2 As shown, this application embodiment provides a schematic diagram of the framework for the electrical connection between the first address storage module 110 and the repair control module 120. (As...) Figure 2 As shown, the repair control module 120 includes: a row address comparison module 121, a first control module 122, a column address comparison module 123, and a second control module 124.

[0044] The row address comparison module 121 is electrically connected to the address storage module 110. The row address comparison module 121 is configured to compare the received target row address with each failed row address. If the target row address matches any failed row address, the first matching information is generated.

[0045] The first control module 122 is electrically connected to the row address comparison module 121. The first control module 122 is configured to generate a first control signal based on the first matching information output by the row address comparison module 121 and output it to the word line of the row of redundant memory cells corresponding to the failed row address, so as to control the switching device electrically connected to the word line to be turned on.

[0046] The column address comparison module 123 is electrically connected to the address storage module 110. The column address comparison module 123 is configured to match the received target column address with at least two sets of redundant column addresses. If the target column address matches any set of redundant column addresses, second matching information is generated. The second matching information is used to indicate the set of redundant column addresses that are matched.

[0047] The second control module 124 is electrically connected to the column address comparison module 123. The second control module 124 is configured to generate a second control signal based on the second matching information output by the column address comparison module 123 and output it to the control line of the column selection switch device corresponding to a set of matched redundant column addresses to control the column selection switch device to be turned on.

[0048] In some embodiments, the row address comparison module 121 is further configured to generate third matching information if the target row address does not match any of the failed row addresses.

[0049] The first control module 122 is also configured to generate a third control signal based on the third matching information output by the row address comparison module 121 and output it to the word line of the memory cell corresponding to the target row address, so as to control the switching device electrically connected to the word line to be turned on.

[0050] In some embodiments, the column address comparison module 123 is further configured to generate fourth matching information if the target column address does not match any of the redundant column addresses.

[0051] The second control module 124 is configured to generate a fourth control signal based on the fourth matching information output by the column address comparison module 123 and output it to the control line of the column selection switch device corresponding to the target column address, so as to control the column selection switch device to be turned on.

[0052] See Figure 3 As shown, this application embodiment provides a schematic diagram of the framework for the electrical connection between the second address storage module 110 and the repair control module 120. Figure 3 As shown, the first control module 122 includes: a redundant row decoding unit 1221, a first voltage control unit 1222, a row address decoding unit 1223, and a second voltage control unit 1224.

[0053] The redundant row decoding unit 1221 is electrically connected to the row address comparison module 121. The redundant row decoding unit 1221 is configured to generate a redundant row address based on the first matching information output by the row address comparison module 121, and generate a first enable signal based on the redundant row address. The redundant row address is used to represent the row address of a row of redundant storage cells.

[0054] The first voltage control unit 1222 is electrically connected to the redundant row decoding unit 1221. The first voltage control unit 1222 is configured to generate a first control signal according to the first enable signal output by the redundant row decoding unit 1221, and output it to the word line of the row of redundant memory cells corresponding to the failed row address, so as to control the switching device electrically connected to the word line to be turned on.

[0055] The row address decoding unit 1223 is electrically connected to the row address comparison module 121. The row address decoding unit 1223 is configured to generate a second enable signal based on the third matching information output by the row address comparison module 121 and the target row address.

[0056] The second voltage control unit 1224 is electrically connected to the row address decoding unit 1223. The second voltage control unit 1224 is configured to generate a third control signal according to the second enable signal output by the row address decoding unit 1223, and output it to the word line of the memory cell corresponding to the target row address to control the switching device electrically connected to the word line to be turned on.

[0057] See Figure 3 As shown, the second control module 124 includes: a redundant column decoding unit 1241, a third voltage control unit 1242, a column address decoding unit 1243, and a fourth voltage control unit 1244.

[0058] The redundant column decoding unit 1241 is electrically connected to the column address comparison module 123. The redundant column decoding unit 1241 is configured to generate a set of matching redundant column addresses based on the second matching information output by the column address comparison module 123, and generate a third enable signal based on the set of matching redundant column addresses.

[0059] The third voltage control unit 1242 is electrically connected to the redundant column decoding unit 1241. The third voltage control unit 1242 is configured to generate a second control signal based on the third enable signal output by the redundant column decoding unit 1241 and output it to the control line of the column selection switch device corresponding to a set of matched redundant column addresses, so as to control the column selection switch device to be turned on.

[0060] The column address decoding unit 1243 is electrically connected to the column address comparison module 123. The column address decoding unit 1243 is configured to generate a fourth enable signal based on the fourth matching information output by the column address comparison module 123 and the target column address.

[0061] The fourth voltage control unit 1244 is electrically connected to the column address decoding unit 1243. The fourth voltage control unit 1244 is configured to generate a fourth control signal based on the fourth enable signal output by the column address decoding unit 1243, and output it to the control line of the column selection switch device corresponding to the target column address to control the column selection switch device to be turned on.

[0062] See Figure 4 As shown, this application embodiment provides a schematic diagram of the framework of a second repair circuit 10. Figure 4 In the illustrated embodiment, only the structure of one repair control module 120 is shown; the structures of the remaining repair control modules 120 included in the repair circuit 10 are identical.

[0063] See Figure 4 As shown, the repair circuit 10 also includes a repair mode selection module 130.

[0064] The repair mode selection module 130 is electrically connected to both the address storage module 110 and the repair control module 120. The repair mode selection module 130 is configured to determine the repair mode based on at least one of the number of failed row addresses output by the address storage module 110 and the number of rows of redundant storage units. The repair modes include a first repair mode and a second repair mode. If the repair mode is the first repair mode, the repair control module 120 is controlled to perform a first comparison stage. If the repair mode is the second repair mode, the repair control module 120 is controlled to perform a first comparison stage and a second comparison stage.

[0065] Optionally, if the repair mode is the first repair mode, the repair control module 120 is controlled to perform a first comparison stage, including: if the target row address matches any failed row address, the word line of the row of redundant storage cells corresponding to the failed row address is activated, and the column selection switch devices corresponding to the column address of the row of redundant storage cells are all turned on; if the target row address does not match any of the failed row addresses, the word line of the storage cell corresponding to the target row address is activated, and the column selection switch devices corresponding to the column address of the row of storage cells are all turned on.

[0066] The repair circuit 10 in this embodiment can perform more flexible repairs. If the errors are concentrated in one row, a row of redundant storage units can be used for repair. If the errors are not concentrated in one row, only one row of redundant storage units can be used for repair.

[0067] In some embodiments, the repair mode selection module 130 is further configured to at least one of the following: If the number of invalid line addresses is one, then the repair mode is determined to be the first repair mode; If the number of invalid line addresses is greater than one, then the repair mode is determined to be the second repair mode; If the difference between the number of rows in the redundant storage unit and the number of failed row addresses is greater than the first preset value, then the repair mode is determined to be the first repair mode. If the difference between the number of rows in the redundant storage unit and the number of failed row addresses is not greater than the first preset value, then the repair mode is determined to be the second repair mode. If the number of rows of redundant storage units is greater than the second preset value, then the repair mode is determined to be the first repair mode.

[0068] Optionally, if the number of failed row addresses is one, it means that the failed storage units are concentrated in one row, and can be directly repaired using a row of redundant storage units. That is, when the erroneous storage units, i.e., the failed storage units, are concentrated in one row, the number of failed row addresses is one, and can be directly repaired using a row of redundant storage units through the first repair mode.

[0069] If the number of failed row addresses is greater than one, segmented repair using a single redundant storage unit is required. If the difference between the number of redundant storage units and the number of failed row addresses is greater than a first preset value, it indicates a large number of redundant storage units; in this case, a single redundant storage unit can directly replace a single failed storage unit. Similarly, if the number of redundant storage units is greater than a second preset value, it also indicates a large number of redundant storage units; in this case, a single redundant storage unit can directly replace a single failed storage unit. The second preset value is greater than the first preset value.

[0070] If the difference between the number of rows of redundant storage units and the number of failed row addresses is not greater than the first preset value, it indicates that the number of rows of redundant storage units is not large, and a single row of redundant storage units can be used to repair multiple failed storage units in different rows.

[0071] In the actual chip manufacturing process, it is possible that the faulty cells are concentrated in one row of memory cells. In this case, the first repair mode can be adjusted by adjusting the repair circuit to enable it to include the function of ordinary repair methods. This way, one less comparator comparison can be performed, saving power and timing, and the repair method will be more flexible.

[0072] The repair circuit 10 in this embodiment adds a repair mode selection bit, which can adopt the first repair mode or the second repair mode according to the actual situation. After the chip manufacturing is completed, the faulty memory cell arrangement of the memory array can be known through testing. Based on the repair circuit 10 in this embodiment, it can determine which repair mode needs to be used for repair.

[0073] See Figure 5 As shown in the diagram, this application embodiment provides a structural schematic diagram of a failed memory cell repaired using a first repair mode. Figure 5As shown, Row0 to RowN correspond to N+1 rows of storage units, Col0 to ColN correspond to N+1 columns of storage units, cell1 and cell2 represent storage units, and R Row0 corresponds to a row of redundant storage units. When three storage units in a row are faulty, a row of R Row0 can be used to replace all storage units in the row containing the faulty storage units.

[0074] Optionally, by storing the row address of the failed storage unit in the address storage module 110 during the initialization phase, the target row address sent from the outside is compared with the stored failed row address during the data access phase, and the comparison result is used to determine whether data access from the redundant unit is required.

[0075] See Figure 6 As shown in the diagram, this application provides a structural schematic of a failed memory cell repaired using a second repair mode. Figure 6 As shown, the three failed memory cells are all in different rows. Since the repair circuit 10 of this application embodiment segments a row of redundant memory cells, a row of redundant memory cells can be used to repair the situation where multiple failed memory cells are in different rows.

[0076] The repair circuit 10 in this embodiment divides a row of redundant storage units using redundant column addresses. The actual data access process requires two comparisons: the first comparison determines whether to activate a row of redundant storage units, and the second comparison determines whether to access the target storage unit or the redundant storage unit.

[0077] In some embodiments, the repair mode selection module 130 is electrically connected to both the row address comparison module 121 and the column address comparison module 123.

[0078] Repair mode selection module 130 is also configured to at least one of the following: If the repair mode is determined to be the first repair mode, a first flag signal is output to the row address comparison module 121 corresponding to each failed row address to start the row address comparison module 121, and a second flag signal is output to the column address comparison module 123 corresponding to each failed row address to stop the column address comparison module 123. If the repair mode is determined to be the second repair mode, a first flag signal is output to the row address comparison module 121 corresponding to each failed row address to start the row address comparison module 121, and a third flag signal is output to the column address comparison module 123 corresponding to the failed row address to start the column address comparison module 123.

[0079] In some embodiments, the redundant column address corresponding to a row of redundant storage cells can be divided into 2ⁿ groups of redundant column addresses, where 1≤n≤13 and n is a positive integer.

[0080] Optionally, a row of redundant storage units can be divided into 2 segments, 4 segments, 8 segments, etc., according to the order of the redundant storage units.

[0081] See Figure 7 As shown in the figure, this application provides a schematic diagram of the framework for fine-grained setting of repair circuit 10. The figure on this page takes half a bank of DRAM as an example. Half a bank has a total of 256 Mbit storage cells, of which there are 32K rows and 8K columns. It is subdivided into 8 storage array pieces (MAT) per row and 40 MATs per column. Each MAT contains 1k columns (bit lines BL) and 832 rows (word lines WL). The fine-grained division is based on columns and is divided into 8 segments, that is, a redundant row of storage cells can be divided into eight segments.

[0082] The fine-grained repair setting in this embodiment allows for precise division of each row of redundant memory cells. More precise division results in stronger repair capabilities, but also increases the required size of the comparison circuitry, leading to higher circuit area overhead. Therefore, in practice, the fine-grained repair setting can be configured according to the specific needs of the memory.

[0083] Optionally, each row of redundant storage units can be configured with an address register, and at least one failed row address and at least two sets of redundant column addresses corresponding to each row of redundant storage units are output to each address register in advance.

[0084] Optionally, the address storage module 110 may be a fuse array module, which is a non-volatile storage.

[0085] This application proposes a novel memory array repair method that allows for more flexible repair methods, enabling the splitting and repair of redundant memory cells into rows or columns. This enhances the repair capability of redundant memory cells, significantly increasing memory reliability. Furthermore, it allows for chip reliability assessment using fewer redundant arrays and reduces chip size.

[0086] Meanwhile, the repair circuit 10 of this application makes the internal repair mode of the memory chip more flexible, and also makes the overall repair capability stronger. It can complete a strong repair with fewer redundant arrays, and can reduce the chip area. Moreover, the novel repair mode designed by the repair circuit 10 of this application can automatically perform repairs inside the chip, which greatly increases the chip yield.

[0087] Based on the same inventive concept, this application provides a memory including: multiple bit lines, multiple word lines, multiple array-distributed memory cells, multiple array-distributed redundant memory cells, multiple sensitive amplifiers, and multiple repair circuits 10 according to this application. One bit line is electrically connected to one column of memory cells, and at least one bit line is electrically connected to one column of redundant memory cells. One word line corresponds to one row of memory cells, and at least one word line corresponds to one row of redundant memory cells. Each sensitive amplifier includes two column select switching devices, each column select switching device being electrically connected to a port; Each repair control module 120 is electrically connected to a row of redundant storage units, and each repair control module 120 is electrically connected to the column selection switching devices of multiple sensitive amplifiers.

[0088] In some embodiments, the memory includes a plurality of first storage blocks 210 and at least one second storage block 220, with storage cells located within the first storage blocks 210 and redundant storage cells located within the second storage blocks 220.

[0089] The second storage block 220 where each row of redundant storage units is located is not adjacent to the first storage block 210 where the corresponding repaired storage unit of each row of redundant storage units is located.

[0090] In practical applications, due to the possibility that the word lines (WL) of redundant memory cells and corresponding repaired memory cells may be activated simultaneously, data readout conflicts between the left and right sensitive amplifiers (SA) can easily occur. Since two adjacent memory blocks share a single sensitive amplifier (SA), this embodiment sets the first memory block 210 containing each row of redundant memory cells and the second memory block 220 containing the corresponding repaired memory cells to be non-adjacent. This also prevents the memory block containing the word line of a row of redundant memory cells from being adjacent to the memory block containing the word line of its corresponding memory cell, thereby avoiding data readout conflicts between the sensitive amplifiers (SA).

[0091] See Figure 8 As shown in the figure, this application provides a schematic diagram of the arrangement structure of a first type of storage block. Figure 8 As shown in the figure, four second storage blocks 220 are used as an example; the remaining storage blocks are all first storage blocks 210. Only the label of one first storage block 210 is used as an example. The arrows in the figure indicate that redundant storage cells within the second storage blocks 220 can be used to repair storage cells within the first storage blocks 210. Using this first type of storage block arrangement structure makes decoding easier.

[0092] Arrange the storage blocks in a top-to-bottom order. The redundant storage units in the fourth second storage block 220 can be used to repair the storage units in the second and third first storage blocks 210. This process is repeated, with the first second storage block 220 being used to repair the storage units in the other second storage blocks 220 that do not correspond to the storage units in the first storage block 210.

[0093] See Figure 9 As shown in the figure, this application embodiment provides a schematic diagram of the arrangement structure of a second type of storage block. Figure 9 and Figure 8 The difference in the embodiments lies in the arrangement of the first storage block 210 and the second storage block 220, and the fact that redundant storage units within the second storage block 220 can be used to adjust the correspondence of storage units within the arranged first storage block 210. The second storage block arrangement structure ensures that each second storage block 220 and the corresponding adjusted first storage block 210 are evenly distributed.

[0094] The storage blocks are arranged in a top-to-bottom order. Taking the second storage block 220, which is the fourth one, as an example, the redundant storage units in the second storage block 220 can be used to repair the storage units in the first and second first storage blocks 210 and the storage units in the seventh first storage block 210.

[0095] The memory in this application embodiment includes the repair circuit 10 of this application embodiment. For the contents of the memory in this application embodiment that are not described in detail, please refer to the contents of the repair circuit 10 of this application embodiment, which will not be repeated here.

[0096] Based on the same inventive concept, embodiments of this application provide an electronic device, including: a repair circuit 10 of embodiments of this application or a memory of embodiments of this application.

[0097] Alternatively, the electronic device can be a smartphone, laptop, digital radio receiver, PDA (personal digital assistant), PAD (tablet computer), PMP (portable multimedia player), in-vehicle terminal (e.g., in-vehicle navigation terminal), wearable device, etc., or a fixed terminal such as a smart TV, desktop computer, etc.

[0098] See Figure 10 As shown, this application provides a flowchart of a control method. This control method is applied to the repair circuit 10 of this application embodiment, as follows: Figure 10 As shown, the control method includes steps S101 to S102.

[0099] S101. In the first comparison stage, the received target row address is compared with each failed row address. If the target row address matches any failed row address, the word line of the redundant storage cell corresponding to the failed row address is activated.

[0100] S102. In the second comparison stage, the received target column address is matched with at least two sets of redundant column addresses. If the target column address matches any set of redundant column addresses, the column selection switch devices corresponding to the matched set of redundant column addresses are turned on so that the corresponding redundant storage units and ports can transmit data.

[0101] In some embodiments, prior to the first comparison stage, the method further includes: determining a repair mode based on at least one of the number of failed row addresses and the number of rows of redundant storage units; the repair mode includes a first repair mode and a second repair mode; if the repair mode is the first repair mode, then the first comparison stage is performed; if the repair mode is the second repair mode, then the first comparison stage and the second comparison stage are performed.

[0102] In some embodiments, a repair mode is determined based on at least one of the number of failed row addresses and the number of rows of redundant storage units, including any of the following: If the number of invalid line addresses is one, then the repair mode is determined to be the first repair mode; If the number of invalid line addresses is greater than one, then the repair mode is determined to be the second repair mode; If the difference between the number of rows in the redundant storage unit and the number of failed row addresses is greater than the first preset value, then the repair mode is determined to be the first repair mode. If the difference between the number of rows in the redundant storage unit and the number of failed row addresses is not greater than the first preset value, then the repair mode is determined to be the second repair mode. If the number of rows of redundant storage units is greater than the second preset value, then the repair mode is determined to be the first repair mode.

[0103] In some embodiments, if the repair mode is a first repair mode, then a first comparison phase is performed, including: If the repair mode is the first repair mode, then the first flag signal is output to the row address comparison module 121 of the repair circuit 10 corresponding to each failed row address to start the row address comparison module 121, and the second flag signal is output to the column address comparison module 123 of the repair circuit 10 corresponding to the failed row address to stop the column address comparison module 123.

[0104] And / or, if the repair mode is the second repair mode, then the first comparison stage and the second comparison stage are executed, including: if the repair mode is the second repair mode, then outputting a first flag signal to the row address comparison module 121 corresponding to each failed row address to start the row address comparison module 121, and outputting a third flag signal to the column address comparison module 123 corresponding to each failed row address to start the column address comparison module 123.

[0105] The control method of this application embodiment is applied to the repair circuit 10 of this application embodiment. For the contents of the control method of this application embodiment that are not described in detail, please refer to the contents of the repair circuit 10 of this application embodiment, which will not be repeated here.

[0106] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0107] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0108] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0109] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0110] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0111] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0112] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A repair circuit, characterized in that, include: The address storage module and multiple repair control modules, each repair control module corresponds to a row of redundant storage units, and each repair control module is electrically connected to the address storage module. Each row of redundant storage units corresponds to at least one failed row address and at least two sets of redundant column addresses. The failed row address is used to represent the row address corresponding to the failed storage unit, and each set of redundant column addresses is used to represent the column addresses corresponding to at least two redundant storage units. The address storage module is configured to store at least one of the failed row addresses and each group of redundant column addresses, and provide them to each of the repair control modules accordingly; The repair control module is configured to compare the received target row address with each of the failed row addresses in the first comparison phase. If the target row address matches any of the failed row addresses, the word line of the row of redundant storage cells corresponding to the failed row address is activated. In the second comparison phase, the received target column address is matched with at least two sets of redundant column addresses. If the target column address matches any set of redundant column addresses, the column selection switch devices corresponding to the matched set of redundant column addresses are turned on so that the corresponding redundant storage units can transmit data with the port. The target row address and the target column address are the row address and column address corresponding to the storage unit that needs to read data, respectively.

2. The repair circuit according to claim 1, characterized in that, The repair control module is also configured to any of the following: If the target row address does not match any of the failed row addresses, then the word line of the memory cell corresponding to the target row address is activated; If the target column address does not match any of the redundant column addresses in each group, the column selection switch device corresponding to the target column address is turned on so that the corresponding storage unit and port can transmit data.

3. The repair circuit according to claim 1, characterized in that, The repair control module includes: The row address comparison module, electrically connected to the address storage module, is configured to compare the received target row address with each of the failed row addresses, and if the target row address matches any of the failed row addresses, generate first matching information. The first control module, electrically connected to the row address comparison module, is configured to generate the first control signal based on the first matching information output by the row address comparison module and output it to the word line of the row redundant memory cell corresponding to the failed row address, so as to control the switching device electrically connected to the word line to be turned on. The column address comparison module, electrically connected to the address storage module, is configured to match the received target column address with at least two sets of redundant column addresses. If the target column address matches any set of redundant column addresses, second matching information is generated. The second matching information is used to indicate the set of redundant column addresses that are matched. The second control module, electrically connected to the column address comparison module, is configured to generate a second control signal based on the second matching information output by the column address comparison module and output it to the control line of the column selection switch device corresponding to the matched set of redundant column addresses, so as to control the column selection switch device to be turned on.

4. The repair circuit according to claim 3, characterized in that, The row address comparison module is further configured to generate third matching information if the target row address does not match any of the failed row addresses. The first control module is further configured to generate a third control signal based on the third matching information output by the row address comparison module and output it to the word line of the memory cell corresponding to the target row address, so as to control the switching device electrically connected to the word line to be turned on.

5. The repair circuit according to claim 3, characterized in that, The column address comparison module is further configured to generate a fourth matching information if the target column address does not match any of the redundant column addresses in each group. The second control module is configured to generate a fourth control signal based on the fourth matching information output by the column address comparison module and output it to the control line of the column selection switch device corresponding to the target column address, so as to control the column selection switch device to be turned on.

6. The repair circuit according to claim 3, characterized in that, The first control module includes: A redundant row decoding unit, electrically connected to the row address comparison module, is configured to generate a redundant row address based on the first matching information output by the row address comparison module, and generate a first enable signal based on the redundant row address; the redundant row address is used to represent the row address of a row of the redundant storage cells. The first voltage control unit, electrically connected to the redundant row decoding unit, is configured to generate the first control signal according to the first enable signal output by the redundant row decoding unit, and output it to the word line of the row of redundant memory cells corresponding to the failed row address, so as to control the switching device electrically connected to the word line to be turned on. The row address decoding unit is electrically connected to the row address comparison module and is configured to generate a second enable signal based on the third matching information output by the row address comparison module and the target row address. The second voltage control unit, electrically connected to the row address decoding unit, is configured to generate a third control signal based on the second enable signal output by the row address decoding unit, and output it to the word line of the memory cell corresponding to the target row address to control the switching device electrically connected to the word line to turn on.

7. The repair circuit according to claim 3, characterized in that, The second control module includes: The redundant column decoding unit is electrically connected to the column address comparison module and is configured to generate a matching set of redundant column addresses based on the second matching information output by the column address comparison module, and generate a third enable signal based on the matching set of redundant column addresses. The third voltage control unit, electrically connected to the redundant column decoding unit, is configured to generate a second control signal based on the third enable signal output by the redundant column decoding unit and output it to the control line of the column selection switching device corresponding to a set of the redundant column addresses, so as to control the column selection switching device to be turned on. The column address decoding unit is electrically connected to the column address comparison module and is configured to generate a fourth enable signal based on the fourth matching information output by the column address comparison module and the target column address. The fourth voltage control unit, electrically connected to the column address decoding unit, is configured to generate a fourth control signal based on the fourth enable signal output by the column address decoding unit, and output it to the control line of the column selection switch device corresponding to the target column address to control the column selection switch device to be turned on.

8. The repair circuit according to claim 3, characterized in that, Also includes: The repair mode selection module is electrically connected to both the address storage module and the repair control module, and is configured to determine the repair mode based on at least one of the number of failed row addresses output by the address storage module and the number of rows of the redundant storage unit. The repair mode includes a first repair mode and a second repair mode. If the repair mode is the first repair mode, then the repair control module is controlled to perform the first comparison stage; if the repair mode is the second repair mode, then the repair control module is controlled to perform the first comparison stage and the second comparison stage.

9. The repair circuit according to claim 8, characterized in that, The repair mode selection module is also configured to at least one of the following: If the number of failed line addresses is one, then the repair mode is determined to be the first repair mode; If the number of failed line addresses is greater than one, then the repair mode is determined to be the second repair mode; If the difference between the number of rows in the redundant storage unit and the number of failed row addresses is greater than a first preset value, then the repair mode is determined to be the first repair mode. If the difference between the number of rows in the redundant storage unit and the number of failed row addresses is not greater than a first preset value, then the repair mode is determined to be the second repair mode. If the number of rows in the redundant storage unit is greater than the second preset value, then the repair mode is determined to be the first repair mode.

10. The repair circuit according to claim 8, characterized in that, The repair mode selection module is electrically connected to both the row address comparison module and the column address comparison module. The repair mode selection module is also configured to at least one of the following: If the repair mode is determined to be the first repair mode, then a first flag signal is output to the row address comparison module corresponding to each of the failed row addresses to start the row address comparison module, and a second flag signal is output to the column address comparison module corresponding to each of the failed row addresses to stop the column address comparison module. If the repair mode is determined to be the second repair mode, a first flag signal is output to the row address comparison module corresponding to each of the failed row addresses to start the row address comparison module, and a third flag signal is output to the column address comparison module corresponding to the failed row address to start the column address comparison module.

11. The repair circuit according to claim 1, characterized in that, The redundant column addresses corresponding to the redundant storage units in a row are divided into 2ⁿ groups of redundant column addresses, where 1≤n≤13 and n is a positive integer.

12. A memory, characterized in that, include: Multiple bit lines, multiple word lines, multiple array-distributed memory cells, multiple array-distributed redundant memory cells, multiple sensitive amplifiers, and multiple repair circuits as described in any one of claims 1-11; One bit line is electrically connected to a column of memory cells, and at least one bit line is electrically connected to a column of redundant memory cells; One word line is electrically connected to a row of the memory cells, and at least one word line is electrically connected to a row of redundant memory cells; Each of the aforementioned sensitive amplifiers includes two column select switching devices, each of the column select switching devices being electrically connected to a corresponding port; Each of the repair control modules is electrically connected to a row of the redundant storage units, and each of the repair control modules is electrically connected to the column selection switching devices of the plurality of the sensitive amplifiers.

13. The memory according to claim 12, characterized in that, The memory includes a plurality of first memory blocks and at least one second memory block, wherein the memory cell is located within the first memory block and the redundant memory cell is located within the second memory block; The second storage block containing the redundant storage unit in each row is not adjacent to the first storage block containing the storage unit that is repaired corresponding to the redundant storage unit in each row.

14. An electronic device, characterized in that, include: The repair circuit as described in any one of claims 1-11 or the memory as described in any one of claims 12-13.

15. A control method, characterized in that, The control method, applied to the repair circuit as described in any one of claims 1-11, comprises: In the first comparison phase, the received target row address is compared with each failed row address. If the target row address matches any of the failed row addresses, the word line of the row of redundant storage cells corresponding to the failed row address is activated. In the second comparison phase, the received target column address is matched with at least two sets of redundant column addresses. If the target column address matches any set of redundant column addresses, the column selection switch devices corresponding to the matched set of redundant column addresses are turned on so that the corresponding redundant storage units and ports can transmit data.

16. The control method according to claim 15, characterized in that, Prior to the first comparison phase, it also includes: A repair mode is determined based on at least one of the number of failed row addresses and the number of rows in the redundant storage units; the repair mode includes a first repair mode and a second repair mode. If the repair mode is the first repair mode, then the first comparison phase is executed; If the repair mode is the second repair mode, then the first comparison phase and the second comparison phase are executed.

17. The control method according to claim 16, characterized in that, The step of determining the repair mode based on at least one of the number of failed row addresses and the number of rows in the redundant storage units includes any one of the following: If the number of failed line addresses is one, then the repair mode is determined to be the first repair mode; If the number of failed line addresses is greater than one, then the repair mode is determined to be the second repair mode; If the difference between the number of rows in the redundant storage unit and the number of failed row addresses is greater than a first preset value, then the repair mode is determined to be the first repair mode. If the difference between the number of rows in the redundant storage unit and the number of failed row addresses is not greater than a first preset value, then the repair mode is determined to be the second repair mode. If the number of rows in the redundant storage unit is greater than the second preset value, then the repair mode is determined to be the first repair mode.

18. The control method according to claim 16, characterized in that, If the repair mode is the first repair mode, then the first comparison phase is performed, including: If the repair mode is the first repair mode, then a first flag signal is output to the row address comparison module of the repair circuit corresponding to each failed row address to start the row address comparison module, and a second flag signal is output to the column address comparison module of the repair circuit corresponding to the failed row address to stop the column address comparison module; and / or, If the repair mode is the second repair mode, then the first comparison stage and the second comparison stage are executed, including: If the repair mode is the second repair mode, then a first flag signal is output to the row address comparison module corresponding to each of the failed row addresses to start the row address comparison module, and a third flag signal is output to the column address comparison module corresponding to each of the failed row addresses to start the column address comparison module.

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