Reliability demonstration test device and test method for NAND Flash with multi-MCU (Microprogrammed Control Unit) collaboration

Abstract

The invention discloses a NAND Flash reliability demonstration test device with multiple MCUs cooperating. The NAND Flash reliability demonstration test device comprises a communication main control board, a pluggable test small board, a unified bottom board, a dynamic voltage switching module, a high-reliability communication mechanism and a segmented temperature control system. The communication main control board is provided with a first MCU for coordinating test tasks and managing temperature control; each small test board is provided with a second MCU and an interface circuit adaptive to NAND Flash packaging, and a dynamic voltage switching module is integrated to output a working voltage matched with the electrical specification of the chip; the unified bottom plate provides a power supply network and a communication bus; the high-reliability communication mechanism is based on an annular DMA buffer area, a double-byte frame header and a BCC check code, and first-level near-end realignment and second-level far-end frame skip advancing are executed. The segmented temperature control system is controlled in a closed-loop mode through the first MCU according to the strategy of four stages of fast temperature rise, slow approximation, keep steady state and slow-stop temperature reduction. The NAND Flash chip reliability demonstration test system is suitable for reliability demonstration test of the NAND Flash chip under high-temperature and high-load conditions, and the test compatibility, the communication robustness and the temperature control precision are effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor memory reliability test, in particular to a NAND Flash reliability demonstration test device and test method based on multi-MCU cooperation. BACKGROUND

[0002] As the most core non-volatile memory in modern electronic devices, NAND Flash is widely used in intelligent terminals, solid state disks, vehicle-mounted systems, industrial control and Internet of Things devices. With continuous miniaturization of the process, the erase-write life of the device, the evolution characteristics of bad blocks and high-temperature reliability become increasingly important. Before the device is shipped, the manufacturer must perform RDT (Reliability Demonstration Test) to verify the stability of the chip under high temperature, high load and long cycle.

[0003] However, the existing NAND Flash RDT test device still has the following technical bottlenecks in actual application:

[0004] (1) In a test cycle of hundreds to thousands of hours, a large amount of state data such as bad block statistics and ECC errors need to be continuously uploaded, but the existing serial communication link is prone to packet loss or frame synchronization loss in an industrial electromagnetic interference environment, and lacks local fault tolerance recovery mechanism, often causing the whole machine to reset or test interruption;

[0005] (2) Because NAND Flash has multiple packaging forms such as BGA132 and BGA154, and power supply specifications such as 1.2V, 1.8V and 3.3V, the traditional test fixture and power module need to be manually replaced, making it difficult to achieve fast switching and automatic adaptation;

[0006] (3) The existing temperature control system mostly uses single PID control or open-loop heating, which is prone to significant overshoot (such as overshoot > 5℃) in the temperature rising stage, and temperature drift due to thermal inertia in the steady state stage, making it difficult to meet the ±2℃ temperature control accuracy requirement of JEDEC standard in RDT test. SUMMARY

[0007] In view of the deficiencies in the prior art, the present application aims to provide a NAND Flash reliability test device and test method based on multi-MCU cooperation to solve the problems of insufficient packaging or voltage adaptation, simple temperature control strategy and poor communication stability of the existing test device.

[0008] To solve the above technical problems, the present application realizes the following scheme:

[0009] The application discloses a NAND Flash reliability demonstration test device based on multiple MCUs, which comprises a communication main control board, at least one pluggable test small board, a unified bottom plate, a dynamic voltage switching module, a high-reliability communication mechanism and a segmented temperature control system.

[0010] The communication main control board is provided with a first MCU, which is connected with the unified bottom plate and is used for coordinating the erasing and writing test tasks of each test small board and controlling a temperature control process.

[0011] Each test small board is provided with a second MCU and an interface circuit adapted to a NAND Flash chip package, the interface circuit is connected with a NAND Flash chip to be tested, and the second MCU communicates with the first MCU through the unified bottom plate.

[0012] The unified bottom plate is provided with a power supply network and a communication bus, and is electrically connected with the communication main control board and all test small boards.

[0013] The test small board is provided with a dynamic voltage switching module controlled by the second MCU and used for outputting a working voltage adapted to the electrical specification of the NAND Flash chip to be tested.

[0014] The high-reliability communication mechanism comprises a ring-shaped DMA buffer, a double-byte frame header, a minimum frame length threshold and a BCC check code, and performs a one-level near-end realignment operation and a two-level far-end frame skipping and advancing operation to realize fault tolerance recovery.

[0015] The segmented temperature control system comprises a temperature sensor, a heating / cooling unit and a PWM driving circuit, and the first MCU executes a four-stage power control strategy of fast heating, slow approaching, keep steady and slow-stop cooling.

[0016] Preferably, the test small board is provided with a signal pin interface circuit adapted to a BGA132 package or a BGA154 package, and all test small boards are connected to the same power supply network and communication bus through the unified bottom plate.

[0017] Preferably, the working voltage is 1.2V, 1.8V or 3.3V, and the working voltage is selected and output by the second MCU according to the model of the NAND Flash chip to be tested.

[0018] Preferably, the high-reliability communication mechanism triggers frame boundary identification through a serial bus idle interrupt.

[0019] Preferably, the high-reliability communication mechanism is configured as follows:

[0020] Based on the local search of the ring-shaped DMA buffer, the double-byte frame header is searched and verified, and after the BCC check code is verified, the valid data frame is parsed to realize the first-level near-end realignment.

[0021] When the continuous multiple frame checks fail, the invalid data segment is skipped forward based on the ring-shaped DMA buffer, and the frame start position is repositioned to realize the second-level far-end frame skipping promotion.

[0022] Preferably, the segmented temperature control system is configured with a power mapping table, and the first MCU queries the power mapping table according to the deviation of the current temperature and the target temperature, and outputs the corresponding PWM duty cycle signal to the PWM drive circuit.

[0023] Preferably, the first MCU adjusts the switching threshold of the four-stage power control strategy according to the number of erase-write cycles and the power consumption load state.

[0024] Preferably, a plurality of test small plates are operated in parallel, and any communication exception or test interruption of any test small plate is handled locally by the second MCU thereof.

[0025] Preferably, the first MCU or the second MCU is configured with a dual-backup firmware storage area for performing online firmware update and version rollback operations.

[0026] The application also provides a NAND Flash reliability demonstration test method, which is applied to the NAND Flash reliability demonstration test device with multiple MCU cooperation, and includes the following steps:

[0027] Step S100, the second MCU controls the dynamic voltage switching module to output a working voltage matching the electrical specifications of the NAND Flash chip to be tested according to the model of the NAND Flash chip to be tested.

[0028] Step S200, the first MCU starts the four-stage power control strategy of the segmented temperature control system.

[0029] Step S300, the test small plate performs a high-temperature erase-write cycle test, and synchronously collects the number of bad blocks, the ECC error rate and temperature data.

[0030] Step S400, the high-reliability communication mechanism uploads the test data, and performs a hierarchical fault-tolerant recovery operation when the frame check fails.

[0031] Step S500, after the test is completed, a reliability evaluation report containing the life prediction result and the temperature fluctuation curve is generated.

[0032] Compared with the prior art, the application has the following beneficial effects:

[0033] The existing device needs to replace a complete set of fixtures or power supply modules for different packages and power supply voltages, and the switching takes a long time and is prone to errors. The present application adopts a pluggable test small plate design, each small plate integrates an interface circuit adapted to a specific package, and the small plate is built-in with a dynamic voltage switching module controlled by a second MCU, which can automatically output a matching operating voltage according to the chip model. Due to the difference in packaging, only the small plate interface layout is different, while the power supply and communication are accessed through a unified bottom plate standardized. The voltage switching is realized by the second MCU software controlling the MOS switch array, without manual intervention. Users only need to replace the corresponding small plate to complete the full adaptation from BGA132 to BGA154 and from 1.2V to 3.3V, avoiding the cumbersome process of mechanical disassembly and power supply reconfiguration of traditional equipment.

[0034] In long-period testing, serial communication is prone to electromagnetic interference, resulting in frame synchronization loss or check failure, often causing the whole machine to reset and interrupt testing. The present application has strong communication fault tolerance and supports single-channel fault isolation. The ring-shaped DMA ensures continuous data caching without loss, and the double-byte frame header reduces the probability of false triggering. When noise causes partial byte errors, the first-level realignment can locally recover and parse in the buffer area without emptying the entire queue. If multiple consecutive frames fail, the second-level jump frame actively skips the contaminated data segment to quickly find the synchronization point. This mechanism limits communication abnormalities to a single data frame level and prevents them from spreading to the main control or other test channels, ensuring continuous operation for thousands of hours of testing.

[0035] Traditional single-stage PID temperature control has large overshoot and high steady-state fluctuation, which cannot meet the ±2℃ precision requirement of RDT testing by JEDEC. The present application controls the steady-state temperature fluctuation within ±1.5℃, with an overshoot of <2℃, significantly improving the repeatability of RDT results. In the fast warming-up phase, the target temperature is quickly approached with high power; in the slow approaching phase, the power slope is reduced to avoid overshoot caused by thermal inertia; in the keep steady phase, the PWM duty cycle is adjusted according to the measured deviation to maintain high steady-state precision; and in the slow-stop cooling-down phase, the heat source is gradually turned off to prevent temperature sudden drop from affecting chip stress evaluation. The four-stage strategy actively compensates for the nonlinear characteristics of the thermal system, rather than relying on single feedback regulation, fundamentally suppressing overshoot and drift.

[0036] In the prior art, any test channel failure of the test equipment often causes the whole machine to stop, resulting in low resource utilization. The present application does not affect other channels to continue testing when a single channel fails, significantly improving the overall system availability by several times. Since each test small plate has independent control, power supply, and communication logic, its second MCU can handle local exceptions such as retrying erasing and reporting error states without the need for main control intervention or global reset. Even if a small plate is deadlocked due to chip damage, the remaining channels can still complete the entire RDT process, greatly improving equipment throughput and line efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 It is a circuit schematic diagram of a test small plate in a NAND Flash reliability demonstration test device of a plurality of MCU cooperation of the application.

[0038] Figure 2 It is a control flow chart of a segmented temperature control system in a NAND Flash reliability demonstration test device of a plurality of MCU cooperation of the application.

[0039] Figure 3 It is a flow schematic diagram of a high-reliability communication mechanism in a NAND Flash reliability demonstration test device of a plurality of MCU cooperation of the application.

[0040] Figure 4 It is a flow schematic diagram of a NAND Flash reliability demonstration test method of the application.

[0041] Figure 5 It is a flow schematic diagram of step S100 of a NAND Flash reliability demonstration test method of the application.

[0042] Figure 6 It is a flow schematic diagram of step S200 of a NAND Flash reliability demonstration test method of the application.

[0043] Figure 7 It is a flow schematic diagram of step S300 of a NAND Flash reliability demonstration test method of the application.

[0044] Figure 8 It is a flow schematic diagram of step S400 of a NAND Flash reliability demonstration test method of the application.

[0045] Figure 9 It is a flow schematic diagram of step S500 of a NAND Flash reliability demonstration test method of the application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application, so that the advantages and characteristics of the application can be more easily understood by those skilled in the art, and the protection scope of the application can be more clearly and definitely defined. Obviously, the described embodiments of the application are only some of the embodiments of the application, but not all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application.

[0047] In addition, the technical features involved in different embodiments of the application described below can be combined with each other as long as there is no conflict.

[0048] NAND Flash is the most core non-volatile memory in modern electronic devices, and is widely used in smart terminals, solid state disks, vehicle-mounted systems, industrial control and Internet of Things devices. With continuous miniaturization of the process, the erase-write life of the device, the evolution characteristics of bad blocks and high temperature reliability become increasingly important. Before the device is shipped, the manufacturer must perform RDT (Reliability Demonstration Test) to verify the stability of the chip under high temperature, high load and long cycle.

[0049] However, the existing NAND Flash RDT test device still has the following technical bottlenecks in practical application:

[0050] In a test cycle of hundreds to thousands of hours, a large amount of state data such as bad block statistics and ECC errors need to be continuously uploaded. However, the existing serial communication link is prone to packet loss or frame synchronization loss in an industrial electromagnetic interference environment, and lacks local fault tolerance recovery mechanism, often causing the whole machine to reset or test interruption;

[0051] Because NAND Flash has multiple packaging forms such as BGA132 and BGA154, and power supply specifications such as 1.2V, 1.8V and 3.3V, the traditional test fixture and power module need to be manually replaced, making it difficult to achieve fast switching and automatic adaptation;

[0052] The existing temperature control system mostly uses single PID control or open-loop heating, which is prone to significant overshoot (such as overshoot > 5℃) in the warming-up stage, and temperature drift in the steady-state stage due to thermal inertia, making it difficult to meet the requirement of ±2℃ temperature control accuracy in RDT test according to JEDEC standard.

[0053] To solve the above technical problems, the present application provides a NAND Flash reliability demonstration test device and test method with multiple MCU cooperation.

[0054] Embodiment 1: The specific structure of the present application is as follows:

[0055] The application discloses a NAND Flash reliability demonstration test device based on multi-MCU cooperation, which comprises a communication main control board, at least one pluggable test small board, a unified bottom plate, a dynamic voltage switching module, a high-reliability communication mechanism and a segmented temperature control system; the communication main control board is provided with a first MCU, the first MCU is connected with the unified bottom plate, and is used for coordinating erasing and writing test tasks of each test small board and controlling a temperature control process; each test small board is provided with a second MCU and an interface circuit matched with a NAND Flash chip package, the interface circuit is connected with a NAND Flash chip to be tested, and the second MCU communicates with the first MCU through the unified bottom plate; the unified bottom plate is provided with a power supply network and a communication bus, and is electrically connected with the communication main control board and all test small boards; the test small board is provided with a dynamic voltage switching module controlled by the second MCU, and is used for outputting a working voltage matched with an electrical specification of the NAND Flash chip to be tested; the high-reliability communication mechanism comprises a ring-shaped DMA buffer, a double-byte frame header, a minimum frame length threshold and a BCC check code, and performs a first-level near-end realignment operation and a second-level far-end frame skipping operation to realize fault tolerance recovery; and the segmented temperature control system comprises a temperature sensor, a heating / cooling unit and a PWM driving circuit, and the first MCU executes a four-stage power control strategy of fast heating, slow approaching, keep steady and slow-stop cooling.

[0056] In the embodiment, the existing device needs to replace a complete set of clamps or power supply modules for different packages and power supply voltages, and the switching takes a long time and is prone to errors. The application adopts a pluggable test small board design, each small board is integrated with an interface circuit matched with a specific package, and the small board is provided with a dynamic voltage switching module controlled by a second MCU, which can automatically output a matched working voltage according to the chip model. The package difference is only reflected in the small board interface layout, and the power supply and communication are accessed through the unified bottom plate. The voltage switching is realized by the second MCU software controlling a MOS switch array, without manual intervention. Users only need to replace the corresponding small board, so that full adaptation from BGA132 to BGA154 and from 1.2V to 3.3V can be realized, and the cumbersome process of mechanical disassembly and power supply reconfiguration of the traditional device is avoided.

[0057] It should be noted that the implementation mode of the dynamic voltage switching module in the application is to realize accurate power supply of the NAND Flash chip at 1.2V, 1.8V, 3.3V and other working voltages by combining a multi-stage DC-DC converter with a PMU power management chip, and support the compatibility of different package types such as BGA132 / BGA154. For example, Figure 1As shown, the dynamic voltage switching module includes at least one DC-DC converter, a PMU power management chip and a plurality of MOS switches. The DC-DC converter converts 5V input into 3.3V or 2.5V for NAND Flash I / O power supply; the PMU power management chip generates 1.2V, 1.8V or 3.3V core voltage according to the chip model to be tested, and the second MCU controls the enable signal thereof through GPIO to realize automatic voltage switching. Power is an external DC power input, usually +5V or 12V, which provides main power for the whole system. OVP is an overvoltage protection module to prevent the subsequent circuit from being damaged by abnormally high input voltage. After the external DC power input 5V is connected to the system, it first passes through the OVP overvoltage protection module for overvoltage detection and protection. If the input voltage exceeds the safety threshold (such as >5.5V), the OVP overvoltage protection module will cut off the output to avoid burning downstream devices. The 5V output by OVP is sent to different DC-DC converters in three ways. The first way is to reduce 5V to 3.3V for the second MCU, which is used as a core controller to schedule test tasks, handle communications, control temperature control, etc. The second way is to reduce 5V to 3.3V, and then further convert it to 1.8V by the PMU power management chip, to provide 1.8V working voltage for the I / O or auxiliary logic circuit of the first MCU, and to convert it to 0.8V / 3.3V to supply the I / O interface and core power supply of the NAND Flash, respectively. The third way is to reduce 5V to 3.3V or 2.5V to directly supply the NAND Flash chip. This voltage is used for NAND VCCQ (I / O power supply), and the core voltage VCC is independently controlled by the PMU power management chip, such as 1.2V / 1.8V.

[0058] In long-period testing, serial communication is prone to electromagnetic interference, resulting in loss of frame synchronization or check failure, often causing the whole machine to reset and interrupt testing. The communication fault tolerance of the present application is extremely strong, supporting single-channel fault isolation. The ring DMA ensures that the data is continuously cached without loss, and the double-byte frame header reduces the probability of false triggering. When noise causes partial byte errors, the first-level realignment can locally recover and parse in the buffer area without the need to empty the entire queue; if multiple frames are invalid in succession, the second-level jump frame actively skips the contaminated data segment and quickly finds the synchronization point. This mechanism limits communication abnormalities to a single data frame level and does not spread to the host or other test channels, ensuring continuous operation of the test for thousands of hours.

[0059] Traditional single-stage PID temperature control has large overshoot and high steady-state fluctuation, which cannot meet the requirement of JEDEC on RDT test ±2℃ precision. The steady-state temperature fluctuation of the present application is controlled within ±1.5℃, and the overshoot of temperature rise is less than 2℃, which significantly improves the repeatability of RDT results. In the fast temperature rise stage, the target temperature is quickly approached with high power; in the slow approach stage, the power slope is reduced to avoid overshoot caused by thermal inertia; in the keep steady stage, the PWM duty cycle is fine-tuned according to the measured deviation to maintain high steady-state precision; and in the slow-stop cooling stage, the heat source is gradually turned off to prevent temperature drop from affecting chip stress evaluation. The four-stage strategy actively compensates for the nonlinear characteristics of the thermal system, rather than relying on single feedback regulation, which fundamentally suppresses overshoot and drift.

[0060] In the prior art, any test channel failure of the test equipment often leads to machine downtime, and the resource utilization is low. The single-channel failure of the present application does not affect the continuous testing of other channels, and the overall availability of the system is improved by more than several times. Because each test board has independent control, power supply and communication logic, the second MCU can independently handle local exceptions, such as retrying erasing, reporting error states, without the need for the host to intervene or globally reset. Even if a small board is deadlocked due to chip damage, the remaining channels can still complete the entire RDT process, greatly improving equipment throughput and line efficiency.

[0061] It should be further pointed out that the segmented temperature control system includes a temperature sensor, a heating / cooling unit and a PWM drive circuit, and the first MCU executes a four-stage power control strategy of fast temperature rise, slow approach, keep steady and slow-stop temperature drop. As shown in Figure 2 The four-stage power control strategy automatically switches to different control modes according to the difference between the current temperature and the target temperature, thereby achieving optimal response in different stages. Specifically, after the system is powered on, the first MCU initializes the temperature sensor, the heating circuit PWM output, obtains the current RDT test task parameters such as the target temperature and whether to enable the adaptive mode, and then sets the initial control parameters such as Δ_high, the maximum PWM duty cycle, etc. Δ_high is a large temperature difference threshold used to divide the boundary between the "temperature rise stage" and the "steady-state stage". The temperature is collected every certain time (such as 100ms), and the current error e is calculated as the basis for subsequent judgment. The temperature T is periodically read, and the error e=Tset-T is calculated.

[0062] When the absolute value of the error e is greater than Δ_high, enter the heating stage. When the temperature is far from the target, for example: 85℃ to 105℃, the error e > 10℃, the system enters the rapid heating stage, starts the power loop adaptive heating, and dynamically adjusts the PWM duty cycle according to the absolute value of the error |e|: when |e| is large, high PWM duty cycle, that is, full power heating; when |e| is medium, medium PWM duty cycle; when |e| is small, low PWM duty cycle. The slope of the power change is limited to avoid sudden changes that cause thermal shock and quickly approach the target temperature, but prevent overshoot.

[0063] When the absolute value of the error e is less than or equal to Δ_high, enter the steady state / cooling stage. When the temperature is close to the target (error < Δ_high, such as ±8℃), the system enters the fine control stage, and when e > 0 (low temperature), it enters the steady state / heating stage, enabling power loop and temperature loop control to smoothly rise to the target temperature and avoid repeated fluctuations. Power loop: adjust PWM according to error e, such as PID control; temperature loop: slowly fine-tune to suppress oscillation.

[0064] When e ≤ 0 (high temperature), enter the steady state / cooling stage, enabling predictive cooling control: based on the thermal model (such as RC thermal network) to predict the temperature trend, reduce the PWM output in advance to avoid overshoot due to thermal inertia, if the error is very negative, that is, serious over-temperature, then quickly cool down, otherwise slowly cool down, actively suppress overshoot, and achieve fast convergence.

[0065] The test board is provided with a signal pin interface circuit adapted to BGA132 package or BGA154 package, and all test boards are connected to the same power supply network and communication bus through the unified backplane.

[0066] In the present embodiment, there are multiple packaging forms of NAND Flash chips, such as BGA132 and BGA154, which differ in the number, arrangement and signal definition (such as I / O0-I / O7 vs I / O0-I / O15) of their pins. Therefore, a dedicated test board is designed for each packaging form, and the signal pin interface circuit on the test board is strictly wired according to the packaging specification of the target chip to ensure correct electrical connection and good signal integrity. Although the front-end interfaces are different, all test boards are connected to the same power supply network (such as +3.3V, GND) and communication bus (such as serial bus, I2C) through a unified backplane. This means that the power supply mode is consistent, the voltage rail, current capacity and filtering design are unified, and the communication protocol, electrical characteristics such as baud rate and level standard of the main control board are completely the same. The unified backplane serves as a universal carrier and does not need to be redesigned due to changes in packaging type. When the user replaces the chip to be tested, only the corresponding test board needs to be plugged in, such as replacing the BGA132 board with the BGA154 board, without the need to modify the backplane, main control board or external wiring. After the system is powered on, the second MCU automatically identifies the local chip type or is configured by the upper computer, starts the matching voltage and test process, and the entire process is seamlessly connected.

[0067] Due to the localization of packaging differences to the pluggable test board inside, the power supply, communication and control logic are all standardized through the unified backplane. The operator only needs to replace the physical board, i.e. the "hardware adapter", without the need to rewire, calibrate the power supply or modify the main control configuration, significantly improving the test compatibility and switching efficiency of multi-packaging NAND Flash chips. The unified backplane, communication main control board, temperature control system and other high-cost core components are reused, and only the low-value test board is customized according to the packaging. When a new packaging is added, only the new board needs to be developed, without the need to re-certify the entire system, significantly reducing the research and development and spare parts costs. All test boards share the same power supply network impedance characteristics, communication bus electrical parameters and temperature control environment. Even if the chip packaging is different, the power supply quality, instruction response delay and thermal stress conditions remain the same.

[0068] The operating voltage is 1.2V, 1.8V or 3.3V, which is selected and output by the second MCU according to the model of the NAND Flash chip to be tested.

[0069] In the embodiment, different types of NAND Flash chips have significant differences in requirements for core voltage VCC or I / O voltage VCCQ due to process, architecture and interface standards. For example, early SLC NAND mostly uses 3.3V; mainstream eMMC / UFS compatible TLC NAND commonly uses 1.8V; advanced 3D TLC / QLC NAND generally uses low-power 1.2V. Before the test starts, the system obtains the type of the chip to be tested through the host computer instruction or the local storage table. The second MCU queries the pre-stored voltage-type mapping table to determine the corresponding working voltage value, such as 1.2V / 1.8V / 3.3V. The second MCU controls the dynamic voltage switching module through GPIO or I2C, which is usually composed of multiple LDOs or DC-DCs cooperating with MOS switches, activates the corresponding voltage output channel, and closes other channels to ensure that only the accurate working voltage specified in the specification book is provided to the chip to be tested. After switching is completed, the actual output voltage can be optionally sampled by ADC to verify whether it is within the tolerance range, such as ±3%, to prevent chip damage due to power module failure.

[0070] Traditional devices often rely on manual jumper or fixed power module, which is prone to overvoltage burnout or undervoltage misjudgment due to operation errors. In the present scheme, the voltage selection is automatically completed by the second MCU according to the chip type, eliminating the human intervention link. As long as the chip type input is correct, it can be automatically obtained by scanning the code or database, and the voltage output is 100% matched with the specification book requirements, fundamentally eliminating the power supply risk. Since the voltage switching is automatically executed by the second MCU in the test initialization stage, the entire RDT process including voltage configuration, temperature control startup and erase cycle can be completely scripted. For example: test 1.2V UFS chip in the morning, automatically switch to 3.3V SLC industrial chip in the afternoon, without the need for engineers to intervene, improving the test automation level and throughput efficiency.

[0071] The high-reliability communication mechanism triggers frame boundary recognition through serial bus idle interruption.

[0072] In the embodiment, the communication master board and each test small board interact with each other through a serial bus, and the transmission content includes test instructions, bad block statistics, temperature data and the like. Due to the factors such as industrial electromagnetic interference in the test environment, long cable transmission, and multiple nodes sharing a bus, the traditional synchronization mode relying on fixed frame length or start symbol matching is prone to failure. The second MCU configures the serial bus peripheral to be in a DMA cyclic reception mode, and the data stream is continuously written into a ring buffer, without relying on byte-by-byte reading through interruption, so as to avoid CPU overload. The serial bus hardware monitors the bus state, and when no new data is received for a plurality of bit times (such as ≥3 character periods), it is determined that the bus enters an "idle" state, and an idle interruption is automatically triggered. The idle interruption service program (ISR) is called, at which time it can be determined that the previous frame of data has been completely received. The system extracts all the bytes received since the last idle interruption from the ring DMA buffer as a frame of candidate data. The extracted data frame is then subjected to double-byte frame header matching and BCC check. If the check passes, the payload is parsed; if it fails, hierarchical fault tolerance is started, such as first-level realignment and second-level frame skipping.

[0073] As shown in Figure 3 , the high-reliability communication mechanism is configured to search locally for the double-byte frame header based on the ring DMA buffer and verify the subsequent BCC check code, continue to parse the valid data frame after the check passes to realize first-level near-end realignment, and skip the invalid data segment based on the ring DMA buffer and reposition the frame start position to realize second-level far-end frame skipping when a plurality of consecutive frames fail to pass the check.

[0074] In the embodiment, the first-level near-end realignment: when the communication link fails to pass the check of a single frame due to transient interference, such as BCC error, the system does not immediately discard the entire buffer; instead, it searches for a predefined double-byte frame header, such as 0xAA55, within a small range around the current read pointer, for example, within the last 256 bytes, byte by byte; if a candidate frame header is found, it is immediately verified whether the data immediately following it meets the minimum frame length, and the BCC check code is calculated; if the check passes, it is considered that the synchronization has been successfully recovered, and the subsequent valid data frame is continued to be parsed; if the check fails, the search is continued or the next idle interruption is waited for.

[0075] Secondary far-end frame skipping advance: if the system detects that the check fails for consecutive N frames (such as N = 3), it is determined that the communication has been seriously out of sync, and local realignment is invalid; at this time, the mechanism actively skips a preset length of invalid data segment, such as 512 bytes or a maximum frame length, after the skipping area, it starts searching for a double-byte frame header from the current position of the buffer again; once a valid frame header is found and verified by BCC, the remote synchronization reconstruction is completed, and data parsing is resumed. The segmented temperature control system is configured with a power mapping table, and the first MCU queries the power mapping table according to the deviation of the current temperature and the target temperature, and outputs the corresponding PWM duty cycle signal to the PWM drive circuit. DMA continuously writes serial bus received data into a fixed size ring buffer, such as 2KB, all search, jump and verification operations are performed in the buffer, without the need to clear or reset the receiving channel; the read and write pointers are managed by software, supporting non-destructive backtracking and jumping, and ensuring data integrity.

[0076] In this embodiment, the first MCU adjusts the switching threshold of the four-stage power control strategy according to the number of erase-write cycles and the power consumption load state.

[0077] In this embodiment, the first MCU obtains the number of erase-write cycles completed by the NAND flash chip to be tested from the second MCU of each test panel through the communication bus, such as 100 times, 500 times, and 3000 times. This value reflects the degree of chip aging - as P / E increases, chip leakage current increases, and self-heating increases. The first MCU monitors the test task type such as full page programming, block erase and read verification, and the number of concurrent channels, and estimates the current total thermal load of the system in combination with the pre-stored power consumption model, for example: the power consumption is high when multiple channels are erased in parallel, and the power consumption is low when a single channel is read. A threshold mapping table or algorithm model is pre-stored in the first MCU, which maps P / E times and power consumption levels to temperature boundaries for four-stage switching, for example: P / E = 0, low load, fast warming-up stage switches to slow approximation stage, and the switching threshold is target temperature -8℃. The first MCU reads the temperature sensor data in real time, compares it with the dynamically calculated threshold, and once the switching condition is met, it immediately adjusts the PWM duty cycle and enters the next stage. The entire process runs continuously throughout the RDT test, achieving on-demand temperature control.

[0078] Multiple test panels run in parallel, and communication anomalies or test interruptions of any test panel are handled locally by the second MCU thereof.

[0079] In the embodiment, the system comprises a communication main control board and a plurality of pluggable test sub-boards, all of which are connected to the same power supply network and communication bus through a unified bottom plate, but are electrically and logically isolated from each other; a first MCU is responsible for issuing test tasks, summarizing results, managing temperature control and other global coordination work, and does not directly participate in real-time erasing control of each sub-board. A second MCU of each test sub-board independently performs NAND Flash erasing, reading, bad block management and other operations. When a serial bus communication timeout or verification failure occurs, the NAND Flash returns an ECC uncorrectable error, the chip does not respond, and the voltage is abnormal or the temperature is out of limit, the second MCU immediately triggers a local exception handling process, retries the current operation up to 3 times; or records error logs to the local storage, cuts off the power supply of the sub-board to protect the chip, reports to the first MCU that "channel X is abnormal", but does not request system reset, enters a safe standby state, and waits for the master control instruction or manual intervention. All exception handling logic runs completely within the test sub-board and does not depend on the master control or other sub-boards; the communication bus uses a non-blocking protocol, such as a serial bus with an ID frame header, and single-channel deadlock will not lower the bus level or block other nodes. The power supply network supplies power to each sub-board through independent LDO or MOS switches, and a short circuit in one path does not affect the remaining channels.

[0080] The first MCU or the second MCU is configured with a dual-backup firmware storage area for performing online firmware update and version rollback operations.

[0081] In the embodiment, the first MCU of the communication main control board and / or the second MCU of each test sub-board divides the internal Flash or externally connected SPI Flash into two independent firmware storage areas, such as Bank A and Bank B, to achieve a safe and reliable firmware management mechanism. When the system is powered on, the Bootloader reads the firmware metadata area, which contains the current active area identifier, version number and verification. According to the identifier, the effective and latest firmware image is loaded. If the current active area verification fails, such as firmware damage caused by write interruption, the Bootloader automatically switches to another backup area for startup. The new firmware is transmitted to the first MCU or the second MCU in packets through the communication bus. After receiving, it is written to the non-active area, for example, the current running Bank A, and the new firmware is written to Bank B. The writing process does not affect the current test task. After the update is completed, the metadata is updated, and the new version is marked as "to be activated", which will take effect next time the system is restarted. If the new firmware fails after startup, such as incompatible communication protocol, out-of-control temperature control, the system can be reset by the watchdog timeout, or actively request rollback by the application layer when detecting a key error. The Bootloader detects the "new version running failure" flag during restart, and automatically restores the use of the original backup area firmware, such as reactivating Bank A. The user can also forcibly specify to roll back to any stored version through instructions.

[0082] The application also provides a NAND Flash reliability demonstration test method, which is applied to a NAND Flash reliability demonstration test device with multiple MCU cooperation, as shown in the figure, and includes the following steps: Figure 4

[0083] Step S100, the second MCU controls the dynamic voltage switching module to output working voltage matching the electrical specifications of the NAND Flash chip to be tested according to the type of the NAND Flash chip to be tested.

[0084] Step S200, the first MCU starts the four-stage power control strategy of the segmented temperature control system.

[0085] Step S300, the test board performs high-temperature erase-write cycle test, and synchronously collects the number of bad blocks, ECC error rate and temperature data.

[0086] Step S400, the high-reliability communication mechanism uploads the test data, and performs hierarchical fault-tolerant recovery operation when frame check fails.

[0087] Step S500, after the test is completed, a reliability evaluation report containing the life prediction result and the temperature fluctuation curve is generated.

[0088] In this embodiment, in step S100, the second MCU controls the dynamic voltage switching module to output working voltage matching the electrical specifications of the NAND Flash chip to be tested according to the type of the NAND Flash chip to be tested, so as to ensure that the chip operates under the electrical conditions defined in the specification book, and avoid overvoltage damage or under-voltage misjudgment, as shown in the figure, including the following steps: Figure 5

[0089] S110, before the test starts, the operator inputs / recognizes the type of the chip to be tested through the upper computer or the code scanning device;

[0090] S120, the information is sent to the second MCU of the corresponding test board through the communication bus of the unified base plate;

[0091] S130, the second MCU queries the voltage-type mapping table pre-stored in it;

[0092] S140, according to the query result, the second MCU controls the MOS switch array or the DC-DC enable pin in the dynamic voltage switching module through the GPIO or I2C signal;

[0093] S150, the module outputs 1.2V, 1.8V or 3.3V working voltage precisely matching the VCC / VCCQ pin of the NAND Flash chip;

[0094] ​​S160, sampling the feedback voltage by the ADC to verify whether it is within ±3% tolerance.

[0095] In step S200, the first MCU starts the four-stage power control strategy of the segmented temperature control system to achieve high-precision temperature control within ±1.5℃ and meet the JEDEC RDT standard, as shown in Figure 6 , including the following steps:

[0096] S210, the first MCU reads the target temperature set by the user, such as 85℃ or 105℃;

[0097] S220, start the temperature sensor to collect the cavity temperature in real time;

[0098] S230, execute the four-stage power control strategy:

[0099] In the fast heating stage, the current temperature is less than the target temperature-8℃, and the PWM duty cycle is set to 90%, full power heating;

[0100] In the slow approaching stage, when the temperature enters the interval [target temperature-8℃, target temperature-2℃], the duty cycle is reduced to 30%, and the heating rate is slowed down;

[0101] In the keep steady stage, the temperature is within the interval [target temperature±2℃], and the duty cycle is dynamically adjusted according to the power mapping table;

[0102] In the slow-stop cooling stage, the test is completed, the heating is turned off, and the fan is intermittently started and stopped to prevent thermal shock.

[0103] S240, if the adaptive mode is enabled, the first MCU also dynamically adjusts the switching threshold of each stage according to the number of erase-write cycles and the current power consumption load.

[0104] In step S300, the test board performs high-temperature erase-write cycle test, synchronously collects the number of bad blocks, ECC error rate and temperature data, obtains the core degradation index reflecting the reliability of the chip, and is used for life modeling, as shown in Figure 7 , including the following steps:

[0105] S310, after the target temperature is stabilized, the second MCU starts the erase-write cycle task, performs "program→read→erase" cycle on the NAND Flash full disk or specified area, and performs bad block scanning once every N cycles, reads the BBM table or tries to write and verify;

[0106] S320, synchronously collect three types of data, which are the number of bad blocks, the ECC error rate and the local temperature, wherein the number of bad blocks is the cumulative number of unreparable blocks, the ECC error rate is the number of bit error corrections when reading each page, and the local temperature is the actually measured temperature near the chip obtained through an NTC or a digital sensor on the test board;

[0107] S330, temporarily store the data in the SRAM or the Flash log area of the second MCU, and wait for uploading.

[0108] In step S400, the test data is uploaded through the high-reliability communication mechanism, and a hierarchical fault-tolerant recovery operation is performed when frame checking fails, so that the communication link is not interrupted and the data is completely uploaded in thousands of hours of testing. Figure 8 As shown in the figure, the following steps are included:

[0109] S410, the second MCU packages the collected data into a structured frame, including a frame header 0xAA55, a payload and a BCC check code;

[0110] S420, send to the first MCU through a serial bus;

[0111] S430, the first MCU or the second MCU itself enables the high-reliability communication mechanism: data is continuously received through a ring DMA buffer, frame boundary recognition is triggered by a serial bus idle interrupt, and if BCC checking fails:

[0112] First-order near-end realignment: search for a frame header in a local buffer and retry parsing;

[0113] Second-order far-end frame skipping: skip 512 bytes and reposition after three consecutive failures;

[0114] S440, after the checking passes, the data is sent to a master processing queue; the failed data does not block subsequent transmission.

[0115] In step S500, a reliability evaluation report containing the life prediction result and the temperature fluctuation curve is generated after the test is completed, providing quantifiable and auditable reliability verification basis for chip manufacturing. As shown in the figure, the following steps are included: Figure 9

[0116] S510, the first MCU summarizes the final data of all test boards: cumulative erase-write times vs. bad block growth curve, first occurrence time of ECC uncorrectable error, and full-temperature record;

[0117] S520, call a life prediction model to estimate the equivalent life of the chip at room temperature;

[0118] S530, draw a temperature fluctuation curve and mark the four-stage switching points and the steady-state interval;

[0119] ​S540, generating a PDF or CSV format report containing chip model, test condition, key indicator table, life prediction conclusion and temperature stability analysis.

[0120] The above merely describes the preferred embodiments of the present application, and is not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process conversion, or direct or indirect application in other related technical fields, based on the content of the present application specification and drawings, are also included in the patent protection scope of the present application.

Claims

1. A multi-MCU collaborative NAND Flash reliability demonstration and testing device, comprising a communication main control board, at least one pluggable test board, a unified baseboard, a dynamic voltage switching module, a high-reliability communication mechanism, and a segmented temperature control system; The communication main control board is equipped with a first MCU, which is connected to the unified baseboard and is used to coordinate the erase and write test tasks of each test board and control the temperature control process. Each of the test boards is equipped with a second MCU and an interface circuit adapted to the NAND Flash chip package. The interface circuit is connected to the NAND Flash chip under test. The second MCU communicates with the first MCU through the unified baseboard. The unified baseboard is equipped with a power network and a communication bus, and the unified baseboard is electrically connected to the communication main control board and all test boards. The test board is equipped with a dynamic voltage switching module controlled by the second MCU, which is used to output a working voltage that is compatible with the electrical specifications of the NAND Flash chip under test. The high-reliability communication mechanism includes a ring DMA buffer, a double-byte frame header, a minimum frame length threshold, and a BCC checksum, and performs a first-level near-end realignment operation and a second-level far-end frame skipping and advancement operation to achieve fault-tolerant recovery. The segmented temperature control system includes a temperature sensor, a heating / heat dissipation unit, and a PWM drive circuit. The first MCU executes a four-stage power control strategy: fast heating, slow approximation, keep steady state, and slow-stop cooling.

2. The NAND Flash reliability demonstration test device with multi-MCU collaboration as described in claim 1, wherein the test board is equipped with signal pin interface circuits adapted to BGA132 or BGA154 packages, and all test boards are connected to the same power network and communication bus through the unified baseboard.

3. The NAND Flash reliability demonstration and testing device with multi-MCU collaboration as described in claim 1, wherein the operating voltage is 1.2V, 1.8V or 3.3V, and the operating voltage is selected and output by the second MCU according to the model of the NAND Flash chip under test.

4. The apparatus as described in claim 1, wherein the communication bus is a serial bus, and the high-reliability communication mechanism triggers frame boundary identification through a serial bus idle interrupt.

5. The multi-MCU collaborative NAND Flash reliability demonstration and testing device as described in claim 1, wherein the high-reliability communication mechanism is configured as follows: Based on the circular DMA buffer, the double-byte frame header is locally searched and the subsequent BCC checksum is verified. After the verification is successful, the valid data frame is parsed to achieve first-level near-end realignment. When multiple consecutive frame verifications fail, the system skips invalid data segments forward based on the circular DMA buffer and repositions the frame start position to achieve secondary remote frame skipping.

6. The NAND Flash reliability demonstration and testing device with multi-MCU collaboration as described in claim 1, wherein the segmented temperature control system is configured with a power mapping table, and the first MCU queries the power mapping table according to the deviation between the current temperature and the target temperature, and outputs the corresponding PWM duty cycle signal to the PWM drive circuit.

7. The NAND Flash reliability demonstration and testing device with multi-MCU collaboration as described in claim 1, wherein the first MCU adjusts the switching threshold of the four-stage power control strategy according to the number of erase / write cycles and power load status.

8. The NAND Flash reliability demonstration test device with multi-MCU collaboration as described in claim 1, wherein multiple test boards operate in parallel, and any communication abnormality or test interruption of any test board is handled locally by its second MCU.

9. The NAND Flash reliability demonstration and testing device with multi-MCU collaboration as described in claim 1, wherein the first MCU or the second MCU is configured with a dual backup firmware storage area, the dual backup firmware storage area being used to perform online firmware updates and version rollback operations.

10. A NAND Flash reliability demonstration test method, applied to a multi-MCU collaborative NAND Flash reliability demonstration test apparatus as described in any one of claims 1 to 9, comprising the following steps: Step S100: The second MCU controls the dynamic voltage switching module to output a working voltage that matches the electrical specifications of the NAND Flash chip under test according to the model of the NAND Flash chip under test; Step S200: The first MCU starts the four-stage power control strategy of the segmented temperature control system; Step S300: The test board performs a high-temperature erase / write cycle test, and simultaneously collects data on the number of bad blocks, ECC error rate, and temperature. Step S400: The high-reliability communication mechanism uploads test data and performs a graded fault-tolerant recovery operation when frame verification fails; Step S500: After the test is completed, a reliability assessment report containing life prediction results and temperature fluctuation curves is generated.

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