Equalization circuit

Abstract

The invention provides an equalization circuit which at least comprises a first transistor which comprises a first source region, a first grid electrode and a first drain region; the first transistor comprises a first source region, a first grid electrode and a first drain region, the second transistor comprises a second source region, a second grid electrode and a second drain region, the first grid electrode and the second grid electrode extend in the first direction and are staggered in the second direction, and the first drain region and the second drain region are located between the first grid electrode and the second grid electrode and are used for receiving balanced voltage; the first source region and the second source region are at least partially staggered in the first direction; the second direction is perpendicular to the first direction; the first type of contact holes comprise a first contact hole and a second contact hole, the first contact hole is formed in the first source region and connected with a first conductive wire, the second contact hole is formed in the second source region and connected with a second conductive wire, the first type of contact holes are formed in the first direction, and the second type of contact holes are formed in the second direction; the first conductive wire and the second conductive wire extend along the second direction and are at least partially adjacent.

Description

Technical Field

[0001] This application relates to the semiconductor field, and in particular to an equalization circuit. Background Technology

[0002] With the continuous development of science and technology, the size of integrated circuits is becoming smaller and smaller. In many integrated circuits, equalization circuits are often an essential component. These circuits are used to level the potentials of different data lines, or in other words, to adjust the potentials of different data lines to a balanced voltage level, allowing the data lines to return to their state before receiving the data signal. The area of ​​the equalization circuit has a significant impact on the overall area of ​​the integrated circuit; therefore, reducing the area of ​​the equalization circuit is one of the most pressing problems to be solved. Summary of the Invention

[0003] This application provides an equalization circuit that at least helps to reduce the overall height of the equalization circuit.

[0004] According to some embodiments of this application, one aspect of this application provides an equalization circuit, including: a first transistor, the first transistor including a first source region, a first gate and a first drain region; a second transistor, the second transistor including a second source region, a second gate and a second drain region, the first gate and the second gate both extending along a first direction and offset in a second direction, the first drain region and the second drain region being located between the first gate and the second gate and used to receive an equalization voltage, the first source region and the second source region being at least partially offset in the first direction; the second direction being perpendicular to the first direction; and a first type of contact hole, including a first contact hole and a second contact hole, the first contact hole being disposed on the first source region and connected to a first conductive line, the second contact hole being disposed on the second source region and connected to a second conductive line, the first type of contact hole being disposed along the first direction, the first conductive line and the second conductive line both extending along the second direction and at least partially adjacent to each other.

[0005] In some embodiments, the first source region and the first drain region are symmetrically disposed on opposite sides of the first gate, and the second source region and the second drain region are symmetrically disposed on opposite sides of the second gate.

[0006] In some embodiments, there is an overlapping region between the first leak region and the second leak region.

[0007] In some embodiments, the equalization circuit further includes: a third transistor and a fourth transistor, the relative positional relationship between the fourth transistor and the third transistor being the same as the relative positional relationship between the second transistor and the first transistor, the third transistor and the fourth transistor being located on one side of the first transistor and the second transistor in the first direction; the third transistor comprising a third drain region and a third source region, the third source region being used to connect to a third conductive line, the fourth transistor comprising a fourth drain region and a fourth source region, the fourth source region being connected to a fourth conductive line; and a second type of contact hole, comprising at least one contact hole, the second type of contact hole being used to provide the equalization voltage to the first drain region, the second drain region, the third drain region and the fourth drain region, the second type of contact hole being disposed along the first direction or along the second direction.

[0008] In some embodiments, there is a first overlapping region between the first leak region and the second leak region, a second overlapping region between the second leak region and the third leak region, and a third overlapping region between the third leak region and the fourth leak region.

[0009] In some embodiments, the second overlapping region is provided with the second type of contact hole, while the first overlapping region and the third overlapping region are not provided with the second type of contact hole, and the second type of contact hole is provided along the first direction.

[0010] In some embodiments, the first overlapping region, the second overlapping region, and the third overlapping region are all provided with the second type of contact hole, and the second type of contact hole is provided along the second direction.

[0011] In some embodiments, the second type of contact hole includes a fifth contact hole disposed in the second overlapping region; wherein, in the first direction, the second contact hole is located between the first contact hole and the fifth contact hole, and the second contact hole is equidistant from the first contact hole and the fifth contact hole; or, in the first direction, the side of the fifth contact hole facing the second contact hole is aligned with the side of the second contact hole facing the fifth contact hole.

[0012] In some embodiments, the conductive wire connected to the first type of contact hole is a first type of conductive wire. In the first direction, the first type of contact hole has a first contact edge and a second contact edge opposite to each other. The first type of conductive wire has a first conductive edge near the first contact edge and a second conductive edge near the second contact edge. There is a first distance between the first contact edge and the first conductive edge, and a second distance between the second contact edge and the second conductive edge. The first distance is equal to the second distance.

[0013] In some embodiments, in the second direction, one side of the second drain region has a first isolation structure, the first isolation structure having doped regions on both sides in the first direction, and the centerline of the second source region being aligned with the centerline of the first isolation structure. Attached Figure Description

[0014] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0015] Figures 1 to 7 A schematic diagram of the equalization circuit provided in an embodiment of this application. Detailed Implementation

[0016] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0017] Figures 1 to 7 A schematic diagram of the equalization circuit provided in an embodiment of this application.

[0018] refer to Figure 1 The equalization circuit includes: a first transistor TR1, which includes a first source region S1, a first gate GT1, and a first drain region D1; a second transistor TR2, which includes a second source region S2, a second gate GT2, and a second drain region D2. The first gate GT1 and the second gate GT2 both extend along a first direction X and are offset in a second direction Y. The first drain region D1 and the second drain region D2 are located between the first gate GT1 and the second gate GT2 and are used to receive the equalization voltage. The first source region S1 and the second source region S2 are at least partially offset in the first direction X. The second direction Y is perpendicular to the first direction X. A first type of contact hole 11 includes a first contact hole CT1 and a second contact hole CT2. The first contact hole CT1 is disposed on the first source region S1 and connected to a first conductive line 121. The second contact hole CT2 is disposed on the second source region S2 and connected to a second conductive line 122. The first type of contact hole 11 is disposed along the first direction X. The first conductive line 121 and the second conductive line 122 both extend along the second direction Y and are at least partially adjacent.

[0019] In this embodiment, by controlling the first source region S1 and the second source region S2 to be at least partially misaligned in the first direction X, it is beneficial to expand the setting space of the first contact hole CT1 and the second contact hole CT2 in the first direction X. This allows the first conductive line 121 and the second conductive line 122 to avoid excessive bending due to design rules when the first type of contact hole 11 is set along the first direction X. At the same time, it ensures that each conductive line can better cover the corresponding contact hole, avoiding the conductive line from failing to make sufficient contact with the contact hole due to manufacturing defects. In this way, it can ensure that each conductive line has a small contact resistance with the corresponding contact hole, and reduce the equivalent length and equivalent resistance of the conductive line. Furthermore, by controlling the first type of contact hole to be set along the first direction, the height of the equalization circuit in the second direction is reduced, which in turn helps to reduce the total height of the integrated circuit containing the equalization circuit in the second direction Y.

[0020] If the first source region S1 and the second source region S2 are not misaligned in the first direction X, the setting space of the first contact hole CT1 and the second contact hole CT2 in the first direction X is the first width W1. In the case of partial misalignment, the setting space of the first contact hole CT1 and the second contact hole CT2 in the first direction X is the second width W2, and the second width W2 is greater than the first width W1.

[0021] Furthermore, the aforementioned design rule refers to the requirement that the spacing between adjacent conductive lines must be greater than a preset value when laying out conductive lines. If the space for the first contact hole and the second contact hole in the first direction is narrow and the spacing between them is less than the spacing specified in the design rule, then the first conductive line and the second conductive line must extend by a certain dimension in opposite directions, resulting in an increase in the length of the first conductive line and the second conductive line and an increase in resistance.

[0022] Furthermore, when setting the first and second conductive lines, if the space between the first and second contact holes in the first direction is narrow, the design spacing or layout spacing between the edge of the first conductive line and the edge of the first contact hole in the first direction will be narrow. The same applies to the second conductive line and the second contact hole. When fabricating the first contact hole and the first conductive line according to the design spacing or layout spacing, due to defects such as photolithography (e.g., photolithography proximity effect), the corner of the first conductive line may be missing, or the fabrication width of the first conductive line in the first direction may be smaller than the design width. This results in the fabricated first conductive line not completely covering the first contact hole, thus increasing the contact resistance.

[0023] In this embodiment, by setting the first type of contact hole along the first direction (or extending along the first direction), the height H1 of the first type of contact hole in the second direction will be reduced compared to the second contact hole being set along the second direction. Simultaneously, there is no need to extend the width W1 of the first and second source regions in the first direction. This helps to reduce the overall height of the equalization circuit in the second direction Y. It should be noted that this application does not limit the shape of the first type of contact hole; the first type of contact hole can be rectangular or other shapes, such as those with curved sides. Setting the first type of contact hole along the first direction in this application refers to controlling the extension of the edge with the longer linear extension length in the first direction.

[0024] In this embodiment of the application, "at least partially adjacent to the first conductive line and the second conductive line" means that the partial structures of the first conductive line and the partial structures of the second conductive line are adjacent in projection along the first direction X and coincide in projection along the second direction Y.

[0025] The embodiments of this application will be described in more detail below with reference to the accompanying drawings.

[0026] The equalization circuit provided in this application embodiment is limited to adjusting the voltage of the first conductive line 121 to an equalization voltage through the first transistor TR1 and adjusting the voltage of the second conductive line 122 to an equalization voltage through the second transistor TR2. It does not limit the actual application scenario of the equalization circuit, the connection objects of the first conductive line 121 and the second conductive line 122, the relative relationship of the connection objects of the first conductive line 121 and the second conductive line 122, or the conduction time of the first transistor TR1 and the second transistor TR2.

[0027] Regarding application scenarios, equalization circuits can be applied to different types of circuits such as memory, sensors, or processors. Furthermore, equalization circuits can be used to adjust the voltage of data transmission paths or control signal transmission paths. In memory, the smallest storage cell is connected to the memory port via bit lines, local data lines, global data lines, and a data bus to read or write data. Specifically, bit lines are connected to local data lines via column selectors, local data lines are connected to global data lines via read / write conversion circuits, and global data lines are connected to the data bus via driver circuits.

[0028] Regarding the connection objects of the first conductive line 121 and the second conductive line 122, taking the data transmission path of the equalization circuit applied to the memory as an example, the first conductive line 121 and the second conductive line 122 can be used to connect any one of the bit lines, local data lines, global data lines or data buses.

[0029] Regarding the relative relationship between the connection objects of the first conductive line 121 and the second conductive line 122, taking the example that both the first conductive line 121 and the second conductive line 122 are connected to bit lines, the first conductive line 121 can be used to connect the first bit line, and the second conductive line 122 can be used to connect the second bit line parallel to the first bit line, that is, the connection objects of the first conductive line 121 and the second conductive line 122 are in a parallel relationship; or, the first conductive line 121 is used to connect the first bit line, and the second conductive line 122 is used to connect the first complementary bit line that is mutually referenced with the first bit line, that is, the connection objects of the first conductive line 121 and the second conductive line 122 are mutually referenced; or, the first conductive line 121 and the second conductive line 122 are connected to the same bit line.

[0030] Regarding the conduction time of the first transistor TR1 and the second transistor TR2, the first transistor TR1 and the second transistor TR2 can conduct simultaneously or at different times. It should be noted that regardless of whether the connection between the first conductive line 121 and the second conductive line 122 is parallel or mutually referenced, the first transistor TR1 and the second transistor TR2 can conduct simultaneously.

[0031] It should be noted that the embodiments of this application do not limit the connection method between the first conductive line 121 and the second conductive line 122 and the corresponding connected object. The connection method can be either a direct connection or an indirect connection. The difference between direct and indirect connections lies in whether a switch transistor based on a control signal is provided between the first conductive line 121 / second conductive line 122 and the connected object. If a switch transistor is provided and the switch transistor is in the off state for part of the time, it is considered an indirect connection.

[0032] In some embodiments, the memory includes a sensing amplifier connected between mutually referenced bit lines and complementary bit lines, also referred to as bit line pairs. The sensing amplifier amplifies the voltage difference between corresponding bit line pairs. The sensing amplifier can be indirectly connected to the bit line pairs via isolation transistors or directly connected to them. The first transistor TR1 and / or the second transistor TR2 can be either discretely disposed with the sensing amplifier or integrated as part of it.

[0033] In one exemplary embodiment, the equalization circuit is applied to the data transmission path of the memory. The first conductive line 121 and the second conductive line 122 are used to connect different parallel bit lines, which belong to different bit line pairs. The first transistor TR1 and the second transistor TR2 belong to different sense amplifiers. The equalization voltage is the pre-charge voltage. The following example uses a sense amplifier containing the first transistor TR1:

[0034] refer to Figure 2The sensing amplifier includes a first P-type transistor M1, a second P-type transistor M2, a first N-type transistor M7, a second N-type transistor M8, a first isolation transistor M3, a second isolation transistor M4, a first bias cancellation transistor M5, a second bias cancellation transistor M6, and a first transistor TR1. The first terminals of the first P-type transistor M1 and the second P-type transistor M2 are connected to a first voltage node PCS. The second terminal of the first P-type transistor M1 is connected to the first terminal of the first N-type transistor M7. The second terminal of the second P-type transistor M2 is connected to the first terminal of the second N-type transistor M8. The second terminals of the first N-type transistor M7 and the second N-type transistor M8 are connected to a second voltage node NCS. The second terminal of the first P-type transistor M1 serves as a second node S2, and the second terminal of the second P-type transistor M2 serves as a first node S1. The first node S1 is connected to the first isolation transistor M6. The first end of transistor M3 is connected to the second end of the first isolation transistor M3, the second end of the first bias cancellation transistor M5, and the gate of the first N-type amplifier M7 are connected to the bit line Bla. The first end of the first bias cancellation transistor M5 is connected to the second node S2. The second node S2 is connected to the first end of the second isolation transistor M4. The second end of the second isolation transistor M4, the second end of the second bias cancellation transistor M6, and the gate of the second N-type amplifier M8 are connected to the complementary bit line Blab. The first end of the second bias cancellation transistor M6 and the first end of the first transistor TR1 are connected to the first node S1. The first isolation transistors M3 and M4 are turned on based on the isolation signal ISO. The first bias cancellation transistors M5 and M6 are turned on based on the bias cancellation signal Oc. The first transistor TR1 is turned on based on the precharge signal PreEq and transmits the precharge voltage Va2d to the first node S1. Among them, the first P-type amplifier M1 and the second P-type amplifier M2 constitute a P-type amplifier, and the first N-type amplifier M7 and the second N-type amplifier M8 constitute an N-type amplifier.

[0035] exist Figure 2 In the illustrated embodiment, the sensing amplifier includes a first transistor TR1. The first transistor TR1 transmits the pre-charge voltage Va2d (i.e., the equalization voltage) to the first node S1 during the pre-charge phase characterized by the pre-charge signal PreEq. The source region of the first transistor TR1 is indirectly connected to the bit line Bla through a first isolation transistor M3. In fact, after the voltage at the first node S1 reaches the equalization voltage, the voltage at the second node S2 will also be equal to the equalization voltage, and the voltages of both the bit line Bla and the complementary bit line Blab will be adjusted to the equalization voltage. That is, the first transistor TR1 corresponds to one bit line pair, and the first transistor TR1 and the second transistor TR2 correspond to different bit line pairs.

[0036] In other embodiments, the first bias cancellation transistor M5 and the second bias cancellation transistor M6 may be omitted from the sensing amplifier, and the corresponding connections may be deleted. Alternatively, the first isolation transistor M3 and the second isolation transistor M4 may be omitted and replaced with wires. It is understood that the sensing amplifier can have various structures. Figure 2 The example is only for illustration purposes. The first conductive line is used to connect the internal nodes (first node S1 or second node S2) of the first transistor TR1 sensing amplifier. The internal nodes may have amplified voltage or equalized voltage, and the bit line pair receives the amplified voltage or equalized voltage through the internal amplification node. This application does not limit the specific structure of the sensing amplifier.

[0037] exist Figure 1 In the illustrated embodiment, the first source region S1 and the second source region S2 are partially misaligned in the first direction X, and the first drain region D1 and the second drain region D2 partially overlap in the second direction Y. It can be understood that the partial misalignment of the first source region S1 and the second source region S2 in the first direction X indicates that the first source region S1 and the second source region S2 partially overlap in the first direction X, and the sum of the overlapping size and the misalignment size is equal to the width W1 of the first source region S1 in the first direction X. When the first source region S1 and the second source region S2 are completely misaligned in the first direction X, the first source region S1 and the second source region S2 do not overlap in the first direction X. Similarly, the partial overlap of the first drain region D1 and the second drain region D2 in the second direction Y indicates that the first drain region D1 and the second drain region D2 are partially misaligned in the second direction Y.

[0038] In another embodiment, the first source region and the second source region are partially misaligned in the first direction, and the first drain region and the second drain region are completely misaligned in the second direction. It is understood that complete misalignment includes both no gap (equivalent to boundary overlap) and gaps in the second direction. When there is no gap in the second direction, the first drain region and the second drain region remain electrically connected; when there is a gap in the second direction, the first drain region and the second drain region can be electrically connected by setting an intermediate active region. (See reference...) Figure 3 The first drain area D1 and the second drain area D2 are spaced apart in the second direction Y. A first intermediate active area A1 is provided between the first drain area D1 and the second drain area D2. The first intermediate active area A1 is used to electrically connect the first drain area D1 and the second drain area D2 so that the first drain area D1 and the second drain area D2 can share a contact hole for receiving equalization voltage.

[0039] In some other embodiments, the first source region and the second source region are completely misaligned in the first direction, and the first drain region and the second drain region partially overlap in the second direction. (See reference...) Figure 4The first drain region D1 and the second drain region D2 are spaced apart in the first direction X. A second intermediate active region A2 is provided between the first drain region D1 and the second drain region D2. The second intermediate active region A2 is used to electrically connect the first drain region D1 and the second drain region D2, so that the first drain region D1 and the second drain region D2 can share a contact hole for receiving equalization voltage. It is understood that in some embodiments, the first source region and the second source region may be completely misaligned in the first direction, and the first drain region and the second drain region may be completely misaligned in the second direction, with the first drain region and the second drain region electrically connected by the intermediate active region.

[0040] In some embodiments, further references Figure 1 The first source region S1 and the first drain region D1 are symmetrically disposed on opposite sides of the first gate GT1, and the second source region S2 and the second drain region D2 are symmetrically disposed on opposite sides of the second gate GT2. In other words, the first source region S1 and the first drain region D1 have the same shape and size, and the second source region S2 and the second drain region D2 have the same shape and size. The shapes of the first source region S1 and the second source region S2 can be set as needed.

[0041] In some embodiments, further references Figure 1 There is an overlapping region A3 between the first drain region D1 and the second drain region D2. The overlapping region A3 belongs to both the first drain region D1 and the second drain region D2. This is beneficial for further compressing the size of the equalization circuit in the first direction X and the second direction Y.

[0042] In some embodiments, the overlapping region A3 can be square or rectangular, and the width of the overlapping region A3 in the first direction X is greater than or equal to the width of the first contact hole CT1 in the first direction X. This is advantageous because it ensures that when a contact hole of the same size as the first contact hole CT1 is provided in the overlapping region A3, the contact hole can be completely located within the overlapping region.

[0043] In some embodiments, the first source region S1 includes a first portion and a second portion. The first portion is located between the second portion and the first gate GT1, or in other words, the first portion is located between the second portion and the first gate GT1 in a third direction. The width of the first portion in the first direction X is smaller than the width of the second portion in the first direction X. The third direction is perpendicular to the first direction and the second direction.

[0044] In some embodiments, reference Figure 5The equalization circuit further includes: a third transistor TR3 and a fourth transistor TR4, the relative positional relationship between the fourth transistor TR4 and the third transistor TR3 is the same as the relative positional relationship between the second transistor TR2 and the first transistor TR1, the third transistor TR3 and the fourth transistor TR4 are located on one side of the first transistor TR1 and the second transistor TR2 in the first direction X; the third transistor TR3 includes a third drain region D3 and a third source region S3, the third source region S3 is connected to a third conductive line, the fourth transistor TR4 includes a fourth drain region D4 and a fourth source region S4, the fourth source region S4 is connected to a fourth conductive line; a second type of contact hole (not shown), including at least one contact hole, the second type of contact hole is used to provide equalization voltage for the first drain region D1, the second drain region D2, the third drain region D3 and the fourth drain region D4, the second type of contact hole is arranged along the first direction X or along the second direction Y.

[0045] The relative positional relationship between the fourth transistor TR4 and the third transistor TR3 is the same as that between the second transistor TR2 and the first transistor TR1, meaning that the third gate GT3 in the third transistor TR3 and the fourth gate GT4 in the fourth transistor TR4 both extend along the first direction X and are offset in the second direction Y. The fourth drain region D4 and the third drain region D3 are located between the third gate GT3 and the fourth gate GT4 and are used to receive the equalization voltage. The third source region S3 and the fourth source region S4 are at least partially offset in the first direction X. Furthermore, the first type of contact hole also includes a third contact hole CT3 and a fourth contact hole CT4. The third contact hole CT3 is disposed in the third source region S3 and connected to the third conductive line (not shown), and the fourth contact hole CT4 is disposed in the fourth source region S4 and connected to the fourth conductive line (not shown).

[0046] Similarly, the relative relationship between the connection objects of the third and fourth conductive lines can be the same as the relative relationship between the connection objects of the second and first conductive lines. In one embodiment, the connection object of the first conductive line is the first bit line, the connection object of the second conductive line is the second bit line, and the connection objects of the third conductive line and the fourth bit line are the third and fourth bit lines parallel to the first and second bit lines. The first, second, third, and fourth bit lines each have a corresponding reference bit line, that is, they belong to different bit line pairs.

[0047] exist Figure 1 In the illustrated embodiment, the third transistor TR3 and the first transistor TR1 are disposed along the first direction X, and the fourth transistor TR4 and the second transistor TR2 are disposed along the first direction X. It should be noted that the first direction X can be either horizontal or oblique. This application does not impose any limitation on the first direction X, but the different features along the first direction X should be parallel, such as the second gate GT2 extending along the first direction X and the third gate GT3 extending along the first direction X.

[0048] This application does not limit the electrical connection relationship between the first drain region D1 and the fourth drain region D4. In different embodiments, the electrical connection methods between the first drain region D1 and the fourth drain region D4 include at least the following three:

[0049] First, the second drain region D2 is physically connected to both the first drain region D1 and the third drain region D3. The third drain region D3 is physically connected to both the second drain region D2 and the fourth drain region D4. The first drain region D1 and the third drain region D3 can be physically connected or electrically connected only through the second drain region D2. Similarly, the second drain region D2 and the fourth drain region D4 can be physically connected or electrically connected only through the third drain region D3. In this case, it can be considered that the first transistor TR1 to the fourth transistor TR4 together constitute a single equalization unit. It is understandable that the physical connection between different drain regions necessarily results in an electrical connection.

[0050] Second, the first leakage area D1 is physically connected to the second leakage area D2, the third leakage area D3 is physically connected to the fourth leakage area D4, and the second leakage area D2 and the third leakage area D3 are not physically connected. The first leakage area D1 and the third leakage area D3 may or may not be electrically connected, as may the second leakage area D2 and the fourth leakage area D4. When the first leakage area D1 is electrically connected to both the second and third leakage areas D2 and D3 respectively, and the fourth leakage area D4 is electrically connected to both the second and third leakage areas D2 and D3 respectively, and the first leakage area D1 and the fourth leakage area D4 are not physically connected, and the second leakage area D2 and the third leakage area D3 are not physically connected, the first leakage area D1 to the fourth leakage area D4 form a ring-shaped electrical connection. When there is no electrical connection between the first drain region D1 and the third drain region D3, and no electrical connection between the second drain region D2 and the fourth drain region D4, it can be considered that the first transistor TR1 and the second transistor TR2 together constitute one equalization unit, and the third transistor TR3 and the fourth transistor TR4 together constitute another equalization unit.

[0051] Third: The first leakage zone D1 to the fourth leakage zone D4 are not electrically connected to each other.

[0052] It is understandable that "no electrical connection" means neither a physical connection nor an electrical connection through other conductive media. When making a physical connection, it can be achieved either through direct contact or overlap between different drain regions, or through an intermediate active region (including...). Figure 3 and Figure 4 (As shown in the embodiment), it can also be physically connected through a conductive layer adjacent to the active region.

[0053] In the first electrical connection method and the second connection method of ring electrical connection, since the first drain area D1 to the fourth drain area D4 are electrically connected to each other, one or more second type contact holes can be shared to receive equal voltage, without the need for each drain area to have an independent second type contact hole to receive equal voltage.

[0054] exist Figure 5 In the illustrated embodiment, a first overlapping region A4 exists between the first drain area D1 and the second drain area D2, a second overlapping region A5 exists between the second drain area D2 and the third drain area D3, and a third overlapping region A6 exists between the third drain area D3 and the fourth drain area D4. That is, the second drain area D2 is physically connected to the first drain area D1 and the third drain area D3 in an overlapping manner, and the third drain area D3 is physically connected to the second drain area D2 and the fourth drain area D4 in an overlapping manner. The first drain area D1 and the third drain area D3 are isolated by a first isolation structure STI1 and are electrically connected only through the second drain area D2. The second drain area D2 and the fourth drain area D4 are isolated by a second isolation structure STI2 and are electrically connected only through the third drain area D3.

[0055] Furthermore, in Figure 5 In the illustrated embodiment, the second overlapping region A5 is provided with a fifth contact hole CT5, which is a type of second-class contact hole. The first overlapping region A4 and the third overlapping region A6 are not provided with type-second contact holes. Type-second contact holes are provided along the first direction X. Since the first drain region D1 to the fourth drain region D4 are all used to receive equalization voltage, only type-second contact holes for receiving equalization voltage can be provided. Therefore, "the first overlapping region A4 and the third overlapping region A6 are not provided with type-second contact holes" means that no contact holes are provided on the first overlapping region A4 and the third overlapping region A6, not that other types of contact holes can be provided. By sharing the fifth contact hole CT5, it is beneficial to reduce the routing area occupied by the second type of conductive wires connected to the second type of contact hole. While ensuring the routing margin of the first type of conductive wires connected to the first type of contact hole, it avoids the situation where the first type of conductive wire is located between two second type of contact holes arranged along the first direction. In this case, the extension direction of some second type of conductive wires used to connect different second type of contact holes is perpendicular to the extension direction of the first type of conductive wire. Some second type of conductive wires need to avoid conflict with the first type of conductive wires by using jumpers. This makes the arrangement of the first type of conductive wires and the second type of conductive wires simpler and smoother. At the same time, setting the second type of contact hole along the first direction X helps to shorten the distance between the second type of contact hole and different drain areas, providing power supply capability for the second type of contact hole.

[0056] Conductive wires connected to type 1 contact holes are called type 1 conductive wires, and conductive wires connected to type 2 contact holes are called type 2 conductive wires. A jumper wire refers to a wire that, when different conductive wires collide on the same conductive layer, is connected to another metal layer, skipping the collision area, and then reconnected to the current conductive layer.

[0057] In some embodiments, a fifth contact hole is provided in the second overlapping region. The fifth contact hole is a second type of contact hole, while the first and third overlapping regions do not have second type of contact holes. The second type of contact holes are arranged along the second direction. This allows for a further reduction in the width of the second type of conductive wire connected to the fifth contact hole in the first direction while meeting the design spacing requirements. It also further increases the routing margin of the first type of conductive wire, enabling the first type of conductive wires corresponding to the second and third contact holes adjacent to the fifth contact hole in the first direction to become straighter and achieve better electrical performance.

[0058] In some other embodiments, the first overlapping region, the second overlapping region, and the third overlapping region are all provided with second type contact holes, which are arranged along a second direction. By providing multiple second type contact holes, it is beneficial to provide power supply capability for the second type contact holes, while improving damage resistance.

[0059] exist Figure 5 In the illustrated embodiment, in the first direction X, the second contact hole CT2 is located between the first contact hole CT1 and the fifth contact hole CT5. Alternatively, the orthographic projection of the second contact hole CT2 along the second direction Y lies between the orthographic projections of the first contact hole CT1 and the fifth contact hole CT5 along the second direction Y. The side of the fifth contact hole CT5 facing the second contact hole CT2 is aligned with the side of the second contact hole CT2 facing the fifth contact hole CT5. In other words, the side of the fifth contact hole CT5 facing the first drain region D1 is aligned with the side of the second contact hole CT2 facing the fourth source region S4. That is, these two sides are in the same position in the first direction X. This helps ensure that the first type of conductive lines corresponding to the first contact hole CT1 and the fourth contact hole CT4 have a larger routing space.

[0060] Similarly, in the first direction X, the orthographic projection of the third contact hole CT3 along the second direction Y is located between the orthographic projections of the fourth contact hole CT4 and the fifth contact hole CT5 along the second direction Y, and the side of the fifth contact hole CT5 facing the third contact hole CT3 is aligned with the side of the third contact hole CT3 facing the fifth contact hole CT5.

[0061] In other embodiments, in the first direction, the second contact hole is located between the first contact hole and the fifth contact hole; or, in other words, the orthographic projection of the second contact hole along the second direction lies between the orthographic projections of the first and fifth contact holes along the second direction, and the second contact hole is equidistant from both the first and fifth contact holes. "Distance" refers to the distance in the first direction, and the two endpoints used to calculate the distance can be the adjacent sides of the two contact holes in the first direction, or the center point of the two contact holes. This helps to ensure a more uniform distribution of the first and second types of conductive wires.

[0062] Similarly, in the first direction, the third contact hole is located between the fourth and fifth contact holes, or in other words, the orthographic projection of the third contact hole along the second direction is located between the orthographic projections of the fourth and fifth contact holes along the second direction, and the third contact hole is at the same distance from the fourth and fifth contact holes.

[0063] In some embodiments, the third transistor includes a third gate, the fourth transistor includes a fourth gate, the third gate and the first gate are positioned in the same direction in a second direction and are integrally formed, and the fourth gate and the second gate are positioned in the same direction in a second direction and are integrally formed. (Reference) Figure 5 The third transistor TR3 includes a third gate GT3, and the fourth transistor TR4 includes a fourth gate GT4. The third gate GT3 and the first gate GT1 are located at the same position in the second direction Y, and the third gate GT3 and the first gate GT1 are integrally formed. The fourth gate GT4 and the second gate GT2 are located at the same position in the second direction Y, and the fourth gate GT4 and the second gate GT2 are integrally formed. Integral forming means that they are formed in the same fabrication process.

[0064] In some embodiments, in the second direction, one side of the second drain region has a first isolation structure, the first isolation structure has doped regions on both sides in the first direction, and the centerline of the second source region is aligned with the centerline of the first isolation structure. (Reference) Figure 5 In the second direction Y, the second drain region D2 has a first isolation structure STI1 on one side, and the first isolation structure STI1 has doped regions on both sides in the first direction X. The center line of the second source region S2 is aligned with the center line of the first isolation structure STI1. Correspondingly, the third drain region D3 has a second isolation structure STI2 on one side, and the second isolation structure STI2 has doped regions on both sides in the first direction X. The center line of the third source region S3 is aligned with the center line of the second isolation structure STI2.

[0065] It is understood that the doped regions on both sides of the isolation structure include the source or drain regions mentioned in this paper. The centerline of the source region and the centerline of the isolation structure both extend along the second direction Y, and centerline alignment can also be considered as centerline coincidence.

[0066] In some embodiments, at least two equalization units can be provided in the first direction, and the drain regions of different equalization units can be either electrically connected or electrically isolated. Figure 6 In the illustrated embodiment, the equalization circuit includes at least three equalization units in the first direction X. The first equalization unit includes a first transistor TR1 to a fourth transistor TR4. The second equalization unit includes at least a fifth transistor TR5, and the fifth transistor TR5 is located in the same position as the first transistor TR1 in the first equalization unit. The third equalization unit includes at least a sixth transistor TR6, and the sixth transistor TR6 is located in the same position as the fourth transistor TR4 in the first equalization unit.

[0067] exist Figure 6 In the illustrated embodiment, the drain regions of different equalization units are electrically connected. There is an overlapping region between the fourth drain region D4 of the fourth transistor TR4 and the fifth drain region D5 of the fifth transistor TR5, and an overlapping region between the first drain region D1 of the first transistor TR1 and the sixth drain region D6 of the sixth transistor TR6. It can be understood that when different equalization units... Figure 6 When the method shown is repeated in the first direction X, each drain region has an isolation structure on one side of the second direction Y. Except for the isolation structure at the edge, the two sides of each isolation structure are doped regions. The center line of the source region, which belongs to the same transistor as the drain region, is aligned with the center line of the corresponding isolation structure.

[0068] The isolation structure with a centerline discussed in this article actually refers to a local isolation structure located between different doped regions. The doped regions discussed in this article include the source and drain regions in each transistor.

[0069] Figure 6 The diagram also illustrates all the first-type conductive wires connected to the first contact hole to the fourth contact hole, and the second-type conductive wires connected to the fifth contact hole. The first contact hole is connected to the first conductive wire 221, the second contact hole is connected to the second conductive wire 222, the third contact hole is connected to the third conductive wire 223, the fourth contact hole is connected to the fourth conductive wire 224, and the fifth contact hole is connected to the fifth conductive wire 225. The first conductive wires 221 to the fourth conductive wire 224 belong to the first-type conductive wires, and the fifth conductive wire 225 belongs to the second-type conductive wires.

[0070] In some embodiments, in a first direction, a first type of contact hole has opposing first and second contact edges, and a first type of conductive wire has a first conductive edge near the first contact edge and a second conductive edge near the second contact edge. In the first direction, there is a first spacing between the first contact edge and the first conductive edge, and a second spacing between the second contact edge and the second conductive edge, wherein the first spacing and the second spacing are equal. It is understood that the first conductive edge and the second conductive edge are opposing edges of the first type of conductive wire in the first direction.

[0071] refer to Figure 7 , Figure 7 for Figure 6 Enlarged schematic diagram of local structure K1. (Reference) Figure 7 Taking the first contact hole CT1 and the first conductive line 221 as an example, the first contact hole CT1 has a first contact edge Y12 and a second contact edge Y22 opposite to each other in the first direction X. The first conductive line 221 has a first conductive edge Y11 near the first contact edge Y12 and a second conductive edge Y21 near the second contact edge Y22. There is a first distance L1 between the first contact edge Y12 and the first conductive edge Y11, and there is a second distance L2 between the second contact edge Y22 and the second conductive edge Y21. The first distance L1 and the second distance L2 are equal.

[0072] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. An equalization circuit, characterized by, The application relates to a transistor structure, comprising: a first transistor comprising a first source region, a first gate and a first drain region; a second transistor comprising a second source region, a second gate and a second drain region, the first gate and the second gate extending in a first direction and being staggered in a second direction, the first drain region and the second drain region being between the first gate and the second gate and used for receiving an equalization voltage, the first source region and the second source region being at least partially staggered in the first direction, the second direction being perpendicular to the first direction; a first type of contact hole comprising a first contact hole and a second contact hole, the first contact hole being arranged on the first source region and connected with a first conductive line, the second contact hole being arranged on the second source region and connected with a second conductive line, the first type of contact hole being arranged in the first direction, the first conductive line and the second conductive line extending in the second direction and being at least partially adjacent.

2. The equalization circuit of claim 1, wherein, The first source region and the first drain region are symmetrically arranged on opposite sides of the first gate, and the second source region and the second drain region are symmetrically arranged on opposite sides of the second gate.

3. The equalization circuit of claim 1, wherein, The first drain region and the second drain region have an overlapping region.

4. The equalization circuit of claim 1, wherein, The application further comprises a third transistor and a fourth transistor, the relative position relationship of the fourth transistor and the third transistor being the same as that of the second transistor and the first transistor, the third transistor and the fourth transistor being located on one side of the first transistor and the second transistor in the first direction, the third transistor comprising a third drain region and a third source region, the third source region being used for being connected with a third conductive line, the fourth transistor comprising a fourth drain region and a fourth source region, the fourth source region being connected with a fourth conductive line; a second type of contact hole comprising at least one contact hole, the second type of contact hole being used for providing the equalization voltage for the first drain region, the second drain region, the third drain region and the fourth drain region, the second type of contact hole being arranged in the first direction or in the second direction.

5. The equalization circuit of claim 4, wherein, The first drain region and the second drain region have a first overlapping region, the second drain region and the third drain region have a second overlapping region, and the third drain region and the fourth drain region have a third overlapping region.

6. The equalization circuit of claim 5, wherein, The second overlapping region is provided with the second type of contact hole, and the first overlapping region and the third overlapping region are not provided with the second type of contact hole, the second type of contact hole being arranged in the first direction.

7. The equalization circuit of claim 5, wherein, The first overlapping region, the second overlapping region and the third overlapping region are all provided with the second type of contact hole, and the second type of contact hole is arranged in the second direction.

8. The equalization circuit of claim 6, wherein, The second type of contact hole comprises a fifth contact hole arranged in the second overlapping region; wherein, in the first direction, the second contact hole is between the first contact hole and the fifth contact hole, and the second contact hole is equidistant from the first contact hole and the fifth contact hole; or in the first direction, the side of the fifth contact hole facing the second contact hole is aligned with the side of the second contact hole facing the fifth contact hole.

9. The equalization circuit of claim 1, wherein, The conductive line connected with the first type of contact hole is a first type of conductive line, in the first direction, the first type of contact hole has opposite first and second contact edges, the first type of conductive line has a first conductive edge close to the first contact edge and a second conductive edge close to the second contact edge, the first contact edge and the first conductive edge have a first spacing, and the second contact edge and the second conductive edge have a second spacing, and the first spacing is equal to the second spacing.

10. The equalization circuit of claim 1, wherein, In the second direction, one side of the second drain region has a first isolation structure, and both sides of the first isolation structure in the first direction are doped regions, and the center line of the second source region is aligned with the center line of the first isolation structure.

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