Pulse synchronous capturer based on asynchronous setting end triggering and processor

Abstract

The invention relates to a pulse synchronous capturer based on asynchronous setting end triggering and a processor, the pulse synchronous capturer comprises a parameterization configuration module, a test control module, an asynchronous edge triggering capture module and a two-stage synchronization module, and the asynchronous edge triggering capture module is realized based on a D trigger group with an asynchronous setting end. According to the capturer, through an asynchronous setting end triggering design, pulse capture with a high capture rate is realized, an additional delay loop does not exist in a framework, and capture delay can be minimized while circuit resources are saved; meanwhile, by switching the working modes, the circuit logic of the capturer can be compatible with a mass production chip design process, so that the applicability of the capturer is improved.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit design technology, and in particular to a pulse synchronization capture device and processor based on asynchronous set-terminal triggering. Background Technology

[0002] In high-performance digital systems such as high-performance processors, artificial intelligence, 5G base stations, medical imaging equipment, and industrial Ethernet controllers, it is often necessary to process asynchronous interrupt signals with ultra-high frequency and narrow pulses from different clock domains, such as picosecond-level pulses from RF link feedback and data trigger pulses from high-speed sensors.

[0003] like Figure 1 As shown, traditional pulse synchronization capture circuits 100 generally adopt a logic architecture of asynchronous signal, flip-flop data terminal, clock edge sampling, and multi-level synchronization. This architecture connects the asynchronous interrupt signal to the data terminal (D terminal) of a general D flip-flop, relies on the rising or falling edge of the local core clock (core_clk) to sample the signal, then filters out metastability through a synchronization register, and finally outputs the synchronized interrupt signal. To improve narrow pulse capture capability, some existing solutions also use methods such as adding pulse widening circuits and feedback reset logic. Figure 1 The architecture shown is optimized.

[0004] However, there are still three major technical bottlenecks in the existing pulse synchronization capture architecture:

[0005] One issue is the problem of missed detections due to ultra-narrow pulses. For example... Figure 2 As shown, the existing pulse synchronization capture device 100 relies on clock edge sampling. When the interrupt pulse width is less than the clock period, the pulse is likely to fall between two clock edges, resulting in missed sampling and failing to meet the requirements of ultra-high frequency scenarios. Second, the acquisition delay is too large. Existing solutions have sampling waiting delays, and some improved solutions add additional delay loops, resulting in a total delay of 1.5-3ns in scenarios with a 1GHz clock speed. Furthermore, it is impossible to balance the missed detection rate and the level of delay. Either the delay is increased in order to improve the acquisition rate, or the acquisition rate is sacrificed in order to reduce the delay. Third, there are functional integration conflicts. Existing solutions require additional auxiliary circuits such as pulse widening and feedback reset, which are complex in structure and increase resource overhead. In their integrated processor circuits, they are difficult to be compatible with multi-channel parametric design and design for testability (DFT), resulting in poor mass production applicability.

[0006] Therefore, a new pulse synchronization capture scheme is urgently needed to solve the above-mentioned technical problems. Summary of the Invention

[0007] This invention provides a pulse synchronization capture device and processor based on asynchronous set-terminal triggering, aiming to solve the technical problems of existing pulse synchronization capture device solutions, which are difficult to balance capture rate and latency and have poor compatibility.

[0008] To address the aforementioned technical problems, in a first aspect, the present invention provides a pulse synchronization capture device based on asynchronous set-terminal triggering. The pulse synchronization capture device includes a parameterized configuration module, a test control module, an asynchronous edge-triggered capture module, and a two-stage synchronization module, wherein: The parameterized configuration module is used to define the preset number of channels for the asynchronous pulse signals that need to be captured; The test control module is used to losslessly forward and output the asynchronous pulse signal corresponding to the preset number of channels from the external input to the asynchronous edge triggering capture module according to the preset working mode; The asynchronous edge-triggered capture module is implemented based on a D flip-flop group with an asynchronous set terminal. The asynchronous edge-triggered capture module is used to receive and capture the asynchronous pulse signal through the asynchronous set terminal of the D flip-flop group to obtain a latch signal corresponding to the asynchronous pulse signal. The two-stage synchronization module is used to eliminate metastability in the latched signal and output a synchronization pulse signal corresponding to the asynchronous pulse signal.

[0009] Furthermore, the D flip-flop group with asynchronous set input includes a cascaded first D flip-flop and a second D flip-flop. The asynchronous set input of the D flip-flop group with asynchronous set input is used to receive the asynchronous pulse signal, and the clock input of the D flip-flop group with asynchronous set input is used to receive a clock signal. The data input of the first D flip-flop is connected to a fixed low-level signal, and the output input of the first D flip-flop is connected to the data input of the second D flip-flop. The first D flip-flop and the second D flip-flop share the same clock signal, wherein: The asynchronous set terminal of the D flip-flop group with asynchronous set terminal is level sensitive. When the asynchronous set terminal of the first D flip-flop receives the rising edge of the asynchronous pulse signal, it starts to capture the asynchronous pulse signal and outputs the captured asynchronous pulse signal as the latch signal to the second D flip-flop, which then buffers the latch signal.

[0010] Furthermore, the asynchronous edge-triggered capture module is also used for: After receiving the falling edge of the asynchronous pulse signal at the asynchronous set terminal of the first D flip-flop, the first D flip-flop is reset when the rising edge of the clock signal is received.

[0011] Furthermore, the asynchronous edge-triggered capture module is also used for: After the first D flip-flop is reset, the second D flip-flop is reset when the rising edge of the clock signal is received.

[0012] Furthermore, the test control module is implemented based on a two-input one-output multiplexer, and the preset working modes include a capture mode and a test mode, wherein: In the capture mode, the test control module takes the asynchronous pulse signal as input and forwards the asynchronous pulse signal for output. In the test mode, the test control module takes a global reset signal for circuit initialization as input and forwards the global reset signal to the output.

[0013] Furthermore, the test control module is also used for: In the test mode, the global reset signal is inverted, and the number of channels of the global reset signal is expanded to the same bit width as the preset number of channels before the global reset signal is forwarded and output.

[0014] Furthermore, the two-stage synchronization module includes a cascaded first synchronization register and a second synchronization register. The data terminal of the first synchronization register is used to receive the latch signal, and the output terminal of the first synchronization register is connected to the data terminal of the second synchronization register. The first synchronization register and the second synchronization register share the same clock signal. The two-stage synchronization module is used to eliminate the metastability of the latched signal by synchronizing it through two pulses as it passes through the first synchronization register and the second synchronization register, and outputs the synchronization pulse signal through the output terminal of the second synchronization register.

[0015] In a second aspect, the present invention also provides a processor, the processor comprising a pulse synchronization capture device based on asynchronous set-terminal triggering as described above.

[0016] The beneficial effects achieved by this invention are that it proposes a pulse synchronization capture device based on asynchronous set-terminal triggering. This capture device achieves high capture rate pulse capture through asynchronous set-terminal triggering design, and the architecture has no additional delay loop, saving circuit resources while minimizing capture delay. At the same time, by switching the working mode, the circuit logic of the capture device can be compatible with the mass production chip design process, thus improving the applicability of this invention. Attached Figure Description

[0017] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1This is a block diagram of a pulse synchronization capture device in the prior art; Figure 2 This is a timing waveform diagram of a pulse synchronization capture device in the prior art; Figure 3 This is a structural block diagram of a pulse synchronization capture device based on asynchronous set-end triggering provided in an embodiment of the present invention; Figure 4 This is a block diagram of the principle of a pulse synchronization capture device based on asynchronous set-end triggering provided in an embodiment of the present invention; Figure 5 This is a timing waveform diagram of a pulse synchronization capture device based on asynchronous set-terminal triggering provided in an embodiment of the present invention. Detailed Implementation

[0018] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0019] The specific embodiments / examples described herein are specific implementations of the present invention, used to illustrate the concept of the invention, and are illustrative and exemplary, and should not be construed as limiting the implementation methods or scope of the present invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein, all of which are within the protection scope of the present invention.

[0020] Example 1 Please refer to Figure 3 , Figure 3 This is a structural block diagram of a pulse synchronization capture device based on asynchronous set-end triggering provided in an embodiment of the present invention. The pulse synchronization capture device 200 includes a parameterization configuration module 201, a test control module 202, an asynchronous edge-triggered capture module 203, and a two-stage synchronization module 204, wherein: The parameterization configuration module 201 is used to define the preset number of channels for the asynchronous pulse signals that need to be captured; The test control module 202 is used to forward and output the asynchronous pulse signal corresponding to the preset number of channels from the external input to the asynchronous edge trigger capture module 203 without loss, according to the preset working mode. The asynchronous edge-triggered capture module 203 is implemented based on a D flip-flop group with an asynchronous set terminal. The asynchronous edge-triggered capture module 203 is used to receive and capture the asynchronous pulse signal through the asynchronous set terminal of the D flip-flop group to obtain a latch signal corresponding to the asynchronous pulse signal. The two-stage synchronization module 204 is used to eliminate metastability in the latched signal and output a synchronization pulse signal corresponding to the asynchronous pulse signal.

[0021] The D flip-flop group with asynchronous set input includes a cascaded first D flip-flop 2031 and a second D flip-flop 2032. The asynchronous set input of the D flip-flop group with asynchronous set input is used to receive the asynchronous pulse signal, and the clock input of the D flip-flop group with asynchronous set input is used to receive a clock signal. The data input of the first D flip-flop 2031 is connected to a fixed low-level signal, and the output input of the first D flip-flop 2031 is connected to the data input of the second D flip-flop 2032. The first D flip-flop 2031 and the second D flip-flop 2032 share the same clock signal, wherein: The asynchronous set terminal of the D flip-flop group with asynchronous set terminal is level sensitive. When the asynchronous set terminal of the first D flip-flop 2031 receives the rising edge of the asynchronous pulse signal, it starts to capture the asynchronous pulse signal and outputs the captured asynchronous pulse signal as the latch signal to the second D flip-flop 2032, which buffers the latch signal.

[0022] For ease of explanation, the embodiments of the present invention are combined with, as follows Figure 4 The block diagram shown illustrates the process of acquiring asynchronous pulse signals. The acquisition of asynchronous pulse signals involves the processing of various signals. The signals and their definitions involved in this embodiment are as follows: A global reset signal is used to initialize the circuit module. The clock signal provides the global clock frequency; Asynchronous pulse signal, the target of pulse synchronization capture device 200; Synchronous pulse signal, the final output of the pulse synchronization capture device 200 after capturing and processing asynchronous pulse signals.

[0023] Before entering the working state, all modules in this embodiment of the invention complete power-on initialization through a global reset signal, and the asynchronous edge trigger capture module 203 and the two-level synchronization module 204 are both initially low level; The clock signal runs continuously. In the default working mode of the test control module 202, it only serves as a signal pass-through and does not interfere with the capture process.

[0024] The preset number of channels defined by the parameterized configuration module 201 corresponds one-to-one with the number of channels for asynchronous pulse signals, the number of signal channels for the test control module 202, the asynchronous edge-triggered capture module 203, and the two-stage synchronization module 204. For example, setting the preset number of channels to 4 means that 4 asynchronous pulse signals are captured in parallel. During implementation, the capture logic for single-channel and multi-channel signals is the same. In this embodiment, the capture logic for single-channel signals is used as an example for explanation.

[0025] The core of the asynchronous edge-triggered capture module 203 is a group of D flip-flops with an asynchronous set input, which includes a cascaded first D flip-flop 2031 and a second D flip-flop 2032. The asynchronous set input of the flip-flops is level-sensitive and not clock-constrained, which is key to achieving width-limit-free and missed detection-free capture. Specifically: like Figure 5 The timing waveform diagram shows that when the effective rising edge of the external ultra-narrow asynchronous pulse signal arrives, the asynchronous set terminal is directly triggered without waiting for the clock edge of the clock signal. At this time, the first D flip-flop 2031 is instantly set to a high level, completing the pulse latching. Since the asynchronous set terminal is level sensitive, it can be captured instantly as long as there is a rising edge of the signal, thus avoiding missed detection at the source.

[0026] The asynchronous edge-triggered capture module 203 is also used for: After receiving the falling edge of the asynchronous pulse signal at the asynchronous set terminal of the first D flip-flop 2031, the first D flip-flop 2031 is reset when the rising edge of the clock signal is received.

[0027] When the asynchronous pulse signal returns to a low level (falling edge of pulse release), and the next rising edge of the clock signal arrives, the first D flip-flop 2031 is synchronously set to 0 under the control of the clock edge, returning to the initial low level state, and waiting for the next rising edge of the asynchronous pulse signal to trigger. Correspondingly, after the first D flip-flop 2031 is reset, the second D flip-flop 2032 is reset when the rising edge of the clock signal is received, so that it returns to the initial low level state and waits for the next rising edge of the asynchronous pulse signal to trigger.

[0028] Based on the design of a D flip-flop group with an asynchronous set terminal, the asynchronous edge trigger capture module 203 requires a delay of less than 1 ns to capture the asynchronous pulse signal at a 1 GHz clock. This delay is determined by the physical characteristic of the level response speed of the asynchronous set terminal.

[0029] In this embodiment of the invention, the test control module 202 is implemented based on a two-input one-output multiplexer, and the preset working modes include a capture mode and a test mode, wherein: In the capture mode, the test control module 202 takes the asynchronous pulse signal as input and forwards the asynchronous pulse signal to the output. In the test mode, the test control module 202 takes a global reset signal for circuit initialization as input and forwards the global reset signal to the output.

[0030] The test control module 202 is also used for: In the test mode, the global reset signal is inverted, and the number of channels of the global reset signal is expanded to the same bit width as the preset number of channels before the global reset signal is forwarded and output.

[0031] The test control module 202 is a design feature of this embodiment of the invention to improve the hardware compatibility of the pulse synchronization capture device 200, aiming to address the testing requirements during mass production of processor chips. The test control module 202 determines the operating mode based on the received operating mode signal, and uses one of the signals as input: In capture mode, the test control module 202 selects an asynchronous pulse signal as input and connects it to the asynchronous set terminal of the asynchronous edge-triggered capture module 203, retaining the narrow pulse capture function without width limitation; In test mode, the test control module 202 selects the inverted and extended global reset signal as the input, and the global reset signal takes over the control of the asynchronous edge trigger capture module 203, which meets the chip scan test requirements and does not affect the synchronous timing characteristics of the module.

[0032] As described in the above embodiments, in capture mode, the test control module 202 only serves as a pass-through for the asynchronous pulse signal and does not interfere with the capture process. However, in test mode, although the global reset signal is also forwarded, since the global reset signal is active low and the asynchronous pulse signal is active high, the test control module 202 needs to invert the global reset signal to convert it to active high. At the same time, through a bit-width expansion operation, the global reset signal is expanded into a bus with the same bit width as the asynchronous pulse signal to ensure that the polarity of the two inputs of the test control module 202 is completely matched with the bit width, thus avoiding logical conflicts.

[0033] The latch signal output by the asynchronous edge-triggered capture module 203 may exhibit metastability due to cross-clock domain transmission, meaning the signal level is unstable and fluctuates between high and low, making it unusable directly for subsequent circuits. This embodiment of the invention eliminates metastability through a two-stage synchronization module 204. The two-stage synchronization module 204 consists of a first synchronization register 2041 and a second synchronization register 2042. The data terminal of the first synchronization register 2041 receives the latch signal, and its output terminal is connected to the data terminal of the second synchronization register 2042. The first synchronization register 2041 and the second synchronization register 2042 share the same clock signal. The two-stage synchronization module 204 eliminates the metastability of the latch signal by synchronizing it through two clock cycles as it passes through the first synchronization register 2041 and the second synchronization register 2042, and outputs the synchronization pulse signal through the output terminal of the second synchronization register 2042.

[0034] This process follows the industry's two-step synchronous metastability elimination criterion, stabilizing the signal in two steps simultaneously: The first synchronization step is used to initially filter out metastability. The latch signal acquired by the asynchronous edge-triggered capture module 203 is input to the first synchronization register 2041 and is sampled and latched on the next rising edge of the clock signal to initially eliminate metastability and make the signal level tend to stabilize. The second synchronization is used to completely eliminate metastability. The output signal of the first synchronization register 2041 is then input to the second synchronization register 2042, and is sampled and latched on the next rising edge of the clock signal to completely eliminate metastability, and finally output a stable synchronization pulse signal without glitches or metastability.

[0035] The two-step synchronization process eliminates metastability, ensuring that the final synchronization pulse signal can be directly connected to the subsequent synchronization logic. The synchronization output delay of this process is 1-2 clock cycles (1-2ns / 1GHz), which is a necessary delay for the circuit function, with no additional delay superposition. Based on this design, the total delay of the pulse synchronization capture device 200 proposed in this embodiment of the invention is 1-3ns at a 1GHz clock speed (the total delay is the sum of the physical delay of the asynchronous set terminal and the standard delay of the two-step synchronization), that is, there is no additional delay superposition other than the physical delay of the asynchronous set terminal and the standard delay of the two-step synchronization, achieving a balance between capture rate and delay level.

[0036] The beneficial effects achieved by this invention are that it proposes a pulse synchronization capture device based on asynchronous set-terminal triggering. This capture device achieves high capture rate pulse capture through asynchronous set-terminal triggering design, and the architecture has no additional delay loop, saving circuit resources while minimizing capture delay. At the same time, by switching the working mode, the circuit logic of the capture device can be compatible with the mass production chip design process, thus improving the applicability of this invention.

[0037] Example 2 The present invention also provides a processor comprising the pulse synchronization capture device 200 triggered by an asynchronous set terminal as described above. It is understood that, based on the specific structure of the pulse synchronization capture device 200 triggered by an asynchronous set terminal, the processor can achieve a higher capture rate and lower latency compared to existing technologies when capturing asynchronous pulse signals. Referring to the description in the above embodiments, further details are omitted here.

[0038] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0039] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A pulse synchronous capturer based on an asynchronous set-true edge trigger, characterized by, The pulse synchronous capture device comprises a parameterized configuration module, a test control module, an asynchronous edge trigger capture module and a two-stage synchronization module, wherein: The parameterized configuration module is configured to define a preset channel number of asynchronous pulse signals to be captured. The test control module is configured to forward the asynchronous pulse signals corresponding to the preset channel number input from outside to the asynchronous edge trigger capture module according to a preset working mode. The asynchronous edge trigger capture module is implemented based on a D flip-flop group with an asynchronous set end, and is configured to receive and capture the asynchronous pulse signals through the asynchronous set end of the D flip-flop group to obtain a latch signal corresponding to the asynchronous pulse signals. The two-stage synchronization module is configured to eliminate metastability of the latch signal and output a synchronous pulse signal corresponding to the asynchronous pulse signal.

2. The pulse synchronous capturer based on asynchronous set-true edge trigger according to claim 1, characterized in that, The D flip-flop group with the asynchronous set end comprises a first D flip-flop and a second D flip-flop connected in cascade, the asynchronous set end of the D flip-flop group is configured to receive the asynchronous pulse signal, a clock end of the D flip-flop group is configured to receive a clock signal, a data end of the first D flip-flop receives a fixed low-level signal, an output end of the first D flip-flop is connected with a data end of the second D flip-flop, and the first D flip-flop and the second D flip-flop share the same clock signal, wherein: The asynchronous set end of the D flip-flop group with the asynchronous set end is level sensitive, and when the rising edge of the asynchronous pulse signal is received by the asynchronous set end of the first D flip-flop, the asynchronous pulse signal is captured and output as the latch signal to the second D flip-flop.

3. The asynchronous set-true edge triggered pulse synchronous capture as claimed in claim 2, wherein, The asynchronous edge trigger capture module is further configured to: After the falling edge of the asynchronous pulse signal is received by the asynchronous set end of the first D flip-flop, the first D flip-flop is reset when the rising edge of the clock signal is received.

4. The asynchronous set-true edge triggered pulse synchronous capture as claimed in claim 3, wherein, The asynchronous edge trigger capture module is further configured to: After the first D flip-flop is reset, the second D flip-flop is reset when the rising edge of the clock signal is received.

5. The asynchronous set-true edge triggered pulse synchronous capturer of claim 1, wherein, The test control module is implemented based on a multiplexer with a binary output, and the preset working mode comprises a capture mode and a test mode, wherein: In the capture mode, the test control module takes the asynchronous pulse signal as input and forwards the asynchronous pulse signal. In the test mode, the test control module takes a global reset signal for circuit initialization as input and forwards the global reset signal.

6. The asynchronous set-true edge triggered pulse synchronous capture as claimed in claim 5, wherein, The test control module is further configured to: In the test mode, the global reset signal is inverted, the channel number of the global reset signal is expanded to the same bit width as the preset channel number, and then the global reset signal is forwarded.

7. The asynchronous set-true edge triggered pulse synchronous capturer according to claim 2, wherein, The two-stage synchronization module comprises a first synchronization register and a second synchronization register connected in cascade, a data end of the first synchronization register is configured to receive the latch signal, an output end of the first synchronization register is connected with a data end of the second synchronization register, and the first synchronization register and the second synchronization register share the same clock signal; The two-stage synchronization module is configured to eliminate metastability of the latch signal by two-tap synchronization in a process that the latch signal passes through the first synchronization register and the second synchronization register in sequence, and output the synchronization pulse signal through an output end of the second synchronization register.

8. A processor, comprising: The processor comprises the pulse synchronization capturer based on the asynchronous set end trigger as claimed in any one of claims 1-7.

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