A high-speed four-switch architecture applied to a digital-to-analog converter
By introducing cross-coupling capacitors into the digital-to-analog converter to accelerate switch switching, the problem of slow switching speed caused by parasitic capacitance in the four-switch architecture is solved, and higher sampling rate and higher frequency signal processing are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN AEROSPACE MINXIN TECH CO LTD
- Filing Date
- 2025-12-23
- Publication Date
- 2026-06-19
Smart Images
Figure CN121749965B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-speed four-switch architecture for use in digital-to-analog converters. Background Technology
[0002] In recent years, with the continuous development of technology, the feature size of transistors has been shrinking and the operating frequency has been increasing. In modern electronic warfare technology and modern wireless communication systems, high-performance digital-to-analog converters, as radio frequency transceivers, are indispensable.
[0003] Currently, the architecture of high-speed digital-to-analog converters is mainly based on the current-steering architecture because this structure can be directly used as an output module without the need for an additional voltage buffer. In addition, it can perform high-precision matching and calibration of the current, which helps to achieve higher accuracy. In this scheme, the current-steering switch is the most critical module, and the performance of the switch directly affects the final performance of the digital-to-analog converter.
[0004] The four-switch architecture is widely used because it can support multiple signal stream output modes such as non-return-to-zero, return-to-zero, dual-edge output, and mixed-mode output. However, the introduction of four MOS transistors introduces more parasitic capacitance, which slows down the switching speed and limits the sampling rate of the digital-to-analog converter. As a result, digital-to-analog converters based on this architecture have been difficult to apply in high-speed fields. Summary of the Invention
[0005] This invention provides a high-speed four-switch architecture for digital-to-analog converters, which can solve the problems existing in the prior art.
[0006] This invention provides a high-speed four-switch architecture for digital-to-analog converters, including a tail current source I1, MOS transistors M1, M2, M3, M4, M5 and M6, and cross-coupling capacitors C1, C2, C3 and C4.
[0007] The output terminal of the tail current source I1 is connected to the source of MOS transistors M1, M2, M3 and M4 respectively; the source of MOS transistor M5 is connected to the drain of MOS transistors M2 and M4 respectively; the source of MOS transistor M6 is connected to the drain of MOS transistors M1 and M3 respectively; the drain of MOS transistor M5 is connected to the output node VOUTP; and the drain of MOS transistor M6 is connected to the output node VOUTN.
[0008] One end of cross-coupling capacitor C1 is connected to the gate of MOS transistor M1, and the other end of cross-coupling capacitor C1 is connected to the drain of MOS transistor M5; one end of cross-coupling capacitor C2 is connected to the gate of MOS transistor M3, and the other end of cross-coupling capacitor C2 is connected to the drain of MOS transistor M5; one end of cross-coupling capacitor C3 is connected to the gate of MOS transistor M2, and the other end of cross-coupling capacitor C3 is connected to the drain of MOS transistor M6; one end of cross-coupling capacitor C4 is connected to the gate of MOS transistor M4, and the other end of cross-coupling capacitor C4 is connected to the drain of MOS transistor M6.
[0009] The control signal for MOS transistor M1 is data D0, the control signal for MOS transistor M2 is data D0N, the control signal for MOS transistor M3 is data D1, and the control signal for MOS transistor M4 is data D1N.
[0010] Preferably, the MOS transistors M1 and M2 are a pair of differential input transistors, and the MOS transistors M3 and M4 are a pair of differential input transistors.
[0011] Preferably, the control signal D0 and the control signal D0N are a pair of control signals, and the control signal D1 and the control signal D1N are a pair of control signals.
[0012] Preferably, in any operating cycle of the high-speed four-switch architecture, among the control signals D0, D0N, D1 and D1N, only one control signal is at a low level, while the rest are at a high level.
[0013] Preferably, the cross-coupling capacitor C1 is connected between the gate of MOS transistor M1 and the drain of MOS transistor M5 to form a gate-drain cross-coupling, which is used to provide a voltage feedforward path during switching.
[0014] The cross-coupling capacitor C2 is connected between the gate of MOS transistor M3 and the drain of MOS transistor M5 to form a gate-drain cross-coupling, which is used to provide a voltage feedforward path during switching.
[0015] The cross-coupling capacitor C3 is connected between the gate of MOS transistor M2 and the drain of MOS transistor M6 to form a gate-drain cross-coupling, which is used to provide a voltage feedforward path during switching.
[0016] The cross-coupling capacitor C4 is connected between the gate of MOS transistor M4 and the drain of MOS transistor M6 to form a gate-drain cross-coupling, which is used to provide a voltage feedforward path during switching.
[0017] Preferably, the MOS transistors M1, M2, M3, M4, M5 and M6 are all N-type MOS transistors.
[0018] Preferably, the high-speed four-switch architecture is applied to the digital-to-analog converter, and when the sampling rate frequency of the digital-to-analog converter is 25GHz, the spurious-free dynamic range (SFDR) is improved from 42dB to 59dB when the input signal of the digital-to-analog converter is 12.09GHz.
[0019] This invention provides a high-speed four-switch architecture for digital-to-analog converters, which has the following advantages compared with the prior art:
[0020] In operation, the high-speed four-switch architecture of this invention uses a pair of control signals D0 and DON to control differential input transistors M1 and M2, and another pair of control signals D1 and D1N to control differential input transistors M3 and M4. When D0 transitions from high to low, DON transitions from low to high. At this time, both D1 and D1N are high, so M1 switches from off to on, M2 switches from on to off, and M3 and M4 are off. The tail current source I1 then flows the output current to the output node VOUTN through M1 and M6. During this process, the current charges the intermediate node Vx, which is connected to the source of M6 and the drain of M1 and M3 respectively. As Vx charges, it transitions from low to high, and DON transitions from low to high. Due to the presence of the cross-coupling capacitor C3, during switch switching... The voltage feedforward path further helps the Vx node accelerate its transition from low to high level, thus accelerating the establishment of the VOUTN node. Conversely, when D0N transitions from low to high, M2 is turned off, the Vy node transitions from high to low, and D0 transitions from high to low. Due to the presence of the cross-coupling capacitor C1, the Vy node accelerates its transition from high to low, thus accelerating the establishment of the VOUTP node. Similarly, when D1 transitions from high to low, the presence of the cross-coupling capacitors C2 and C4 also helps the VOUTN and VOUTP nodes establish themselves more quickly. This overall accelerates the switching speed and significantly improves the sampling rate of the digital-to-analog converter, making this type of digital-to-analog converter widely used in high-speed applications. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of a traditional four-switch architecture;
[0022] Figure 2 This is a schematic diagram of the overall architecture of a high-speed four-switch architecture applied to a digital-to-analog converter, provided by an embodiment of the present invention.
[0023] Figure 3 This invention provides a schematic diagram of the input control signal for a high-speed four-switch architecture applied to a digital-to-analog converter.
[0024] Figure 4This is a schematic diagram comparing the operation of the high-speed four-switch architecture of the present invention with that of the traditional four-switch architecture;
[0025] Figure 5 This is a schematic comparison diagram of the output voltage of the high-speed four-switch architecture of the present invention and the traditional four-switch architecture;
[0026] Figure 6 This is a schematic diagram comparing the output waveforms of a 10-bit digital-to-analog converter with the high-speed four-switch architecture of the present invention and a traditional four-switch architecture.
[0027] Figure 7 This is a schematic diagram of the spectrum of a traditional four-switch architecture 10-bit digital-to-analog converter;
[0028] Figure 8 This is a spectrum diagram of a 10-bit digital-to-analog converter with a high-speed four-switch architecture applied to a digital-to-analog converter, provided as an embodiment of the present invention. Detailed Implementation
[0029] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
[0030] Currently, the traditional four-switch architecture, such as Figure 1 As shown, this architecture is widely used because it supports multiple signal stream output modes, including non-return-to-zero, return-to-zero, dual-edge output, and mixed-mode output. However, the introduction of four MOS transistors introduces more parasitic capacitance, which slows down the switching speed and limits the sampling rate of the digital-to-analog converter (DAC). This has hindered the application of this architecture in high-speed applications, significantly limiting its application scenarios. Therefore, implementing a 4-switch architecture in high-speed DACs remains a challenge.
[0031] To address the shortcomings of existing technologies, this invention provides a high-speed four-switch architecture operating technology and implementation circuit for digital-to-analog converters. Compared with existing four-switch architectures, this structure can effectively improve the switching speed, alleviate the problem of slow setup due to large parasitic capacitance at high frequencies, effectively improve the switching speed, extend the sampling speed of the digital-to-analog converter, and realize a higher speed and higher performance digital-to-analog converter.
[0032] like Figure 2 As shown, it includes a tail current source I1, six MOS transistors M1~M6 and four capacitors C1~C4.
[0033] Among them, the tail current source I1 is connected to the source terminals of MOSFETs M1 to M4, where M1 and M2 are a pair of differential input transistors, and M3 and M4 are another pair of differential input transistors; the source terminal of M5 is connected to the drain terminals of M2 and M4, and the source terminal of M6 is connected to the drain terminals of M1 and M3; one end of the cross-coupling capacitor C1 is connected to the gate of M1, and the other end is connected to the drain of M5; one end of the cross-coupling capacitor C2 is connected to the gate of M3, and the other end is connected to the drain of M5; one end of the cross-coupling capacitor C3 is connected to the gate of M2, and the other end is connected to the drain of M6; one end of the cross-coupling capacitor C4 is connected to the gate of M4, and the other end is connected to the drain of M6.
[0034] Among them, the gate control signal of M1 is data D0, and the gate control signal of M2 is data D0N; D0 and D0N are a pair of control signals; similarly, the gate control signal of M3 is data D1, and the gate control signal of M4 is data D1N; D1 and D1N are a pair of control signals.
[0035] Because the control signals of the four switches are based on the code pattern rules, only one switch can be turned on at any given time, such as Figure 3 As shown, D0 and D0N are a pair of input control signals that control differential input transistors M1 and M2, and D1 and D1N are a pair of control signals that control differential input transistors M3 and M4.
[0036] When D0 transitions from high to low, DON transitions from low to high; at this time, both D1 and D1N are high; therefore, transistor M1 switches from off to on, transistor M2 switches from on to off, and transistors M3 and M4 are off; at this time, the tail current source I1 flows the output current to the VOUTN output node through transistors M1 and M6; during this process, the Vx node is charged, and the waveform of the Vx node is shown in Figure V4, correspondingly changing from low to high; DON transitions from low to high at this time, and due to the presence of feedforward capacitor C3, it further helps the Vx node accelerate the transition from low to high, as shown in Figure V4. Figure 4 As shown in V2; this helps the VOUTN node to complete its establishment faster, as... Figure 5 As shown.
[0037] Conversely, when D0N transitions from low to high, switch M2 turns off, and node Vy should transition from high to low. D0 then transitions from high to low. Due to the presence of feedforward capacitor C1, node Vy accelerates its transition from high to low. Figure 4 As shown in V1; ultimately, this helps the VOUTP output node to be established faster, as... Figure 5 As shown. When D1 transitions from high to low, D1N transitions from low to high; at this time, both D0 and D0N are high, and the operating state is similar.
[0038] To better compare the optimization effect of the high-speed 4-switch architecture of this invention, a traditional 4-switch structure and the high-speed 4-switch architecture of this invention were applied to a 10-bit current-controlled analog-to-digital converter (ADC); the output waveforms of the ADCs were compared as follows: Figure 6 As shown, it can be seen that the output waveform of this structure is established more fully and has fewer glitches in the same amount of time; further analysis in the frequency domain, such as Figure 7 and Figure 8 As shown, Fast Fourier Transform (FFT) analysis was performed on the output waveforms of the digital-to-analog converters based on the traditional 4-switch architecture and the high-speed 4-switch architecture of this invention. It can be found that for the same 25GHz sampling rate digital-to-analog converter, when the input signal is equal to 12.09GHz, the spurious-free dynamic range (SFDR) is improved from 42dB to 59dB.
[0039] This invention provides a feedforward path at the moment of switching by using cross-coupling capacitors, which accelerates the voltage changes of the two key nodes Vx and Vy, enabling the switching transistor to turn on or off faster, thereby effectively improving the switching speed and supporting digital-to-analog converters with higher sampling rates.
[0040] Compared to the traditional 4-switch architecture, this invention only adds four capacitors and two MOS transistors without changing the original switch control logic. It has a simple structure, is easy to integrate into existing current-controlled DACs, and can be easily ported to more advanced integrated circuit processes, exhibiting good process compatibility. At the same time, this invention does not change the advantages of the traditional four-switch architecture, which supports non-return-to-zero, return-to-zero, dual-edge output, and mixed-mode output. While improving speed, it does not affect its multi-mode output capability, making it suitable for high-speed and high-flexibility applications such as modern wireless communication and electronic warfare.
[0041] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.
Claims
1. A high-speed four-switch architecture for digital-to-analog converters, characterized in that, include: Tail current source I1, MOS transistors M1, M2, M3, M4, M5 and M6, and cross-coupling capacitors C1, C2, C3 and C4; The output terminal of the tail current source I1 is connected to the source of MOS transistors M1, M2, M3 and M4 respectively; the source of MOS transistor M5 is connected to the drain of MOS transistors M2 and M4 respectively; the source of MOS transistor M6 is connected to the drain of MOS transistors M1 and M3 respectively; the drain of MOS transistor M5 is connected to the output node VOUTP; and the drain of MOS transistor M6 is connected to the output node VOUTN. One end of the cross-coupling capacitor C1 is connected to the gate of MOS transistor M1, and the other end of the cross-coupling capacitor C1 is connected to the drain of MOS transistor M5; one end of the cross-coupling capacitor C2 is connected to the gate of MOS transistor M3, and the other end of the cross-coupling capacitor C2 is connected to the drain of MOS transistor M5; one end of the cross-coupling capacitor C3 is connected to the gate of MOS transistor M2, and the other end of the cross-coupling capacitor C3 is connected to the drain of MOS transistor M6; one end of the cross-coupling capacitor C4 is connected to the gate of MOS transistor M4, and the other end of the cross-coupling capacitor C4 is connected to the drain of MOS transistor M6. The control signal for MOS transistor M1 is data D0, the control signal for MOS transistor M2 is data D0N, the control signal for MOS transistor M3 is data D1, and the control signal for MOS transistor M4 is data D1N. The MOS transistors M1 and M2 are a pair of differential input transistors, and the MOS transistors M3 and M4 are a pair of differential input transistors; The control signal D0 and the control signal D0N are a pair of control signals, and the control signal D1 and the control signal D1N are a pair of control signals; In any operating cycle of the high-speed four-switch architecture, among the control signals D0, D0N, D1 and D1N, only one control signal is at a low level, while the rest are at a high level.
2. The high-speed four-switch architecture for digital-to-analog converters according to claim 1, characterized in that, The cross-coupling capacitor C1 is connected between the gate of MOS transistor M1 and the drain of MOS transistor M5 to form a gate-drain cross-coupling, which is used to provide a voltage feedforward path during switching. The cross-coupling capacitor C2 is connected between the gate of MOS transistor M3 and the drain of MOS transistor M5 to form a gate-drain cross-coupling, which is used to provide a voltage feedforward path during switching. The cross-coupling capacitor C3 is connected between the gate of MOS transistor M2 and the drain of MOS transistor M6 to form a gate-drain cross-coupling, which is used to provide a voltage feedforward path during switching. The cross-coupling capacitor C4 is connected between the gate of MOS transistor M4 and the drain of MOS transistor M6 to form a gate-drain cross-coupling, which is used to provide a voltage feedforward path during switching.
3. The high-speed four-switch architecture for digital-to-analog converters according to claim 1, characterized in that, The MOS transistors M1, M2, M3, M4, M5 and M6 are all N-type MOS transistors.
4. The high-speed four-switch architecture for a digital-to-analog converter of claim 1, wherein, A high-speed four-switch architecture is applied to a digital-to-analog converter (DAC), and when the DAC's sampling rate frequency is 25 GHz, the spurious-free dynamic range (SFDR) is improved from 42 dB to 59 dB when the DAC's input signal is 12.09 GHz.