Parasitic capacitance elimination circuit and parasitic capacitance elimination method
By using a parasitic capacitance elimination circuit and method, and employing a coupler and a negative impedance generator, the parasitic capacitance of transistors is eliminated, thus solving the problem of parasitic capacitance changing with bias voltage and improving the stability and efficiency of the circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2026-03-27
Smart Images
Figure CN121749971A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a parasitic capacitance elimination circuit and a parasitic capacitance elimination method, and more particularly to a parasitic capacitance elimination circuit and a parasitic capacitance elimination method for eliminating the parasitic capacitance of a transistor. BACKGROUND
[0002] With the development of technology, a metal oxide semiconductor field effect transistor (MOSFET) has emerged and is widely used in various circuits. However, the MOSFET has parasitic capacitance, and the capacitance value of the parasitic capacitance changes with different bias voltages (such as gate-source voltage Vgs), which will affect the performance of the circuit. SUMMARY
[0003] In view of the deficiencies of the prior art, one of the purposes of the present application (but not limited to) is to provide a parasitic capacitance elimination circuit and a parasitic capacitance elimination method to improve the deficiencies of the prior art.
[0004] In some embodiments, the parasitic capacitance elimination circuit includes a first transistor, a first coupler, a second coupler, and a negative impedance generator. The first transistor includes a first terminal, a control terminal, and a second terminal. The first coupler is used to couple the control terminal and the first terminal of the first transistor. The second coupler is used to couple the control terminal and the second terminal of the first transistor. The negative impedance generator is used to generate and provide a negative impedance to the control terminal of the first transistor to eliminate the parasitic capacitance of the first transistor.
[0005] In some embodiments, the parasitic capacitance elimination method includes: coupling the control terminal and the first terminal of the first transistor by the first coupler; coupling the control terminal and the second terminal of the first transistor by the second coupler; and generating and providing a negative impedance to the control terminal of the first transistor by the negative impedance generator to eliminate the parasitic capacitance of the first transistor.
[0006] The technical means embodied in the embodiments of the present application can improve at least one of the shortcomings of the prior art. The parasitic capacitance elimination circuit and the parasitic capacitance elimination method of the present application can be used to eliminate the parasitic capacitance of a transistor.
[0007] The features, implementations, and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS
[0008] Figure 1 To draw a schematic diagram of a parasitic capacitance elimination circuit according to some embodiments of the present application;
[0009] Figure 2 FIG. 2 shows a flowchart of a method for eliminating parasitic capacitance according to some embodiments of the present application;
[0010] Figure 3 FIG. 4 shows a graph of the relevant electrical properties of a parasitic capacitance elimination circuit according to some embodiments of the present application;
[0011] Figure 4 FIG. 5 shows a schematic diagram of a parasitic capacitance elimination circuit according to some embodiments of the present application;
[0012] Figure 5 FIG. 6 shows a schematic diagram of a parasitic capacitance elimination circuit according to some embodiments of the present application; and
[0013] Figure 6 FIG. 7 shows a graph of the relevant electrical properties of a parasitic capacitance elimination circuit according to some embodiments of the present application. DETAILED DESCRIPTION
[0014] All words used herein are used in their normal meaning. The definitions of the above words in the commonly used dictionaries are included in the content of the present application, and the use examples of the words discussed herein are only examples and should not limit the scope and meaning of the present application. Similarly, the present application is not limited to the various embodiments shown in the specification.
[0015] As used herein, "coupled" or "connected" can mean either a direct electrical or physical contact between two or more components or an indirect electrical or physical contact between two or more components through other components. As used herein, the term "circuit" can be a device that processes signals by connecting at least one transistor and / or at least one active or passive component in a certain manner.
[0016] As used herein, the term "and / or" includes any combination of one or more of the associated items. In this document, the use of the terms first, second, and third, etc., is used to describe and distinguish various components. Therefore, the first component in this document can also be referred to as the second component without departing from the spirit of the present application. For ease of understanding, similar components in the various drawings will be designated by the same reference numerals.
[0017] To improve the problem that the parasitic capacitance of a metal oxide semiconductor field effect transistor in the prior art affects the performance of a circuit, the present application proposes a parasitic capacitance elimination circuit and a parasitic capacitance elimination method, which are described in detail as follows.
[0018] Figure 1A schematic diagram of a parasitic capacitance elimination circuit 100 is shown in accordance with some embodiments of the present application. As shown, the parasitic capacitance elimination circuit 100 includes a first transistor Ml, a first coupler 110, a second coupler 120, and a negative impedance generator 130. The first transistor Ml includes a first terminal (e.g., source), a control terminal (e.g., gate), and a second terminal (e.g., drain). To facilitate an understanding of the operation of the parasitic capacitance elimination circuit 100 of the present application, reference is made to Figure 2 , Figure 2 A flowchart of a parasitic capacitance elimination method 200 is shown in accordance with some embodiments of the present application.
[0019] Referring to Figure 1 and Figure 2 , in step 210, the control terminal and the first terminal of the first transistor Ml are coupled by the first coupler 110. In step 220, the control terminal and the second terminal of the first transistor Ml are coupled by the second coupler 120. In step 230, a negative impedance is generated and provided to the control terminal of the first transistor Ml by the negative impedance generator 130 to eliminate the parasitic capacitance of the first transistor Ml.
[0020] Referring to Figure 1 and Figure 3 , the initial parasitic capacitance of the first transistor Ml is A(S), the present application can provide a first parameter aY(S) by the first coupler 110 and a second parameter βH(S) by the second coupler 120 to adjust the initial parasitic capacitance A(S) of the first transistor Ml to be less dependent on the bias voltage (e.g., gate-source voltage Vgs). In some embodiments, a and β of the present application can be set according to actual needs to adjust the ratio of Y(S) and H(S) to adjust the initial parasitic capacitance A(S) of the first transistor Ml to be less dependent on the bias voltage (e.g., gate-source voltage Vgs).
[0021] In addition, the present application further provides a third parameter γK(S) by the negative impedance generator 130 to form a negative impedance to offset the initial parasitic capacitance A(S) of the first transistor Ml. From Figure 3It is known that the equivalent parasitic capacitance X(S) of the first transistor Ml is smaller than the initial parasitic capacitance A(S) of the first transistor Ml, and the equivalent parasitic capacitance X(S) hardly varies with the bias voltage. In some embodiments, the values of a, β and γ can be set according to actual requirements to offset the initial parasitic capacitance A(S) of the first transistor Ml, and to make the equivalent parasitic capacitance X(S) hardly vary with the bias voltage. It is noted that although only one set of a and Y(S), one set of β and H(S), and one set of γ and K(S) are drawn in the embodiments, multiple sets of a and Y(S), multiple sets of β and H(S), and multiple sets of γ and K(S) can be set according to actual requirements to more effectively offset the initial parasitic capacitance A(S) of the first transistor Ml, and to make the equivalent parasitic capacitance X(S) hardly vary with the bias voltage.
[0022] Figure 4 A schematic diagram of a parasitic capacitance cancellation circuit 100 according to some embodiments is drawn. Compared with the parasitic capacitance cancellation circuit 100 of Figure 1 the prior art, Figure 4 a detailed circuit diagram of the parasitic capacitance cancellation circuit 100 is shown. As shown in Figure 4 the first coupler 110 includes a second transistor M2, and the second transistor M2 includes a first terminal, a control terminal and a second terminal. The first terminal (e.g. the left end) of the second transistor M2 is coupled to the first terminal (e.g. the lower end) of the first transistor Ml. The control terminal (e.g. the gate terminal) of the second transistor M2 is coupled to the control terminal (e.g. the gate terminal) of the first transistor Ml. The second terminal (e.g. the right end) of the second transistor M2 is coupled to the first terminal (e.g. the left end) of the second transistor M2 and the first terminal (e.g. the lower end) of the first transistor Ml.
[0023] In some embodiments, the second coupler 120 includes a third transistor M3 including a first terminal, a control terminal, and a second terminal. The first terminal (e.g., left end) of the third transistor M3 is coupled to the second terminal (e.g., upper end) of the first transistor Ml. The control terminal (e.g., gate terminal) of the third transistor M3 is coupled to the control terminal (e.g., gate terminal) of the first transistor Ml and the control terminal (e.g., gate terminal) of the second transistor M2. The second terminal (e.g., right end) of the third transistor M3 is coupled to the first terminal (e.g., left end) of the third transistor M3 and the second terminal (e.g., upper end) of the first transistor Ml. In some embodiments, the first transistor Ml, the second transistor M2, the third transistor M3, and the transistor M9 can be Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). However, the present application is not limited to this embodiment, which is merely used to exemplarily illustrate one of the implementations of the present application. In other embodiments, the first transistor Ml, the second transistor M2, the third transistor M3, and the transistor M9 can also be other suitable components, as required.
[0024] In some embodiments, the negative impedance generator 130 includes a capacitor C including a first terminal and a second terminal. The first terminal (e.g., left end) of the capacitor C is configured to receive a first control signal (e.g., a control signal provided by the transistor M9 according to the signal Vg2, and the voltage of the signal Vg2 is not the same as the voltage of Vg). The second terminal (e.g., right end) of the capacitor C is coupled to the control terminal (e.g., gate terminal) of the first transistor Ml. The control terminal (e.g., gate terminal) of the first transistor Ml is configured to receive a second control signal Vg. The negative impedance generator 130 is configured to provide a negative impedance to the control terminal (e.g., gate terminal) of the first transistor Ml according to the first control signal (e.g., a control signal provided by the transistor M9 according to the signal Vg2, and the voltage of the signal Vg2 is not the same as the voltage of Vg). However, the present application is not limited to this embodiment, which is merely used to exemplarily illustrate one of the implementations of the present application. In other embodiments, the negative impedance generator 130 can also be other suitable components, as required.
[0025] Please refer to Figure 3The parasitic capacitance A(S) of the first transistor M1 includes the parasitic capacitance A(S) and the control signal Vg curve. The second transistor M2 provides the first parameter αY(S) and the control signal Vg curve, the third transistor M3 provides the second parameter βH(S) and the control signal Vg curve, and the capacitor C of the negative impedance generator 130 provides the third parameter γK(S) and the control signal Vg curve. The aforementioned curves of the first parameter αY(S) and the control signal Vg, the second parameter βH(S) and the control signal Vg, and the third parameter γK(S) and the control signal Vg curve are used to cancel out the parasitic capacitance A(S) and the control signal curve Vg. Therefore, the equivalent parasitic capacitance X(S) of the first transistor M1 is smaller than the initial parasitic capacitance A(S), and the equivalent parasitic capacitance X(S) hardly changes with the bias voltage.
[0026] Figure 5 A schematic diagram of a parasitic capacitance elimination circuit 100 is provided based on some embodiments of this invention. Compared to Figure 4 Parasitic capacitance elimination circuit 100, Figure 5 The parasitic capacitance elimination circuit 100A further includes a first power supply 140A and a second power supply 150A. For example... Figure 5 As shown, the first power supply 140A provides a first power supply to the base terminal of the second transistor M2. The second power supply 150A provides a second power supply to the base terminal of the third transistor M3. For an understanding of the effects of the first power supply 140A and the second power supply 150A, please refer to the following sections. Figure 6 .
[0027] Figure 6 This diagram illustrates the electrical characteristics of a parasitic capacitance elimination circuit 100A according to some embodiments of the present invention. The initial parasitic capacitance of the first transistor M1 is A(S). In this invention, a first parameter αY(S) can be provided by a first coupler 110A, and a first power supply 140A can be provided to the base of the second transistor M2 to adjust the curve of the first parameter αY(S) and the control signal Vg. When the first power supply increases, the base voltage of the second transistor M2 increases, and the curve of the first parameter αY(S) and the control signal Vg shifts to the left. When the first power supply decreases, the base voltage of the second transistor M2 decreases, and the curve of the first parameter αY(S) and the control signal Vg shifts to the right.
[0028] Further, the second parameter βH(S) can be provided by the second coupler 120A, and the second power source can be provided by the second power supply 150A to the base of the third transistor M3 to adjust the second parameter βH(S) and the control signal Vg curve. When the second power source is increased, the base voltage of the third transistor M3 is increased, and the second parameter βH(S) and the control signal Vg curve are shifted to the left. When the second power source is decreased, the base voltage of the third transistor M3 is decreased, and the second parameter βH(S) and the control signal Vg curve are shifted to the right.
[0029] Therefore, the first parameter αY(S) and the control signal Vg curve and the second parameter βH(S) and the control signal Vg curve can be adjusted by the first power supply 140A and the second power supply 150A to adjust the parasitic capacitance A(S) and the control signal Vg curve, so that the initial parasitic capacitance A(S) of the first transistor M1 is adjusted to be almost unchanged with the bias voltage (such as the gate-source voltage Vgs). Further, the third parameter γK(S) is provided by the negative impedance generator 130A to form a negative impedance to offset the initial parasitic capacitance A(S) of the first transistor M1. By Figure 6 It can be known that the equivalent parasitic capacitance X(S) of the first transistor M1 is smaller than the initial parasitic capacitance A(S), and the equivalent parasitic capacitance X(S) is almost unchanged with the bias voltage.
[0030] It should be noted that the embodiments of the present application are not limited to the embodiments shown in the drawings, which are only used to exemplarily show one of the implementation manners of the present application, so that the technology of the present application is easy to understand. The modifications and decorations to the embodiments of the present application made by those skilled in the art without departing from the spirit of the present application still fall within the patent application scope of the present application. Figures 1 to 6 It should be noted that the embodiments of the present application are not limited to the embodiments shown in the drawings, which are only used to exemplarily show one of the implementation manners of the present application, so that the technology of the present application is easy to understand. The modifications and decorations to the embodiments of the present application made by those skilled in the art without departing from the spirit of the present application still fall within the patent application scope of the present application.
[0031] In summary, the technical means embodied by the embodiments of the present application can improve at least one of the shortcomings of the prior art. The parasitic capacitance elimination circuit and the parasitic capacitance elimination method can be used to offset the parasitic capacitance of the transistor, and the parasitic capacitance is almost unchanged with the bias voltage.
[0032] Although the embodiments of the present application are described above, the embodiments are not used to limit the present application. Those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit content of the present application. Any changes may fall within the scope of the patent protection sought by the present application. In other words, the patent protection scope of the present application should be defined by the patent application scope of the present specification. BRIEF DESCRIPTION OF DRAWINGS
[0034] 100: parasitic capacitance elimination circuit
[0035] 110: first coupler
[0036] 120: second coupler
[0037] 130: negative impedance generator
[0038] A(S): parasitic capacitance
[0039] M1: first transistor
[0040] M9: transistor
[0041] Vg: control signal
[0042] Vg2: signal
[0043] aY(S): first parameter
[0044] bH(S): second parameter
[0045] gK(S): third parameter
Claims
1. A parasitic capacitance elimination circuit, comprising: The first transistor includes a first terminal, a control terminal, and a second terminal; A first coupler is used to couple the control terminal of the first transistor and the first terminal; A second coupler is used to couple the control terminal of the first transistor to the second terminal; as well as A negative impedance generator is used to generate and provide a negative impedance to the control terminal of the first transistor to eliminate the parasitic capacitance of the first transistor.
2. The parasitic capacitance elimination circuit according to claim 1, wherein the first coupler includes a second transistor, the second transistor comprising: The first terminal is coupled to the first terminal of the first transistor; A control terminal, coupled to the control terminal of the first transistor; as well as The second terminal is coupled to the first terminal of the second transistor and the first terminal of the first transistor.
3. The parasitic capacitance elimination circuit according to claim 2, wherein the second coupler includes a third transistor, the third transistor comprising: The first terminal is coupled to the second terminal of the first transistor; A control terminal, coupled to the control terminal of the first transistor and the control terminal of the second transistor; as well as The second terminal is coupled to the first terminal of the third transistor and the second terminal of the first transistor.
4. The parasitic capacitance elimination circuit according to claim 3, wherein the parasitic capacitance of the first transistor includes a parasitic capacitance and control signal curve, the second transistor is used to provide a first parameter and control signal curve, and the third transistor is used to provide a second parameter and control signal curve, wherein the first parameter and control signal curve and the second parameter and control signal curve are used to adjust the parasitic capacitance and control signal curve.
5. The parasitic capacitance elimination circuit according to claim 4, further comprising: A first power supply is used to provide a first power supply to the base terminal of the second transistor.
6. The parasitic capacitance elimination circuit according to claim 5 further comprises: A second power supply is provided to the base terminal of the third transistor.
7. The parasitic capacitance elimination circuit according to claim 6, wherein the first power supply adjusts the first parameter and control signal curve by adjusting the first power supply, and the second power supply adjusts the second parameter and control signal curve by adjusting the second power supply.
8. The parasitic capacitance elimination circuit according to claim 7, wherein the adjusted first parameter and control signal curve and the adjusted second parameter and control signal curve are used to adjust the parasitic capacitance and control signal curve.
9. The parasitic capacitance elimination circuit according to claim 1, wherein the negative impedance generator includes a capacitor, the capacitor comprising: The first terminal is used to receive the first control signal; as well as The second terminal is coupled to the control terminal of the first transistor; The control terminal of the first transistor is used to receive a second control signal, wherein the negative impedance generator provides the negative impedance to the control terminal of the first transistor according to the first control signal.
10. A method for eliminating parasitic capacitance, comprising: The first coupler is used to couple one of the control terminals of the first transistor to the first terminal; The control terminal and the second terminal of the first transistor are coupled by means of a second coupler; as well as A negative impedance generator is used to generate and provide a negative impedance to the control terminal of the first transistor to eliminate the parasitic capacitance of the first transistor.