Phase-locked loop chip, frequency switching method of phase-locked loop chip and display equipment

Abstract

The invention discloses a phase-locked loop chip, a frequency switching method of the phase-locked loop chip and display equipment, in the phase-locked loop chip, a control module configures a reference clock signal for a phase-locked loop circuit and generates and sends a clock switching control signal; the spread spectrum modulation circuit generates a frequency modulation step value according to the frequency division coefficient and the modulation coefficient under the control of the clock switching control signal; and the phase-locked loop circuit performs frequency adjustment on the feedback clock signal by using the frequency modulation step value to generate an output clock signal, wherein the frequency of the output clock signal is consistent with that of the reference clock signal. Because the frequency modulation step value is determined according to the frequency division coefficient and the modulation coefficient of spread spectrum modulation, the frequency modulation step value is used for frequency adjustment, so that the lock loss abnormity can be effectively avoided, the system stability is improved, the spread spectrum modulation circuit is multiplexed, other devices do not need to be additionally arranged, the chip cost is reduced, and the power consumption is reduced. And a small-step multi-frequency frequency approximation mode is adopted, so that the frequency switching time is shortened, and the chip performance is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and in particular to a phase-locked loop chip, a frequency switching method of the phase-locked loop chip, and a display device. BACKGROUND

[0002] A phase-locked loop (PLL) is a negative feedback control system that uses a phase-synchronized voltage to tune a voltage-controlled oscillator (VCO) to generate a target frequency. The phase-locked loop is a basic functional module integrated in a chip, and thus the stability and reliability of the phase-locked loop directly affect the overall performance of the chip.

[0003] In actual applications, because chips have different application scenarios, when the application scenario of the chip is switched, the phase-locked loop needs to be reconfigured, that is, a new frequency point needs to be loaded for the phase-locked loop, so that the voltage-controlled oscillator inside the phase-locked loop is relocked at the new frequency point. However, when the gap between the current and the previous two frequency points is large, the voltage-controlled oscillator is prone to lose lock.

[0004] To avoid the occurrence of the loss of lock, in the related art, before the frequency point of the phase-locked loop is switched, the relevant functional modules inside the chip are switched to a special mode, the potentially affected functional modules are closed, and after the phase-locked loop is phase-locked, the relevant functional modules are opened again. However, the above-mentioned method for avoiding the loss of lock needs software process intervention for state monitoring and switching, and thus the frequency switching process is time-consuming and inefficient. SUMMARY

[0005] The present application provides a phase-locked loop chip, a frequency switching method of the phase-locked loop chip, and a display device, to solve the problem that the frequency switching process is time-consuming and inefficient in the prior art method for avoiding the loss of lock of the phase-locked loop.

[0006] In a first aspect, an embodiment of the present application provides a phase-locked loop chip, comprising a phase-locked loop circuit, a spread spectrum modulation circuit, and a control module, wherein:

[0007] The control module is electrically connected to the phase-locked loop circuit and the spread spectrum modulation circuit, and the phase-locked loop circuit is electrically connected to the spread spectrum modulation circuit.

[0008] The control module is configured to configure a reference clock signal for the phase-locked loop circuit and generate a clock switching control signal sent to the spread spectrum modulation circuit.

[0009] The spread spectrum modulation circuit is configured to generate a frequency modulation step value according to the frequency division coefficient and the modulation coefficient under the control of the clock switching control signal, and send the frequency modulation step value to the phase-locked loop circuit.

[0010] The phase-locked loop circuit is configured to adjust the frequency of a feedback clock signal by using the frequency modulation step value to generate an output clock signal, wherein the frequency of the output clock signal is consistent with the frequency of the reference clock signal.

[0011] In the phase-locked loop chip provided by the embodiment of the present application, the frequency modulation step value is generated by multiplexing the spread spectrum modulation circuit and using the frequency division coefficient and the modulation coefficient in the spread spectrum modulation circuit, and the phase-locked loop circuit uses the frequency modulation step value to adjust the frequency of the feedback clock signal in small steps and multiple frequencies, gradually approximates the frequency of the reference clock signal, so as to realize frequency switching and relocking. Since the frequency modulation step value is determined according to the frequency division coefficient and the modulation coefficient of the spread spectrum modulation, the frequency adjustment by using the frequency modulation step value can effectively avoid the phase-locked loop circuit from losing lock and improve the stability of the system. In addition, by multiplexing the spread spectrum modulation circuit, other devices do not need to be additionally added, the chip cost can be effectively reduced, the frequency adjustment is in small steps and multiple frequencies, compared with the existing method of needing software process intervention for state monitoring and switching, the frequency switching time can be effectively shortened to the level of microseconds, the switching efficiency is improved, and the chip performance is improved.

[0012] In an optional embodiment, the control module is further configured to configure a spread spectrum period for the spread spectrum modulation circuit, and send a spread spectrum enable signal to the spread spectrum modulation circuit.

[0013] The spread spectrum modulation circuit is further configured to determine the working mode of the spread spectrum modulation circuit based on the spread spectrum enable signal and the spread spectrum period.

[0014] The working mode includes a first working mode and a second working mode, the first working mode is used to represent that the spread spectrum modulation circuit opens the frequency tracking function and closes the spread spectrum function, and the second working mode is used to represent that the spread spectrum modulation circuit opens the frequency tracking function and opens the spread spectrum function.

[0015] The above technical solution has the following advantages or beneficial effects: the control module configures a spread spectrum period for the spread spectrum modulation circuit and generates a spread spectrum enable signal, the spread spectrum modulation circuit can control the working mode according to the set spread spectrum period and the level state of the spread spectrum enable signal, so as to realize the multiplexing of the spread spectrum modulation circuit. The frequency switching control can be realized by multiplexing the spread spectrum modulation circuit, and other devices do not need to be additionally added, therefore, compared with the existing method of additionally adding a phase-locked loop for generating a secure clock signal, the method provided by the embodiment of the present application can effectively reduce the chip cost.

[0016] In an optional embodiment, when the spread spectrum modulation circuit is in the first working mode, the spread spectrum modulation circuit is specifically configured to generate the frequency modulation step value according to the sum of the frequency division coefficient and the modulation coefficient under the control of the clock switching control signal.

[0017] Wherein, after receiving the clock switching control signal, the phase-locked loop circuit adjusts the frequency of the feedback clock signal first adjusted by the frequency modulation step value to be consistent with the frequency of the reference clock signal previously configured by the control module.

[0018] The above technical solution has the following advantages or beneficial effects: when the spread spectrum modulation circuit only enables the frequency tracking function and does not enable the spread spectrum function, since the spread spectrum function is not enabled in this case, there is no spread spectrum adjustment on the clock signal generated by the phase-locked loop circuit. At this time, the spread spectrum modulation circuit directly generates the frequency modulation step value under the control of the clock switching control signal and sends the generated frequency modulation step value to the phase-locked loop circuit. Since the frequency modulation step value is determined according to the frequency division coefficient and the modulation coefficient of the spread spectrum modulation, frequency adjustment using the frequency modulation step value can effectively avoid the phase-locked loop circuit from losing lock and improve the stability of the system.

[0019] In an optional embodiment, when the spread spectrum modulation circuit is in the second working mode, the spread spectrum modulation circuit is further configured to generate a spread spectrum modulation signal according to the frequency division coefficient and the modulation coefficient, and send the spread spectrum modulation signal to the phase-locked loop circuit.

[0020] The phase-locked loop circuit is further configured to perform spread spectrum modulation on the output clock signal according to the spread spectrum modulation signal, and output the spread spectrum modulated output clock signal.

[0021] The above technical solution has the following advantages or beneficial effects: when the spread spectrum modulation circuit simultaneously enables the frequency tracking function and the spread spectrum function, the spread spectrum modulation circuit will determine the spread spectrum modulation signal according to the frequency division coefficient and the modulation coefficient before the phase-locked loop circuit performs frequency switching and after completing frequency switching, and perform spread spectrum modulation on the clock signal generated by the phase-locked loop circuit using the spread spectrum modulation signal. The frequency of the output clock signal of the phase-locked loop circuit will be frequency dithered in a small range with a fixed period, thereby expanding the narrowband spectrum, dispersing the radiant energy, and achieving the purpose of reducing electromagnetic interference (English: Electromagnetic Interference, EMI for short).

[0022] In an optional embodiment, when the spread spectrum modulation circuit is in the second working mode, the spread spectrum modulation circuit is specifically configured to:

[0023] stop generating the spread spectrum modulation signal and generate the frequency modulation step value according to the sum of the frequency division coefficient and the modulation coefficient after receiving the clock switching control signal;

[0024] wherein, after receiving the clock switching control signal, the frequency of the feedback clock signal first adjusted by the phase-locked loop circuit using the frequency modulation step value is inconsistent with the frequency of the reference clock signal previously configured by the control module.

[0025] The above technical solution has the following advantages or beneficial effects: when the spread spectrum modulation circuit simultaneously opens the frequency tracking function and the spread spectrum function, the spread spectrum modulation circuit needs to stop spread spectrum modulation first after receiving the clock switching control signal, then generate the frequency modulation step value, and send the generated frequency modulation step value to the phase-locked loop circuit. Through the above-mentioned manner, time multiplexing of the spread spectrum modulation circuit is realized. By multiplexing the spread spectrum modulation circuit, the phase-locked loop circuit is prevented from losing lock, which is not only suitable for a single phase-locked loop chip, but also suitable for a chip integrated with multiple phase-locked loops, and no additional devices are needed, thereby effectively reducing the chip cost.

[0026] In an optional embodiment, the spread spectrum modulation circuit is specifically used for:

[0027] When it is identified that the level state of the spread spectrum enable signal is the valid level state and the spread spectrum period is a first set value, the spread spectrum modulation circuit enters the first working mode;

[0028] When it is identified that the level state of the spread spectrum enable signal is the valid level state and the spread spectrum period is a second set value, the spread spectrum modulation circuit enters the second working mode;

[0029] wherein, the first set value and the second set value are different.

[0030] The above technical solution has the following advantages or beneficial effects: the spread spectrum modulation circuit can control whether to simultaneously open the spread spectrum and frequency tracking functions or only open the frequency tracking function according to the spread spectrum period and the level state of the spread spectrum enable signal, thereby realizing multiplexing of the spread spectrum modulation circuit. By multiplexing the spread spectrum modulation circuit, frequency switching control can be realized, and no additional devices are needed, thereby effectively reducing the chip cost.

[0031] In an optional embodiment, the phase-locked loop circuit includes a core module and a feedback frequency divider, wherein:

[0032] one input end of the core module is used for receiving the reference clock signal, another input end of the core module is electrically connected with the output end of the feedback frequency divider, and the output end of the core module is electrically connected with the input end of the feedback frequency divider.

[0033] The control end of the feedback frequency divider is electrically connected with the output end of the spread spectrum modulation circuit, for receiving the frequency modulation step value output by the spread spectrum modulation circuit;

[0034] The core module is configured to generate an intermediate clock signal based on the reference clock signal and the adjusted feedback clock signal, and take the adjusted feedback clock signal with a frequency equal to the first frequency as the output clock signal;

[0035] The feedback frequency divider is configured to perform frequency division processing on the intermediate clock signal to generate the feedback clock signal, and perform frequency adjustment processing on the feedback clock signal by using the frequency modulation step value, and send the adjusted feedback clock signal to the core module;

[0036] The first frequency is used to represent the frequency of the reference clock signal, and the frequency of the adjusted feedback clock signal is the sum of the frequency of the unadjusted feedback clock signal and the frequency modulation step value.

[0037] The above technical solution has the following advantages or beneficial effects: the feedback frequency divider adjusts the frequency of the clock signal output by the core module by using the received frequency modulation step value, so that the frequency of the feedback clock signal is gradually approximated to the frequency of the reference clock signal in a small-step and multi-frequency adjustment manner; when the core module identifies that the frequency of the adjusted feedback clock signal is consistent with the frequency of the reference clock signal, it means that the frequency switching has been completed, and the frequency relocking is achieved. In this way, the gradual and step-by-step adjustment manner can not only effectively avoid the loss of lock of the phase-locked loop circuit and improve the stability of the system, but also effectively shorten the frequency switching time and achieve a frequency switching efficiency of microsecond level.

[0038] In an optional embodiment, the control module is specifically configured to: at a first time, configure the reference clock signal for the phase-locked loop circuit, and at a second time, generate the clock switching control signal, wherein the first time is earlier than the second time.

[0039] The above technical solution has the following advantages or beneficial effects: by setting the time when the control module configures the reference clock signal of the new frequency to be earlier than the time when the clock switching control signal is generated, it is ensured that the frequency relocking is performed only after the new frequency value is set, so as to ensure the system stability of the chip.

[0040] In a second aspect, the embodiments of the present application provide a frequency switching method of a phase-locked loop chip, comprising:

[0041] The control module is configured to configure the reference clock signal for the phase-locked loop circuit, and generate the clock switching control signal sent to the spread spectrum modulation circuit;

[0042] The spread spectrum modulation circuit generates a frequency modulation step value according to the frequency division coefficient and the modulation coefficient under the control of the clock switching control signal, and sends the frequency modulation step value to the phase-locked loop circuit.

[0043] The phase-locked loop circuit adjusts the frequency of the feedback clock signal by using the frequency modulation step value to generate an output clock signal, wherein the frequency of the output clock signal is consistent with the frequency of the reference clock signal.

[0044] In an optional embodiment, before the control module configures the reference clock signal for the phase-locked loop circuit, it further comprises:

[0045] The control module configures a spread spectrum period for the spread spectrum modulation circuit, and sends a spread spectrum enable signal to the spread spectrum modulation circuit.

[0046] Based on the spread spectrum enable signal and the spread spectrum period, the working mode of the spread spectrum modulation circuit is determined.

[0047] The working mode includes a first working mode and a second working mode, the first working mode is used to represent that the spread spectrum modulation circuit opens the frequency tracking function and closes the spread spectrum function, and the second working mode is used to represent that the spread spectrum modulation circuit opens the frequency tracking function and opens the spread spectrum function.

[0048] In an optional embodiment, when the spread spectrum modulation circuit is in the first working mode, the spread spectrum modulation circuit generates a frequency modulation step value according to the frequency division coefficient and the modulation coefficient under the control of the clock switching control signal, which comprises:

[0049] The spread spectrum modulation circuit generates the frequency modulation step value according to the sum of the frequency division coefficient and the modulation coefficient under the control of the clock switching control signal.

[0050] After receiving the clock switching control signal, the phase-locked loop circuit adjusts the frequency of the feedback clock signal by using the frequency modulation step value for the first time, which is consistent with the frequency of the reference clock signal configured by the control module last time.

[0051] In an optional embodiment, when the spread spectrum modulation circuit is in the second working mode, it further comprises:

[0052] The spread spectrum modulation circuit generates a spread spectrum modulation signal according to the frequency division coefficient and the modulation coefficient, and sends the spread spectrum modulation signal to the phase-locked loop circuit.

[0053] The phase-locked loop circuit performs spread spectrum modulation on the output clock signal according to the spread spectrum modulation signal, and outputs the spread spectrum modulated output clock signal.

[0054] In an alternative embodiment, when the spread spectrum modulation circuit is in the second working mode, the generating of the frequency modulation step value under the control of the clock switching control signal comprises:

[0055] After receiving the clock switching control signal, the spread spectrum modulation signal is stopped being generated, and the frequency modulation step value is generated according to the sum of the frequency division coefficient and the modulation coefficient;

[0056] Wherein, after receiving the clock switching control signal, the frequency of the feedback clock signal first adjusted by the phase-locked loop circuit using the frequency modulation step value is inconsistent with the frequency of the reference clock signal previously configured by the control module.

[0057] In an alternative embodiment, the determination of the working mode of the spread spectrum modulation circuit based on the spread spectrum enable signal and the spread spectrum period comprises:

[0058] When the level state of the spread spectrum enable signal is identified as the valid level state, and the spread spectrum period is the first set value, it is determined that the working mode of the spread spectrum modulation circuit is the first working mode;

[0059] When the level state of the spread spectrum enable signal is identified as the valid level state, and the spread spectrum period is the second set value, it is determined that the working mode of the spread spectrum modulation circuit is the second working mode;

[0060] Wherein, the first set value and the second set value are different.

[0061] In an alternative embodiment, the adjustment of the frequency of the feedback clock signal using the frequency modulation step value to generate an output clock signal comprises:

[0062] Generating, by a core module, an intermediate clock signal based on the reference clock signal and the adjusted feedback clock signal, and taking the adjusted feedback clock signal with a frequency equal to a first frequency as the output clock signal;

[0063] Frequency dividing, by a feedback frequency divider, the intermediate clock signal to generate the feedback clock signal, and adjusting the frequency of the feedback clock signal using the frequency modulation step value, and sending the adjusted feedback clock signal to the core module;

[0064] Wherein, the first frequency is used to represent the frequency of the reference clock signal, and the frequency of the adjusted feedback clock signal is the sum of the frequency of the feedback clock signal before adjustment and the frequency modulation step value.

[0065] In an alternative embodiment, the control module configures a reference clock signal for the phase-locked loop circuit and generates a clock switching control signal sent to the spread spectrum modulation circuit, comprising:

[0066] At a first time, the control module configures the reference clock signal for the phase-locked loop circuit, and at a second time, the control module generates the clock switching control signal, wherein the first time is earlier than the second time.

[0067] In a third aspect, the embodiments of the present application provide a display device comprising the phase-locked loop chip according to any one of the embodiments of the first aspect.

[0068] The frequency switching method of the phase-locked loop chip disclosed in the second aspect and the display device disclosed in the third aspect can achieve the technical effects as described above for the first aspect or various possible solutions in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0070] Figure 1 A working timing diagram of a phase-locked loop provided by the related art for frequency locking;

[0071] Figure 2 A schematic diagram for avoiding phase-locked loop loss provided by the related art;

[0072] Figure 3 An application scenario diagram of a phase-locked loop chip provided by the embodiments of the present application;

[0073] Figure 4 A module structure diagram of a phase-locked loop chip provided by the embodiments of the present application;

[0074] Figure 5 A structure diagram of a phase-locked loop circuit in a phase-locked loop chip provided by the embodiments of the present application;

[0075] Figure 6 A structure diagram of a core module in a phase-locked loop circuit provided by the embodiments of the present application;

[0076] Figure 7 A working timing diagram of a phase-locked loop circuit provided by the embodiments of the present application for frequency switching;

[0077] Figure 8 A working timing diagram of a spread spectrum modulation circuit in a first working mode is provided for an embodiment of the present application.

[0078] Figure 9 A working timing diagram of a spread spectrum modulation circuit in a second working mode is provided for an embodiment of the present application.

[0079] Figure 10 A waveform diagram of a spread spectrum modulation signal is provided for an embodiment of the present application.

[0080] Figure 11 A complete working flow diagram of a phase-locked loop chip is provided for an embodiment of the present application.

[0081] Figure 12 A working flow diagram of a frequency switching method of a phase-locked loop chip is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0082] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0083] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all the embodiments consistent with the present application. On the contrary, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0084] As mentioned above, the phase-locked loop is a basic functional module integrated in the chip, and thus the stability and reliability of the phase-locked loop will directly affect the overall performance of the chip. In practical applications, the chip will be applied in various different scenarios, such as power consumption mode switching, working voltage variation, temperature variation, working load updating and other application scenarios, and the configuration requirements of the chip in different application scenarios will also be different.

[0085] Therefore, when the application scenario of the chip is switched, the phase-locked loop needs to be reconfigured, that is, a new frequency setting value needs to be loaded for the phase-locked loop, so that the voltage-controlled oscillator inside the phase-locked loop is re-locked at the new frequency setting value. However, when the gap between the current and the previous two frequency setting values is large, the voltage-controlled oscillator is prone to lose lock.

[0086] Figure 1 A working timing diagram of frequency locking of a phase-locked loop provided by a related technology is shown. As shown in Figure 1 , when the phase-locked loop is configured, the original frequency setting value 1 is changed to a new frequency setting value 2, and then the working frequency point of the voltage-controlled oscillator in the phase-locked loop is re-locked from the frequency setting value 1 to the frequency setting value 2. However, during the re-locking from the frequency setting value 1 to the frequency setting value 2, the phase-locked loop is in an unstable state and is prone to lose lock, which will result in unstable clock output and thus abnormal system.

[0087] To avoid the occurrence of the loss of lock, the following solutions are usually used in the related technology:

[0088] Solution one: for a chip integrated with multiple phase-locked loops, a phase-locked loop for generating a safe clock signal is separately arranged. During frequency switching, first, the application clock signal output to the subsequent functional module is switched from the output clock signal of the phase-locked loop to be locked to the stable safe clock signal, and then the phase-locked loop is re-locked in frequency, and after the locking is completed, the application clock signal is switched back to the output clock signal of the phase-locked loop.

[0089] Figure 2 A diagram for avoiding loss of lock of a phase-locked loop provided by a related technology is shown. As shown in Figure 2 , the chip 10 is integrated with a phase-locked loop PLL1, a phase-locked loop PLL2 and a selector MUX1. The output end of the phase-locked loop PLL1 is electrically connected to one input end of the selector MUX1, and the output end of the phase-locked loop PLL2 is electrically connected to the other input end of the selector MUX1. The selector MUX1 is used to output an application clock signal to an in-chip functional module, wherein:

[0090] In the case that the phase-locked loop PLL1 normally works, the selector MUX1 outputs the clock signal PLL1_CLK generated by the phase-locked loop PLL1 and sends the clock signal PLL1_CLK as an application clock signal to the in-chip functional module. During frequency locking of the phase-locked loop PLL1, the selector MUX1 outputs the safe clock signal SAFE_CLK generated by the phase-locked loop PLL2 and sends the safe clock signal SAFE_CLK to the in-chip functional module.

[0091] Although this mode can avoid the influence of signal disturbance caused by lock loss on the internal functional modules to some extent, it cannot fundamentally solve the lock loss problem, and an additional phase-locked loop for generating a safe clock signal needs to be additionally arranged in the chip, which not only increases the cost of the chip, but also is not suitable for a single phase-locked loop chip.

[0092] Mode two: for a chip integrating only one phase-locked loop, the internal related functional modules of the chip are switched to a special mode before the phase-locked loop performs frequency switching, the potentially affected functional modules are closed, and the related functional modules are opened again after the phase-locked loop is monitored to complete the phase locking. However, the above-mentioned mode for avoiding lock loss needs software process intervention for state monitoring and switching, and therefore, the frequency switching process reaches the millisecond level, which is time-consuming and low in efficiency.

[0093] In addition, in the actual application of the chip, if the frequency of the output clock signal of the phase-locked loop always remains a fixed value, the electromagnetic interference of the internal system of the chip will be more serious, and the system is easy to be damaged. Therefore, in order to reduce the electromagnetic interference of the working frequency of the phase-locked loop, the phase-locked loop in the chip usually supports a certain specification of spread spectrum function. Specifically, the phase-locked loop is connected with a spread spectrum modulation circuit, the spread spectrum modulation circuit adjusts the feedback frequency divider connected with the voltage controlled oscillator in the phase-locked loop, so that the frequency of the output clock signal of the phase-locked loop is frequency dithered in a small range with a fixed period, the narrowband spectrum is expanded, the radiant energy is dispersed, and the purpose of reducing EMI is achieved.

[0094] Based on this, the embodiment of the present application provides a phase-locked loop chip, a frequency switching method of the phase-locked loop chip and a display device. By multiplexing the spread spectrum modulation circuit in the chip, the step length setting of the spread spectrum modulation function is used to re-lock the frequency of the phase-locked loop in a small step and multiple frequency mode, which can not only effectively avoid the lock loss abnormality of the phase-locked loop, but also shorten the frequency switching time and improve the stability of the internal system of the chip.

[0095] The object implementation, functional characteristics and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0096] The application scene of the phase-locked loop chip provided by the embodiment of the present application will be introduced below in combination with the accompanying drawings:

[0097] The phase-locked loop chip provided by the embodiment of the present application can be arranged in various display devices. Figure 3 An application scene schematic diagram of the improved phase-locked loop chip according to the embodiment of the present application is shown. As shown in FIG. 1, the phase-locked loop chip is arranged in a display device. Figure 3As shown, the application scenario includes a display device 20, and the display device 20 is provided with a system on chip (System on Chip, SoC for short), which is a phase-locked loop chip improved by the embodiment of the application.

[0098] Specifically, when the display device 20 is switched from a normal working mode to a sleep mode, the power consumption mode of the display device 20 also changes accordingly, and the working mode of the on-chip functional modules of the SoC also changes accordingly. At this time, the clock signals adapted to the working modes of these functional modules need to be provided for these functional modules, and therefore, a new frequency value needs to be set for the phase-locked loop in the SoC to change the frequency of the clock signal generated by the phase-locked loop. In the process of frequency switching of the phase-locked loop, the frequency relocking in the manner provided by the embodiment of the application can not only effectively avoid the loss of lock of the phase-locked loop and improve the stability of the on-chip system, but also shorten the frequency switching time and improve the performance of the chip.

[0099] It should be noted that the specific type of the display device is not limited in the embodiment of the application. For example, the display device in the embodiment of the application can be an electronic device with an image display device (such as a display panel) ; for example, it can be a smart terminal, a smart mobile terminal, a tablet computer, a notebook computer, a smart handheld device, a personal computer (Personal Computer, PC for short), a computer, a smart screen, a display device, a vehicle-mounted device, various wearable devices, a personal digital assistant (Personal Digital Assistant, PDA for short), etc.; wherein, the wearable device is, for example, a virtual reality (Virtual Reality, VR for short) device, an augmented reality (Augmented Reality, AR for short) device, etc.

[0100] Of course, the device provided by the embodiment of the application is not limited to the display device. Figure 3 The application scenario shown can also be used in other possible application scenarios, for example, a television, a notebook computer, etc., and the embodiment of the application does not limit the application scenario. For the functions that can be achieved by each part of the application scenario shown, the functions will be described together in subsequent embodiments, and no more details are described here. Figure 3 The functions that can be achieved by each part of the application scenario shown will be described together in subsequent embodiments, and no more details are described here.

[0101] After the application scenario of the embodiment of the application is introduced, the preferred embodiments of the application will be further described in detail with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the application, and are not used to limit the application, and the features of the embodiments and the embodiments can be combined with each other without conflict.

[0102] The phase-locked loop chip provided by the embodiment of the application will be specifically introduced below with reference to the accompanying drawings.

[0103] Figure 4 A module structure schematic diagram of a phase-locked loop chip is shown. Figure 4 As shown, the phase-locked loop chip 30 comprises a phase-locked loop circuit 31, a spread spectrum modulation circuit 32 and a control module 33, the control module 33 is electrically connected with the phase-locked loop circuit 31 and the spread spectrum modulation circuit 32 respectively, and the phase-locked loop circuit 31 is electrically connected with the spread spectrum modulation circuit 32; wherein:

[0104] The control module 33 is configured to configure a reference clock signal CLK_ref for the phase-locked loop circuit 31, and generate a clock switching control signal sent to the spread spectrum modulation circuit 32;

[0105] The spread spectrum modulation circuit 32 is configured to generate a frequency modulation step value step_f according to a frequency division coefficient reg_fbdiv and a modulation coefficient δ under the control of the clock switching control signal, and send the frequency modulation step value step_f to the phase-locked loop circuit 31;

[0106] The phase-locked loop circuit 31 is configured to adjust the frequency of a feedback clock signal by using the frequency modulation step value step_f, and generate an output clock signal CLK_out, wherein the frequency f_out of the output clock signal CLK_out is consistent with the frequency f_ref1 of the reference clock signal CLK_ref.

[0107] In the phase-locked loop chip 30 provided by the embodiment of the present application, the spread spectrum modulation circuit 32 is multiplexed, the frequency modulation step value is generated by using the frequency division coefficient and the modulation coefficient for spread spectrum modulation in the spread spectrum modulation circuit 32, and the phase-locked loop circuit 31 uses the frequency modulation step value to adjust the frequency of the feedback clock signal in small steps and multiple frequencies, gradually approaches the frequency of the reference clock signal, so as to realize the switching and relocking of the frequency. Since the frequency modulation step value is determined according to the frequency division coefficient and the modulation coefficient for spread spectrum modulation, the frequency adjustment by using the frequency modulation step value can effectively avoid the abnormal loss of lock of the phase-locked loop circuit 31, and improve the stability of the system.

[0108] In addition, by multiplexing the spread spectrum modulation circuit 32, other devices do not need to be additionally added, the chip cost can be effectively reduced, the frequency adjustment mode in small steps and multiple frequencies is adopted, compared with the existing mode of needing software process intervention for state monitoring and switching, the frequency switching time can be effectively shortened to the level of microsecond, the switching efficiency is improved to the level of microsecond, and the chip performance is improved.

[0109] The modules in the phase-locked loop chip provided by the embodiment of the present application will be specifically introduced as follows:

[0110] Figure 5 A structure schematic diagram of a phase-locked loop circuit in a phase-locked loop chip is shown. Figure 5As shown, the phase-locked loop circuit 31 comprises a core module 311 and a feedback frequency divider 312, wherein:

[0111] One input terminal of the core module 311 is configured to receive a reference clock signal CLK_ref, another input terminal of the core module 311 is electrically connected with an output terminal of the feedback frequency divider 312, and an output terminal of the core module 311 is electrically connected with an input terminal of the feedback frequency divider 312, so that the core module 311 and the feedback frequency divider 312 form a feedback loop; a control terminal of the feedback frequency divider 312 is electrically connected with an output terminal of the spread spectrum modulation circuit 32, and is configured to receive a frequency modulation step value step_f output by the spread spectrum modulation circuit 32.

[0112] The core module 311 is configured to generate an intermediate clock signal based on the reference clock signal CLK_ref and an adjusted feedback clock signal CLK_fbdiv, and take the adjusted feedback clock signal CLK_fbdiv with a frequency equal to a first frequency f_ref1 as an output clock signal CLK_out, wherein the first frequency f_ref1 is used to represent the frequency of the reference clock signal CLK_ref.

[0113] Further, Figure 6 A structural schematic diagram of a core module in a phase-locked loop circuit is shown. As shown in Figure 6 The core module 311 comprises a phase detector (PD) 3111, a charge pump (CP) 3112, a filter 3113 and a voltage-controlled oscillator 3114, which are electrically connected in sequence, an input terminal of the feedback frequency divider 312 is electrically connected with an output terminal of the voltage-controlled oscillator 3114, and an output terminal of the feedback frequency divider 312 is electrically connected with an input terminal of the phase detector 3111.

[0114] The phase detector 3111 is configured to receive the reference clock signal CLK_ref and the feedback clock signal CLK_fbdiv output by the feedback frequency divider 312, and compare the phase of the reference clock signal CLK_ref with the phase of the feedback clock signal CLK_fbdiv, to generate a pulse signal.

[0115] In a specific implementation, the phase detector 3111 generates a corresponding pulse signal according to the magnitude relationship between the phase of the reference clock signal CLK_ref and the phase of the feedback clock signal CLK_fbdiv. For example, when the phase detector 3111 identifies that the phase of the feedback clock signal CLK_fbdiv is less than the phase of the reference clock signal CLK_ref, an up pulse signal, i.e., an UP signal, is generated; when the phase detector 3111 identifies that the phase of the feedback clock signal CLK_fbdiv is greater than the phase of the reference clock signal CLK_ref, a down pulse signal, i.e., a DN signal, is generated.

[0116] The charge pump 3112 is configured to perform a charging / discharging operation under the control of the pulse signal and output a first voltage control signal. For example, when the charge pump 3112 receives the up pulse signal, a charging operation is performed; when the charge pump 3112 receives the down pulse signal, a discharging operation is performed.

[0117] The filter 3113 is configured to filter the first voltage control signal to generate a second voltage control signal. In actual applications, the filter 3113 in the embodiment of the present application can be a loop low pass filter (Low Pass Filter, LPF for short).

[0118] The voltage-controlled oscillator 3114 is configured to generate an intermediate clock signal under the control of the second voltage control signal and send the intermediate clock signal to the feedback frequency divider 312.

[0119] The feedback frequency divider 312 is configured to divide the intermediate clock signal to generate a feedback clock signal CLK_fbdiv and adjust the frequency of the feedback clock signal CLK_fbdiv by using a frequency adjustment step value step_f, and send the adjusted feedback clock signal CLK_fbdiv to the phase detector 3111.

[0120] In some embodiments, when the feedback frequency divider 312 adjusts the frequency of the feedback clock signal CLK_fbdiv, the frequency of the adjusted feedback clock signal is the sum of the frequency of the unadjusted feedback clock signal and the frequency adjustment step value.

[0121] In a specific implementation, assuming that the control module 33 last configured the frequency of the reference clock signal for the phase-locked loop circuit 31 as f_ref0 and this time configured the frequency of the reference clock signal for the phase-locked loop circuit 31 as a first frequency f_ref1, the phase-locked loop circuit 31 can switch the frequency f_ref0 to the first frequency f_ref1 in the following manner:

[0122] The first frequency adjustment process: the feedback frequency divider 312 generates the feedback clock signal CLK_fbdiv, at this time, the frequency of the feedback clock signal CLK_fbdiv is f_ref0, then the frequency of the feedback clock signal CLK_fbdiv is adjusted by using the frequency adjustment step value step_f, the frequency of the adjusted feedback clock signal CLK_fbdiv is f_ref0+step_f, and the adjusted feedback clock signal CLK_fbdiv is sent to the phase detector 3111.

[0123] The second frequency adjustment process: the feedback frequency divider 312 generates the feedback clock signal CLK_fbdiv, at this time, the frequency of the feedback clock signal CLK_fbdiv is f_ref0+step_f, then the frequency of the feedback clock signal CLK_fbdiv is adjusted by using the frequency adjustment step value step_f, the frequency of the adjusted feedback clock signal CLK_fbdiv is f_ref0+2×step_f, and the adjusted feedback clock signal CLK_fbdiv is sent to the phase detector 3111.

[0124] In this way, until the phase detector 3111 detects that the frequency of the adjusted feedback clock signal CLK_fbdiv is consistent with the first frequency f_ref1, the frequency switching is completed.

[0125] Wherein, if the frequency f_ref0 before the reconfiguration is less than the first frequency f_ref1 after the reconfiguration, the generated frequency adjustment step value step_f is positive. In the process of adjusting the frequency of the feedback clock signal CLK_fbdiv by using the frequency adjustment step value step_f, the frequency of the feedback clock signal CLK_fbdiv will increase by one frequency adjustment step value step_f every time, until the first frequency f_ref1 is reached.

[0126] If the frequency f_ref0 before the reconfiguration is greater than the first frequency f_ref1 after the reconfiguration, the generated frequency adjustment step value step_f is negative. In the process of adjusting the frequency of the feedback clock signal CLK_fbdiv by using the frequency adjustment step value step_f, the frequency of the feedback clock signal CLK_fbdiv will decrease by one frequency adjustment step value step_f every time, until the first frequency f_ref1 is reached.

[0127] Figure 7 The working timing diagram of the phase-locked loop circuit for frequency switching is shown. As shown in FIG. 4, the phase-locked loop circuit includes a phase detector 3111, a loop filter 3112, a voltage controlled oscillator 3113, a feedback frequency divider 312, and a frequency adjustment step value generator 313. Figure 7As shown, during the process of setting the reference clock signal for the phase-locked loop circuit 31, the frequencies of the reference clock signal are set sequentially as f1, f2, and f3, with the relationship between the three frequency values ​​being: f2 > f1 > f3. During the frequency switching process of the phase-locked loop circuit 31, the feedback divider 312, based on the received frequency modulation step size value step_f, adjusts the frequency of the clock signal generated by the voltage-controlled oscillator 3114 from f1 to f2 through multiple adjustments; then, during the next frequency switching process, the frequency of the clock signal generated by the voltage-controlled oscillator 3114 is gradually decreased from f2 to f3.

[0128] like Figure 7 As shown, when the phase-locked loop circuit 31 switches between two frequencies, the slope corresponding to the dashed line in the figure can represent the frequency modulation step size value step_f. From Figure 7 The waveform diagram of the clock signal generated by the medium-voltage controlled oscillator clearly shows that the slope corresponding to the switching from frequency f1 to frequency f2 is significantly gentler than the slope corresponding to the switching from frequency f2 to frequency f3. Therefore, the frequency modulation step size step_f corresponding to the switching from frequency f1 to frequency f2 can be different from the frequency modulation step size step_f corresponding to the switching from frequency f2 to frequency f3.

[0129] In this embodiment of the invention, the frequency modulation step size value step_f may be the same or different during different frequency switching processes. It can be flexibly set according to actual business needs, and this embodiment of the invention does not impose any restrictions on it.

[0130] In specific implementation, after receiving the feedback clock signal CLK_fbdiv output by the feedback divider 312, the phase detector 3111 continues to cycle through the above process until the phase detector 3111 recognizes that the received feedback clock signal CLK_fbdiv is consistent with the first frequency f_ref1 of the reference clock signal CLK_ref. Then it is considered that the frequency has been relocked, and the clock signal generated by the voltage-controlled oscillator 3114 is used as the output clock signal CLK_out and output to the subsequent stage.

[0131] In some embodiments, such as Figure 6 As shown, the core module 311 may also include a frequency divider 3115, which is electrically connected to the output of the frequency divider 3115. The frequency divider 3115 is used to divide the intermediate clock signal generated by the voltage-controlled oscillator 3114 according to the division coefficient reg_postdiv, and send the divided clock signal as the output clock signal CLK_out to the subsequent stage.

[0132] The frequency division coefficient reg_postdiv can be a fixed value preconfigured in a register, or can be modified by the control module 33 according to actual service requirements, and the embodiment of the application does not make any limitation in this regard.

[0133] In the above embodiment, the feedback frequency divider 312 adjusts the frequency of the clock signal output by the core module 311 by the received frequency modulation step value, so that the frequency of the feedback clock signal is gradually approximated to the frequency of the reference clock signal in a small step and multiple frequency adjustment mode; when the core module 311 identifies that the frequency of the adjusted feedback clock signal is consistent with the frequency of the reference clock signal, it means that the frequency switching has been completed, and the frequency relocking is achieved. In this way, the gradual step-by-step adjustment mode can not only effectively avoid the loss of lock of the phase-locked loop circuit and improve the stability of the system, but also effectively shorten the frequency switching time and achieve the frequency switching efficiency of microsecond level.

[0134] In some embodiments, the control module 33 can also configure a spread spectrum period for the spread spectrum modulation circuit 32, and send a spread spectrum enable signal to the spread spectrum modulation circuit 32; the spread spectrum modulation circuit 32 can determine its working mode based on the spread spectrum enable signal and the spread spectrum period.

[0135] In the embodiment of the application, the control module 33 can be a host computer. Of course, the control module 33 can also use other devices with control functions, and the embodiment of the application does not make any limitation in this regard.

[0136] When the spread spectrum modulation circuit 32 identifies that the level state of the spread spectrum enable signal is the effective level state and the spread spectrum period is the first set value, the spread spectrum modulation circuit 32 enters the first working mode; the first working mode is used to represent that the spread spectrum modulation circuit 32 opens the frequency tracking function and closes the spread spectrum function.

[0137] In specific implementation, the effective level state can be a high level, and the first set value can be 0. That is, when the spread spectrum modulation circuit 32 identifies that the spread spectrum enable signal is pulled high and the set spread spectrum period is 0, it enters the first working mode to close the spread spectrum function and start the frequency tracking function.

[0138] It should be noted that the effective level state in the embodiment of the application can also be a low level state, and the first set value can also be other values, which can be flexibly set according to actual service requirements, and the embodiment of the application does not make any limitation in this regard.

[0139] The following embodiments are described by taking the effective level state as a high level and the first set value as 0 as an example:

[0140] Figure 8A timing diagram of a spread spectrum modulation circuit in its first operating mode is shown. Figure 8 As shown, the spread spectrum period set by the control module 33 is 0x0 (=0), and when the spread spectrum enable signal changes from low level to high level, the spread spectrum modulation circuit 32 enters the first working mode.

[0141] And by Figure 8 As can be seen from the spread spectrum state signals, when the spread spectrum enable signal is low, the spread spectrum state is in the IDLE (wait) state. Since the set spread spectrum period is 0, when the spread spectrum enable signal goes high, the spread spectrum state remains in the IDLE state until the clock switching control signal sent by the control module 33 is received, at which point the IDLE state ends and the SYNC (synchronization) state begins. Frequency switching is performed while the spread spectrum modulation circuit 32 is in the SYNC state.

[0142] Furthermore, in this embodiment of the invention, the control module 33 can configure a reference clock signal for the phase-locked loop circuit 31 at a first moment and generate a clock switching control signal at a second moment, wherein the first moment is earlier than the second moment.

[0143] In practice, the timing of configuring the reference clock signal for the new frequency by the control module 33 is earlier than the timing of generating the clock switching control signal. This ensures that the frequency is relocked only after the new frequency value has been set, thus guaranteeing the system stability of the chip.

[0144] like Figure 8 As shown, when the control module 33 changes the operating frequency of the phase-locked loop circuit 31 from frequency f_ref0 to frequency f_ref1, the control module 33 starts timing and triggers the generation of a clock switching control signal when the preset duration is reached. Therefore, the first moment is earlier than the second moment, and the time difference between the first moment and the second moment is equal to the preset duration t1. In practical applications, this preset duration t1 can be flexibly set according to business requirements.

[0145] In some embodiments, when the spread spectrum modulation circuit 32 is in the first operating mode, the spread spectrum modulation circuit 32 can generate a frequency modulation step size value step_f under the control of the clock switching control signal, based on the sum of the frequency division coefficient reg_fbdiv and the modulation coefficient δ; wherein, after receiving the clock switching control signal, the frequency of the feedback clock signal CLK_fbdiv first adjusted by the feedback frequency divider 312 using the frequency modulation step size value step_f is consistent with the frequency of the reference clock signal previously configured by the control module 33.

[0146] like Figure 8As shown, since the spread spectrum modulation circuit 32 is in the first working mode, the spread spectrum function is not enabled, and thus, when the feedback frequency divider 312 first adjusts the feedback clock signal CLK_fbdiv by using the frequency modulation step value step_f, the frequency of the feedback clock signal is the original frequency, i.e., the frequency f_ref0.

[0147] In actual applications, the frequency division coefficient reg_fbdiv can be a fixed value pre-configured in the register, or can be modified by the control module 33 according to actual service requirements, and the present embodiment does not make any limitation in this aspect.

[0148] In the present embodiment, the spread spectrum modulation circuit 32 can perform weighted sum calculation according to the frequency division coefficient reg_fbdiv, the modulation coefficient δ and the weighting coefficient, to determine the frequency modulation step value step_f. The specific value of the weighting coefficient can be determined by one or more factors such as the size relationship between the original set frequency and the new set frequency, the frequency difference between the two, the frequency switching rate, and the present embodiment does not make any limitation in this aspect.

[0149] For example, if the weighting coefficient is 1, then the frequency modulation step value step_f = frequency division coefficient reg_fbdiv + modulation coefficient δ; if the weighting coefficient is -1, then the frequency modulation step value step_f = frequency division coefficient reg_fbdiv - modulation coefficient δ; if the weighting coefficient is 2, then the frequency modulation step value step_f = frequency division coefficient reg_fbdiv + 2*modulation coefficient δ; and if the weighting coefficient is -3, then the frequency modulation step value step_f = frequency division coefficient reg_fbdiv - 3*modulation coefficient δ.

[0150] In specific implementation, after the spread spectrum modulation circuit 32 generates the frequency modulation step value step_f, it is sent to the feedback frequency divider 312. As shown, Figure 8 The feedback frequency divider 312 will perform linear pursuit from the frequency f_ref0 to the frequency f_ref1 according to the frequency modulation step value step_f, until the frequency f_ref1 is reached; and after locking to the frequency f_ref1, the feedback frequency divider 312 re-enters the IDLE state.

[0151] In the above embodiment, when the spread spectrum modulation circuit 32 only enables the frequency tracking function and does not enable the spread spectrum function, since the spread spectrum function is not enabled in this case, there is no spread spectrum adjustment on the clock signal generated by the phase-locked loop circuit 31. At this time, the spread spectrum modulation circuit 32 directly generates a frequency modulation step value under the control of the clock switching control signal and sends the generated frequency modulation step value to the phase-locked loop circuit 31. Since the frequency modulation step value is determined according to the frequency division coefficient and the modulation coefficient of the spread spectrum modulation, frequency adjustment using the frequency modulation step value can effectively avoid the phase-locked loop circuit 31 from losing lock and improve the stability of the system.

[0152] In some embodiments, when the spread spectrum modulation circuit 32 identifies that the level state of the spread spectrum enable signal is the active level state and the spread spectrum period is the second set value, the spread spectrum modulation circuit 32 enters the second working mode; the second working mode represents that the spread spectrum modulation circuit enables the frequency tracking function and enables the spread spectrum function, and the first set value and the second set value are different.

[0153] In specific implementation, the active level state can be a high level, and the second set value can be a non-0 value. That is, when the spread spectrum modulation circuit 32 identifies that the spread spectrum enable signal is pulled high and the set spread spectrum period = non-0 value, the second working mode is entered to simultaneously enable the spread spectrum function and the frequency tracking function.

[0154] The following embodiments are described by taking the active level state as a high level and the second set value as a non-0 value as an example:

[0155] Figure 9 A working timing diagram of a spread spectrum modulation circuit in the second working mode is shown. As shown in Figure 9 , the spread spectrum period set by the control module 33 is a non-0 value, and when the spread spectrum enable signal changes from a low level to a high level, the spread spectrum modulation circuit 32 enters the second working mode.

[0156] And from Figure 9 the signal of the spread spectrum state, it can be known that during the period when the spread spectrum enable signal is a low level, the spread spectrum state is an IDLE state; when the spread spectrum enable signal changes to a high level, the spread spectrum state changes to a working state and performs periodic spread spectrum modulation according to the spread spectrum period. As shown in Figure 9 , one spread spectrum period can be divided into four phases, namely PHASE0, PHASE1, PHASE2, and PHASE3. Until the clock switching control signal triggered by the control module 33 is received, the current spread spectrum period will be immediately ended and the SYNC state will be entered to perform frequency switching operation during the SYNC state.

[0157] In the above embodiment, the control module 33 configures the spread spectrum period for the spread spectrum modulation circuit 32 and generates a spread spectrum enable signal, and the spread spectrum modulation circuit 32 controls whether to simultaneously enable the spread spectrum and frequency tracking functions or only enable the frequency tracking function according to the set spread spectrum period and the level state of the spread spectrum enable signal, thereby realizing the multiplexing of the spread spectrum modulation circuit. The multiplexing of the spread spectrum modulation circuit can realize the control of frequency switching, and thus it is not necessary to additionally increase other devices. Therefore, compared with the existing method of additionally increasing a phase-locked loop for generating a secure clock signal, the method provided in the embodiment of the present application can effectively reduce the chip cost.

[0158] In some embodiments, when the spread spectrum modulation circuit 32 is in the second working mode, the spread spectrum modulation circuit 32 can also generate a spread spectrum modulation signal according to the frequency division coefficient reg_fbdiv and the modulation coefficient δ, and send the spread spectrum modulation signal to the feedback frequency divider 312; the feedback frequency divider 312 can perform spread spectrum modulation on the output clock signal CLK_out according to the spread spectrum modulation signal, and output the spread spectrum modulation output clock signal.

[0159] In a specific implementation, the spread spectrum modulation signal generated by the spread spectrum modulation circuit 32 according to the frequency division coefficient reg_fbdiv and the modulation coefficient δ can be a triangular wave signal; the feedback frequency divider 312 can perform superposition processing on the triangular wave signal and the clock signal received by itself, thereby realizing the spread spectrum modulation function.

[0160] Figure 10 A waveform diagram of a spread spectrum modulation signal is shown. As shown in Figure 10 the spread spectrum modulation signal is a triangular wave signal, and at the end of the PHASE0 stage, the corresponding modulation frequency n%, after the clock signal is modulated by using the modulation frequency, the frequency of the generated clock signal is (1+n%)x frequency f_out; at the end of the PHASE3 stage, the corresponding modulation frequency is -n%, after the clock signal is modulated by using the modulation frequency, the frequency of the generated clock signal is (1-n%)x frequency f_out.

[0161] In a specific implementation, the modulation frequency corresponding to each time point in the spread spectrum period can be determined according to the frequency division coefficient reg_fbdiv, and the length of the spread spectrum period can be determined according to the modulation coefficient δ, and the determination method can refer to the existing generation method of the spread spectrum modulation signal, and thus it is not necessary to repeat it.

[0162] As Figure 9As shown, when the spread spectrum modulation circuit simultaneously enables both the frequency tracking function and the spread spectrum function, whether before or after frequency switching, the output clock signal will be modulated using the spread spectrum modulation signal. This causes the frequency of the output clock signal to follow the spread spectrum period and undergo small-range frequency jitter centered on the frequency of the output clock signal, thereby expanding the narrowband spectrum, dispersing radiated energy, and achieving the purpose of reducing EMI.

[0163] In some embodiments, when the spread spectrum modulation circuit 32 is in the second operating mode, after receiving the clock switching control signal, the spread spectrum modulation circuit 32 immediately stops generating the spread spectrum modulation signal and generates the frequency modulation step size value step_f according to the sum of the frequency division coefficient reg_fbdiv and the modulation coefficient δ; wherein, after receiving the clock switching control signal, the frequency of the feedback clock signal initially adjusted by the feedback frequency divider 312 using the frequency modulation step size value is inconsistent with the frequency of the reference clock signal previously configured by the control module.

[0164] like Figure 9 As shown, since the spread spectrum modulation circuit 32 is in the second working mode and the spread spectrum function is enabled, when the feedback frequency divider 312 adjusts the feedback clock signal CLK_fbdiv for the first time using the frequency modulation step size value step_f, the frequency of the feedback clock signal may be the original frequency, i.e., frequency f_ref0, or it may not be equal to frequency f_ref0, which is related to the actual received clock switching control signal.

[0165] Furthermore, when the spread spectrum modulation circuit 32 is in the second operating mode, the way it generates the frequency modulation step size value step_f is similar to the way it generates the frequency modulation step size value step_f when it is in the first operating mode. It can be referred to the above embodiment, so it will not be described again.

[0166] In practical implementation, after the spread spectrum modulation circuit 32 generates the frequency modulation step size value step_f, it sends it to the feedback frequency divider 312. For example... Figure 9 As shown, the feedback frequency divider 312 will linearly chase from frequency f_ref0 to frequency f_ref1 according to the frequency modulation step size value step_f, until the frequency f_ref1 is reached; and after locking to frequency f_ref1, the feedback frequency divider 312 will re-enter the spread spectrum modulation working state.

[0167] In the above embodiment, when the spread spectrum modulation circuit simultaneously starts the frequency tracking function and the spread spectrum function, the spread spectrum modulation circuit needs to stop spread spectrum modulation first after receiving the clock switching control signal, then generates the frequency modulation step value, and sends the generated frequency modulation step value to the phase-locked loop circuit. Through the above manner, time multiplexing of the spread spectrum modulation circuit can be realized. Through the manner of multiplexing the spread spectrum modulation circuit, the phase-locked loop circuit is prevented from being out of lock, which is not only suitable for a single phase-locked loop chip, but also suitable for a chip integrated with multiple phase-locked loops, and no additional device is needed, so that the chip cost can be effectively reduced.

[0168] As shown in Figure 11 , a complete working process schematic diagram of the phase-locked loop chip provided by the embodiment of the application is provided, which specifically includes the following steps:

[0169] Step S1101, the control module configures a spread spectrum period for the spread spectrum modulation circuit, and sends a spread spectrum enable signal to the spread spectrum modulation circuit;

[0170] Step S1102, the spread spectrum modulation circuit identifies that the spread spectrum enable signal is at a high level and the spread spectrum period is 0, and starts the frequency tracking function and stops the spread spectrum function;

[0171] Step S1103, the control module changes the working frequency of the phase-locked loop circuit from an original frequency f_ref0 to a first frequency f_ref1;

[0172] Step S1104, the control module triggers a clock switching control signal, and sends the clock switching control signal to the spread spectrum modulation circuit;

[0173] Step S1105, after the spread spectrum modulation circuit receives the clock switching control signal, a frequency modulation step value is generated according to a frequency division coefficient and a modulation coefficient, and the frequency modulation step value is sent to a feedback frequency divider in the phase-locked loop circuit;

[0174] Step S1106, the feedback frequency divider adjusts the frequency of the clock signal received by itself multiple times by using the frequency modulation step value until the frequency is consistent with the first frequency f_ref1;

[0175] Step S1107, the spread spectrum modulation circuit identifies that the spread spectrum enable signal is at a high level and the spread spectrum period is not 0, and starts the frequency tracking function and the spread spectrum function;

[0176] Step S1108, the spread spectrum modulation circuit generates a spread spectrum modulation signal according to the frequency division coefficient and the modulation coefficient, and sends the spread spectrum modulation signal to the feedback frequency divider;

[0177] Step S1109, the feedback frequency divider performs spread spectrum modulation on the clock signal received by itself according to the spread spectrum modulation signal;

[0178] Step S1110, the control module changes the working frequency of the phase-locked loop circuit from the original frequency f_ref0 to the first frequency f_ref1.

[0179] Step S1111, the control module triggers the clock switching control signal and sends the clock switching control signal to the spread spectrum modulation circuit.

[0180] Step S1112, after the spread spectrum modulation circuit receives the clock switching control signal, it immediately stops generating the spread spectrum modulation signal, and starts generating the frequency modulation step value according to the frequency division coefficient and the modulation coefficient, and sends the frequency modulation step value to the feedback frequency divider in the phase-locked loop circuit.

[0181] Step S1113, the feedback frequency divider uses the frequency modulation step value to adjust the frequency of the clock signal received by itself multiple times until the frequency is consistent with the first frequency f_ref1.

[0182] Step S1114, the spread spectrum modulation circuit restarts to generate the spread spectrum modulation signal, and the feedback frequency divider restarts to perform spread spectrum modulation.

[0183] Step S1115, the phase-locked loop circuit completes frequency locking.

[0184] Based on the same concept, the embodiment of the present application also provides a frequency switching method of a phase-locked loop chip, which is applied to the phase-locked loop chip provided in any of the above embodiments. Since the method is the method executed by the phase-locked loop chip in the embodiment of the present application, and the problem solving principle of the method is similar to that of the phase-locked loop chip, the implementation of the method can be referred to the implementation of the phase-locked loop chip, and the repeated parts will not be described here.

[0185] As shown in the method, the method comprises the following steps: Figure 12

[0186] Step S1201, the control module configures a reference clock signal for the phase-locked loop circuit, and generates a clock switching control signal sent to the spread spectrum modulation circuit.

[0187] Step S1202, the spread spectrum modulation circuit generates a frequency modulation step value according to the frequency division coefficient and the modulation coefficient under the control of the clock switching control signal, and sends the frequency modulation step value to the phase-locked loop circuit.

[0188] Step S1203, the phase-locked loop circuit uses the frequency modulation step value to adjust the frequency of the feedback clock signal to generate an output clock signal, wherein the frequency of the output clock signal is consistent with the frequency of the reference clock signal.

[0189] In some embodiments, before the control module configures a reference clock signal for the phase-locked loop circuit, it further comprises:

[0190] ​The control module configures a spread spectrum period for the spread spectrum modulation circuit, and sends a spread spectrum enable signal to the spread spectrum modulation circuit;

[0191] Based on the spread spectrum enable signal and the spread spectrum period, the working mode of the spread spectrum modulation circuit is determined;

[0192] The working mode includes a first working mode and a second working mode, the first working mode is used to represent that the spread spectrum modulation circuit opens the frequency tracking function and closes the spread spectrum function, and the second working mode is used to represent that the spread spectrum modulation circuit opens the frequency tracking function and opens the spread spectrum function.

[0193] In some embodiments, when the spread spectrum modulation circuit is in the first working mode, under the control of the clock switching control signal, a frequency modulation step value is generated according to the frequency division coefficient and the modulation coefficient, including:

[0194] Under the control of the clock switching control signal, the frequency modulation step value is generated according to the sum of the frequency division coefficient and the modulation coefficient;

[0195] After receiving the clock switching control signal, the frequency of the feedback clock signal first adjusted by the phase-locked loop circuit using the frequency modulation step value is consistent with the frequency of the reference clock signal previously configured by the control module.

[0196] In some embodiments, when the spread spectrum modulation circuit is in the second working mode, further comprising:

[0197] The spread spectrum modulation circuit generates a spread spectrum modulation signal according to the frequency division coefficient and the modulation coefficient, and sends the spread spectrum modulation signal to the phase-locked loop circuit;

[0198] The phase-locked loop circuit performs spread spectrum modulation on the output clock signal according to the spread spectrum modulation signal, and outputs the spread spectrum modulation output clock signal.

[0199] In some embodiments, when the spread spectrum modulation circuit is in the second working mode, under the control of the clock switching control signal, a frequency modulation step value is generated according to the frequency division coefficient and the modulation coefficient, including:

[0200] After receiving the clock switching control signal, the generation of the spread spectrum modulation signal is stopped, and a frequency modulation step value is generated according to the sum of the frequency division coefficient and the modulation coefficient;

[0201] After receiving the clock switching control signal, the frequency of the feedback clock signal first adjusted by the phase-locked loop circuit using the frequency modulation step value is inconsistent with the frequency of the reference clock signal previously configured by the control module.

[0202] In some embodiments, based on the spread spectrum enable signal and the spread spectrum period, the working mode of the spread spectrum modulation circuit is determined, including:

[0203] When it is identified that the level state of the spread spectrum enable signal is a valid level state and the spread spectrum period is a first set value, it is determined that the working mode of the spread spectrum modulation circuit is a first working mode.

[0204] When it is identified that the level state of the spread spectrum enable signal is a valid level state and the spread spectrum period is a second set value, it is determined that the working mode of the spread spectrum modulation circuit is a second working mode.

[0205] The first set value and the second set value are different.

[0206] In some embodiments, the frequency of the feedback clock signal is adjusted by using the frequency adjustment step value to generate the output clock signal, including:

[0207] The intermediate clock signal is generated based on the reference clock signal and the adjusted feedback clock signal by the core module, and the adjusted feedback clock signal with the frequency equal to the first frequency is taken as the output clock signal.

[0208] The feedback divider is used to perform frequency division processing on the intermediate clock signal to generate the feedback clock signal, and the frequency of the feedback clock signal is adjusted by using the frequency adjustment step value, and the adjusted feedback clock signal is sent to the core module.

[0209] The first frequency is used to represent the frequency of the reference clock signal, and the frequency of the adjusted feedback clock signal is the sum of the frequency of the unadjusted feedback clock signal and the frequency adjustment step value.

[0210] In some embodiments, the reference clock signal is configured for the phase-locked loop circuit by the control module, and the clock switching control signal sent to the spread spectrum modulation circuit is generated by the control module, including:

[0211] The reference clock signal is configured for the phase-locked loop circuit by the control module at the first time, and the clock switching control signal is generated by the control module at the second time, wherein the first time is earlier than the second time.

[0212] Based on the same concept, the embodiments of the present application also provide a display device, which comprises the phase-locked loop chip provided by any of the above embodiments. The display device solves the problem in the same principle as the aforementioned phase-locked loop chip, and therefore the implementation of the display device can be referred to the implementation of the aforementioned phase-locked loop chip, and the repeated parts will not be described herein.

[0213] In the specific implementation, the phase-locked loop chip provided in the display device can be a SoC chip, a Scaler chip, or other possible chips, and the embodiments of the present application do not make any limitation in this regard. In addition, in the embodiments of the present application, other essential components of the display device are understood by those skilled in the art, which will not be described herein and should not be regarded as a limitation of the present application.

[0214] While the preferred embodiments of the application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the present disclosure without departing from the spirit and scope of the application. Accordingly, it is intended that the appended claims include all such modifications and variations as fall within the scope of the present application.

[0215] It is apparent that those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. It is therefore intended that the present application cover all such changes and modifications that are within its scope.

Claims

1. A phase-locked loop chip, characterized in that, It includes a phase-locked loop circuit, a spread spectrum modulation circuit, and a control module, wherein: The control module is electrically connected to the phase-locked loop circuit and the spread spectrum modulation circuit, respectively, and the phase-locked loop circuit is electrically connected to the spread spectrum modulation circuit; The control module is used to configure a reference clock signal for the phase-locked loop circuit and generate a clock switching control signal to be sent to the spread spectrum modulation circuit. The spread spectrum modulation circuit is used to generate a frequency modulation step value based on the frequency division coefficient and the modulation coefficient under the control of the clock switching control signal, and send the frequency modulation step value to the phase-locked loop circuit. The phase-locked loop circuit is used to adjust the frequency of the feedback clock signal using the frequency modulation step size value to generate an output clock signal, wherein the frequency of the output clock signal is consistent with the frequency of the reference clock signal.

2. The chip as described in claim 1, characterized in that, The control module is also configured to: configure the spread spectrum period for the spread spectrum modulation circuit, and send a spread spectrum enable signal to the spread spectrum modulation circuit; The spread spectrum modulation circuit is also used to: determine its own operating mode based on the spread spectrum enable signal and the spread spectrum period; The operating modes include a first operating mode and a second operating mode. The first operating mode is used to indicate that the spread spectrum modulation circuit enables the frequency tracking function and disables the spread spectrum function. The second operating mode is used to indicate that the spread spectrum modulation circuit enables both the frequency tracking function and the spread spectrum function.

3. The chip as described in claim 2, characterized in that, When the spread spectrum modulation circuit is in the first working mode, the spread spectrum modulation circuit is specifically used to: generate the frequency modulation step size value according to the sum of the frequency division coefficient and the modulation coefficient under the control of the clock switching control signal; Upon receiving the clock switching control signal, the phase-locked loop circuit adjusts the frequency of the feedback clock signal using the frequency modulation step size value to match the frequency of the reference clock signal previously configured by the control module.

4. The chip as described in claim 2, characterized in that, When the spread spectrum modulation circuit is in the second operating mode, the spread spectrum modulation circuit is further configured to: generate a spread spectrum modulation signal according to the frequency division coefficient and the modulation coefficient, and send the spread spectrum modulation signal to the phase-locked loop circuit; The phase-locked loop circuit is also used to: perform spread spectrum modulation on the output clock signal according to the spread spectrum modulation signal, and output the spread spectrum modulated output clock signal.

5. The chip as described in claim 4, characterized in that, When the spread spectrum modulation circuit is in the second operating mode, the spread spectrum modulation circuit is specifically used for: Upon receiving the clock switching control signal, the generation of the spread spectrum modulation signal is stopped, and the frequency modulation step size value is generated based on the sum of the frequency division coefficient and the modulation coefficient. Upon receiving the clock switching control signal, the frequency of the feedback clock signal initially adjusted by the phase-locked loop circuit using the frequency modulation step size is inconsistent with the frequency of the reference clock signal previously configured by the control module.

6. The chip as described in claim 2, characterized in that, The spread spectrum modulation circuit is specifically used for: When the spread spectrum enable signal is detected to be in an effective state and the spread spectrum period is a first set value, the spread spectrum modulation circuit enters the first working mode. When the spread spectrum enable signal is identified as having an effective level and the spread spectrum period is a second set value, the spread spectrum modulation circuit enters the second operating mode. The first setting value and the second setting value are different.

7. The chip as described in any one of claims 1-6, characterized in that, The phase-locked loop circuit includes a core module and a feedback frequency divider, wherein: One input terminal of the core module is used to receive the reference clock signal, and the other input terminal of the core module is electrically connected to the output terminal of the feedback frequency divider. The output terminal of the core module is electrically connected to the input terminal of the feedback frequency divider. The control terminal of the feedback frequency divider is electrically connected to the output terminal of the spread spectrum modulation circuit, and is used to receive the frequency modulation step value output by the spread spectrum modulation circuit; The core module is used to generate an intermediate clock signal based on the reference clock signal and the adjusted feedback clock signal, and to use the adjusted feedback clock signal with a frequency equal to the first frequency as the output clock signal. The feedback frequency divider is used to divide the intermediate clock signal to generate the feedback clock signal, and to adjust the frequency of the feedback clock signal using the frequency adjustment step value, and then send the adjusted feedback clock signal to the core module. Wherein, the first frequency is used to characterize the frequency of the reference clock signal, and the frequency of the adjusted feedback clock signal is the sum of the frequency of the feedback clock signal before adjustment and the frequency modulation step size value.

8. The chip as described in any one of claims 1-6, characterized in that, The control module is specifically used to: configure the reference clock signal for the phase-locked loop circuit at a first time, and generate the clock switching control signal at a second time, wherein the first time is earlier than the second time.

9. A frequency switching method for a phase-locked loop chip, characterized in that, include: The control module configures a reference clock signal for the phase-locked loop circuit and generates a clock switching control signal to be sent to the spread spectrum modulation circuit. Through the spread spectrum modulation circuit, under the control of the clock switching control signal, a frequency modulation step value is generated according to the frequency division coefficient and the modulation coefficient, and the frequency modulation step value is sent to the phase-locked loop circuit. The frequency of the feedback clock signal is adjusted by using the frequency modulation step size value through a phase-locked loop circuit to generate an output clock signal, wherein the frequency of the output clock signal is consistent with the frequency of the reference clock signal.

10. A display device, characterized in that, Includes the phase-locked loop chip as described in any one of claims 1-8.

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