Phase-locked loop circuit, control method, charge pump, and chip

Abstract

The application provides a phase-locked loop circuit, a control method, a charge pump and a chip. The phase-locked loop circuit comprises a frequency discriminator and phase discriminator, which is used for receiving a reference clock signal and an output signal of a frequency divider, and generating a charge and discharge control signal; a charge pump module, which is used for determining charging or discharging, and determining the current size of a charge pump proportional unit and a charge pump integral unit, and generating corresponding charging current or discharging current according to the determined charging or discharging and the current size of the charge pump proportional unit and the charge pump integral unit; a loop filter, which is used for filtering the charging current or the discharging current to obtain a control voltage signal; a voltage-controlled oscillator, which is used for generating a phase-locked loop output signal with a preset frequency; and a frequency divider, which is used for dividing the frequency of the phase-locked loop output signal, taking the divided signal as an output signal, and inputting the output signal to the frequency discriminator and phase discriminator. The phase-locked loop circuit provided by the application can greatly reduce the spurs in the phase-locked loop.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of phase-locked loop, and particularly relates to a phase-locked loop circuit, a control method, a charge pump and a chip. BACKGROUND

[0002] The phase-locked loop is a circuit that synchronizes the phase and frequency of a divided signal generated by a voltage-controlled oscillator with an input reference signal. In the synchronization state, the phase difference between the output signal of the oscillator and the input reference signal is 0 or a fixed constant. If the phase difference between the two changes, there is a feedback control mechanism in the phase-locked loop to adjust the output of the oscillator so that the phase difference decreases and eventually reaches the locked state. In this circuit, the phase of the output signal is actually locked to the phase of the input reference signal, which is why the circuit is called a phase-locked loop. The existing phase-locked loop circuit has high spurs, and high spurs will seriously affect the use effect of the phase-locked loop. SUMMARY

[0003] Therefore, the present application provides a phase-locked loop circuit, which comprises a frequency discriminator, a charge pump module, a loop filter, a voltage-controlled oscillator and a frequency divider, the charge pump module comprises a charge pump proportional unit and a charge pump integral unit;

[0004] The frequency discriminator is configured to receive a reference clock signal and an output signal of the frequency divider, and generate a charge and discharge control signal according to the reference clock signal and the output signal of the frequency divider.

[0005] The charge pump module is configured to receive the charge and discharge control signal, determine charging or discharging according to the charge and discharge control signal, and determine the current size of the charge pump proportional unit and the charge pump integral unit according to the size of the capacitor in the loop filter, and generate a corresponding charging current or discharging current according to the determined charging or discharging and the current size of the charge pump proportional unit and the charge pump integral unit.

[0006] The loop filter is configured to filter the charging current or discharging current to obtain a control voltage signal.

[0007] The voltage-controlled oscillator is configured to generate a phase-locked loop output signal of a preset frequency according to the control voltage signal.

[0008] The frequency divider is configured to divide the phase-locked loop output signal, input the divided signal as an output signal to the frequency discriminator.

[0009] Optionally, the charge pump module further comprises a dynamic unit matching module, and the dynamic unit matching module is configured to determine the current size of the charge pump proportional unit and the charge pump integral unit according to the size of the capacitor in the loop filter.

[0010] Optionally, the charge pump proportional unit and the charge pump integral unit each comprise a plurality of current mirror units.

[0011] The dynamic unit matching module is further configured to determine the number of turned-on current mirror units in the charge pump proportional unit and the charge pump integral unit according to the current sizes of the charge pump proportional unit and the charge pump integral unit, and turn on the current mirror units in the charge pump proportional unit and the charge pump integral unit according to the number of turned-on current mirror units.

[0012] Optionally, the charge pump proportional unit is configured to generate a corresponding charging current or discharging current according to the determined charging or discharging and the number of turned-on current mirror units in the charge pump proportional unit; and the charge pump integral unit is configured to generate a corresponding charging current or discharging current according to the determined charging or discharging and the number of turned-on current mirror units in the charge pump integral unit.

[0013] Optionally, the charge pump proportional unit comprises a first charging unit and a first discharging unit, the first charging unit comprises a first P-type field effect transistor, and the first discharging unit comprises a first N-type field effect transistor; a gate of the first P-type field effect transistor is configured to receive a first bias voltage, a source of the first P-type field effect transistor is connected to a power supply, and a drain of the first P-type field effect transistor is connected to the dynamic unit matching module; a gate of the first N-type field effect transistor is configured to receive a second bias voltage, a source of the first N-type field effect transistor is connected to ground, and a drain of the first N-type field effect transistor is connected to the dynamic unit matching module.

[0014] Optionally, the charge pump integral unit comprises a second charging unit and a second discharging unit, the second charging unit comprises a second P-type field effect transistor, and the second discharging unit comprises a second N-type field effect transistor; a gate of the second P-type field effect transistor is configured to receive the first bias voltage, a source of the second P-type field effect transistor is connected to the power supply, and a drain of the second P-type field effect transistor is connected to the dynamic unit matching module; a gate of the second N-type field effect transistor is configured to receive the second bias voltage, a source of the second N-type field effect transistor is connected to ground, and a drain of the second N-type field effect transistor is connected to the dynamic unit matching module.

[0015] Optionally, the first charging unit, the first discharging unit, the second charging unit, and the second discharging unit each comprise a plurality of current mirror units; and the dynamic unit matching module comprises a first dynamic unit matcher and a second dynamic unit matcher.

[0016] The first dynamic unit matcher is used for determining the number of turned-on current mirror units in the first charging unit and the second charging unit according to the size of the capacitor in the loop filter, and turning on the current mirror units in the first charging unit and the second charging unit respectively according to the number of turned-on current mirror units in the first charging unit and the second charging unit.

[0017] The second dynamic unit matcher is used for determining the number of turned-on current mirror units in the first discharging unit and the second discharging unit according to the size of the capacitor in the loop filter, and turning on the current mirror units in the first discharging unit and the second discharging unit respectively according to the number of turned-on current mirror units in the first discharging unit and the second discharging unit.

[0018] Optionally, the turning on of the current mirror units in the first charging unit and the second charging unit respectively specifically comprises randomly turning on the current mirror units in the first charging unit and the second charging unit respectively, and the turning on of the current mirror units in the first discharging unit and the second discharging unit respectively specifically comprises randomly turning on the current mirror units in the first discharging unit and the second discharging unit respectively.

[0019] Optionally, the charge pump module further comprises a first switch, a second switch, a third switch and a fourth switch; one end of the first switch is connected to the first dynamic unit matcher, the other end of the first switch is connected to one end of the second switch and a voltage-controlled oscillator, the other end of the second switch is connected to the second dynamic unit matcher, one end of the third switch is connected to the first dynamic unit matcher, the other end of the third switch is connected to one end of the fourth switch and the voltage-controlled oscillator, and the other end of the fourth switch is connected to the second dynamic unit matcher.

[0020] Optionally, the loop filter comprises an integral capacitor Ci, a proportional capacitor Cp, a resistor Rp and a buffer BUF, one end of the proportional capacitor Cp is connected to the other end of the first switch, the other end of the proportional capacitor Cp and one end of the integral capacitor Ci are grounded, the other end of the integral capacitor Ci is connected to the other end of the third switch and the input end of the buffer BUF, the output end of the buffer BUF is connected to one end of the resistor Rp, and the other end of the resistor Rp is connected to one end of the proportional capacitor Cp.

[0021] The application further provides a phase-locked loop control method, which comprises the following steps:

[0022] A reference clock signal and a frequency division signal are acquired, and a charge-discharge control signal is generated according to the phase difference between the reference clock signal and the frequency division signal.

[0023] determining charging or discharging according to the charge-discharge control signal, determining the current size of the charge pump proportional unit and the charge pump integral unit according to the size of the capacitor in the loop filter, and generating corresponding charging current or discharging current according to the determined charging or discharging and the current size of the charge pump proportional unit and the charge pump integral unit;

[0024] filtering the charging current or discharging current to obtain a control voltage signal;

[0025] generating a phase-locked loop output signal of a preset frequency according to the control voltage signal;

[0026] frequency dividing the phase-locked loop output signal to obtain the frequency divided signal.

[0027] The application further provides a charge pump, which comprises a charge pump proportional unit and a charge pump integral unit, and is configured to receive the charge-discharge control signal, determine charging or discharging according to the charge-discharge control signal, determine the current size of the charge pump proportional unit and the charge pump integral unit, and generate corresponding charging current or discharging current according to the determined charging or discharging and the current size of the charge pump proportional unit and the charge pump integral unit.

[0028] The application further provides a chip comprising the phase-locked loop circuit or the charge pump according to any of the technical solutions.

[0029] The application has the following beneficial effects: the frequency discriminator and phase discriminator generate a charge-discharge control signal according to a reference clock signal and an output signal of a frequency divider, the charge pump module receives the charge-discharge control signal, determines charging or discharging according to the charge-discharge control signal, determines the current size of the charge pump proportional unit and the charge pump integral unit according to the size of the capacitor in the loop filter, and generates corresponding charging current or discharging current according to the determined charging or discharging and the current size of the charge pump proportional unit and the charge pump integral unit; the loop filter filters the charging current or discharging current to obtain a control voltage signal; the voltage-controlled oscillator generates a phase-locked loop output signal of a preset frequency; the frequency divider frequency divides the phase-locked loop output signal, inputs the frequency-divided signal as an output signal to the frequency discriminator and phase discriminator, and realizes the function of the phase-locked loop while optimizing the current mismatch in the charge pump and greatly reducing the spurs in the phase-locked loop. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 a circuit block diagram of the phase-locked loop circuit of the first embodiment of the application;

[0031] Figure 2 a circuit schematic diagram of the phase-locked loop circuit of the first embodiment of the application;

[0032] Figure 3 a principle block diagram of a charge pump module of a first embodiment of the present application;

[0033] Figure 4 a circuit principle diagram of the charge pump module of the first embodiment of the present application;

[0034] Figure 5 a flow chart of a phase-locked loop control method of a second embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to facilitate the understanding of the present application, a more comprehensive description of the present application will be given below with reference to the relevant drawings. The drawings show the preferred embodiments of the present application. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0036] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there can be a middle element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there can be a middle element.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description of the present application herein only for the purpose of describing the specific embodiments of the present application and is not intended to limit the present application.

[0038] Figure 1 is a circuit block diagram of a phase-locked loop circuit of a first embodiment of the present application. It should be noted that the circuit of the present application is not limited to the circuit principle diagram shown in Figure 1 . As shown in Figure 1 , the phase-locked loop circuit includes a phase frequency detector PFD, a charge pump module CP, a loop filter LPF, a voltage controlled oscillator VCO and a frequency divider DIV, wherein the charge pump module CP includes a charge pump proportional unit CPP and a charge pump integral unit CPI;

[0039] The phase frequency detector PFD is configured to receive a reference clock signal and an output signal of the frequency divider DIV, and generate a charge and discharge control signal according to the reference clock signal and the output signal of the frequency divider DIV;

[0040] The charge pump module CP is configured to receive the charge and discharge control signal, determine charging or discharging according to the charge and discharge control signal, determine the current size of the charge pump proportional unit CPP and the charge pump integral unit CPI according to the size of the capacitor in the loop filter LPF, and generate a corresponding charging current or discharging current according to the determined charging or discharging and the current size of the charge pump proportional unit CPP and the charge pump integral unit CPI.

[0041] The loop filter LPF is configured to filter the charging current or discharging current to obtain a control voltage signal.

[0042] The voltage-controlled oscillator VCO is configured to generate a phase-locked loop output signal of a preset frequency according to the control voltage signal.

[0043] The frequency divider DIV is configured to divide the phase-locked loop output signal, and input the divided signal as an output signal to the phase-frequency detector PFD.

[0044] It should be noted that, in the embodiment of the present application, the phase-frequency detector generates a charge and discharge control signal according to the phase difference between the reference clock signal and the output signal of the frequency divider, the dynamic unit matching module determines the number of turned-on current mirror units in the charge pump proportional unit and the charge pump integral unit according to the size of the capacitor in the loop filter, turns on the current mirror units in the charge pump proportional unit and the charge pump integral unit according to the number of turned-on current mirror units, filters the charging current or discharging current by the loop filter to obtain a control voltage signal, and the voltage-controlled oscillator generates a phase-locked loop output signal of a preset frequency according to the control voltage signal. In this way, the current mismatch in the charge pump is optimized while realizing the function of the phase-locked loop, greatly reducing the spurs in the phase-locked loop.

[0045] As an embodiment, the phase-locked loop circuit includes a phase-frequency detector PFD, a charge pump module CP, a loop filter LPF, a voltage-controlled oscillator VCO, and a frequency divider DIV. The phase-frequency detector is configured to detect the phase difference between the input reference clock clkin and the divided feedback clock clkdiv, and output control signals UP and DN. The control signal UP controls the charge pump proportional unit CPP and the charge pump integral unit CPI to charge, and the control signal DN controls the charge pump proportional unit CPP and the charge pump integral unit CPI to discharge. The output currents of the charge pump proportional unit CPP and the charge pump integral unit CPI are Icpp and Icpi, respectively. After Icpp and Icpi pass through the loop filter LPF, a control voltage Vc of the voltage-controlled oscillator VCO is obtained. Vc adjusts the output clock frequency of the voltage-controlled oscillator VCO. The current passes through the frequency divider DIV and returns to the phase-frequency detector PFD, thus forming a feedback loop.

[0046] In some embodiments, the loop filter comprises an integrating capacitor Ci, a proportional capacitor Cp, a resistor Rp, and a buffer BUF, one end of the proportional capacitor Cp is connected to the other end of the first switch, the other end of the proportional capacitor Cp and one end of the integrating capacitor Ci are grounded, the other end of the integrating capacitor Ci is connected to the other end of the third switch and the input end of the buffer BUF, the output end of the buffer BUF is connected to one end of the resistor Rp, and the other end of the resistor Rp is connected to one end of the proportional capacitor Cp.

[0047] As an implementation, the circuit schematic diagram of the phase-locked loop circuit is as shown in Figure 2 Figure 2 In the figure, clkin is an input reference clock, clkdiv is a feedback clock after frequency division, and the loop filter LPF comprises an integrating capacitor Ci, a proportional capacitor Cp, a resistor Rp, and a buffer BUF, wherein the transfer function of the LPF is

[0048]

[0049]

[0050] The loop gain of the phase-locked loop circuit is approximately

[0051]

[0052] The zero point of the loop gain is

[0053]

[0054] The sub-pole of the loop gain is

[0055]

[0056] The phase margin PM of the phase-locked loop circuit is

[0057]

[0058] wherein K vco is the gain of the voltage-controlled oscillator, N is the frequency division coefficient, Icp is the unit current, which is equal to the current size of the charge pump integrating unit CPI, and B is the ratio of the current of the charge pump proportional unit CPP to the current size of the charge pump integrating unit CPI. As can be seen from the above formula, the phase margin is related to the ratio of Ci and Cp, and if PM=60° is required, only B Ci is 13 times of Cp, which means that by setting the current coefficient B, the size requirement of the capacitor Ci can be reduced, and thus the on-chip integration of the LPF with small area and low cost is realized. ​​

[0059] In addition, since the unit area capacitance of MOM capacitor and MIM capacitor is small in advanced size process, it is usually necessary to rely on MOS capacitor to realize large capacitor on chip, so reducing the capacitor Ci can effectively reduce the periodic disturbance of phase-locked loop caused by the leakage of MOS tube gate end, thereby suppressing the spurs.

[0060] As an embodiment, the loop unit gain bandwidth of the phase-locked loop circuit is

[0061]

[0062] Natural frequency

[0063]

[0064] Damping factor

[0065]

[0066] For the phase-locked loop circuit, considering that the input reference comes from a high-precision crystal oscillator with good phase noise performance, the loop bandwidth design should be as close to 1 / 20 of the input reference as possible, so that the phase noise suppression effect of the ring oscillator VCO is best.

[0067] In some embodiments, the charge pump module further comprises a dynamic unit matching module, which is configured to determine the current size of the charge pump proportional unit and the charge pump integral unit according to the size of the capacitor in the loop filter.

[0068] As an embodiment, the principle block diagram of the charge pump module is as shown in Figure 3 . Figure 3 The charge pump module in the figure comprises a charge pump proportional unit 301, a charge pump integral unit 302 and a dynamic unit matching module 303.

[0069] In some embodiments, the charge pump proportional unit and the charge pump integral unit each comprise a plurality of current mirror units;

[0070] The dynamic unit matching module is further configured to determine the number of turned-on current mirror units in the charge pump proportional unit and the charge pump integral unit according to the current size of the charge pump proportional unit and the charge pump integral unit, and turn on the current mirror units in the charge pump proportional unit and the charge pump integral unit respectively according to the number of turned-on current mirror units.

[0071] As an implementation, the current mirror units in the charge pump proportional unit and the charge pump integral unit are randomly turned on according to the number of the turned-on current mirror units in the charge pump proportional unit and the charge pump integral unit, which can eliminate the mismatch between the charging current and the discharging current of the charge pump proportional unit and the charge pump integral unit, and eliminate the mismatch of the current ratio between the charge pump integral unit and the charge pump proportional unit.

[0072] As an implementation, the circuit schematic diagram of the charge pump module is as shown in Figure 4 . Figure 2 The two circuits of the charge pump proportional unit CPP and the charge pump integral unit CPI in Figure 4 are combined together for matching and logical control.

[0073] In some embodiments, the charge pump proportional unit is configured to generate a corresponding charging current or discharging current according to a determined charging or discharging and the number of the turned-on current mirror units in the charge pump proportional unit; and the charge pump integral unit is configured to generate a corresponding charging current or discharging current according to a determined charging or discharging and the number of the turned-on current mirror units in the charge pump integral unit.

[0074] As an implementation, the charge pump module includes P-type field effect tubes PM1-PMK and N-type field effect tubes, wherein K=B+1, B is the ratio of the current of the charge pump proportional unit CPP to the current of the charge pump integral unit CPI. It should be noted that K can also be an integer multiple of B+1, in which case the ratio of the number of the turned-on current mirror units in the charge pump proportional unit to the number of the turned-on current mirror units in the charge pump integral unit is B.

[0075] In some embodiments, the charge pump proportional unit includes a first charging unit and a first discharging unit, the first charging unit includes a first P-type field effect tube, and the first discharging unit includes a first N-type field effect tube; the gate of the first P-type field effect tube is configured to receive a first bias voltage, the source of the first P-type field effect tube is connected to a power supply, and the drain of the first P-type field effect tube is connected to the dynamic unit matching module; the gate of the first N-type field effect tube is configured to receive a second bias voltage, the source of the first N-type field effect tube is connected to ground, and the drain of the first N-type field effect tube is connected to the dynamic unit matching module.

[0076] As an implementation, the charge pump proportional unit includes a first charging unit and a first discharging unit, the current mirror unit in the first charging unit includes a first P-type field effect transistor, and the first discharging unit includes a first N-type field effect transistor; a gate of the first P-type field effect transistor is connected to a P-type bias voltage, a source of the first P-type field effect transistor is connected to a power supply, and a drain of the first P-type field effect transistor is connected to the dynamic cell matching module; a gate of the first N-type field effect transistor is connected to an N-type bias voltage, a source of the first N-type field effect transistor is connected to ground, and a drain of the first P-type field effect transistor is connected to the dynamic cell matching module.

[0077] As an example, the gates of the P-type field effect transistors PM1-PMK are all connected to a P-type bias voltage V biasp , the sources are all connected to a power supply voltage VDD, and the drains are connected to corresponding interfaces of the dynamic cell matching module; the gates of the N-type field effect transistors NM1-NMK are all connected to a current mirror bias voltage V biasn , the sources are all connected to ground, and the drains are connected to corresponding interfaces of the dynamic cell matching module.

[0078] In some embodiments, the charge pump integral unit includes a second charging unit and a second discharging unit, the second charging unit includes a second P-type field effect transistor, and the second discharging unit includes a second N-type field effect transistor; a gate of the second P-type field effect transistor is configured to receive a first bias voltage, a source of the second P-type field effect transistor is connected to a power supply, and a drain of the second P-type field effect transistor is connected to the dynamic cell matching module; a gate of the second N-type field effect transistor is configured to receive a second bias voltage, a source of the second N-type field effect transistor is connected to ground, and a drain of the second N-type field effect transistor is connected to the dynamic cell matching module.

[0079] As an implementation, the charge pump integral unit includes a second charging unit and a second discharging unit, the current mirror unit in the first charging unit includes a first P-type field effect transistor, and the first discharging unit includes a first N-type field effect transistor; a gate of the first P-type field effect transistor is connected to a P-type bias voltage, a source of the first P-type field effect transistor is connected to a power supply, and a drain of the first P-type field effect transistor is connected to the dynamic cell matching module; a gate of the first N-type field effect transistor is connected to an N-type bias voltage, a source of the first N-type field effect transistor is connected to ground, and a drain of the first P-type field effect transistor is connected to the dynamic cell matching module.

[0080] In some embodiments, the first charging unit, the first discharging unit, the second charging unit, and the second discharging unit each include a plurality of current mirror units; and the dynamic cell matching module includes a first dynamic cell matcher and a second dynamic cell matcher.

[0081] The first dynamic unit matcher is used to determine the number of current mirror units in the first charging unit and the second charging unit that are turned on based on the size of the capacitor in the loop filter, and to turn on the current mirror units in the first charging unit and the second charging unit respectively based on the number of current mirror units in the first charging unit and the second charging unit.

[0082] The second dynamic unit matcher is used to determine the number of current mirror units in the first discharge unit and the second discharge unit that are turned on based on the size of the capacitor in the loop filter, and to turn on the current mirror units in the first discharge unit and the second discharge unit respectively based on the number of current mirror units in the first discharge unit and the second discharge unit.

[0083] As an example, several current mirror units in the first charging unit, the first discharging unit, the second charging unit, and the second discharging unit respectively constitute a current mirror, and each current mirror unit is an output branch of the current mirror.

[0084] In some embodiments, the current mirror units in the first charging unit and the second charging unit are turned on respectively, specifically including randomly turning on the current mirror units in the first charging unit and the second charging unit respectively; the current mirror units in the first discharging unit and the second discharging unit are turned on respectively, specifically including randomly turning on the current mirror units in the first discharging unit and the second discharging unit respectively.

[0085] In one implementation, the first dynamic unit matched circuit (DEM logic1) receives current from P-field effect transistors PM1~PMK. The input clock clkin controls the internal logic of the first dynamic unit matched circuit to perform random selection, generating two current paths with a magnitude of B. Icp and Icp flow from the first switch SW1 and the third switch SW3 respectively. The first switch SW1 and the third switch SW3 are controlled by the output signal UP of the frequency and phase detector PFD. The second dynamic unit matching circuit receives the current from the N field-effect transistors NM1~NMK. The input clock clkin controls the internal logic of the second dynamic unit matching circuit to make a random selection, generating two currents with a magnitude of B. Icp and Icp flow out from the lower ends of the second switch SW2 and the fourth switch SW4, respectively. The switches are controlled by the output signal DN of the frequency and phase detector PFD. The other end of the first switch SW1 is connected to one end of the second switch SW2 to obtain the output Icpp, which is given to the loop filter LPF. The other end of the third switch SW3 is connected to one end of SW4 to obtain the output Icpi, which is given to the loop filter LPF.

[0086] As an example, P-type field-effect transistors all have the same dimensions, and therefore all have the same output current, i.e., I0. P1=I P2 =…=I PK Since all N-type field-effect transistors have the same dimensions, their corresponding output currents are also the same, i.e., I0. N1 =I N2 =…=I NK And all of them are the same as the unit current.

[0087] In some embodiments, the charge pump module further includes a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4; one end of the first switch SW1 is connected to the first dynamic unit matcher, the other end of the first switch SW1 is connected to one end of the second switch SW2 and the voltage-controlled oscillator, the other end of the second switch SW2 is connected to the second dynamic unit matcher, one end of the third switch SW3 is connected to the first dynamic unit matcher, the other end of the third switch SW3 is connected to one end of the fourth switch SW4 and the voltage-controlled oscillator, and the other end of the fourth switch SW4 is connected to the second dynamic unit matcher.

[0088] The phase-locked loop (PLL) circuit provided in this embodiment of the invention uses a dual-path structure. The output currents of the charge pump proportional unit (CPP) and the charge pump integral unit (CPI) are set to a certain ratio. The loop filter (LPF) converts the two currents to the input voltage of the voltage-controlled oscillator (VCO). The loop of this PLL circuit can be effectively reduced in size by setting the current ratio of the charge pump proportional unit (CPP) and the charge pump integral unit (CPI). Based on the dual-path structure, dynamic unit matching is used, which can eliminate the self-charging current I of the charge pump proportional unit (CPP) and the charge pump integral unit (CPI). up and discharge current I dn The mismatch between them can also eliminate the current ratio mismatch between the charge pump integrator CPI and the charge pump proportional unit CPP, effectively suppressing stray currents.

[0089] A schematic flowchart of the phase-locked loop control method according to the second embodiment of the present invention is shown below. Figure 5 As shown, the phase-locked loop control method includes the following steps:

[0090] S501, acquire a reference clock signal and a frequency divider signal, and generate a charge / discharge control signal based on the reference clock signal and the frequency divider signal;

[0091] S502, determine charging or discharging according to the charging and discharging control signal, determine the current magnitude of the charge pump proportional unit and the charge pump integral unit according to the size of the capacitor in the loop filter, and generate the corresponding charging current or discharging current according to the determined charging or discharging and the current magnitude of the charge pump integral unit.

[0092] S503, the charging current or discharging current is filtered to obtain a control voltage signal;

[0093] S504, Generate a phase-locked loop output signal of a preset frequency according to the control voltage signal;

[0094] S505, divide the frequency of the phase-locked loop output signal to obtain the divided frequency signal.

[0095] A third embodiment of the present invention provides a charge pump, which includes a charge pump proportional unit and a charge pump integral unit. The charge pump is used to receive a charge / discharge control signal, determine charging or discharging based on the charge / discharge control signal, and further determine the current magnitudes of the charge pump proportional unit and the charge pump integral unit. Based on the determined charging or discharging and the current magnitudes of the charge pump proportional unit and the charge pump integral unit, it generates a corresponding charging current or discharging current. Specifically, when the charge pump is applied to a phase-locked loop circuit, determining the current magnitudes of the charge pump proportional unit and the charge pump integral unit is based on the size of the capacitor in the loop filter.

[0096] As one implementation, the charge pump further includes a dynamic unit matching module, which is used to determine the current magnitudes of the charge pump proportional unit and the charge pump integral unit based on the magnitude of the capacitor in the loop filter.

[0097] In one implementation, both the charge pump proportional unit and the charge pump integral unit mentioned above include several current mirror units;

[0098] The dynamic unit matching module is further configured to determine the number of current mirror units in the charge pump proportional unit and the charge pump integral unit that are turned on based on the current magnitude of the charge pump proportional unit and the charge pump integral unit, and to turn on the current mirror units in the charge pump proportional unit and the charge pump integral unit respectively based on the number of current mirror units in the charge pump proportional unit and the charge pump integral unit.

[0099] In one implementation, the charge pump proportional unit is used to generate a corresponding charging current or discharging current based on a determined charging or discharging and the number of current mirror units in the charge pump proportional unit that are turned on; the charge pump integral unit is used to generate a corresponding charging current or discharging current based on a determined charging or discharging and the number of current mirror units in the charge pump integral unit that are turned on.

[0100] In one embodiment, the charge pump proportional unit includes a first charging unit and a first discharging unit. The first charging unit includes a first P-type field-effect transistor (FET), and the first discharging unit includes a first N-type field-effect transistor (FET). The gate of the first P-type FET is used to receive a first bias voltage, the source of the first P-type FET is connected to a power supply, and the drain of the first P-type FET is connected to the dynamic unit matching module. The gate of the first N-type FET is used to receive a second bias voltage, the source of the first N-type FET is grounded, and the drain of the first N-type FET is connected to the dynamic unit matching module.

[0101] In one embodiment, the charge pump integration unit includes a second charging unit and a second discharging unit. The second charging unit includes a second P-type field-effect transistor (FET), and the second discharging unit includes a second N-type field-effect transistor (FET). The gate of the second P-type FET is used to receive a first bias voltage, the source of the second P-type FET is connected to a power supply, and the drain of the second P-type FET is connected to the dynamic unit matching module. The gate of the second N-type FET is used to receive a second bias voltage, the source of the second N-type FET is grounded, and the drain of the second N-type FET is connected to the dynamic unit matching module.

[0102] In one implementation, the first charging unit, the first discharging unit, the second charging unit, and the second discharging unit each include a plurality of current mirror units; the dynamic unit matching module includes a first dynamic unit matcher and a second dynamic unit matcher.

[0103] The first dynamic unit matcher is used to determine the number of current mirror units in the first charging unit and the second charging unit that are turned on based on the size of the capacitor in the loop filter, and to turn on the current mirror units in the first charging unit and the second charging unit respectively based on the number of current mirror units in the first charging unit and the second charging unit.

[0104] The second dynamic unit matcher is used to determine the number of current mirror units in the first discharge unit and the second discharge unit that are turned on based on the size of the capacitor in the loop filter, and to turn on the current mirror units in the first discharge unit and the second discharge unit respectively based on the number of current mirror units in the first discharge unit and the second discharge unit.

[0105] In one implementation, the current mirror units in the first charging unit and the second charging unit are turned on, specifically including randomly turning on the current mirror units in the first charging unit and the second charging unit; the current mirror units in the first discharging unit and the second discharging unit are turned on, specifically including randomly turning on the current mirror units in the first discharging unit and the second discharging unit.

[0106] The charge pump provided in this embodiment of the invention determines charging or discharging based on a charge / discharge control signal, determines the current magnitude of the charge pump proportional unit and the charge pump integral unit, and generates a corresponding charging current or discharging current based on the determined charging or discharging and the current magnitude of the charge pump proportional unit and the charge pump integral unit. This can eliminate the mismatch between the charging current and discharging current of the charge pump proportional unit and the charge pump integral unit themselves, as well as the mismatch in the current ratio between the charge pump integral unit and the charge pump proportional unit, thereby effectively suppressing stray emissions.

[0107] The fourth embodiment of the present invention provides a chip including the phase-locked loop circuit or charge pump described in any of the above embodiments.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A phase-locked loop circuit, characterized in that, It includes a frequency and phase detector, a charge pump module, a loop filter, a voltage-controlled oscillator, and a frequency divider. The charge pump module includes a charge pump proportional unit, a charge pump integral unit, and a dynamic unit matching module. The charge pump proportional unit and the charge pump integral unit each include several current mirror units. The frequency and phase detector is used to receive a reference clock signal and the output signal of the frequency divider, and to generate a charge and discharge control signal based on the reference clock signal and the output signal of the frequency divider. The charge pump module is used to receive the charge / discharge control signal and determine charging or discharging based on the charge / discharge control signal; The dynamic unit matching module is used to determine the current magnitude of the charge pump proportional unit and the charge pump integral unit based on the size of the capacitor in the loop filter. The dynamic unit matching module is also used to determine the number of current mirror units in the charge pump proportional unit and charge pump integral unit that are turned on based on the current magnitude of the charge pump proportional unit and charge pump integral unit, and to turn on the current mirror units in the charge pump proportional unit and charge pump integral unit respectively based on the number of current mirror units in the charge pump proportional unit and charge pump integral unit. The charge pump proportional unit is used to generate a corresponding charging current or discharging current based on a determined charging or discharging time and the number of current mirror units in the charge pump proportional unit that are turned on. The charge pump integrator is used to generate a corresponding charging current or discharging current based on a determined charging or discharging time and the number of current mirror units in the charge pump integrator. The loop filter is used to filter the charging current or discharging current to obtain a control voltage signal; The voltage-controlled oscillator is used to generate a phase-locked loop output signal of a preset frequency according to the control voltage signal; The frequency divider is used to divide the output signal of the phase-locked loop, and the divided signal is used as the output signal and input to the frequency and phase detector.

2. The phase-locked loop circuit according to claim 1, characterized in that, The charge pump proportional unit includes a first charging unit and a first discharging unit. The first charging unit includes a first P-type field-effect transistor, and the first discharging unit includes a first N-type field-effect transistor. The gate of the first P-type field-effect transistor is used to receive a first bias voltage, the source of the first P-type field-effect transistor is connected to a power supply, and the drain of the first P-type field-effect transistor is connected to the dynamic unit matching module. The gate of the first N-type field-effect transistor is used to receive the second bias voltage, the source of the first N-type field-effect transistor is grounded, and the drain of the first N-type field-effect transistor is connected to the dynamic unit matching module.

3. The phase-locked loop circuit according to claim 2, characterized in that, The charge pump integration unit includes a second charging unit and a second discharging unit. The second charging unit includes a second P-type field-effect transistor, and the second discharging unit includes a second N-type field-effect transistor. The gate of the second P-type field-effect transistor is used to receive a first bias voltage. The source of the second P-type field-effect transistor is connected to the power supply, and the drain of the second P-type field-effect transistor is connected to the dynamic unit matching module. The gate of the second N-type field-effect transistor is used to receive the second bias voltage, the source of the second N-type field-effect transistor is grounded, and the drain of the second N-type field-effect transistor is connected to the dynamic unit matching module.

4. The phase-locked loop circuit according to claim 3, characterized in that, The first charging unit, the first discharging unit, the second charging unit, and the second discharging unit each include a plurality of current mirror units; the dynamic unit matching module includes a first dynamic unit matcher and a second dynamic unit matcher; The first dynamic unit matcher is used to determine the number of current mirror units in the first charging unit and the second charging unit that are turned on based on the size of the capacitor in the loop filter, and to turn on the current mirror units in the first charging unit and the second charging unit respectively based on the number of current mirror units in the first charging unit and the second charging unit. The second dynamic unit matcher is used to determine the number of current mirror units in the first discharge unit and the second discharge unit that are turned on based on the size of the capacitor in the loop filter, and to turn on the current mirror units in the first discharge unit and the second discharge unit respectively based on the number of current mirror units in the first discharge unit and the second discharge unit.

5. The phase-locked loop circuit according to claim 4, characterized in that, The current mirror units in the first charging unit and the second charging unit are turned on respectively, specifically including randomly turning on the current mirror units in the first charging unit and the second charging unit respectively; the current mirror units in the first discharging unit and the second discharging unit are turned on respectively, specifically including randomly turning on the current mirror units in the first discharging unit and the second discharging unit respectively.

6. The phase-locked loop circuit according to claim 4, characterized in that, The charge pump module further includes a first switch, a second switch, a third switch, and a fourth switch; one end of the first switch is connected to the first dynamic unit matching device, the other end of the first switch is connected to one end of the second switch and the voltage-controlled oscillator, the other end of the second switch is connected to the second dynamic unit matching device, one end of the third switch is connected to the first dynamic unit matching device, the other end of the third switch is connected to one end of the fourth switch and the voltage-controlled oscillator, and the other end of the fourth switch is connected to the second dynamic unit matching device.

7. The phase-locked loop circuit according to claim 6, characterized in that, The loop filter includes an integrating capacitor Ci, a proportional capacitor Cp, a resistor Rp, and a buffer BUF. One end of the proportional capacitor Cp is connected to the other end of the first switch. The other end of the proportional capacitor Cp and one end of the integrating capacitor Ci are grounded. The other end of the integrating capacitor Ci is connected to the other end of the third switch and the input terminal of the buffer BUF. The output terminal of the buffer BUF is connected to one end of the resistor Rp, and the other end of the resistor Rp is connected to one end of the proportional capacitor Cp.

8. A phase-locked loop control method, characterized in that, Includes the following steps: Obtain a reference clock signal and a frequency divider signal, and generate a charge / discharge control signal based on the reference clock signal and the frequency divider signal; The charging or discharging is determined based on the charging / discharging control signal. The current magnitudes of the charge pump proportional unit and charge pump integral unit are determined based on the capacitance value in the loop filter. The number of current mirror units in the charge pump proportional unit and charge pump integral unit that are turned on is determined based on the current magnitudes of these units. Based on the number of current mirror units turned on in the charge pump proportional unit and charge pump integral unit, the current mirror units in these units are turned on. A corresponding charging current or discharging current is generated based on the determined charging or discharging and the number of current mirror units turned on in the charge pump proportional unit. A corresponding charging current or discharging current is generated based on the determined charging or discharging and the number of current mirror units turned on in the charge pump integral unit. The charging current or discharging current is filtered to obtain a control voltage signal; A phase-locked loop output signal of a preset frequency is generated based on the control voltage signal; The frequency-divided signal is obtained by dividing the output signal of the phase-locked loop.

9. A charge pump, characterized in that, The charge pump includes a charge pump proportional unit, a charge pump integral unit, and a dynamic unit matching module. The charge pump proportional unit and the charge pump integral unit each include several current mirror units. The charge pump is used to receive charge and discharge control signals, determine charging or discharging based on the charge and discharge control signals, and also to determine the current magnitude of the charge pump proportional unit and the charge pump integral unit. The dynamic unit matching module is used to determine the current magnitude of the charge pump proportional unit and the charge pump integral unit based on the size of the capacitor in the loop filter. The dynamic unit matching module is also used to determine the number of current mirror units in the charge pump proportional unit and charge pump integral unit that are turned on based on the current magnitude of the charge pump proportional unit and charge pump integral unit, and to turn on the current mirror units in the charge pump proportional unit and charge pump integral unit respectively based on the number of current mirror units in the charge pump proportional unit and charge pump integral unit. The charge pump proportional unit is used to generate a corresponding charging current or discharging current based on a determined charging or discharging time and the number of current mirror units in the charge pump proportional unit that are turned on. The charge pump integrator is used to generate a corresponding charging current or discharging current based on a determined charging or discharging time and the number of current mirror units in the charge pump integrator that are turned on.

10. A chip, characterized in that, Includes the phase-locked loop circuit as described in any one of claims 1-7 or the charge pump as described in claim 9.

Images