Bit interleaving method, electronic device and computer readable storage medium

Abstract

The embodiment of the invention provides a bit interleaving method, an electronic device and a computer readable storage medium, and the method comprises the steps: dividing a to-be-interleaved bit sequence into two parts, and carrying out the bit interleaving of the first part through employing a first interleaving mode, and bit-interleaving or not bit-interleaving the second part in a second interleaving mode, the first interleaving mode being different from the second interleaving mode. In the embodiment of the invention, the bit sequence to be interleaved is divided into two parts, the part meeting the integral multiple of the specified interleaving block is subjected to bit interleaving by adopting the first interleaving mode, and the part not meeting the integral multiple of the specified interleaving block is subjected to bit interleaving by adopting the second interleaving mode or is not subjected to bit interleaving, so that the bit interleaving efficiency is improved. The bit interleaving problem that an area to be interleaved is integer multiples of a non-specified interleaving block can be solved.

Description

Technical Field

[0001] The present invention relates to the field of communications, and more specifically, to a bit interleaving method, an electronic device, and a computer-readable storage medium. Background Technology

[0002] To address bit-centric errors, ITU-T G.9804.2 HSP (Higher Speed ​​Passive Optical Network) optionally employs bit interleaving in the downlink direction. The interleaving method involves bit interleaving every four Forward Error Correction (FEC) blocks. Each Forward Error Correction (FEC) block is 17280 bits. The interleaving method is as follows: Figure 1 As shown.

[0003] Figure 1 This is a schematic diagram of G.9804.2 bit interleaving, as shown below. Figure 1 As shown, the bit interleaving process is the formation of one interleaved block from four codewords during transmission. For every four FEC codewords, the first bit is taken from the beginning of the first codeword and sent, then the first bit from the beginning of the second codeword and sent, then the first bit from the beginning of the third and fourth codewords respectively, and so on, until all four codewords have been sent, forming an interleaved block of 17280 * 4 = 69120 bits. The process of forming four codewords from one interleaved block during reception is also described. For each 4-bit interleaved block, the first bit is used as the first bit of the first code block, the second bit is used as the first bit of the second code block, the third and fourth bits are used as the first bits of the third and fourth code blocks respectively, the fifth, sixth, seventh and eighth bits are used as the second bits of the first, second, third and fourth code blocks respectively, and so on, until the 4*17280-bit interleaved blocks form 4 FEC code blocks.

[0004] When the downlink rate of ITU-T G.9804.2HSP is 49.7664Gbps, the length of a superframe of 125 microseconds is 777600 bytes, or 6220800 bits, which is 360 times that of 17280 bits. It can be divided into 90 code block groups, and each code block group is 4 FEC code blocks. The downlink superframe length is an integer multiple of 4 FEC code blocks, and complete 4FEC code block bit interleaving can be used. Currently, standards organizations are discussing the need to introduce different FEC (Featured Overlay) codes for the downlink based on link loss. Potential FEC code options include LDPC (15872, 14592) and LDPC (17664-S, 14592-S), where S = CS * 256, and CS is a value between 19 and 35. Alternatively, there is the more general LDPC (C, P), where C is the block length, P is the payload length, and CP is the parity check length. LDPC stands for Low Density Parity Check. The FEC block lengths are 15872 bits, 17664-S bits, and C bits, respectively. When using these FEC code options, the downlink superframe length may no longer be an integer multiple of four FEC blocks. Therefore, how to achieve bit interleaving where the interleaved area is an integer multiple of the specified interleaving block is a problem that needs to be studied. Summary of the Invention

[0005] This invention provides a bit interleaving method, an electronic device, and a computer-readable storage medium to at least solve the problem of bit interleaving where the area to be interleaved is an integer multiple of a non-specified interleaving block in related technologies.

[0006] According to an embodiment of the present invention, a bit interleaving method is provided, the method comprising: dividing a bit sequence to be interleaved into two parts, performing bit interleaving on the first part using a first interleaving method, and performing bit interleaving on the second part using a second interleaving method or not performing bit interleaving, wherein the first interleaving method and the second interleaving method are different.

[0007] In an exemplary embodiment, the first interleaving method being different from the second interleaving method includes: the number of interleaving blocks in the first interleaving method being different from the number of interleaving blocks in the second interleaving method, or the length of the interleaving blocks in the first interleaving method being different from the length of the interleaving blocks in the second interleaving method.

[0008] In one exemplary embodiment, the first interleaving method includes a specified interleaving block length and the number of interleaving blocks.

[0009] In one exemplary embodiment, the first part is the part that meets the specified length, and the second part is the part that does not meet the specified length, wherein the specified length is an integer multiple of the number of interleaving blocks specified by the first interleaving method multiplied by the length of the interleaving blocks.

[0010] In one exemplary embodiment, the method further includes: indicating the second interleaving mode through configuration information in the first message, wherein the configuration information includes whether to perform bit interleaving on the second portion, or the number of interleaving blocks in the second interleaving mode.

[0011] In an exemplary embodiment, bit interleaving of the first portion using a first interleaving method includes bit interleaving of the first portion based on the number of interleaving blocks specified by the first interleaving method and the specified interleaving block length.

[0012] In one exemplary embodiment, if the length of the second part is less than or equal to the number of interleaving blocks of the second interleaving method multiplied by the parity length, the second part is not bit interleaved; if the length of the second part is greater than the number of interleaving blocks of the second interleaving method multiplied by the parity length, the second interleaving method is used to bit interleave the second part.

[0013] In one exemplary embodiment, bit interleaving of the second part using a second interleaving method includes:

[0014] Divide the length of the second part by the number of interleaving blocks in the second interleaving method to obtain the length of the interleaving block in the second interleaving method; perform bit interleaving on the second part based on the number of interleaving blocks and the length of the interleaving block in the second interleaving method.

[0015] In one exemplary embodiment, the bit sequence to be bit interleaved is a downlink frame or an uplink frame.

[0016] In one exemplary embodiment, the interleaving block length specified by the first interleaving method is the FEC code block length.

[0017] According to yet another embodiment of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0018] According to yet another embodiment of the present invention, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0019] According to yet another embodiment of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0020] By using the above embodiments of the present invention, since the bit sequence to be interleaved is divided into two parts, the first interleaving method is used for the part that satisfies the integer multiple of the specified interleaving block, and the second interleaving method or no bit interleaving is used for the part that does not satisfy the integer multiple of the specified interleaving block, the bit interleaving problem of the region to be interleaved being an integer multiple of the specified interleaving block can be solved. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the bit interleaving process based on relevant technologies;

[0022] Figure 2 This is a schematic diagram of the system architecture for the bit interleaving method according to an embodiment of the present invention;

[0023] Figure 3 This is a flowchart of a bit interleaving method according to an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of the basic interlacing method according to an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of uplink bandwidth according to an embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram of the bandwidth tail interleaving method according to an embodiment of the present invention;

[0027] Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0028] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0030] As described earlier, when the FEC coding scheme is used in the downlink of ITU-T G.9804.2HSP, the downlink superframe length may no longer be an integer multiple of four FEC blocks. Therefore, how to achieve bit interleaving where the area to be interleaved is an integer multiple of the specified interleaving blocks is a problem that needs to be studied. In addition, bit concentration errors also exist in the uplink direction of ITU-T G.9804.2HSP, thus requiring bit interleaving functionality in the uplink as well. Uplink bandwidth is allocated from the OLT (Optical Line Terminal) to the ONU (Optical Network Unit). Uplink bit interleaving is generally implemented within a burst transmitted by a single ONU. However, the uplink service of the ONU is dynamic, and the obtained uplink bandwidth is also dynamic. Within a specific burst, assuming the FEC coding scheme is LDPC (C, P), the area to be interleaved may not be an integer multiple of four FEC blocks. For portions less than four FEC blocks, bit interleaving may not be possible. Figure 1 The bit interleaving method shown.

[0031] The present invention addresses the problem of how to achieve bit interleaving where the area to be interleaved is an integer multiple of a non-specified interleaving block. This invention provides a bit interleaving method, an electronic device, a computer-readable storage medium, and a computer program product.

[0032] The methods and embodiments provided in this application can be executed on a mobile terminal, a computer terminal, or a similar computing device. Taking running on a computer terminal as an example, Figure 2 This is a hardware structure block diagram of the computer terminal used in the embodiments of the method of the present invention. For example... Figure 2 As shown, a computer terminal may include one or more ( Figure 2 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The computer terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 2 The structure shown is for illustrative purposes only and does not limit the structure of the computer terminal described above. For example, the computer terminal may also include components that are more complex than those described above. Figure 2 The more or fewer components shown, or having the same Figure 2 The different configurations shown.

[0033] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the bit interleaving method in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0034] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0035] This embodiment provides a bit interleaving method that can be run on the aforementioned computer terminal. Figure 3 This is a flowchart of a bit interleaving method according to an embodiment of the present invention, such as... Figure 3 As shown, the process includes the following steps:

[0036] Step S302: Divide the bit sequence to be interleaved into two parts, wherein the first part is the part that meets the specified length, and the second part is the part that does not meet the specified length.

[0037] The bit interleaving method provided in this embodiment can be applied to downlink bit interleaving using flexible FEC coding schemes, or uplink bit interleaving using flexible uplink bandwidth allocation and flexible FEC coding schemes. Therefore, the bit sequence to be interleaved can be, for example, a downlink superframe or an uplink burst frame.

[0038] In this embodiment, the first part refers to the portion that satisfies an integer multiple of the specified interleaving block, and the second part refers to the portion that, excluding the first part, does not satisfy an integer multiple of the specified interleaving block. For example, when the downlink direction of G.9804.2HSP uses the LDPC(15872, 14592) FEC code pattern, the code block length is 15872 bits, the payload length is 14592 bits, the parity length is 15872-14592=1280 bits, and the downlink superframe length is 6220800 bits, consisting of 391 code blocks and the remaining 14848 bits. Assuming a 4-block bit interleaving is used, 388 code blocks satisfy an integer multiple of the specified interleaving block, and are therefore divided into the first part, while the remaining 3 code blocks and 14848 bits do not satisfy an integer multiple of the specified interleaving block, and are therefore divided into the second part.

[0039] Step S304: Perform bit interleaving on the first part using the first interleaving method, and perform bit interleaving on the second part using the second interleaving method or do not perform bit interleaving.

[0040] In this embodiment, different interleaving methods can be used for bit interleaving for the first part and the second part. For example, the number of interleaving blocks in the first interleaving method is different from the number of interleaving blocks in the second interleaving method, or the length of the interleaving block in the first interleaving method is different from the length of the interleaving block in the second interleaving method.

[0041] The first interleaving method can use a specified number of interleaving blocks and interleaving block length. For example, using 4-block bit interleaving, each block is 15872 bits long. First, take one bit from the beginning of the first block and send it. Then take one bit from the beginning of the second block and send it. Then take one bit from the beginning of the third and fourth blocks and send them in sequence. Then take the second bit from the first, second, third, and fourth blocks and send them in sequence, and so on, until all 4 blocks are sent, forming a total of 4*15872 bit interleaving blocks.

[0042] For the second interleaving method, the number of interleaving blocks in the second interleaving method can be indicated by configuration information.

[0043] For example, considering the first and second parts divided in step S302, the first part includes 388 FEC codes, which can be interleaved using a 4-block bit interleaving method. The second part includes 3 code blocks and 14848 bits, totaling 62464 bits, which are interleaved using the second interleaving method. That is, the second part is further divided into 4 bit blocks, each 15616 bits. In each bit block, 1280 bits are parity bits and 14336 bits are payload bits. When calculating the parity, the payload needs to be padded with 0s at the beginning or end to make it 14592 bits, and then the parity bits are calculated according to LDPC(15872, 14592). This can still be done by taking the first bit of each bit and sending it sequentially, as described above, until all 4 bit blocks have been sent. Here, the number of bit blocks n = 4, and the bit block length X = 15616. The length of the interleaving block in the second interleaving method is different from the length of the interleaving block in the first interleaving method.

[0044] By using the above steps S302 and S304, the bit sequence to be interleaved is divided into two parts. The first interleaving method is used for the part that meets the integer multiple of the specified interleaving block, and the second interleaving method or no bit interleaving is used for the part that does not meet the integer multiple of the specified interleaving block. Therefore, the bit interleaving problem of the area to be interleaved being an integer multiple of the specified interleaving block can be solved.

[0045] It should be noted that the above steps are mainly described from the interleaving end. Similarly, at the deinterleaving end, deinterleaving can be performed according to the corresponding deinterleaving method described above to obtain the original bit sequence. For example, at the deinterleaving end, for every n*X bit interleaving block, the first bit of the interleaving block is used as the first bit of the first bit block, the second bit of the interleaving block is used as the first bit of the second bit block, the third, ..., nth bits of the interleaving block are used as the first bits of the third, ..., nth bit blocks respectively, the (n+1), (n+2), ..., 2nth bits of the interleaving block are used as the second bits of the first, second, ..., nth bit blocks respectively, and so on, until n*X bits form n bit blocks.

[0046] To facilitate understanding of the technical solution provided by this invention, the following description will be based on specific implementation scenarios.

[0047] Before describing the specific implementation scenarios of the present invention, let's first introduce the basic interleaving methods involved in the implementation of the present invention.

[0048] The basic interleaving methods involved in the embodiments of the present invention are as follows: Figure 4 As shown, n X-bit blocks are interleaved into n*X-bit interleaved blocks, and n*X-bit interleaved blocks are deinterleaved into n X-bit blocks.

[0049] During transmission, for every n bit blocks, the first bit is taken from the beginning of the first bit block and sent, then the first bit is taken from the beginning of the second bit block and sent, then the first bit is taken from the beginning of the third, ..., nth bit blocks and sent in sequence, then the second bit is taken from the first, second, third, ..., nth bit blocks and sent in sequence, and so on, until all n bit blocks are sent, forming an interleaved block of a total of n*X bits.

[0050] During the reception process, for each n*X bit interleaving block, the first bit of the interleaving block becomes the first bit of the first bit block, the second bit of the interleaving block becomes the first bit of the second bit block, the third, ..., nth bits of the interleaving block become the first bits of the third, ..., nth bit blocks respectively, the (n+1), (n+2), ..., 2nth bits of the interleaving block become the second bits of the first, second, ..., nth bit blocks respectively, and so on, until n*X bits form n bit blocks.

[0051] Taking the FEC code patterns LDPC (17280, 14592) and 4FEC code block interleaving methods in the existing standards as examples, the following is adopted: Figure 4 Interleaving and deinterleaving are performed in a manner where the number of bit blocks n = 4 and the bit block length X = 17280. For shorter bit blocks, less than 4 * 17280 bits, they can generally be represented as n * X', where the bit block length X' < 17280. When X' ≤ the parity length (here, 17280 - 14592 = 2688), these bit blocks do not transmit service data because there is insufficient space in X' to transmit the payload; therefore, only padding values ​​are transmitted. Of course, to consider bandwidth utilization, this part can adopt a new interleaving method, such as using a smaller number of bit blocks n' to obtain a larger bit block, or even not interleaving and only transmitting a single FEC code block, so that these parts can transmit the payload in addition to sending the parity check. This function is implemented through configuration. When X' > the parity length, X' can transmit the payload in addition to sending the parity check. Flexible bit interleaving methods can be adopted, continuing to follow... Figure 4 Interleaving is performed in a manner that keeps the number of bit blocks n=4 unchanged, and the bit block length is X=X'.

[0052] The interleaving method for the tail (i.e., the second part in the previous embodiment) can be set, for example, by the RR bits in the 6th byte of the Burst_Profile message, as shown in Table 1 below. For example, RR=00 indicates no interleaving in the tail portion, 01 indicates 2-block interleaving in the tail portion, 10 indicates 3-block interleaving in the tail portion, and 11 indicates 4-block interleaving in the tail portion. RR is valid for both uplink and downlink.

[0053] Table 1

[0054]

[0055] Implementation Method 1:

[0056] In this first embodiment, we will take the interleaving of the LDPC (15872, 14592) FEC code pattern in the downlink direction of G.9804.2HSP as an example.

[0057] When the downlink direction of G.9804.2HSP uses the LDPC(15872, 14592) FEC code pattern, the block length is 15872 bits, the payload length is 14592 bits, and the parity check length is 15872-14592=1280 bits. The bit interleaving method is as follows:

[0058] The downlink superframe length is 6,220,800 bits, consisting of 391 code blocks and the remaining 14,848 bits. Assuming 4-code-block bit interleaving is used, 388 code blocks can be interleaved into 97 interleaved blocks. The remaining 3 code blocks and 14,848 bits cannot be interleaved using the complete 4-code-block bit interleaving method, so the tail bit interleaving method (i.e., the second interleaving method in the second part of the previous embodiment) is used.

[0059] The tail bit interleaving method in this embodiment is as follows: The three code blocks and 14848 bits (a total of 62464 bits) are divided into four bit blocks, each containing 15616 bits. Within each block, 1280 bits are parity bits and 14336 bits are payload bits. When calculating the parity, the payload is padded with 0s at the beginning or end to make it 14592 bits, and then the parity bits are calculated according to LDPC(15872, 14592). Then, the tail bit interleaving method is used, i.e., it still follows... Figure 4 The interleaving method shown has n = 4 bit blocks and X = 15616 bit blocks. The specific interleaving process will not be described in detail here.

[0060] Implementation Method 2

[0061] In this second implementation method, the G.9804.2HSP downlink direction using the LDPC(17664-CS*256, 14592-CS*256) FEC code pattern is used as an example for explanation.

[0062] When the downlink direction of G.9804.2HSP uses the LDPC (17664-CS*256, 14592-CS*256) FEC code pattern (where CS is 19 to 35), the block length is 17664-CS*256 bits, the payload length is 14592-CS*256 bits, and the parity check length is (17664-CS*256)-(14592-CS*256)=3072 bits. The bit interleaving method is as follows:

[0063] When CS=19, the LDPC(12800, 9728) is used, with a block length of 12800 bits, a payload length of 9728 bits, and a downlink superframe length of 6220800 bits, resulting in 486 blocks. Assuming 4-block bit interleaving is used, all 484 blocks can be interleaved into 121 interleaved blocks. The remaining two blocks, totaling 19456 bits, are divided into four 4864-bit blocks, each containing 3072 parity bits and 1792 payload bits. When calculating the parity, the payload is padded with 0s to make it 9728 bits before or after the calculation, and then the parity bits are calculated according to LDPC(12800, 9728) to form a 12800-bit block. Finally, the tail bit interleaving method is used, i.e., it still follows... Figure 4 The interleaving method shown has a bit block number n = 4 and a bit block length X = 4864.

[0064] When CS=35, the LDPC (8704, 5632) is used, with a block length of 8704 bits, a payload length of 5632 bits, and a downlink superframe length of 6220800 bits, resulting in 712 blocks and 23552 bits remaining. Assuming 4-block bit interleaving is used, all 712 blocks can be interleaved into 178 interleaved blocks. The remaining 23552 bits are divided into 4 bit blocks, each with 5888 bits, of which 3072 bits are parity bits and 2816 bits are payload bits. When calculating the parity, the payload needs to be padded with 0s at the beginning or end to make it 5632 bits before calculating the parity bits according to LDPC (8704, 5632) to form a block with a bit length of 8704 bits. Then, the tail bit interleaving method is used, i.e., still according to... Figure 4 The interleaving method shown has a bit block number n = 4 and a bit block length X = 5888.

[0065] Other CS values ​​are shown in Table 2 below (taking 4-bit block interleaving as an example). When CS = 24, the number of downlink code blocks is exactly a multiple of 4, and bit interleaving can be performed according to the number of bit blocks n = 4 and the bit block length X = 11520. When CS = 22, the number of downlink code blocks is 129 4-bit code blocks. This part is bit interleaved according to the number of bit blocks n = 4 and the bit block length X = 12032, leaving 4 * 3072 bits. Each bit block is equal to the parity length, which cannot carry the payload. Send padding values. CS=26 is similar; CS=23, 25, 28, 32, which include 132, 138, 148, and 164 4-code blocks respectively, are bit-interleaved according to the number of bit blocks n=4 and the bit block length X=i1776, 11264, 10496, and 9472 respectively. The remaining number of bits is less than 4*3072, and the length of each bit block is less than 3072 bits. Then send padding values; for other CS values, refer to the interleaving method for CS=19 and 35.

[0066] Of course, for CS=22, 26, 23, 25, 28, 32, in order to consider bandwidth utilization, the tail portion can adopt a new interleaving method, such as using a smaller number of bit blocks n' to obtain a larger bit block, or even not interleaving and only sending a single FEC code block, so that these tail portions can send the payload in addition to sending the check.

[0067] Table 2 Interleaving References under Different CS Conditions

[0068]

[0069]

[0070] Implementation Method 3

[0071] This implementation method three uses row bit interleaving as an example for explanation.

[0072] The uplink FEC of G.9804.2HSP uses LDPC, which has three code types. Taking LDPC (17280, 14592) as an example, and taking 4LDPC code block interleaving as an example.

[0073] The uplink data transmission of the ONU is arranged by the uplink bandwidth allocated by the OLT, such as... Figure 5 As shown, the uplink bandwidth allocated by the OLT includes the uplink bandwidth explicitly allocated to the T-CONT, such as... Figure 5 The GrantSize A and GrantSize B, Allocation A and Allocation B, and other implicitly allocated uplink bandwidth, including... Figure 5The bandwidth used for FS header, FS trailer, etc., and the bandwidth for adding FEC check run FEC-protected data to FSburst (Framing Sublayer burst).

[0074] During the bandwidth allocation process from the OLT to the ONU, in order to achieve tail bit interleaving, the bandwidth corresponding to 4 parity blocks is reserved for the payload at the tail of the FS burst. Of course, the bandwidth allocation by the OLT can also be adjusted according to specific needs. If the goal is to achieve uniform bit interleaving in the uplink direction, the OLT can ensure that the length of the FS burst is an integer multiple of 4 FEC payloads when allocating uplink bandwidth. If the goal is to achieve uplink bandwidth utilization, fewer bit blocks can be interleaved or even no interleaving can be implemented for the payload at the tail of the FS burst, so that the OLT can reserve less uplink bandwidth corresponding to the FEC parity blocks.

[0075] Uplink bit interleaving begins with the first bit after PSBu. The ONU completes uplink FS burst framing based on the uplink bandwidth allocated by the OLT. The FS burst frame is then segmented according to the 4FEC code block payload, i.e., the FS burst frame is divided into four 14592-bit segments, each with an added checksum, forming a 17280-bit block. For each complete 17280-bit block, according to... Figure 4 Interleaving is performed, with a bit block length of X = 17280 and a bit block number of n = 4.

[0076] For segments with fewer than four 14592-bit segments at the tail, divide them into four equal segments of length X' (<14592). Add a 2688-bit parity block to each segment, forming an X'+2688-bit block, and then proceed according to... Figure 4 Interleaving is performed, where the bit block length X = X' + 2688 and the number of bit blocks n = 4.

[0077] The OLT calculates the length of the ONU-transmitted burst based on the locally stored BWmap (Bandwidth map) and uplink bit interleaving options. Starting from the first bit after the burst PSBu, the burst is divided into four 17280-bit interleaving blocks. Each interleaving block is... Figure 4 Deinterleaving is performed in a manner where the bit block length X = 17280 and the number of bit blocks n = 4. For interleaved blocks with less than 4 * 17280 bits at the end, they are deinterleaved according to the 4 * X' method, and then according to... Figure 4 The deinterleaving is performed by the inverse operation of the interleaving method, where the bit block length X = X' and the number of bit blocks n = 4.

[0078] Other tail weaving methods will not be discussed further here.

[0079] Implementation Method 4

[0080] This fourth implementation method is also described using up-row bit interleaving as an example.

[0081] The uplink FEC of G.9804.2HSP uses LDPC, which has three code types. Taking LDPC (17280, 14592) as an example, and taking 4LDPC code block interleaving as an example.

[0082] The ONU acquires the uplink bandwidth allocated by the OLT, completes uplink FS burst framing, and segments the FS burst frame according to the 4FEC code block payload, that is, segments the FS burst frame into four 14592-bit segments.

[0083] For the complete four 14592-bit segments, according to Figure 4 Interleaving is performed, X = 14592, n = 4. The interleaved bit sequence is then re-divided into four 14594-bit blocks. A 2688-bit checksum is calculated for each bit block. The original payload block and the four checksum blocks are then sent together. The four checksum blocks can be interleaved again (according to...). Figure 4 (X = 2688, n = 4), and then each 2688 bit is placed sequentially after each 14592 bit block.

[0084] Figure 6 This is a schematic diagram of the bandwidth tail interleaving method according to an embodiment of the present invention. Figure 6 As shown, in this embodiment, for segments with less than four 14592-bit tails, if the length is less than or equal to four 2688-bit segments, then this portion is sent with padding values, for example, all zeros. Otherwise, the length of the four 2688-bit parity blocks is subtracted, and the remaining bandwidth is used to send service data to form the original payload block, which is then padded to four 14592-bit payload blocks, and then processed according to... Figure 4 Interleaving is performed, X = 14592, n = 4. The interleaved bit sequence is then re-divided into four 14594-bit blocks. A 2688-bit checksum is calculated for each bit block. The original payload block and the four checksum blocks are then sent together. The four checksum blocks can be interleaved again (according to...). Figure 4 (X = 2688, n = 4). For detailed interleaving processes of fewer than 4 FEC code blocks, please refer to [link to relevant documentation]. Figure 6 .

[0085] It should be noted that in the embodiments of the present invention, bit interleaving is completed when adding FEC check, and then scrambling is performed.

[0086] The uplink deinterleaving process of this embodiment of the invention is described below:

[0087] The OLT calculates the length of the ONU-transmitted burst based on the locally stored BWmap, descrambles the uplink burst, and then segments it according to 4FEC code blocks, that is, it is segmented into four 17280-bit segments.

[0088] For the complete four 17280-bit segments, according to Figure 4 The inverse operation of the interleaving method is used for deinterleaving, X = i7280, n = 4, after completing the FEC check, 4*14592 remain, and then according to... Figure 4 The method is used to de-intertwine, X = 14592, n = 4.

[0089] For segments with less than 414592 bits at the end, if the length is less than four 2688-bit blocks, this part is discarded; otherwise, four 2688-bit parity blocks are taken out, and the remaining part forms the original payload block. This is then filled into four 14592-bit payload blocks, with each parity block inserted into the corresponding 14592-bit payload block. Deinterleaving is then performed, with X = 17280 and n = 4. After completing the FEC check, the four 14592-bit payload blocks are deinterleaved again, with X = 14592 and n = 4. The padding is then removed, thus obtaining the bit sequence before interleaving.

[0090] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0091] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0092] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0093] Embodiments of the present invention also provide a computer program product, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0094] like Figure 7 As shown, embodiments of the present invention also provide an electronic device 400, which includes a processor 401 and a memory 402, wherein the memory 402 stores a computer program, and the processor 401 is configured to run the computer program to perform the steps in any of the above method embodiments.

[0095] In one exemplary embodiment, the electronic device 400 may further include a transmission device and an input / output device (not shown in the figure), wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0096] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0097] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0098] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A bit interleaving method, characterized in that, include: The bit sequence to be interleaved is divided into two parts. The first part is interleaved using a first interleaving method, and the second part is interleaved using a second interleaving method or not interleaved. The first interleaving method and the second interleaving method are different.

2. The method according to claim 1, characterized in that, The first interleaving method is different from the second interleaving method in the following ways: The number of interlacing blocks in the first interlacing method is different from the number of interlacing blocks in the second interlacing method, or the length of the interlacing blocks in the first interlacing method is different from the length of the interlacing blocks in the second interlacing method.

3. The method according to claim 1, characterized in that, The first interleaving method includes a specified interleaving block length and number of interleaving blocks.

4. The method according to claim 3, characterized in that, The first part is the part that meets the specified length, and the second part is the part that does not meet the specified length, wherein the specified length is an integer multiple of the number of interleaving blocks specified by the first interleaving method multiplied by the length of the interleaving blocks.

5. The method according to claim 1, characterized in that, Also includes: The second interleaving method is indicated by the configuration information in the first message, wherein the configuration information includes whether to perform bit interleaving on the second part, or the number of interleaving blocks in the second interleaving method.

6. The method according to claim 3, characterized in that, Bit interleaving of the first part using the first interleaving method includes: The first part is bit-interleaved based on the number of interleaving blocks and the specified interleaving block length specified in the first interleaving method.

7. The method according to claim 2, characterized in that, If the length of the second part is less than or equal to the number of interleaving blocks in the second interleaving method multiplied by the parity length, the second part is not bit interleaved; if the length of the second part is greater than the number of interleaving blocks in the second interleaving method multiplied by the parity length, the second interleaving method is used to bit interleave the second part.

8. The method according to claim 7, characterized in that, The second part is bit-interleaved using the second interleaving method, including: Divide the length of the second part by the number of interlacing blocks in the second interlacing method to obtain the length of the interlacing block in the second interlacing method: The second part is bit-interleaved based on the number of interleaving blocks and the length of the interleaving blocks in the second interleaving method.

9. The method according to claim 1, characterized in that, The bit sequence to be interleaved is a downlink frame or an uplink frame.

10. The method according to claim 1, characterized in that, The interleaving block length specified in the first interleaving method is the forward error correction (FEC) code block length.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 10.

12. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 10.

13. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1 to 10.

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