One-master multi-slave time division multiplexing communication method
By constructing a star topology and using time-division multiplexing communication methods, and employing multi-core heterogeneous SoCs and full-duplex differential buses, the problems of low communication rate, poor anti-interference, and high resource consumption in multi-node real-time communication systems are solved. This achieves efficient, flexible, and stable data transmission and fault recovery, adapting to the needs of different application scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-03-27
AI Technical Summary
Existing technologies in multi-node real-time communication systems suffer from problems such as low communication rate, poor anti-interference performance, difficulty in guaranteeing real-time performance, high resource consumption, and fixed system topology and number of nodes, making it difficult to meet the high real-time and high bandwidth requirements of modern industrial control and automotive networks.
A master-slave time-division multiplexing communication method is adopted to construct a star topology. Multi-core heterogeneous SoC and full-duplex differential bus are used. Time slice allocation and shared cache optimization are achieved through DMA direct memory access and 8b/10b encoding and decoding. Fault detection and recovery are performed to ensure communication latency determinism and data integrity.
It improves real-time communication and data throughput, reduces CPU load, enhances system flexibility and stability, adapts to different application scenarios, has communication latency control at the microsecond level, strong anti-interference capability, and supports automatic recovery of faulty nodes.
Smart Images
Figure CN121750449A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of multi-node real-time communication technology, specifically to a time-division multiplexing communication method with one master and multiple slaves. Background Technology
[0002] In modern industrial control and automotive networks, multi-node real-time communication systems need to meet the core requirements of high real-time performance, high bandwidth and low latency. The stability of their communication directly affects the operating efficiency and reliability of the entire control system. Therefore, a time-division multiplexing communication method with one master and multiple slaves is required.
[0003] Existing technologies generally adopt traditional communication technologies such as CAN, RS-485, SPI, I2C and Ethernet, and realize multi-node data exchange between boards through the built-in communication controller of the chip or the external communication chip.
[0004] The CAN bus is the most widely used multi-node communication scheme. It relies on a multi-master, linear bus architecture, with all nodes communicating in parallel through two lines, CAN_H and CAN_L. However, the traditional CAN bus has obvious limitations: the communication rate is low, with ordinary CAN rates usually below 1Mbps, and even CANFD can only reach 5Mbps, which is difficult to meet the high-speed transmission requirements of large amounts of data; and the sending and receiving of CAN messages depends on the CPU writing to the sending mailbox and reading from the receiving FIFO. If the CPU is occupied by high-priority tasks, the real-time processing of messages cannot be guaranteed.
[0005] Other traditional communication technologies also have significant drawbacks: SPI and I2C are non-differential buses with weak anti-interference performance, and are prone to signal distortion in complex industrial electromagnetic environments; Ethernet is inherently an uncertain network, which cannot guarantee that data packets will be delivered within a fixed time, making it difficult to meet real-time communication requirements; RS-485 lacks a hardware arbitration mechanism and needs to resolve communication conflicts through the software protocol layer, and in mainstream master-slave architectures, the slave station response time depends on the polling cycle, making real-time performance unreliable.
[0006] Traditional solutions often employ an architecture that combines a microprocessor with an independent communication interface chip. This results in bandwidth and latency bottlenecks in inter-chip communication. The processing, encoding, decoding, and polling scheduling of communication messages consume a large amount of CPU resources, affecting the real-time execution of business logic. Furthermore, the system topology, number of nodes, and communication parameters are fixed, making it difficult to flexibly adapt to the differentiated needs of different application scenarios. Summary of the Invention
[0007] To address the aforementioned technical shortcomings, the present invention aims to provide a time-division multiplexing communication method with one master and multiple slaves.
[0008] To solve the above technical problems, the present invention adopts the following technical solution: The present invention provides a one-master-multiple-slave time-division multiplexing communication method, including the following steps: Step 1, star topology construction and configuration: First, configure the master node and each slave node. Based on the master node and each slave node, set up a star topology structure, build physical links, and then perform hardware interconnection verification. After the verification is qualified, configure the core hardware initialization parameters.
[0009] Step 2: Time Division Multiplexing Timing Establishment: After the core hardware initialization parameters are configured, time slice allocation and timing calibration are performed to confirm the timing and enable periodic data interaction.
[0010] Step 3: Data transmission optimization: Optimize data transmission during periodic data interaction.
[0011] Step 4: Transmission Fault Detection: After data optimization, communication fault detection is performed, and a fault recovery process plan is generated.
[0012] Preferably, the core hardware initialization parameter configuration process is as follows: After the system is powered on, the PS side starts the embedded operating system, completes the initialization of the CPU, memory and bus interface, and the PL side loads the preset hardware logic bitstream file and activates the dedicated hardware circuits of the 8b / 10b codec, DMA controller and communication controller.
[0013] The master node and slave node establish communication with the PL side through the AXI on-chip high-speed bus, configure the bus transmission rate and data interaction mode, and initialize the hardware circuit parameters by writing to the PL side control register.
[0014] Each node configures its DDR memory address space via software, defining an independent shared memory area. The master node divides the memory into N transmit buffers and N receive buffers based on the number of slave nodes N. Each buffer corresponds to a unique slave node address, and the starting address and capacity are recorded in the address mapping table. Each slave node is divided into only one transmit buffer and one receive buffer, with a fixed address range and a read-write lock mechanism enabled.
[0015] The master node PS reads the global configuration parameters stored in Flash and writes them into the PL hardware register, thus solidifying the master node communication parameters. The master node initializes the link and sends configuration command messages to the slave nodes one by one in ascending order of slave node addresses. After receiving the messages, the slave nodes verify the integrity of the messages through the PL hardware. The master node's PL high-precision timer generates a timing reference signal and sends it to all slave nodes through a synchronization message. After receiving the synchronization message, the slave nodes calibrate their local timers.
[0016] Preferably, the periodic data interaction is performed as follows: S1, time-slice query interaction: According to the time-slice allocation table of the communication controller, the communication channel corresponding to the first slave node is activated. At the same time, after the master node PS side application organizes the data to be sent according to the preset message format, the PL side DMA controller directly reads the buffer data and sends it to the 8b / 10b encoder for encoding. The encoded differential signal is transmitted to the target slave node through the transmission channel. After the slave node PL side receives the differential signal, it decodes it through the decoder, verifies the frame header and frame tail and the address segment. After confirming that it matches its own address, it writes the data into the local shared receive buffer through the DMA controller and sends an interrupt signal to notify the PS side application.
[0017] S2. Slave Node Response Interaction: The application on the PS side of the slave node responds to the interrupt, reads the data in the receive buffer, processes it and generates response data. The DMA controller on the PL side of the slave node reads the response data, encapsulates it into a response message, encodes it and sends it back to the master node through the receive channel.
[0018] S3. Master Node Reception Processing: The master node (PL) receives the acknowledgment message, decodes it, verifies its integrity, writes it to the shared receive buffer of the corresponding slave node via DMA, and sends an interrupt notification to the PS-side application to read and process it, thus performing master node reception processing.
[0019] When the current time slice ends, the master node communication controller controls the multiplexer to switch to the channel corresponding to the next slave node, repeating S1 to S3 until all slave nodes have completed one round of polling. After one round of polling is completed, the master node automatically starts the next communication cycle to carry out continuous periodic data interaction.
[0020] The beneficial effects of this invention are as follows: 1. This invention first constructs a star topology, configures a multi-core heterogeneous SoC main control core and a full-duplex differential bus, and completes hardware interconnection verification and core parameter initialization; secondly, it establishes time-division multiplexing timing, allocates exclusive time slices according to the polling cycle and calibrates the timing to achieve ordered periodic data interaction; then, it optimizes data transmission through mechanisms such as shared cache read-write locks and overflow protection; finally, it performs communication fault detection and automatic recovery. This invention has the characteristics of deterministic communication latency, high data throughput, excellent resource utilization, and wide applicability to various scenarios, improving real-time performance, reducing CPU load, and further improving flexibility.
[0021] 2. This invention implements time-division multiplexing scheduling and 8b / 10b encoding / decoding functions in hardware based on multi-core heterogeneous SoC programmable logic (PL), avoiding the uncertainty brought about by software scheduling; the fixed polling cycle and exclusive time slice design ensure that the communication timing between the master node and each slave node is strictly isolated, the communication delay is controlled at the microsecond level, and the delay fluctuation is extremely small.
[0022] 3. This invention uses a full-duplex high-speed differential bus as the physical transmission medium, with independent and parallel transmission and reception channels, effectively improving physical bandwidth; combined with the DMA direct memory access mechanism, it realizes zero-copy data transmission, eliminating the need for CPU to participate in data copying and handling, greatly reducing CPU load, freeing up computing power for core business logic execution, while avoiding inter-chip communication bottlenecks, and significantly improving data transmission rate and system throughput.
[0023] 4. In a star topology, the master node and each slave node communicate through independent point-to-point links, avoiding bus contention and conflicts; the read-write lock mechanism and overflow protection design of the shared buffer prevent data overwriting or loss, ensuring the integrity of data transmission; the hardware-level ESD protection and differential transmission anti-interference design improve the system's operational stability in complex environments and reduce signal distortion and communication failures.
[0024] 5. The system supports configurable communication parameters, including the number of nodes, communication cycle, message format, baud rate, etc. The master node can be adapted to different network sizes and application scenarios through initial configuration without modifying the hardware design. The fault detection and automatic recovery mechanism can automatically skip the faulty node and reallocate time slices when some slave nodes fail, ensuring normal communication of the remaining nodes. At the same time, it supports automatic rejoining after the faulty node recovers, improving the system's scalability and fault tolerance. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a schematic diagram of the implementation steps of the method of the present invention. Detailed Implementation
[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0028] according to Figure 1As shown, the present invention provides a time-division multiplexing communication method with one master and multiple slaves, including the following steps: Step 1, star topology construction and configuration: First, configure the master node and each slave node. Based on the master node and each slave node, set up a star topology structure, build physical links, and then perform hardware interconnection verification. After the verification is qualified, configure the core hardware initialization parameters.
[0029] In one specific embodiment, the configuration of the master node and each slave node is as follows: the master node and all slave nodes use a multi-core heterogeneous SoC as the main control core, which integrates an ARM architecture processing system and an FPGA architecture programmable logic.
[0030] Each node is configured with DDR SDRAM memory and equipped with a full-duplex high-speed differential bus interface module.
[0031] The master node is additionally equipped with a time-division multiplexer and a high-precision timer, while the slave nodes are configured with address identification and timing synchronization modules.
[0032] In one specific embodiment, the star topology is configured as follows: the master node connects to each slave node through an independent point-to-point full-duplex physical link. Each link uses two pairs of shielded differential cables, which serve as the transmitting channel and the receiving channel, respectively. All physical layer interfaces of the links are designed with ESD protection enabled.
[0033] In one specific embodiment, the core hardware initialization parameter configuration process is as follows: After the system is powered on, the PS side starts the embedded operating system, completes the initialization of the CPU, memory and bus interface, and the PL side loads the preset hardware logic bitstream file and activates the dedicated hardware circuits of the 8b / 10b codec, DMA controller and communication controller.
[0034] The master node and slave node establish communication with the PL side through the AXI on-chip high-speed bus, configure the bus transmission rate and data interaction mode, and initialize the hardware circuit parameters by writing to the PL side control register.
[0035] Each node configures its DDR memory address space via software, defining an independent shared memory area. The master node divides the memory into N transmit buffers and N receive buffers based on the number of slave nodes N. Each buffer corresponds to a unique slave node address, and the starting address and capacity are recorded in the address mapping table. Each slave node is divided into only one transmit buffer and one receive buffer, with a fixed address range and a read-write lock mechanism enabled.
[0036] The master node PS reads the global configuration parameters stored in Flash and writes them into the PL hardware register, thus solidifying the master node communication parameters. The master node initializes the link and sends configuration command messages to the slave nodes one by one in ascending order of slave node addresses. After receiving the messages, the slave nodes verify the integrity of the messages through the PL hardware. The master node's PL high-precision timer generates a timing reference signal and sends it to all slave nodes through a synchronization message. After receiving the synchronization message, the slave nodes calibrate their local timers.
[0037] Step 2: Time Division Multiplexing Timing Establishment: After the core hardware initialization parameters are configured, time slice allocation and timing calibration are performed to confirm the timing and enable periodic data interaction.
[0038] In one specific embodiment, the time slice allocation and timing calibration confirmation process is as follows: the master node communication controller automatically calculates the exclusive time slice duration t=T / N for each slave node based on the preset polling period T and the number of slave nodes N, and generates a time slice allocation table.
[0039] The master node sends a time slice allocation table synchronization message to each slave node. After receiving the message, the slave node parses its own corresponding time slice information and sets the trigger threshold of its local timer. Subsequently, the slave node sends the timing calibration result back to the master node. The master node checks the calibration status of each slave node. Once there is no timing offset in each slave node, periodic data interaction is performed.
[0040] In one specific embodiment, the generation process of the time slice allocation table is as follows: record the slave node address corresponding to each time slice, obtain the preset first time slice start timestamp according to the order of each time slice, add the exclusive time slice duration in sequence to obtain the start timestamp of each time slice, and obtain the start time and end time corresponding to each time slice in sequence.
[0041] If t is less than the preset minimum interaction time from a single query to a response, the master node will automatically trigger a parameter adjustment prompt, requiring manual increase of the period T or reduction of the number of slave nodes.
[0042] Step 3: Data transmission optimization: Optimize data transmission during periodic data interaction.
[0043] In one specific embodiment, the periodic data interaction is performed as follows: S1, In-time slice query interaction: According to the time slice allocation table of the communication controller, the communication channel corresponding to the first slave node is activated. At the same time, after the master node PS side application organizes the data to be sent according to the preset message format, the PL side DMA controller directly reads the buffer data and sends it to the 8b / 10b encoder for encoding. The encoded differential signal is transmitted to the target slave node through the transmission channel. After the slave node PL side receives the differential signal, it decodes it through the decoder, verifies the frame header and frame tail and the address segment. After confirming that it matches its own address, it writes the data into the local shared receive buffer through the DMA controller and sends an interrupt signal to notify the PS side application.
[0044] It should be noted that the default message format is: frame header K28.5, address field, command field, data field, CRC32 checksum, and frame tail K28.1.
[0045] S2. Slave Node Response Interaction: The application on the PS side of the slave node responds to the interrupt, reads the data in the receive buffer, processes it and generates response data. The DMA controller on the PL side of the slave node reads the response data, encapsulates it into a response message, encodes it and sends it back to the master node through the receive channel.
[0046] It should be noted that the response message format is: frame header K28.5, address field, status code, data field, checksum, and frame trailer K28.1.
[0047] S3. Master Node Reception Processing: The master node (PL) receives the acknowledgment message, decodes it, verifies its integrity, writes it to the shared receive buffer of the corresponding slave node via DMA, and sends an interrupt notification to the PS-side application to read and process it, thus performing master node reception processing.
[0048] When the current time slice ends, the master node communication controller controls the multiplexer to switch to the channel corresponding to the next slave node, repeating S1 to S3 until all slave nodes have completed one round of polling. After one round of polling is completed, the master node automatically starts the next communication cycle to carry out continuous periodic data interaction.
[0049] In one specific embodiment, the data transmission optimization is performed as follows: both the master node and the slave node's shared buffer are equipped with a read-write lock mechanism. When the PS side writes data, it locks the corresponding buffer and prohibits the PL side from reading it simultaneously. After the write is completed, it unlocks and marks the status. When the PL side writes data, it locks the corresponding buffer and prohibits the PS side from reading it simultaneously. After the write is completed, it unlocks.
[0050] Each node shares a cache and enables a capacity monitoring mechanism. When the amount of data stored reaches a preset percentage of the cache capacity, the PL side sends an overflow alarm interrupt, and the PS side application suspends new data writing and prioritizes processing data within the cache.
[0051] Step 4: Transmission Fault Detection: After data optimization, communication fault detection is performed, and a fault recovery process plan is generated.
[0052] In one specific embodiment, the communication fault detection is implemented as follows: after the master node sends a query message, it starts a local timer to collect the query duration. If the query duration exceeds the threshold, the response is determined to be a timeout fault.
[0053] If the CRC32 checksum does not match after the master or slave node receives a message, it is determined to be a data error fault.
[0054] If a node experiences the aforementioned timeout or data error failure a preset number of times consecutively, the slave node is marked as a faulty node, and the fault type and occurrence time are recorded.
[0055] In one specific embodiment, the fault recovery process is generated as follows: when a faulty node occurs, an alarm is triggered to the staff, and the fault type and occurrence time are also indicated. In subsequent communication cycles, the master node skips the faulty node and reallocates time slices to the remaining slave nodes.
[0056] The examples described in this invention are not limited to the specific embodiments listed above. The examples are merely illustrative to facilitate understanding of the invention and do not constitute a limitation on the scope of protection of this invention. Any modifications, equivalent substitutions, etc., made within the spirit and principles of this invention should be included within the scope of protection.
[0057] The above description is merely an example and illustration of the concept of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described or use similar methods to replace them, as long as they do not deviate from the concept of the invention or exceed the scope defined in this specification, they should all fall within the protection scope of the present invention.
Claims
1. A time-division multiplexing communication method with one master and multiple slaves, characterized in that, Includes the following steps: Step 1: Star Topology Construction and Configuration: First, configure the master node and each slave node. Based on the master node and each slave node, set up the star topology structure, build the physical links, and then perform hardware interconnection verification. After the verification is successful, configure the core hardware initialization parameters. Step 2, Time Division Multiplexing Timing Establishment: After the core hardware initialization parameters are configured, time slice allocation and timing calibration are performed to confirm and enable periodic data interaction. Step 3: Data transmission optimization: Optimize data transmission during periodic data interaction. Step 4: Transmission Fault Detection: After data optimization, communication fault detection is performed, and a fault recovery process plan is generated.
2. The time-division multiplexing communication method with one master and multiple slaves according to claim 1, characterized in that, The configuration process for the master node and each slave node is as follows: The master node and all slave nodes use a multi-core heterogeneous SoC as the main control core. This chip integrates an ARM architecture processing system and an FPGA architecture programmable logic. Each node is configured with DDR SDRAM memory and equipped with a full-duplex high-speed differential bus interface module; The master node is additionally equipped with a time-division multiplexer and a high-precision timer, while the slave nodes are configured with address identification and timing synchronization modules.
3. The time-division multiplexing communication method with one master and multiple slaves according to claim 2, characterized in that, The specific process for setting up a star topology is as follows: The master node connects to each slave node through an independent point-to-point full-duplex physical link. Each link uses two pairs of shielded differential cables, which serve as the transmitting channel and the receiving channel, respectively. All physical layer interfaces of the links are designed with ESD protection enabled.
4. The time-division multiplexing communication method with one master and multiple slaves according to claim 3, characterized in that, The core hardware initialization parameter configuration process is as follows: After the system is powered on, the PS side starts the embedded operating system and completes the initialization of the CPU, memory and bus interface. The PL side loads the preset hardware logic bitstream file and activates the dedicated hardware circuits of the 8b / 10b codec, DMA controller and communication controller. The master node and slave node establish communication with the PL side through the AXI on-chip high-speed bus, configure the bus transmission rate and data interaction mode, and the PS side initializes the hardware circuit parameters by writing to the PL side control register. Each node configures the DDR memory address space through software and delineates an independent shared memory area. The master node divides the number of slave nodes into N transmit buffers and N receive buffers. Each buffer corresponds to a unique slave node address. The starting address and capacity are recorded in the address mapping table. The slave node is divided into only 1 transmit buffer and 1 receive buffer, with a fixed address range and a read-write lock mechanism enabled. The master node PS reads the global configuration parameters stored in Flash and writes them into the PL hardware register, thus solidifying the master node communication parameters. The master node initializes the link and sends configuration command messages to the slave nodes one by one in ascending order of slave node addresses. After receiving the messages, the slave nodes verify the integrity of the messages through the PL hardware. The master node's PL high-precision timer generates a timing reference signal and sends it to all slave nodes through a synchronization message. After receiving the synchronization message, the slave nodes calibrate their local timers.
5. The time-division multiplexing communication method with one master and multiple slaves according to claim 1, characterized in that, The time slice allocation and timing calibration confirmation process is as follows: The master node communication controller automatically calculates the exclusive time slice duration t=T / N for each slave node based on the preset polling period T and the number of slave nodes N, and generates a time slice allocation table. The master node sends a time slice allocation table synchronization message to each slave node. After receiving the message, the slave node parses its own corresponding time slice information, sets the trigger threshold of its local timer, and then sends the timing calibration result back to the master node. The master node checks the calibration status of each slave node, and periodic data interaction is performed when there is no timing offset among the slave nodes.
6. The time-division multiplexing communication method with one master and multiple slaves according to claim 5, characterized in that, The specific process for generating the time slice allocation table is as follows: Record the slave node address corresponding to each time slice. According to the order of each time slice, obtain the preset start timestamp of the first time slice. Add the exclusive time slice duration in sequence to obtain the start timestamp of each time slice. Then, obtain the start time and end time corresponding to each time slice in sequence. If t is less than the preset minimum interaction time from a single query to a response, the master node will automatically trigger a parameter adjustment prompt, requiring manual increase of the period T or reduction of the number of slave nodes.
7. The time-division multiplexing communication method with one master and multiple slaves according to claim 1, characterized in that, The periodic data interaction is carried out, and the specific interaction process is as follows: S1. In-time slot query interaction: According to the communication controller's time slot allocation table, the communication channel corresponding to the first slave node is activated. At the same time, after the master node PS side application organizes the data to be sent according to the preset message format, the PL side DMA controller directly reads the buffer data and sends it to the 8b / 10b encoder for encoding. The encoded differential signal is transmitted to the target slave node through the transmission channel. After the slave node PL side receives the differential signal, it decodes it through the decoder, verifies the frame header and frame tail and the address segment. After confirming that it matches its own address, it writes the data into the local shared receive buffer through the DMA controller and sends an interrupt signal to notify the PS side application. S2, Slave Node Response Interaction: The application on the PS side of the slave node responds to the interrupt, reads the data in the receive buffer, processes it and generates response data. The DMA controller on the PL side of the slave node reads the response data, encapsulates it into a response message, encodes it and feeds it back to the master node through the receive channel. S3. Master Node Reception Processing: The master node PL side receives the acknowledgment message, decodes it, verifies its integrity, writes it to the shared receive buffer of the corresponding slave node via DMA, and sends an interrupt notification to the PS side application to read and process it, thereby performing master node reception processing. When the current time slice ends, the master node communication controller controls the multiplexer to switch to the channel corresponding to the next slave node, repeating S1 to S3 until all slave nodes have completed one round of polling. After one round of polling is completed, the master node automatically starts the next communication cycle to carry out continuous periodic data interaction.
8. The time-division multiplexing communication method with one master and multiple slaves according to claim 1, characterized in that, The data transmission optimization process is as follows: Both the master node and the slave node's shared buffer are equipped with a read-write lock mechanism. When writing data on the PS side, the corresponding buffer is locked to prevent the PL side from reading it simultaneously. After the write is completed, the buffer is unlocked and the status is marked. When writing data on the PL side, the corresponding buffer is locked to prevent the PS side from reading it simultaneously. After the write is completed, the buffer is unlocked. Each node shares a cache and enables a capacity monitoring mechanism. When the amount of data stored reaches a preset percentage of the cache capacity, the PL side sends an overflow alarm interrupt, and the PS side application suspends new data writing and prioritizes processing data within the cache.
9. The time-division multiplexing communication method with one master and multiple slaves according to claim 1, characterized in that, The specific implementation process for communication fault detection is as follows: After the master node sends a query message, it starts a local timer to collect the query duration. If the query duration exceeds the threshold, the response is judged as a timeout fault. If the CRC32 checksum does not match after the master node or slave node receives a message, it is determined to be a data error fault. If a node experiences the aforementioned timeout or data error failure a preset number of times consecutively, the slave node is marked as a faulty node, and the fault type and occurrence time are recorded.
10. The time-division multiplexing communication method with one master and multiple slaves according to claim 1, characterized in that, The specific generation process for the fault recovery procedure is as follows: When a faulty node occurs, an alarm is triggered to the staff, along with the fault type and the time of occurrence. In subsequent communication cycles, the master node skips the faulty node and reallocates time slices to the remaining slave nodes.