Multi-machine high-frequency carrier synchronization system based on differential isolation and control method thereof

Abstract

The invention provides a multi-machine high-frequency carrier synchronization system based on differential isolation, which comprises a plurality of converters connected in parallel for operation control, a microcontroller unit of each converter is provided with a carrier synchronization sending module and a carrier synchronization receiving module, and each converter comprises a microcontroller unit and two synchronization signal conversion units. The output end of the sending module and the input end of the receiving module are connected with the logic level side of the synchronizing signal conversion unit, the differential level side of the synchronizing signal conversion unit is connected to the positive and negative lines of a differential bus in parallel, and all converters can send or obtain carrier synchronizing signals through the differential bus; master-slave distribution does not need to be carried out on the converters connected in parallel, the synchronizing signal conversion unit is used for converting logic level signals sent by the microcontroller unit into isolation differential signals to be sent and converting received differential signals into logic level signals to be sent to the microcontroller, and therefore the synchronizing signal transmission capacity is improved.

Description

Technical Field

[0001] This invention relates to the field of converter technology, and in particular to a multi-machine high-frequency carrier synchronization system based on differential isolation and its control method. Background Technology

[0002] With the rapid development of converter technology, the demand and application scenarios for multi-machine parallel operation are increasing. However, the high-frequency circulating current caused by carrier asynchrony in multi-machine parallel operation seriously affects the stability of the system and increases losses. The carrier synchronization technology can effectively solve the above problems. However, traditional carrier synchronization technology uses optical fiber transmission and requires handshake communication. This solution has problems such as high cost, complex function implementation, poor synchronization effect and reliability.

[0003] In the field of new energy power generation and energy storage systems, building large-capacity energy storage systems by connecting multiple inverters in parallel has become the mainstream development direction in the industry. In such systems, the amplitude, frequency and phase of the output voltage of each inverter device must be strictly synchronized to minimize the circulating current loss between units. Excessive circulating current will lead to a decrease in system efficiency, increased device heating, and even trigger protection shutdown, directly affecting the stability and reliability of the energy storage system.

[0004] To address carrier synchronization issues, the industry commonly employs a "master-slave collaborative" architecture: one inverter is designated as the master to generate the reference carrier, while the others act as slaves to track the master's signal, supporting dynamic switching between master and slave roles to improve system redundancy. However, existing master-slave synchronization solutions suffer from significant technical bottlenecks: traditional carrier synchronization relies on communication links such as CAN and Ethernet to transmit synchronization commands. This communication process is susceptible to electromagnetic interference, leading to signal loss or distortion. Furthermore, communication latency (typically tens to hundreds of milliseconds) reduces synchronization response speed, making it difficult to meet the nanosecond-level synchronization accuracy requirements of high-frequency carriers (e.g., above 10kHz). Especially in master-slave switching scenarios, communication delays can cause brief synchronization interruptions, triggering circulating current surges and negatively impacting system stability.

[0005] Furthermore, existing solutions lack adequate fault tolerance mechanisms for synchronization anomalies: when an inverter fails to operate, the traditional master-slave switching logic requires communication negotiation to elect a new master, during which the carrier synchronization link is interrupted, further amplifying the risk of system fluctuations. Simultaneously, most designs do not consider hardware-level protection and isolation of the synchronization signal. In complex electromagnetic environments, the synchronization signal is susceptible to ground current interference, causing the slave to misjudge the master's status and exacerbating the carrier synchronization problem.

[0006] In summary, existing inverter systems face multiple technical challenges in carrier synchronization, including insufficient synchronization accuracy due to communication interference, circulating current impacts caused by switching delays, and weak hardware anti-interference capabilities. Therefore, developing an inverter carrier synchronization solution that does not rely on complex communication and possesses hardware-level rapid synchronization and seamless switching capabilities to improve the operational stability and reliability of large-capacity energy storage systems has become a critical technical issue that urgently needs to be addressed in this field.

[0007] Chinese patent CN120825041B discloses an inverter carrier synchronization system for parallel operation control of multiple inverters in a large-capacity energy storage system. The system includes multiple inverter devices connected via cascaded communication. Each inverter device includes a CPLD unit, a drive unit connected to the first output pin of the CPLD unit, a fault output unit, and a fault identification unit. The CPLD unit generates or forwards a carrier synchronization signal and controls the drive unit to excite the fault output unit, causing the first contact of the relay in the fault output unit to output a fault status to the next-level inverter device. The fault identification unit is used to detect the fault status signal output by the previous inverter device to determine the master / slave identity of the current inverter device. In the cascaded link, the first-stage inverter device is the master, and the fault status signal output by any normal inverter device is low. When any inverter device loses power or malfunctions, the relay in its fault output unit opens, causing the fault status signal output by the first contact to be high. After the next-stage inverter device detects the high-level fault status signal, the next-stage inverter device automatically switches to become the master of the downstream inverter device, solving the problem of high-reliability parallel control. This application avoids the address conflict and data arbitration delay of traditional bus communication through "cascaded communication + CPLD high-speed control". The fast response capability of the CPLD unit can ensure the real-time generation / forwarding of carrier synchronization signals, reduce circulating current when multiple devices are connected in parallel, and improve the output power quality of the energy storage system. It enables fault redundancy and automatic switching: This application relies on hardware-based fault transmission of "relay on / off + level detection," eliminating the need for complex software judgments and enabling rapid fault state identification and automatic host switching. Even if multiple upstream devices fail consecutively, the carrier synchronization signal can still be ensured to remain uninterrupted through "automatic replacement at the next level," significantly improving the operational redundancy of large-capacity energy storage systems and preventing the entire system from shutting down due to the failure of a single device. It is also flexibly adaptable to large-capacity scenarios: This application adopts a cascaded communication method, which can support the expansion of multiple inverter devices. Without making significant modifications to the existing hardware structure, the total power of the energy storage system can be increased by adding the number of inverter devices, adapting to energy storage scenarios with different capacity requirements and possessing good scalability.

[0008] Chinese patent CN112260517A discloses a converter synchronization controller for synchronous control of multiple parallel converters. The controller includes a control unit, a synchronization signal conversion unit, and a synchronization signal transmission unit. The control unit sends a first synchronization signal to the synchronization signal conversion unit. The synchronization signal conversion unit converts the first synchronization signal into multiple second synchronization signals and transmits these signals to each converter via the synchronization signal transmission unit. The peak voltage of the second synchronization signals is higher than that of the first synchronization signal. This design solves the problem of sending a first synchronization signal from the control unit to the synchronization signal conversion unit, converting it into multiple second synchronization signals with higher peak voltages, and then transmitting these signals to each converter. This enhances the anti-interference capability and reliability of the synchronization signal, effectively preventing signal loss and distortion due to interference, and ensuring synchronous signal generation between parallel converters. Furthermore, the technical solution uses conventional components, saving costs, facilitating widespread application, and improving the product's market competitiveness. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a multi-machine high-frequency carrier synchronization system and its control method based on differential isolation, which eliminates the need for master-slave allocation of parallel converters. The synchronization signal conversion unit is used to convert the logic level signal sent by the microcontroller unit into an isolated differential signal for transmission and to convert the received differential signal into a logic level signal for transmission to the microcontroller, thereby improving the synchronization signal transmission capability.

[0010] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A multi-machine high-frequency carrier synchronization system based on differential isolation includes multiple converters operating in parallel. Each converter's microcontroller unit has a carrier synchronization transmitting module and a receiving module. Each converter includes a microcontroller unit and two synchronization signal conversion units. One synchronization signal conversion unit converts logic levels to differential levels for transmission, and the other synchronization signal conversion unit converts differential levels to logic levels for reception. The output terminal of the transmitting module and the input terminal of the receiving module are connected to the logic level side of the synchronization signal conversion unit. The differential level side of the synchronization signal conversion unit is connected to the positive and negative lines of the differential bus in parallel, so that all converters can transmit or receive carrier synchronization signals through the differential bus.

[0011] As a further step, the microcontroller unit consists of a synchronization signal receiving module and a synchronization signal transmitting module. The synchronization signal conversion unit is used to convert the logic level signal sent by the microcontroller unit into an isolated differential signal for transmission and to convert the received differential signal into a logic level signal for transmission to the microcontroller unit.

[0012] As a further step, the synchronization signal conversion unit consists of a filter circuit and a signal conversion chip.

[0013] As a further step, another control method for a multi-machine high-frequency carrier synchronization system based on differential isolation includes the following steps: S201: After the microcontroller unit is powered on, it detects whether the synchronization signal receiving module has received the carrier synchronization signal. At the same time, it performs timing judgment and sets a predetermined value. If the microcontroller unit still does not receive the carrier synchronization signal after the time exceeds the first time predetermined value or detects a fault in the converter itself, it proceeds to step S203; otherwise, it proceeds to step S202. S202: The microcontroller unit enters the carrier synchronization receiving mode. The level conversion unit receives the differential carrier synchronization signal on the differential bus and converts it into a logic level signal that the microcontroller unit can recognize, and transmits it to the microcontroller unit. After receiving the carrier synchronization signal, the microcontroller unit performs a pre-synchronization operation. S203: The microcontroller unit enters the carrier synchronization transmission mode. When a predetermined event occurs in its own carrier generation module, the microcontroller unit sends a carrier synchronization signal. The level conversion unit receives the logic level carrier synchronization signal, converts it into a differential carrier synchronization signal, and transmits it to the differential bus for transmission.

[0014] As a further step, the first time preset value in step S201 is automatically generated by the microcontroller unit based on its own identification information. Different microcontroller units have different identification information, which is set by hardware DIP switches or software. The microcontroller unit can generate different first time preset values ​​by multiplying its own identification information by a time threshold (range 5~10 seconds).

[0015] As a further step, in step S203, the microcontroller unit enters the carrier synchronization transmission mode. When a predetermined event occurs in the carrier generation module, the microcontroller unit sends a carrier synchronization signal. The predetermined event can be set as a carrier count zero-crossing event (generated when the carrier counter value is zero), a carrier count period value event (generated when the carrier counter value is a period value), or a carrier count comparison event (generated when the carrier counter value is any set value).

[0016] As a further step, when the microcontroller unit enters the carrier synchronization receiving mode in step S202, the pre-synchronization operations received by the microcontroller unit after carrier synchronization include the following steps: S401: After the microcontroller unit receives the carrier synchronization signal, it triggers a capture interrupt, and records the phase value θr of the microcontroller carrier generation module at this time in the capture interrupt; S402: The microcontroller unit obtains the initial phase value θ0 of the carrier generation module, and obtains the phase adjustment value △θ at this time according to the phase adjustment value △θ between the initial phase value θ0 and the phase value θr, and calculates the phase adjustment value △θ according to the following formula: △θ = θ0 - θr or △θ = θ0 + θr; when △θ = θ0 - θr, the microcontroller unit obtains the counting direction of the carrier generation module and it is positive counting at this time; when △θ = θ0 + θr, the microcontroller unit obtains the counting direction of the carrier generation module and it is negative counting at this time; S403: The microcontroller unit obtains the period reference value Tref of the carrier generation module, and calculates the actual period value T of the carrier generation module by adopting a proportional adjustment method according to the period reference value and the phase adjustment error value. The calculation formula is as follows: T = Tref + K * △θ / w (0 < K < 1, w is the clock angular frequency of the carrier module).

[0017] As a further step, when the sending module detects that a predetermined event occurs, it generates a square wave signal by changing the level of the output, thereby generating a carrier synchronization signal. At this time, the sending module is the main module and its phase is the reference phase. The phase adjustment value △θ is always equal to zero, that is, no phase adjustment is required. The microcontroller unit in the receiving mode generates an interrupt by capturing the edge change of the carrier signal to obtain the synchronization phase value θ r .

[0018] Compared with the prior art, the present invention has at least the following beneficial effects: (1) The present invention does not need to perform master-slave distribution on the parallel converters. The synchronization signal conversion unit is used to convert the logic level signal sent by the microcontroller unit into an isolated differential signal for transmission and convert the received differential signal into a logic level signal and send it to the microcontroller, thereby improving the synchronization signal transmission ability; (2) Each converter's microcontroller unit has a carrier synchronization transmission module and a receiving module. The converter includes a microcontroller unit and two synchronization signal conversion units. The output of the transmission module and the input of the receiving module are connected to the logic level side of the synchronization signal conversion unit. The differential level side of the synchronization signal conversion unit is connected to the positive and negative lines of the differential bus in parallel. This ensures that all converters can send or receive carrier synchronization signals through the differential bus, guaranteeing the synchronous transmission of synchronization signals between converters. This ensures that each converter can generate waves synchronously, avoiding the generation of circulating currents between parallel converters, which can cause power waste, heat generation, interference, and other problems. (3) High-reliability parallel control: The fast response capability of the microcontroller unit can ensure the real-time generation / forwarding of the carrier synchronization signal, reduce the circulating current when multiple machines are connected in parallel, and improve the output power quality of the energy storage system; (4) Flexible adaptation to large capacity scenarios: It adopts a cascaded communication method, which can support the expansion of multiple converters. Without making significant modifications to the existing hardware structure, the total power of the energy storage system can be increased by increasing the number of converters, adapting to energy storage scenarios with different capacity requirements and having good scalability. Attached Figure Description

[0019] Figure 1 This is a system schematic diagram according to one embodiment of the present invention; Figure 2 This is a schematic diagram of the control process in one embodiment of the present invention; Figure 3 This is a schematic diagram of pre-synchronization operation in one embodiment of the present invention; Figure 4 This is a schematic diagram of synchronization signal generation in one embodiment of the present invention. Detailed Implementation

[0020] The following describes in detail, with reference to the accompanying drawings and specific embodiments, a high-efficiency heat sink for an AI computing device and its usage method provided by the present invention. It should also be noted that, to make the embodiments more detailed, the following embodiments are the best and preferred embodiments; those skilled in the art can also use other alternative methods to implement some well-known technologies; and the accompanying drawings are only for more specific description of the embodiments and are not intended to specifically limit the present invention.

[0021] It should be noted that the use of terms such as "an embodiment," "an embodiment," "an exemplary embodiment," and "some embodiments" in the specification indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not) should be within the knowledge of those skilled in the art.

[0022] Generally, terms can be understood at least partly from their use in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Additionally, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather, alternatively, depending at least partly on the context, to allow for the presence of other factors that are not necessarily explicitly described.

[0023] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on” something, but also includes something with an intermediary feature or layer, and that “above” or “above” means not only “on” something, but also includes something “above” or “above” without an intermediary feature or layer.

[0024] Furthermore, spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for convenience to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the accompanying drawings. Spatially related terms are intended to cover different orientations in the use or operation of the device other than those depicted in the accompanying drawings. The device may be oriented in other ways, and the spatially related descriptive terms used herein can be interpreted similarly.

[0025] like Figure 1As shown, a multi-machine high-frequency carrier synchronization system based on differential isolation includes multiple converters operating in parallel. Each converter's microcontroller unit has a carrier synchronization transmitting module and a receiving module. Each converter includes a microcontroller unit and two synchronization signal conversion units. One synchronization signal conversion unit converts logic levels to differential levels for transmission, and the other synchronization signal conversion unit converts differential levels to logic levels for reception. The output terminal of the transmitting module and the input terminal of the receiving module are connected to the logic level side of the synchronization signal conversion unit. The differential level side of the synchronization signal conversion unit is connected to the positive and negative lines of the differential bus in parallel, so that all converters can transmit or receive carrier synchronization signals through the differential bus.

[0026] Preferably, the microcontroller unit consists of a synchronization signal receiving module and a synchronization signal transmitting module. The synchronization signal conversion unit is used to convert the logic level signal sent by the microcontroller unit into an isolated differential signal for transmission and to convert the received differential signal into a logic level signal for transmission to the microcontroller unit.

[0027] Preferably, the synchronization signal conversion unit consists of a filter circuit and a signal conversion chip.

[0028] like Figure 2 As shown, another control method for a multi-machine high-frequency carrier synchronization system based on differential isolation includes the following steps: S201: After the microcontroller unit is powered on, it detects whether the synchronization signal receiving module has received the carrier synchronization signal. At the same time, it performs timing judgment and sets a predetermined value. If the microcontroller unit still does not receive the carrier synchronization signal after the time exceeds the first time predetermined value or detects a fault in the converter itself, it proceeds to step S203; otherwise, it proceeds to step S202. S202: The microcontroller unit enters the carrier synchronization receiving mode. The level conversion unit receives the differential carrier synchronization signal on the differential bus and converts it into a logic level signal that the microcontroller unit can recognize, and transmits it to the microcontroller unit. After receiving the carrier synchronization signal, the microcontroller unit performs a pre-synchronization operation. S203: The microcontroller unit enters the carrier synchronization transmission mode. When a predetermined event occurs in its own carrier generation module, the microcontroller unit sends a carrier synchronization signal. The level conversion unit receives the logic level carrier synchronization signal, converts it into a differential carrier synchronization signal, and transmits it to the differential bus for transmission.

[0029] Preferably, the first time preset value in step S201 is automatically generated by the microcontroller unit according to its own identification information. Different microcontroller units have different identification information, and the identification information is set through hardware dials or software. The microcontroller unit multiplies its own identification information by a time threshold (range: 5 to 10 seconds) to generate different first time preset values.

[0030] Preferably, when the microcontroller unit in step S203 enters the carrier synchronization transmission mode, the microcontroller unit sends a carrier synchronization signal when a preset event occurs in the carrier generation module. This preset event can be set as a carrier count zero-crossing event (generated when the carrier counter value is zero), a carrier count period value event (generated when the carrier counter value is the period value), or a carrier count comparison event (generated when the carrier counter value is any set value) according to requirements.

[0031] As Figure 3 shown, preferably, when the microcontroller unit in step S202 enters the carrier synchronization reception mode, the pre-synchronization operation after the microcontroller unit receives carrier synchronization includes the following steps: S401: After the microcontroller unit receives the carrier synchronization signal, it triggers a capture interrupt, and records the phase value θr of the microcontroller carrier generation module at this time in the capture interrupt; S402: The microcontroller unit obtains the initial phase value θ0 of the carrier generation module, and obtains the phase adjustment value △θ at this time according to the phase adjustment value △θ between the initial phase value θ0 and the phase value θr, and calculates the phase adjustment value △θ using the following formula: △θ = θ0 - θr or △θ = θ0 + θr; when △θ = θ0 - θr, the microcontroller unit obtains the counting direction of the carrier generation module and it is positive counting at this time; when △θ = θ0 + θr, the microcontroller unit obtains the counting direction of the carrier generation module and it is negative counting at this time; S203: The microcontroller unit obtains the period reference value Tref of the carrier generation module, and calculates the actual period value T of the carrier generation module by adopting a proportional adjustment method according to the period reference value and the phase adjustment error value. The calculation formula is as follows: T = Tref + K * △θ / w (0 < K < 1, w is the clock angular frequency of the carrier module).

[0032] As Figure 4 shown, preferably, when the sending module detects that a preset event occurs, it generates a square wave signal by changing the level of the output, thereby generating a carrier synchronization signal. At this time, the sending module is the main module and its phase is the reference phase. The phase adjustment value △θ is always equal to zero, that is, no phase adjustment is required. The microcontroller unit in the reception mode generates an interrupt by capturing the edge change of the carrier signal to obtain the synchronization phase value θ r .

[0033] This invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of this invention. To provide the public with a thorough understanding of this invention, specific details are described in detail in the following preferred embodiments; however, those skilled in the art will fully understand the invention even without these details. Furthermore, to avoid unnecessary misunderstanding of the essence of this invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0034] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc.

[0035] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A multi-machine high-frequency carrier synchronization system based on differential isolation, characterized in that: This system includes parallel operation control of multiple converters. Each converter's microcontroller unit has a carrier synchronization transmitting module and a receiving module. The converter includes a microcontroller unit and two synchronization signal conversion units. The output of the transmitting module and the input of the receiving module are connected to the logic level side of the synchronization signal conversion unit. The differential level side of the synchronization signal conversion unit is connected to the positive and negative lines of the differential bus in parallel, so that all converters can transmit or receive carrier synchronization signals through the differential bus.

2. The multi-machine high-frequency carrier synchronization system based on differential isolation according to claim 1, characterized in that: The microcontroller unit consists of a synchronization signal receiving module and a synchronization signal transmitting module. The synchronization signal conversion unit is used to convert the logic level signal sent by the microcontroller unit into an isolated differential signal for transmission and to convert the received differential signal into a logic level signal for transmission to the microcontroller unit.

3. The multi-machine high-frequency carrier synchronization system based on differential isolation according to claim 2, characterized in that: The synchronization signal conversion unit consists of a filter circuit and a signal conversion chip.

4. The control method for a multi-machine high-frequency carrier synchronization system based on differential isolation according to any one of claims 1-3, characterized in that, Includes the following steps: S201: After the microcontroller unit is powered on, it detects whether the synchronization signal receiving module has received the carrier synchronization signal. At the same time, it performs timing judgment and sets a predetermined value. If the microcontroller unit still does not receive the carrier synchronization signal after the time exceeds the first time predetermined value or detects a fault in the converter itself, it proceeds to step S203; otherwise, it proceeds to step S202. S202: The microcontroller unit enters the carrier synchronization receiving mode. The level conversion unit receives the differential carrier synchronization signal on the differential bus and converts it into a logic level signal that the microcontroller unit can recognize, and transmits it to the microcontroller unit. After receiving the carrier synchronization signal, the microcontroller unit performs a pre-synchronization operation. S203: The microcontroller unit enters the carrier synchronization transmission mode. When a predetermined event occurs in its own carrier generation module, the microcontroller unit sends a carrier synchronization signal. The level conversion unit receives the logic level carrier synchronization signal, converts it into a differential carrier synchronization signal, and transmits it to the differential bus for transmission.

5. The control method for a multi-machine high-frequency carrier synchronization system based on differential isolation according to claim 4, characterized in that, The first time preset value in step S201 is automatically generated by the microcontroller unit based on its own identification information. Different microcontroller units have different identification information, which is set by hardware DIP switches or software. The microcontroller unit can generate different first time preset values ​​by multiplying its own identification information by a time threshold.

6. The control method for a multi-machine high-frequency carrier synchronization system based on differential isolation according to claim 4, characterized in that, In step S203, the microcontroller unit enters the carrier synchronization transmission mode. When a predetermined event occurs in the carrier generation module, the microcontroller unit sends a carrier synchronization signal. The predetermined event can be set as a carrier count zero-crossing event, a carrier count period value event, or a carrier count comparison event as required.

7. The control method for a multi-machine high-frequency carrier synchronization system based on differential isolation according to claim 4, characterized in that, In step S202, the microcontroller unit enters carrier synchronization reception mode. The pre-synchronization operation after the microcontroller unit receives carrier synchronization includes the following steps: S401: After receiving the carrier synchronization signal, the microcontroller unit triggers a capture interrupt and records the phase value θr of the microcontroller carrier generation module at this time in the capture interrupt; S402: The microcontroller unit obtains the initial phase value θ0 of the carrier generation module, and obtains the phase adjustment value Δθ at this time according to the phase adjustment value Δθ between the initial phase value θ0 and the phase value θr, and calculates the phase adjustment value Δθ at this time according to the following formula: Δθ = θ0 - θr or Δθ = θ0 + θr; when Δθ = θ0 - θr, the microcontroller unit obtains the counting direction of the carrier generation module and the counting direction is positive counting at this time; when Δθ = θ0 + θr, the microcontroller unit obtains the counting direction of the carrier generation module and the counting direction is negative counting at this time; S403: The microcontroller unit obtains the period reference value Tref of the carrier generation module, and calculates the actual period value T of the carrier generation module by adopting a proportional adjustment method according to the period reference value and the phase adjustment error value. The calculation formula is as follows: T = Tref + K * Δθ / w (0 < K < 1, w is the clock angular frequency of the carrier module).

8. The control method for a multi-machine high-frequency carrier synchronization system based on differential isolation according to claim 1, characterized in that, When a predetermined event is detected, the transmitting module generates a square wave signal by changing the output level, thereby producing a carrier synchronization signal. In this mode, the transmitting module is the master module, and its phase is the reference phase; the phase adjustment value Δθ is always equal to zero, meaning no phase adjustment is needed. Meanwhile, the microcontroller unit in receiving mode obtains the synchronization phase value θ by capturing edge changes of the carrier signal and generating an interrupt. r .

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