Nonvolatile memory device and memory system including same

Abstract

The invention provides a nonvolatile memory device and a memory system including the same. The nonvolatile memory device may include a peripheral circuit structure and a cell array structure. The cell array structure may include a common source line layer, a bit line, a bit line routing insulating layer, a cell stack provided between the common source line layer and the bit line and including a plurality of gate electrodes and a plurality of interlayer insulating layers, and a plurality of channel structures extending through the cell stack in the bit line routing insulating layer. Each of the plurality of channel structures includes a channel layer electrically connected to the common source line layer, a bit line pad electrically connecting the channel layer to the bit line and adjacent to an end of the channel layer facing the bit line, and a gate insulating layer covering the channel layer and the bit line pad.

Description

Technical Field

[0001] The present invention relates to non-volatile storage devices, methods of manufacturing non-volatile storage devices, and / or storage systems including non-volatile storage devices, and more specifically, to three-dimensional non-volatile storage devices and / or storage systems including three-dimensional non-volatile storage devices. Background Technology

[0002] Consumers demand non-volatile storage devices with higher performance, smaller size, and / or lower price. Therefore, to achieve more integrated non-volatile storage devices, three-dimensional non-volatile storage devices have been proposed, in which multiple storage cells are arranged vertically. Summary of the Invention

[0003] The present invention provides a non-volatile storage device with improved operational reliability and / or a storage system including the non-volatile storage device.

[0004] According to an exemplary embodiment of the present invention, a non-volatile memory device includes: a peripheral circuit structure including a peripheral circuit comprising a plurality of peripheral circuit transistors; and a cell array structure electrically connected to the peripheral circuit structure, the cell array structure including a common source line layer, a bit line, a bit line wiring insulating layer surrounding the bit line, a cell stack in a vertical direction between the common source line layer and the bit line, and a plurality of channel structures extending through the cell stack into the bit line wiring insulating layer, the cell stack including a plurality of gate electrodes and a plurality of interlayer insulating layers alternating in a vertical direction, each of the plurality of channel structures including a channel layer, a bit line pad, and a gate insulating layer, the channel layer being electrically connected to the common source line layer, the bit line pad electrically connecting the channel layer to the bit line and adjacent to one end of the channel layer facing the bit line, the gate insulating layer covering the channel layer and the bit line pad, the gate insulating layer including an insulating protrusion at the boundary between the bit line wiring insulating layer and the cell stack, the insulating protrusion protruding further in a horizontal direction than the portion of the gate insulating layer penetrating the cell stack.

[0005] According to an exemplary embodiment of the present invention, a non-volatile memory device includes: a peripheral circuit structure including a peripheral circuit comprising a plurality of peripheral circuit transistors; a first cell array structure electrically connected to the peripheral circuit structure, the first cell array structure including a first bit line, a first bit line wiring insulating layer surrounding the first bit line, a first common source line layer, a first cell stack in a vertical direction between the first bit line and the first common source line layer, and a plurality of first channel structures extending through the first cell stack into the first bit line wiring insulating layer, the first cell stack including intersecting in a vertical direction. The system comprises a plurality of first gate electrodes and a plurality of first interlayer insulating layers; and a second cell array structure electrically connected to the first cell array structure. The second cell array structure includes a second common source line layer, a second bit line, a second bit line wiring insulating layer surrounding the second bit line, a second cell stack in the vertical direction between the second common source line layer and the second bit line, and a plurality of second channel structures extending through the second cell stack into the second bit line wiring insulating layer. The second cell stack includes a plurality of second gate electrodes and a plurality of second interlayer insulating layers alternating in the vertical direction, and a first common source line layer and a second common source layer. The line layer is located between the first cell stack and the second cell stack. Each of the plurality of first channel structures includes a first channel layer, a first bit line pad, and a first gate insulating layer. The first channel layer is electrically connected to a first common source line layer. The first bit line pad is electrically connected to the first channel layer and a first bit line. The first bit line pad is adjacent to the end of the first channel layer facing the first bit line. The first gate insulating layer covers the first channel layer and the first bit line pad. Each of the plurality of second channel structures includes a second channel layer, a second bit line pad, and a second gate insulating layer. The second channel layer is electrically connected to a second common source line layer. The second bit line pad is electrically connected to the second channel layer and a second bit line. The second bit line pad is adjacent to the end of the second channel layer facing the second bit line. The second gate insulating layer covers the second channel layer and the second bit line pad. The first gate insulating layer includes a first insulating protrusion at the boundary between the first bit line wiring insulating layer and the first cell stack. The first insulating protrusion protrudes further in the horizontal direction than the portion of the first gate insulating layer that penetrates the first cell stack. The second gate insulating layer includes a second insulating protrusion at the boundary between the second bit line wiring insulating layer and the second cell stack. The second insulating protrusion protrudes further in the horizontal direction than the portion of the second gate insulating layer that penetrates the second cell stack.

[0006] According to an exemplary embodiment of the present invention, a memory system includes a non-volatile memory device and a memory controller. The non-volatile memory device includes: a peripheral circuit structure including peripheral circuitry including a plurality of peripheral circuitry transistors; a first cell array structure on the peripheral circuit structure; a second cell array structure on the first cell array structure; and input / output pads disposed on the second cell array structure. Each of the first and second cell array structures includes a common source line layer, a bit line, a bit line wiring insulation layer surrounding the bit line, a cell stack in a vertical direction between the common source line layer and the bit line, and a plurality of channel structures extending through the cell stack into the bit line wiring insulation layer. The cell stack includes a plurality of gate electrodes and a plurality of interlayer insulating layers alternating in a vertical direction. The memory controller is electrically connected to the non-volatile memory device via the input / output pads. The device is configured to control a non-volatile memory device, wherein a common source line layer of a first cell array structure and a common source line layer of a second cell array structure are disposed between the cell stacks of the first cell array structure and the cell stacks of the second cell array structure. Each of the plurality of channel structures included in each of the first cell array structure and the second cell array structure includes a channel layer, a bit line pad, and a gate insulating layer. The channel layer is electrically connected to the common source line layer. The bit line pad electrically connects the channel layer to a bit line. The bit line pad is adjacent to one end of the channel layer facing the bit line. The gate insulating layer covers the channel layer and the bit line pad. The gate insulating layer included in each of the first cell array structure and the second cell array structure includes an insulating protrusion at the boundary between the bit line wiring insulating layer and the cell stack. The insulating protrusion protrudes further in the horizontal direction than the portion of the gate insulating layer that penetrates the cell stack. Attached Figure Description

[0007] From the following detailed description taken in conjunction with the accompanying drawings, exemplary embodiments of the present invention will be more clearly understood, in which:

[0008] Figure 1 This is a block diagram of a non-volatile storage device according to an example embodiment;

[0009] Figure 2 This is a schematic perspective view of a non-volatile storage device according to an example embodiment;

[0010] Figure 3 This is an equivalent circuit diagram of a memory cell array of a non-volatile memory device according to an example embodiment;

[0011] Figures 4A to 4C This is a cross-sectional view of a non-volatile storage device according to an example embodiment;

[0012] Figures 5A to 5PThis is a schematic diagram illustrating a method for manufacturing a non-volatile storage device according to an example embodiment;

[0013] Figures 6A to 6N This is a cross-sectional view illustrating a method of manufacturing a non-volatile storage device according to an example embodiment;

[0014] Figure 7A and Figure 7B This is a cross-sectional view of a non-volatile storage device according to an example embodiment;

[0015] Figure 8 This is a cross-sectional view of a non-volatile storage device according to an example embodiment;

[0016] Figure 9A and Figure 9B This is a cross-sectional view of a non-volatile storage device according to an example embodiment;

[0017] Figures 10A to 10C This is a cross-sectional view of a method for manufacturing a non-volatile storage device according to an example embodiment;

[0018] Figure 11 This is a cross-sectional view of a non-volatile storage device according to an embodiment;

[0019] Figure 12A and Figure 12B This is a cross-sectional view of a non-volatile storage device according to an example embodiment;

[0020] Figures 13A to 13C This is a cross-sectional view of a method for manufacturing a non-volatile storage device according to an example embodiment;

[0021] Figure 14 This is a cross-sectional view of a non-volatile storage device according to an example embodiment;

[0022] Figure 15A and Figure 15B This is a cross-sectional view of a non-volatile storage device according to an example embodiment;

[0023] Figure 16A and Figure 16B This is a cross-sectional view illustrating a method of manufacturing a non-volatile storage device according to an example embodiment;

[0024] Figure 17 This is a cross-sectional view of a non-volatile storage device according to an example embodiment;

[0025] Figure 18A and Figure 18B This is a cross-sectional view of a non-volatile storage device according to an example embodiment;

[0026] Figures 19A to 19CThis is a cross-sectional view of a method for manufacturing a non-volatile storage device according to an example embodiment;

[0027] Figure 20 This is a cross-sectional view of a non-volatile storage device according to an example embodiment;

[0028] Figure 21A and Figure 21B This is a cross-sectional view of a non-volatile storage device according to an example embodiment;

[0029] Figures 22A to 22C This is a cross-sectional view of a method for manufacturing a non-volatile storage device according to an example embodiment;

[0030] Figure 23 This is a cross-sectional view of a non-volatile storage device according to an example embodiment;

[0031] Figure 24 This is a schematic diagram of a storage system including a non-volatile storage device according to an example embodiment;

[0032] Figure 25 This is a schematic perspective view of a storage system including a non-volatile storage device according to an example embodiment; and

[0033] Figure 26 This is a schematic cross-sectional view of a semiconductor package according to an example embodiment. Detailed Implementation

[0034] Although the terms “identical,” “equal,” or “same” are used in the description of the example implementations, it should be understood that some imprecision may exist. Therefore, when an element is referred to as being identical to another element, it should be understood that an element or value is identical to another element within a desired range of manufacturing or operational tolerances (e.g., ±10%).

[0035] When the terms “about,” “substantially,” or “approximately” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value includes manufacturing or operational tolerances (e.g., ±10%) near the stated numerical value. Furthermore, when the terms “about,” “substantially,” or “approximately” are used in conjunction with geometry, it is intended that no precision of the geometry is required, but the shape is within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified to “about” or “substantially,” it will be understood that such numerical values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near the stated numerical value or shape.

[0036] As used here, expressions such as "one of," "any one of," and "at least one of" modify the entire column of elements when following a column of elements, rather than individual elements within that column. Therefore, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0037] Figure 1 This is a block diagram of a non-volatile storage device according to an example embodiment.

[0038] Reference Figure 1 The non-volatile storage device 10 may include a storage cell array 20 and peripheral circuitry 30. The storage cell array 20 includes multiple storage cell blocks BLK1, BLK2, ..., and BLKn. Each of the multiple storage cell blocks BLK1, BLK2, ..., and BLKn may include multiple storage cells. The storage cell blocks BLK1, BLK2, ..., and BLKn can be connected to the peripheral circuitry 30 via bit lines BL, word lines WL, serial select lines SSL, and ground select lines GSL.

[0039] The peripheral circuitry 30 may include a row decoder 32, a page buffer 34, a data input / output circuitry 36, and control logic 38. According to some example embodiments, the peripheral circuitry 30 may also include input / output interfaces, column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, amplifier circuitry, etc.

[0040] The memory cell array 20 can be connected to the page buffer 34 via bit lines BL, and can be connected to the row decoder 32 via word lines WL, string select lines SSL, and ground select lines GSL. In the memory cell array 20, each of the plurality of memory cells included in each of the memory cell blocks BLK1, BLK2, ..., and BLKn can be a flash memory cell. The memory cell array 20 can include a three-dimensional memory cell array. The three-dimensional memory cell array can include a plurality of NAND strings extending in a vertical direction, each of the plurality of NAND strings including a plurality of memory cells respectively connected to a plurality of word lines WL stacked vertically on a substrate.

[0041] The peripheral circuit 30 can receive address ADDR, command CMD and control signal CTRL from a device outside the non-volatile memory device 10, and can send data DATA to and receive data DATA from the device outside the non-volatile memory device 10.

[0042] The row decoder 32 can select at least one of memory cell blocks BLK1, BLK2, ..., and BLKn in response to an external address ADDR, and select the word line WL, serial select line SSL, and ground select line GSL corresponding to the selected memory cell block. The row decoder 32 can transmit the voltage used to perform the memory operation to the word line WL corresponding to the selected memory cell block.

[0043] Page buffer 34 can be connected to memory cell array 20 via bit line BL. Page buffer 34 can operate as a write driver during programming operations, applying a voltage to bit line BL according to the voltage of the data DATA to be stored in memory cell array 20, and can operate as a sense amplifier during read operations, sensing the data DATA stored in memory cell array 20. Page buffer 34 can operate according to the control signal PCTL provided from control logic 38.

[0044] Data input / output circuitry 36 can be connected to page buffer 34 via data line DL. During programming operations, data input / output circuitry 36 can receive data DATA from the memory controller (not shown) and provide the data DATA to be programmed to page buffer 34 based on the column address C_ADDR provided from control logic 38. During read operations, data input / output circuitry 36 can provide the data DATA to be read stored in page buffer 34 to the memory controller based on the column address C_ADDR provided from control logic 38.

[0045] The data input / output circuit 36 ​​can transmit the address or command input to it to the control logic 38 or the line decoder 32. The peripheral circuit 30 may also include electrostatic discharge (ESD) circuitry and pull-up / pull-down drivers.

[0046] Control logic 38 can receive commands CMD and control signals CTRL from the memory controller. Control logic 38 can provide row address R_ADDR to row decoder 32 and column address C_ADDR to data input / output circuitry 36. Control logic 38 can generate various internal control signals used in the non-volatile memory device 10 in response to the control signal CTRL. For example, when performing memory operations such as programming or erasing, control logic 38 can adjust the voltage levels supplied to word line WL and bit line BL.

[0047] Figure 2 This is a schematic perspective view of a non-volatile storage device according to an example embodiment.

[0048] Reference Figure 2The non-volatile memory device 10 includes a cell array structure CS and a peripheral circuit structure PS that overlap each other in the vertical direction (Z direction). The cell array structure CS may include the above-mentioned references. Figure 1 The described memory cell array 20. The peripheral circuit structure PS may include the above-described references. Figure 1 The peripheral circuit 30 is described.

[0049] The cell array structure CS may include a first cell array structure CS1 and a second cell array structure CS2 that overlap each other in the vertical direction. For example, the non-volatile memory device 10 may include a peripheral circuit structure PS, a first cell array structure CS1, and a second cell array structure CS2 stacked sequentially in the vertical direction (Z direction). Each of the first cell array structure CS1 and the second cell array structure CS2 may include the plurality of memory cell blocks BLK1, BLK2, ..., and BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, ..., and BLKn may include a three-dimensionally arranged memory cell. According to some example embodiments, the plurality of memory cell blocks BLK1, BLK2, ..., and BLKn included in the first cell array structure CS1 and the plurality of memory cell blocks BLK1, BLK2, ..., and BLKn included in the second cell array structure CS2 may have a structure that is symmetrical to each other in the vertical direction (Z direction). According to some example embodiments, at least a portion of the first cell array structure CS1 and at least a portion of the second cell array structure CS2 may have a structure that is symmetrical to each other in the vertical direction (Z direction). For example, apart from some components used for electrically connecting the plurality of memory cell blocks BLK1, BLK2, ... and BLKn included in each of the first cell array structure CS1 and the second cell array structure CS2 and some components for the peripheral circuit structure PS, the first cell array structure CS1 and the second cell array structure CS2 may have a structure that is symmetrical to each other in the vertical direction (Z direction).

[0050] Figure 3 This is an equivalent circuit diagram of a memory cell array of a non-volatile memory device according to an example embodiment.

[0051] Reference Figure 3 The memory cell array (MCA) can be configured in a cell array structure CS, which includes a first cell array structure CS1 and a second cell array structure CS2. The memory cell array (MCA) can include the above-mentioned references. Figure 1 At least a portion of the described memory cell array 20. According to some example embodiments, the memory cell array MCA may include references... Figure 1The described storage cell array 20 includes at least a portion of one of the plurality of storage cell blocks BLK1, BLK2, ..., and BLKn. The storage cell array MCA may include a plurality of first storage cell strings MS1 and a plurality of second storage cell strings MS2. The plurality of first storage cell strings MS1 may be configured in a first cell array structure CS1, and the plurality of second storage cell strings MS2 may be configured in a second cell array structure CS2.

[0052] The plurality of first memory cell strings MS1 and the plurality of second memory cell strings MS2 may each extend in the vertical direction (Z direction). The memory cell array MCA may include, in each of the first cell array structure CS1 in which the plurality of first memory cell strings MS1 are configured and the second cell array structure CS2 in which the plurality of second memory cell strings MS2 are configured, a plurality of word lines WL (WL1, WL2, ..., WLn-1 and WLn), a plurality of bit lines BL (BL1, BL2, ... and BLm), at least one string select line SSL, at least one ground select line GSL, and a common source line CSL. Each of the plurality of word lines (WL: WL1, WL2, ..., WLn-1 and WLn) may extend along a first horizontal direction (X direction), and each of the plurality of bit lines (BL: BL1, BL2, ... and BLm) may extend along a second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction). Each of at least one Serial Select Line (SSL) and at least one Ground Select Line (GSL) may extend in the same direction as the plurality of word lines (WL: WL1, WL2, ..., WLn-1 and WLn), for example, along a first horizontal direction (X direction). A string of memory cells (MS) may be formed between the bit lines BL (BL1, BL2, ..., and BLm) and the common source line (CSL). Figure 3 An example is shown in which each of the plurality of first memory cell strings (MS1) and the plurality of second memory cell strings (MS2) includes a string select line (SSL), but the inventive concept is not limited thereto. For example, each of the plurality of first memory cell strings (MS1) and the plurality of second memory cell strings (MS2) may include two or more string select lines (SSL).

[0053] Each of the plurality of first memory cell strings (MS1) and the plurality of second memory cell strings (MS2) may include a string select transistor (SST), a ground select transistor (GST), and a plurality of memory cell transistors (MC1, MC2, ..., MCn-1, MCn). The drain region of the string select transistor SST may be connected to bit lines BL (BL1, BL2, ..., and BLm), and the source region of the ground select transistor GST may be connected to a common source line CSL. The common source line CSL may be a region where the source regions of the plurality of ground select transistors GST are commonly connected.

[0054] The serial select transistor SST can be connected to the serial select line SSL, and the ground select transistor GST can be connected to the ground select line GSL. The memory cell transistors MC1, MC2, ..., MCn-1 and MCn can be connected to the word lines WL (WL1, WL2, ..., WLn-1 and WLn), respectively.

[0055] The plurality of first memory cell strings MS1 and the plurality of second memory cell strings MS2 can be symmetrical to each other in the vertical direction (Z direction). In other words, the transistors included in the plurality of first memory cell strings MS1 and the transistors included in the plurality of second memory cell strings MS2 can be arranged in opposite orders in the vertical direction (Z direction). For example, in the vertical direction (Z direction), the plurality of second memory cell strings MS2 can be arranged in the order of ground selection transistor GST, the plurality of memory cell transistors MC1, MC2, ... MCn-1 and MCn, and string selection transistor SST, and the plurality of first memory cell strings MS1 can be arranged in the order of string selection transistor SST, the plurality of memory cell transistors MCn, MCn-1, ... MC2 and MC1, and ground selection transistor GST.

[0056] Figures 4A to 4C This is a cross-sectional view of a non-volatile storage device according to an example embodiment. Specifically, Figure 4B yes Figure 4A Enlarged cross-sectional view of part of ENB. Figure 4C yes Figure 4A Enlarged cross-sectional view of part of ENC.

[0057] Refer to together Figure 2 and Figures 4A to 4CThe non-volatile memory device 1 includes a substrate region SUB and a peripheral circuit region Peri., a lower peripheral junction region BPLP, an upper peripheral junction region BPLC, a first bit line region BLR1, a first cell stack region CellST1, a first common source region CSL1, a lower cell junction region BPU1, an upper cell junction region BPU2, a second common source region CSL2, a second cell stack region CellST2, a second bit line region BLR2, and an input / output region I / O.

[0058] The substrate region SUB and the peripheral circuit region Peri. can constitute the peripheral circuit structure PS. The first bit line region BLR1, the first cell stack region Cell ST1, and the first common source region CSL1 can constitute the first cell array structure CS1. The second common source region CSL2, the second cell stack region Cell ST2, and the second bit line region BLR2 can constitute the second cell array structure CS2. In the first cell array structure CS1, the first bit line region BLR1 and the first common source region CSL1 are respectively arranged below and above the first cell stack region Cell ST1. However, in the second cell array structure CS2, the second bit line region BLR2 and the second common source region CSL2 can be arranged above and below the second cell stack region Cell ST2, respectively.

[0059] The lower peripheral junction region BPLP, located above the peripheral circuit region Peri., and the upper peripheral junction region BPLC, located below the first line region BLR1, are joined together, thus allowing the peripheral circuit structure PS and the first cell array structure CS1 to be joined together. The lower cell junction region BPU1, located above the first common source region CSL1, and the upper cell junction region BPU2, located below the second common source region CSL2, are joined together, thus allowing the first cell array structure CS1 and the second cell array structure CS2 to be joined together to form the cell array structure CS. In other words, the lower peripheral junction region BPLP and the upper peripheral junction region BPLC are joined together, thus allowing the peripheral circuit structure PS and the cell array structure CS to be joined together. Input / output (I / O) areas electrically connecting the non-volatile memory device 10 and external devices can be arranged on the cell array structure CS.

[0060] The substrate region SUB may include a substrate SBST. The substrate SBST may include semiconductor materials, such as group IV semiconductor materials, group III-V semiconductor materials, group II-VI semiconductor materials, and group II-VI oxide semiconductor materials. Group IV semiconductor materials may include, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Group III-V semiconductor materials may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), or indium gallium arsenide (InGaAs). Group II-VI semiconductor materials may include, for example, zinc telluride (ZnTe) or cadmium sulfide (CdS). The substrate SBST may be a bulk wafer or an epitaxial layer. The substrate SBST may be provided as a bulk wafer or an epitaxial layer. According to some example embodiments, the substrate SBST may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. An active region may be defined in the substrate SBST by a device isolation film, and multiple peripheral circuit transistors P-TRs may be formed on the active region. The source / drain regions constituting the plurality of peripheral circuit transistors P-TR can be formed in a portion of the substrate SBST.

[0061] Peri., the peripheral circuit area, may include components that reference... Figure 1 The peripheral circuit 30 described includes a plurality of peripheral circuit transistors P-TRs. In the peripheral circuit region Peri., a plurality of peripheral circuit gates constituting the plurality of peripheral circuit transistors P-TRs may be arranged.

[0062] The peripheral circuit region (Peri) may include multiple peripheral circuit wiring layers (SPD-P) and multiple peripheral circuit contacts (ITCS-P). The multiple peripheral circuit wiring layers (SPD-P) may be electrically connected to the substrate (SBST) and / or the multiple peripheral circuit transistors (P-TR) via the multiple peripheral circuit contacts (ITCS-P). Each of the multiple peripheral circuit wiring layers (SPD-P) and the multiple peripheral circuit contacts (ITCS-P) may include a conductive material such as copper (Cu), aluminum (Al), tungsten (W), silver (Ag), gold (Au), or combinations thereof.

[0063] A peripheral circuit insulation structure ILD-P, covering the plurality of peripheral circuit transistors P-TRs and surrounding the plurality of peripheral circuit wiring layers SPD-P and the plurality of peripheral circuit contacts ITCS-P, can be formed on a substrate SBST. The peripheral circuit insulation structure ILD-P may include an insulating material, including silicon oxide, silicon nitride, low-k materials, or combinations thereof. Low-k materials are materials having a dielectric constant lower than that of silicon oxide and may include, for example, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorosilicate glass (FSG), organosilicon glass (OSG), spin-coated glass (SOG), spin-coated polymers, or combinations thereof. According to some example embodiments, the peripheral circuit insulation structure ILD-P may include an ultra-low k (ULK) film having an ultra-low dielectric constant K from about 2.2 to about 2.4. The ULK film may include SiOC or SiCOH.

[0064] The first bit line region BLR1 may include a connection routing layer SPD-B, a bit line interconnect structure ITCS-B connected to the connection routing layer SPD-B, a bit line BL connected to the bit line interconnect structure ITCS-B, a bit line contact BLC connected to the bit line BL, a post STD connected to the bit line contact BLC, and a bit line routing insulating layer IMD-B surrounding the connection routing layer SPD-B, the bit line interconnect structure ITCS-B, the bit line BL, the bit line contact BLC, and the post STD. The bit lines BL may be spaced apart from each other in a first horizontal direction (X direction) and may extend in a second horizontal direction (Y direction), but the inventive concept is not limited thereto. Each of the connection routing layer SPD-B, the bit line interconnect structure ITCS-B, the bit line BL, the bit line contact BLC, and the post STD may include a metal, a conductive metal nitride, a metal silicide, conductive polysilicon, or a combination thereof. The bit line routing insulating layer IMD-B may include an insulating material, including silicon oxide, silicon nitride, a low-k material, or a combination thereof.

[0065] The first cell stack region, Cell ST1, may include a plurality of gate electrodes (CDLs) arranged and spaced apart from each other in the vertical direction (Z direction) and an interlayer insulating layer (ILD). The plurality of gate electrodes (CDLs) may include a conductive material. The interlayer insulating layer (ILD) may include an insulating material. The plurality of gate electrodes (CDLs) may be arranged within the cell region. A through-path (THV) penetrating the interlayer insulating layer (ILD) may be formed in a peripheral connection region (PCR) adjacent to the cell region in the first horizontal direction (X direction). The interlayer insulating layer (ILD) may surround the plurality of gate electrodes (CDLs) and the through-path (THV). According to some example embodiments, in the cell region, the plurality of interlayer insulating layer (ILD) may fill the spaces between the plurality of gate electrodes (CDLs). For example, in the cell region, the plurality of gate electrodes (CDLs) and the plurality of interlayer insulating layer (ILD) may be arranged alternately in the vertical direction (Z direction). In the cell region, the plurality of gate electrodes (CDLs) and the plurality of interlayer insulating layer (ILD) arranged alternately in the vertical direction (Z direction) may be referred to as a cell stack, CST. The portion of the interlayer insulating layer (ILD) located within the cell region can be referred to as the cell interlayer insulating layer, while the portion of the interlayer insulating layer (ILD) located within the peripheral connection region (PCR) can be referred to as the peripheral interlayer insulating layer.

[0066] Multiple cell channel structures (CHS) can be arranged in a cell region (CELL). These multiple cell channel structures (CHS) extend in the vertical direction (Z direction) through a cell stack (CST) including multiple gate electrodes (CDL) and multiple interlayer insulating layers (ILD). The multiple cell channel structures (CHS) can extend through the cell stack (CST) into a line wiring insulating layer (IMD-B). In the first cell stack region (Cell ST1), a first memory cell string (CSC) includes multiple memory cells. Figure 3 MS1) can be formed along each of the plurality of cell channel structures CHS. According to some example embodiments, the plurality of gate electrodes CDL can correspond to... Figure 3 The diagram shows at least one string select line SSL, word lines WL (WL1, WL2, ..., WLn-1 and WLn) and at least one ground select line GSL constituting the first memory cell string MS1. For example, the gate electrode CDL located closest to the first common source region CSL1 can be used as the ground select line GSL, the gate electrode CDL located closest to the first bit line region BLR1 can be used as the string select line SSL, and the remaining gate electrodes CDL can be used as word lines WL. Therefore, a first memory cell string MS1 can be provided in which the ground select transistor GST, the string select transistor SST, and the memory cell transistors MC1, MC2, ..., MCn-1 and MCn are connected in series.

[0067] Each of the plurality of cell channel structures CHS may include a gate insulating layer GDI, a channel layer CHL, a buried insulating layer BIL, and a bit line pad BLP. The gate insulating layer GDI and the channel layer CHL may be sequentially disposed on the inner wall of a channel via CHH. The bit line pad BLP may be disposed at one end of the channel layer CHL facing the bit line BL. For example, the bit line pad BLP may be located within the bit line wiring insulating layer IMD-B. The gate insulating layer GDI may conformally cover the inner wall of the channel via CHH that penetrates the cell stack CST, which includes the plurality of gate electrodes CDL and the plurality of interlayer insulating layers ILD. The bit line pad BLP may be positioned on the gate insulating layer GDI at one end of the channel via CHH facing the bit line BL. The channel layer CHL may conformally cover the gate insulating layer GDI and the bit line pad BLP. The gate insulating layer GDI may conformally cover and surround the channel layer CHL and the bit line pad BLP. The via (CHH) can extend into the bitline wiring insulation layer (IMD-B) up to the post (STD). The cell channel structure (CHS) can be connected to the post (STD). The bitline pad (BLP) can be inserted between the channel layer (CHL) and the post (STD) and electrically connect the channel layer (CHL) and the post (STD). According to some example embodiments, the bitline pad (BLP) and the post (STD) can be aligned in the vertical direction (Z-direction). For example, the bitline pad (BLP) can contact the bottom surface of the post (STD) but may not contact the side surfaces of the post (STD). According to some example embodiments, the bitline pad (BLP) can contact the entire bottom surface of the post (STD).

[0068] According to some example embodiments, the bit line pad BLP may comprise conductive polysilicon. For example, the bit line pad BLP may comprise n+ polysilicon heavily doped with n-type impurities to provide conductivity. The bit line BL may be electrically connected to the channel layer CHL via the bit line contact BLC, the pillar STD, and the bit line pad BLP. A buried insulating layer BIL may be disposed on the channel layer CHL to fill the remaining space of the channel via CHH. The buried insulating layer BIL may fill the space defined by the channel layer CHL. According to some example embodiments, the buried insulating layer BIL may be omitted, and the channel layer CHL may be formed in a pillar shape to fill the remaining portion of the channel via CHH.

[0069] The gate insulating layer (GDI) can have a structure comprising a tunneling dielectric film GDIA, a charge storage film GDIB, and a barrier dielectric film GDIC sequentially disposed on the outer wall of the channel layer CHL. The relative thicknesses of the tunneling dielectric film GDIA, the charge storage film GDIB, and the barrier dielectric film GDIC forming the gate insulating layer GDI are not limited to... Figure 4B The thickness shown can be varied in various ways.

[0070] The tunneling dielectric film GDIA can include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage film GDIB is the region in which electrons pass through the tunneling dielectric film GDIA from the channel layer CHL, and can include silicon nitride, boron nitride, silicon boron nitride, or doped polycrystalline silicon. The barrier dielectric film GDIC can include silicon oxide, silicon nitride, or a metal oxide having a higher dielectric constant than silicon oxide. The metal oxide can include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or combinations thereof.

[0071] The channel orifice CHH can have a corresponding Figures 6C to 6N The diagram shows the extended space ESP of the base opening BOP. The horizontal width of the extended space ESP can be greater than the horizontal width of other portions of the channel via CHH. In other words, the extended space ESP can be a space that extends horizontally from another portion of the channel via CHH. The extended space ESP of the channel via CHH can be located at the boundary between the cell stack CST and the bit line routing insulating layer IMD-B. For example, the extended space ESP of the channel via CHH can be positioned across the cell stack CST and the bit line routing insulating layer IMD-B. The extended space ESP of the channel via CHH can be separated from the plurality of gate electrodes CDL. For example, a portion of the interlayer insulating layer ILD can be disposed between the gate electrode CDL of the nearest bit line BL among the plurality of gate electrodes CDL and the extended space ESP of the channel via CHH. Corresponding to the extended space ESP of the channel via CHH, the gate insulating layer GDI, the channel layer CHL, and the buried insulating layer BIL can each have horizontally protruding insulating protrusions CDIP, channel protrusions CHLP, and buried protrusions BILP, respectively. The channel protrusion CHLP may cover the buried protrusion BILP, and the insulating protrusion CDIP may cover the channel protrusion CHLP. The gate insulating layer GDI may have an insulating extension CDIB extending from the insulating protrusion CDIP toward the bit line BL into the bit line wiring insulating layer IMD-B. The insulating extension CDIB may surround the side of the bit line pad BLP. The pillar STD may be connected to the bit line pad BLP. The insulating extension CDIB may cover the portion of the side surface of the pillar STD adjacent to the bit line pad BLP.

[0072] In the portion of the through-cell stack CST of the gate insulating layer GDI, the channel layer CHL, and the buried insulating layer BIL, the portion excluding the insulating protrusion CDIP, the channel protrusion CHLP, and the buried protrusion BILP can be referred to as the main portion. For example, the gate insulating layer GDI may include the main portion of the gate insulating layer GDI, the insulating protrusion CDIP, and the insulating extension CDIB; the channel layer CHL may include the main portion of the channel layer CHL and the channel protrusion CHLP; and the buried insulating layer BIL may include the main portion of the buried insulating layer BIL and the buried protrusion BILP.

[0073] A through-path THV may include a through-path protrusion THB and a through-path extension THE. The space filled with the through-path protrusion THB may be formed in the same manner as the extended space ESP of the via CHH. The through-path extension THE extends from the through-path protrusion THB toward the post STD and may extend together with or along the post STD. The through-path protrusion THB may be positioned at the same or substantially similar vertical height as each of the insulating protrusion CDIP, the channel protrusion CHLP, and the buried protrusion BILP, and the through-path extension THE may be positioned at the same or substantially similar vertical height as the insulating extension CDIB. The through-path protrusion THB may be positioned across the interlayer insulation layer ILD and the bitline wiring insulation layer IMD-B, and the through-path extension THE may extend from the through-path protrusion THB toward the bitline BL into the bitline wiring insulation layer IMD-B. In the portion of the through-path THV that penetrates the interlayer insulation layer ILD, the portion other than the through-path protrusion THB may be referred to as the main body portion. A through-path THV may include the main body portion of the through-path THV, the through-path protrusion THB, and the through-path extension THE.

[0074] The first common source region CSL1 includes a common source line layer CSL and a source wiring insulating layer IMD-C surrounding the common source line layer CSL. The common source line layer CSL may be connected to the channel layer CHL of a plurality of channel structures CHS. The common source line layer CSL may include a semiconductor material, such as a group IV semiconductor material, a group III-V semiconductor material, and a group II-VI semiconductor material. For example, the common source line layer CSL may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or combinations thereof. In addition, the common source line layer CSL may include a semiconductor doped with n-type impurities. Furthermore, the common source line layer CSL may have a crystal structure including at least one selected from single crystal, amorphous, and polycrystalline. According to some example embodiments, the common source line layer CSL may include a carbon-free semiconductor material. For example, the common source line layer CSL may include polycrystalline silicon. According to some example embodiments, the common source line layer CSL may include carbon-free polycrystalline silicon. According to some implementations, the common source line layer (CSL) may include polycrystalline silicon doped with n-type impurities.

[0075] The first common source region CSL1 may include a gate contact plug CMC that penetrates a portion of the source wiring insulating layer IMD-C. The gate contact plug CMC may be connected to each of the plurality of gate electrodes CDL by penetrating a portion of the source wiring insulating layer IMD-C and a portion of the interlayer insulating layer ILD. According to some example embodiments, a protective insulating layer DMC may be formed around the gate contact plug CMC. The protective insulating layer DMC may be disposed between the gate contact plug CMC and a portion of the source wiring insulating layer IMD-C, between the gate contact plug CMC and a portion of the interlayer insulating layer ILD, and between the gate contact plug CMC and the gate electrode CDL among the plurality of gate electrodes that are not connected to the gate contact plug CMC.

[0076] The internal interconnect structure ITCS-I can be connected to the end of the gate contact plug CMC opposite to the plurality of gate electrodes CDL. The internal interconnect structure ITCS-I can consist of or include a wiring layer and / or contacts surrounded by the source wiring insulating layer IMD-C. The internal interconnect structure ITCS-I can electrically connect the gate contact plug CMC and the through-path THV. The through-path THV can extend from the first cell stack region Cell ST1 into the first common source region CSL1. For example, the through-path THV can penetrate a portion of the interlayer insulating layer ILD and the source wiring insulating layer IMD-C.

[0077] An internal contact ITCS-C surrounded by a source wiring insulation layer IMD-C and an internal wiring layer SPD-C connected to the internal contact ITCS-C can be formed on an internal interconnect structure ITCS-I.

[0078] The second common source region CSL2, the second cell stack region Cell ST2, and the second bit line region BLR2 can each have a structure symmetrical about the first common source region CSL1, the first cell stack region Cell ST1, and the first bit line region BLR1, and can each have a configuration that is the same as or substantially similar to the first common source region CSL1, the first cell stack region Cell ST1, and the first bit line region BLR1. Therefore, descriptions identical to those already given above will be omitted. Although Figure 4A The internal interconnect structure ITCS-I, included in the first common source region CSL1, is shown but not included in the second common source region CSL2. However, this is merely an example, and the inventive concept is not limited thereto. For example, the second common source region CSL2 may also include an interconnect structure that interconnects the gate contact plug CMC included in the second common source region CSL2 and the internal wiring layer SPD-C. The gate contact plug CMC included in the second common source region CSL2 can be electrically connected to the internal wiring layer SPD-C located in the second common source region CSL2. Figure 4AThe internal wiring layer SPD-C shown is located at different portions of the internal wiring layer SPD-C (e.g., different portions in the second horizontal direction (Y direction)).

[0079] The lower peripheral bonding area (BPLP) disposed above the peripheral circuitry area (Peri.) may include a lower peripheral bonding contact (BPC-P), a lower peripheral bonding pad (BPD-P), and a lower peripheral insulating layer (BDL-P) surrounding the lower peripheral bonding contact (BPC-P) and the lower peripheral bonding pad (BPD-P). The lower peripheral bonding contact (BPC-P) may electrically connect the peripheral circuitry routing layer (SPD-P) and the lower peripheral bonding pad (BPD-P). Each of the lower peripheral bonding contact (BPC-P) and the lower peripheral bonding pad (BPD-P) may include a conductive material, which may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or combinations thereof. For example, the lower peripheral bonding pad (BPD-P) may include a material containing copper (Cu). For example, the lower peripheral insulating layer (BDL-P) may include silicon oxide or silicon carbon nitride (SiCN). According to some example embodiments, the top surface of the lower peripheral bonding pad (BPD-P) and the top surface of the lower peripheral insulating layer (BDL-P) may be coplanar.

[0080] The upper peripheral bonding area BPLC disposed on the lower peripheral bonding area BPLP may include an upper peripheral bonding contact BPC-B, an upper peripheral bonding pad BPD-B, and an upper peripheral insulating layer BDL-B surrounding the upper peripheral bonding contact BPC-B and the upper peripheral bonding pad BPD-B. The upper peripheral bonding contact BPC-B may electrically connect the connection wiring layer SPD-B of the first bit line area BLR1 and the upper peripheral bonding pad BPD-B. The upper peripheral bonding contact BPC-B, the upper peripheral bonding pad BPD-B, and the upper peripheral insulating layer BDL-B may be substantially similar to the lower peripheral bonding contact BPC-P, the lower peripheral bonding pad BPD-P, and the lower peripheral insulating layer BDL-P, respectively. According to some example embodiments, the bottom surface of the upper peripheral bonding pad BPD-B and the bottom surface of the upper peripheral insulating layer BDL-B may be coplanar.

[0081] The lower peripheral bonding region (BPLP) and the upper peripheral bonding region (BPLC) can be bonded to each other through hybrid bonding. The lower peripheral bonding pad (BPD-P) and the upper peripheral bonding pad (BPD-B) can face each other, expand upon heating to contact each other, and diffuse to bond together through the diffusion of metal atoms, thus forming a bonded bonding pad. The lower peripheral insulating layer (BDL-P) and the upper peripheral insulating layer (BDL-B) can be connected by forming covalent bonds.

[0082] Each of the lower cell bonding region BPU1 disposed above the first common source region CSL1 and the upper cell bonding region BPU2 disposed on the lower cell bonding region BPU1 may include a cell bonding contact BPC-C, a cell bonding pad BPD-C, and a cell insulating layer BDL-C surrounding the cell bonding contact BPC-C and the cell bonding pad BPD-C. The cell bonding contact BPC-C of the lower cell bonding region BPU1 can be electrically connected to the internal wiring layer SPD-C of the first common source region CSL1 and the cell bonding pad BPD-C, and the cell bonding contact BPC-C of the upper cell bonding region BPU2 can be electrically connected to the internal wiring layer SPD-C of the second common source region CSL2 and the cell bonding pad BPD-C.

[0083] The cell bonding contact BPC-C, cell bonding pad BPD-C, and cell insulating layer BDL-C are generally similar to the lower peripheral bonding contact BPC-P, lower peripheral bonding pad BPD-P, and lower peripheral insulating layer BDL-P, or the upper peripheral bonding contact BPC-B, upper peripheral bonding pad BPD-B, and upper peripheral insulating layer BDL-B, therefore descriptions identical to those given above are omitted.

[0084] The input / output (I / O) area includes input / output pads (PADs), input / output contacts (PDCs), and an input / output insulating layer (IOD) surrounding the input / output pads (PADs) and the input / output contacts (PDCs). The input / output contacts (PDCs) can electrically connect the connection routing layer (SPD-B) of the second bit line area (BLR2) and the input / output pads (PADs). The input / output pads (PADs) can be electrically connected to the bit lines (BLs) of the second bit line area (BLR2). Each of the input / output pads (PADs) and the input / output contacts (PDCs) can include a metal, a conductive metal nitride, a metal silicide, conductive polysilicon, or a combination thereof. The input / output insulating layer (IOD) can include an insulating material, including silicon oxide, silicon nitride, a low-k material, or a combination thereof.

[0085] Figures 5A to 5P This is a schematic diagram illustrating a method for manufacturing a non-volatile storage device according to an example embodiment. Figures 5A to 5P Show in a simplified way Figure 4A The diagram shows the substrate area SUB, peripheral circuit area Peri., lower peripheral junction area BPLP, upper peripheral junction area BPLC, first bit line area BLR1, first cell stack area Cell ST1, first common source area CSL1, lower cell junction area BPU1, upper cell junction area BPU2, second common source area CSL2, second cell stack area Cell ST2, second bit line area BLR2, and input / output area I / O.

[0086] Reference Figure 5AA first substrate region BSUB1 is fabricated. The first substrate region BSUB1 may be, but is not limited to, a semiconductor substrate. According to some example embodiments, the first substrate region BSUB1 may be a bulk wafer.

[0087] Reference Figure 5B The first cell stack region, Cell ST1, is formed on the first substrate region, BSUB1. For example, as... Figure 4A The first cell stack region Cell ST1, which includes the plurality of gate electrodes CDL, interlayer insulating layer ILD, and the plurality of cell channel structures CHS, can be formed on the first substrate region BSUB1.

[0088] Reference Figure 5C The first common source pole region CSL1 is formed on the first cell stack region Cell ST1. For example, as... Figure 4A The first common source region CSL1, which includes a common source line layer CSL, a source wiring insulating layer IMD-C, a gate contact plug CMC, an internal interconnect structure ITCS-I, an internal contact ITCS-C, and an internal wiring layer SPD-C, can be formed on the first cell stack region Cell ST1.

[0089] According to some example implementations, during the process of forming the first common source region CSL1, Figure 4A The through-path THV shown can be formed to extend into the first cell stacking region, Cell ST1. For example, Figure 4A The through-path THV shown can be formed as part of the source wiring insulation layer IMD-C and the interlayer insulation layer ILD. According to some other example embodiments, Figure 4A A portion of the through-path THV shown can be formed during the process of forming the first cell stack region Cell ST1, and another portion of the through-path THV can be formed during the process of forming the first common source region CSL1.

[0090] Reference Figure 5D The carrier substrate CWF is attached to the first common source region CSL1. The carrier substrate CWF can be, but is not limited to, a semiconductor substrate. According to some example embodiments, the carrier substrate CWF can be a bulk wafer.

[0091] Refer to together Figure 5E and Figure 5F , Figure 5D The resulting structure is inverted so that the carrier substrate CWF faces down and the first substrate region BSUB1 faces up. Then the first substrate region BSUB1 is removed to expose the first cell stack region Cell ST1 upwards.

[0092] Reference Figure 5GThe first bit line region BLR1 and the upper peripheral bonding region BPLC are sequentially formed on the first cell stack region Cell ST1. For example, the first bit line region BLR1 can be formed on the first cell stack region Cell ST1. The first bit line region BLR1 includes a pillar STD, a bit line contact BLC, a bit line BL, a bit line interconnect structure ITCS-B, a connection routing layer SPD-B, and a bit line routing insulating layer IMD-B surrounding the pillar STD, the bit line contact BLC, the bit line BL, the bit line interconnect structure ITCS-B, and the connection routing layer SPD-B. The upper peripheral bonding region BPLC can be formed on the first bit line region BLR1. The upper peripheral bonding region BPLC includes an upper peripheral bonding contact BPC-B, an upper peripheral bonding pad BPD-B, and an upper peripheral insulating layer BDL-B surrounding the upper peripheral bonding contact BPC-B and the upper peripheral bonding pad BPD-B.

[0093] The first line region BLR1 and the upper peripheral junction region BPLC formed on the first unit stacking region Cell ST1 can be formed such that they are connected to... Figure 4A The first line region BLR1 and the upper outer periphery junction region BPLC are inverted.

[0094] Reference Figure 5H The peripheral circuit region Peri. and the lower peripheral bonding region BPLP are sequentially formed on the substrate region SUB. The substrate region SUB can be... Figure 4A The substrate region SUB is shown. Forms such as those shown can be formed on the substrate region SUB. Figure 4A The peripheral circuit region Peri. shown includes the plurality of peripheral circuit transistors P-TR, the plurality of peripheral circuit contacts ITCS-P, the plurality of peripheral circuit wiring layers SPD-P, and a peripheral circuit insulation structure ILD-P covering the plurality of peripheral circuit transistors P-TR and surrounding the plurality of peripheral circuit contacts ITCS-P and the plurality of peripheral circuit wiring layers SPD-P. As shown in the figure, a peripheral circuit region Peri. can be formed on the peripheral circuit region Peri. Figure 4A The lower peripheral bonding area BPLP shown includes a lower peripheral bonding contact BPC-P, a lower peripheral bonding pad BPD-P, and a lower peripheral insulating layer BDL-P surrounding the lower peripheral bonding contact BPC-P and the lower peripheral bonding pad BPD-P.

[0095] Reference Figure 5I , Figure 5G The resulting structure is inverted and attached to Figure 5H In the resulting structure, the lower peripheral bonding region (BPLP) and the upper peripheral bonding region (BPLC) can face each other, and the carrier substrate CWF can be exposed. The lower peripheral bonding region (BPLP) and the upper peripheral bonding region (BPLC) can be bonded to each other through hybrid bonding.

[0096] Refer to together Figure 5J and Figure 5K After removing the carrier substrate CWF to expose the first common source region CSL1, a lower cell bonding region BPU1 is formed on the first common source region CSL1. The lower cell bonding region BPU1 can be formed on the first common source region CSL1, and the lower cell bonding region BPU1 includes a cell bonding contact BPC-C, a cell bonding pad BPD-C, and a cell insulating layer BDL-C surrounding the cell bonding contact BPC-C and the cell bonding pad BPD-C.

[0097] Reference Figure 5L A second cell stack region, Cell ST2, is formed on the second substrate region BSUB2, and a second common source region, CSL2, is formed on the second cell stack region Cell ST2. For example, a structure such as... can be formed on the second substrate region BSUB2. Figure 4A The diagram shows a second cell stack region, Cell ST2, comprising the plurality of gate electrodes (CDL), interlayer insulating layer (ILD), and the plurality of cell channel structures (CHS), and a second cell stack region, Cell ST2, can be formed on the second cell stack region, Cell ST2, as shown in the diagram. Figure 4A The diagram shows a second common source region CSL2, which includes a common source line layer CSL, a source wiring insulating layer IMD-C, a gate contact plug CMC, an internal interconnect structure ITCS-I, and an internal wiring layer SPD-C.

[0098] and Figure 4A Compared to the second cell stack region Cell ST2 and the second common source region CSL2, the second cell stack region Cell ST2 and the second common source region CSL2 formed on the second substrate region BSUB2 can be formed to be upside down.

[0099] According to some example implementations, during the process of forming the second common source region CSL2, Figure 4A The through-path THV shown can be formed to extend into the second cell stacking region, Cell ST2. For example, Figure 4A The through-path THV shown can be formed as part of the source wiring insulation layer IMD-C and the interlayer insulation layer ILD. According to some other example embodiments, Figure 4A A portion of the through-path THV shown can be formed during the process of forming the second cell stack region Cell ST2, and another portion of the through-path THV can be formed during the process of forming the second common source region CSL2.

[0100] Reference Figure 5MAn upper cell bonding region BPU2 is formed on the second common source region CSL2. The upper cell bonding region BPU2 includes a cell bonding contact BPC-C, a cell bonding pad BPD-C, and a cell insulating layer BDL-C surrounding the cell bonding contact BPC-C and the cell bonding pad BPD-C. Figure 4A Compared to the upper unit junction region BPU2, the upper unit junction region BPU2 formed on the second common source region CSL2 can be formed inverted.

[0101] Reference Figure 5N , Figure 5M The resulting structure is inverted and attached to Figure 5K In the resulting structure, the lower unit bonding region BPU1 and the upper unit bonding region BPU2 can face each other, and the second substrate region BSUB2 can be exposed. The lower unit bonding region BPU1 and the upper unit bonding region BPU2 can be bonded to each other by hybrid bonding.

[0102] Refer to together Figure 5O and Figure 5P The second substrate region BSUB2 is removed to expose the second cell stack region CellST2. Then, a second bit line region BLR2 and input / output (I / O) regions can be formed on the second cell stack region CellST2, thereby forming a non-volatile memory device 10. For example, the second bit line region BLR2 can be formed on the second cell stack region CellST2. This second bit line region BLR2 includes pillars STD, bit line contacts BLC, bit lines BL, bit line interconnect structures ITCS-B, connection routing layers SPD-B, and a bit line routing insulating layer IMD-B surrounding the pillars STD, bit line contacts BLC, bit lines BL, bit line interconnect structures ITCS-B, and connection routing layers SPD-B. Furthermore, an input / output region I / O can be formed on the second bit line region BLR2. This input / output region I / O includes input / output contacts PDC, input / output pads PAD, and an input / output insulating layer IOD surrounding the input / output contacts PDC and input / output pads PAD.

[0103] Figures 6A to 6N This is a cross-sectional view illustrating a method of manufacturing a non-volatile storage device according to an exemplary embodiment. Specifically, Figures 6A to 6N It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB. Figures 6A to 6L Shown as with Figure 4A The ENB portion is reversed.

[0104] Reference Figure 6AA first substrate region BSUB1 is fabricated. According to some example embodiments, the first substrate region BSUB1 may be a bulk wafer.

[0105] Reference Figure 6B An initial insulating layer PILD is formed covering the first substrate region BSUB1. The initial insulating layer PILD may include an insulating material. According to some example embodiments, the initial insulating layer PILD may include materials that are insulating and insulating. Figure 4A The interlayer insulating layer (ILD) shown is made of the same material, but the inventive concept is not limited thereto.

[0106] Reference Figure 6C A portion of the initial insulating layer PILD and the upper part of the first substrate region BSUB1 are removed to form a substrate opening BOP extending from the uppermost part of the initial insulating layer PILD into the interior of the first substrate region BSUB1. The substrate opening BOP can be formed to penetrate the initial insulating layer PILD, extending from the top surface of the first substrate region BSUB1 into the first substrate region BSUB1, or it can not penetrate the first substrate region BSUB1. According to some example embodiments, the substrate opening BOP can be formed to have a substantially equal horizontal width in the vertical direction. The substrate opening BOP can have a horizontal cross-section having a circular or annular shape.

[0107] Reference Figure 6D A primary spacer layer (MSPC) is formed, which covers the surface of the initial insulating layer (PILD) exposed to the inner wall (e.g., boundary) of the substrate opening (BOP) and the surface of the first substrate region (BSUB1). For example, the primary spacer layer (MSPC) may include a nitride.

[0108] Reference Figure 6E A portion of the first substrate region BSUB1 is removed from the bottom surface or bottom of the substrate opening BOP by using an initial insulating layer PILD and a main spacer layer MSPC as an etching mask to form an extended opening EOP communicating with the substrate opening BOP. Due to the main spacer layer MSPC, the horizontal width of the extended opening EOP can be smaller than the horizontal width of the substrate opening BOP.

[0109] Refer to together Figure 6E and Figure 6F After removing the main spacer layer MSPC, an etch stop sacrificial film STB is formed to fill the substrate opening BOP and extend the opening EOP. The etch stop sacrificial film STB may include components relative to the substrate opening BOP and extend the opening EOP. Figure 6G The multiple interlayer insulating layers (ILDs) and multiple sacrificial films (STLs) formed therein, as well as the first substrate region BSUB1, each have etch-selective materials. According to some embodiments, the etch-stop sacrificial film (STB) may include a carbon-containing material.

[0110] Reference Figure 6G The plurality of interlayer insulating layers (ILDs) and the plurality of sacrificial films (STLs) are alternately formed on the first substrate region BSUB1 and the etch stop sacrificial film STB. The plurality of interlayer insulating layers (ILDs) and the plurality of sacrificial films (STLs) may comprise materials with different etch selectivity. According to some exemplary embodiments, each of the plurality of interlayer insulating layers (ILDs) may comprise an oxide, and the plurality of sacrificial films (STLs) may comprise a nitride, but the inventive concept is not limited thereto.

[0111] According to some exemplary embodiments, the lowermost interlayer insulating layer (ILD) among the plurality of interlayer insulating layers (ILDs) can be formed by forming an insulating material layer on the initial insulating layer (PILD) and the etch stop sacrificial film (STB), such that the lowermost interlayer insulating layer (ILD) includes the initial insulating layer (PILD) and the insulating material layer. According to some exemplary embodiments, after removing the initial insulating layer (PILD), the lowermost interlayer insulating layer (ILD) among the plurality of interlayer insulating layers (ILDs) can be formed to cover the first substrate region (BSUB1) and the etch stop sacrificial film (STB).

[0112] Reference Figure 6H A channel via CHH is formed, penetrating the plurality of interlayer insulating layers (ILDs) and the plurality of sacrificial films (STLs). The channel via CHH can be formed by removing a portion of each of the plurality of interlayer insulating layers (ILDs) and a portion of each of the plurality of sacrificial films (STLs) to expose the etch stop sacrificial film (STB). In the process of forming the channel via CHH, the portion of the etch stop sacrificial film STB embedded in the lowest interlayer insulating layer (ILD) among the plurality of interlayer insulating layers (ILDs) can be removed together, but the inventive concept is not limited thereto. For example, in the process of forming the channel via CHH, the etch stop sacrificial film STB can be retained without removal.

[0113] The horizontal width of the channel aperture (CHH) can be less than the horizontal width of the substrate opening (BOP). The horizontal width of the channel aperture (CHH) can be equal to or greater than the horizontal width of the extension opening (EOP).

[0114] Refer to together Figure 6H and Figure 6I The etch stop sacrificial film STB can be removed, allowing the channel hole CHH to extend to the substrate opening BOP and the extended opening EOP. The first substrate region BSUB1 can be exposed on the bottom surface of the channel hole CHH, which includes the substrate opening BOP and the extended opening EOP.

[0115] Reference Figure 6JA gate insulating layer (GDI) and a pad material layer (PBLP) are formed. The GDI covers the inner surface (e.g., inner and bottom surfaces) of the channel via CHH, which includes a base opening (BOP) and an extension opening (EOP). The GDI may be formed to conformally cover the surfaces of the plurality of interlayer insulating layers (ILDs), the plurality of sacrificial films (STLs), and the first substrate region (BSUB1) exposed on the inner surface (e.g., the boundary) of the channel via CHH, which includes the base opening (BOP) and the extension opening (EOP). The PBLP may conformally cover the GDI within the channel via CHH, such that the PBLP fills the extension opening (EOP). The PBLP may be formed to completely fill the extension opening (EOP) but only partially fill the remaining portion of the channel via CHH (e.g., the portion of the channel via CHH excluding the extension opening (EOP)). For example, the pad material layer PBLP can be formed to fill only the portions of the channel vias CHH that penetrate the plurality of interlayer insulating layers (ILDs) and the plurality of sacrificial films (STLs), as well as a portion of the substrate opening (BOP), leaving the remaining portions unfilled. The pad material layer PBLP can comprise conductive polysilicon. For example, the pad material layer PBLP can comprise n+ polysilicon heavily doped with n-type impurities to provide conductivity.

[0116] Refer to together Figure 6J and Figure 6K A portion of the pad material layer PBLP is removed to form the bit line pad BLP. The bit line pad BLP can be formed to fill at least a portion of the extended opening EOP. For example, the bit line pad BLP can be formed to fill at least the lower part of the extended opening EOP, but may not be formed in the portion of the channel via CHH that penetrates the plurality of interlayer insulating layers ILD and the plurality of sacrificial films STL, as well as in the substrate opening BOP.

[0117] After forming the bit line pads BLP, a channel layer CHL and a buried insulating layer BIL are formed, thereby forming a single-cell channel structure CHS including a gate insulating layer GDI, bit line pads BLP, channel layer CHL, and buried insulating layer BIL. The channel layer CHL can be formed within the channel via CHH to conformally cover the gate insulating layer GDI and the bit line pads BLP, and the buried insulating layer BIL can be formed to completely fill the channel via CHH.

[0118] Refer to together Figure 6K and Figure 6L After removing the plurality of sacrificial films STL, the plurality of gate electrodes CDL are formed to fill the spaces from which the plurality of sacrificial films STL have been removed. The plurality of gate electrodes CDL and the plurality of interlayer insulating layers ILD arranged alternately can form a cell stack CST.

[0119] Refer to together Figure 6M and Figure 6N , Figure 6L The resulting structure is inverted so that the first substrate region BSUB1 faces upward. The first substrate region BSUB1 is removed to expose the gate insulating layer GDI.

[0120] After that, as Figure 4B As shown, a pillar STD connected to the bit line pad BLP through the gate insulating layer GDI, a bit line contact BLC connected to the pillar STD, a bit line BL connected to the bit line contact BLC, and a bit line wiring insulating layer IMD-B surrounding the gate insulating layer GDI, the pillar STD, the bit line contact BLC and the bit line BL can be formed.

[0121] Since the pillar STD is formed to penetrate the gate insulating layer GDI and connect to the bit line pad BLP, the portion of the side surface of the pillar STD adjacent to the bit line pad BLP can be covered by the insulating extension CDIB.

[0122] Refer to together Figures 4A to 4C , Figures 5A to 5P and Figures 6A to 6N In a non-volatile memory device 10 according to some example embodiments, a pad material layer PBLP is formed within a substrate opening BOP and an extension opening EOP (the substrate opening BOP has a horizontal width larger than the horizontal width of the portion of the channel via CHH that penetrates the plurality of interlayer insulating layers ILD and the plurality of sacrificial films STL, and the extension opening EOP has a horizontal width smaller than the horizontal width of the substrate opening BOP). A portion of the pad material layer PBLP is then removed to form a bit line pad BLP within the extension opening EOP, which has a relatively narrow horizontal width. Therefore, the dispersion in the shape of the bit line pad BLP included in the plurality of cell channel structures CHS can be reduced, and the connection reliability between the channel layer CHL and the bit line BL can be improved, thereby realizing a non-volatile memory device 10 with improved operational reliability.

[0123] Figure 7A and Figure 7B This is a cross-sectional view of a non-volatile storage device according to some example embodiments. Specifically, Figure 7A It is based on an example implementation method corresponding to Figure 4A Enlarged cross-sectional view of part of ENB. Figure 7B It is according to another example implementation method corresponding to Figure 4A Enlarged cross-sectional view of part of ENB.

[0124] Reference Figure 7AThe extended space ESP of the channel aperture CHH can contact the gate electrode CDL of the nearest bit line BL among the plurality of gate electrodes CDL. A portion of the surface of the gate electrode CDL closest to the bit line BL among the plurality of gate electrodes CDL (e.g., Figure 4A A portion of the bottom surface of the lowest gate electrode CDL among the plurality of gate electrodes CDL in the first cell stack region Cell ST1, or a portion of the top surface of the uppermost gate electrode CDL among the plurality of gate electrodes CDL in the second cell stack region Cell ST2, may contact the gate insulating layer GDI.

[0125] Figure 4A Each of the lowermost gate electrode CDL among the plurality of gate electrodes CDL in the first cell stack region Cell ST1 and the uppermost gate electrode CDL among the plurality of gate electrodes CDL in the second cell stack region Cell ST2 can be a string select line SSL. Therefore, Figure 3 The operating characteristics of the string selection transistor SST shown can be controlled to be different from the operating characteristics of the ground selection transistor GST and / or the operating characteristics of the plurality of memory cell transistors MC1, MC2, ..., MCn-1 and MCn.

[0126] Reference Figure 7B The extended space ESP of the channel via CHH can be separated from the plurality of gate electrodes CDL. The interlayer insulating layer ILD can be disposed between the gate electrode CDL of the nearest bit line BL among the plurality of gate electrodes CDL and the extended space ESP of the channel via CHH. The extended space ESP can be located only within the bit line routing insulating layer IMD-B, and not within the cell stack CST. For example, the extended space ESP can be located within a portion of the contact cell stack CST of the bit line routing insulating layer IMD-B.

[0127] Figure 8 This is a cross-sectional view of a non-volatile storage device according to an example embodiment. Specifically, Figure 8 It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB.

[0128] Reference Figure 8 Bit line pads (BLP) and pillars (STDs) may not be aligned vertically and may be offset. For example, the pillar STD may be offset from the bit line pad (BLP) horizontally. For example, the bit line pad (BLP) may contact a portion of the bottom surface and a portion of the side surface of the pillar STD.

[0129] Therefore, when forming a pillar STD connected to the bit line pad BLP, even if the bit line pad BLP and the pillar STD are misaligned and the lower part of the pillar STD that contacts the bit line pad BLP is reduced, a portion of the side surface of the pillar STD contacts the bit line pad BLP, thus improving the connection reliability between the channel layer CHL and the bit line BL.

[0130] Figure 9A and Figure 9B This is a cross-sectional view of a non-volatile storage device according to an example embodiment. Specifically, Figure 9A It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB. Figure 9B It corresponds to Figure 4A Enlarged cross-sectional view of part of ENC.

[0131] Refer to together Figure 9A and Figure 9B The channel orifice CHH may include corresponding to Figures 10A to 10C The first extended space ESP1 of the base opening BOP shown and the corresponding Figures 10A to 10C The second extension space ESP2 of the extended opening POP is shown. The horizontal width of each of the first extension spaces ESP1 and the second extension space ESP2 can be greater than the horizontal width of the other portions of the via CHH. The first extension space ESP1 of the via CHH can be positioned across the cell stack CST and the bitline routing insulation layer IMD-B, and the second extension space ESP2 can be positioned within the bitline routing insulation layer IMD-B. The first extension space ESP1 and... Figure 4B , Figure 7A or Figure 7B The extended space ESP shown is the same or substantially similar, therefore descriptions identical to those given above are omitted.

[0132] The cell channel structure CHSa may include a gate insulating layer GDIa, a channel layer CHL, a buried insulating layer BIL, and a bit line pad BLPa. The gate insulating layer GDIa may have a structure including a tunneling dielectric film GDIaA, a charge storage film GDIaB, and a barrier dielectric film GDIaC. The gate insulating layer GDIa may include a body portion of the gate insulating layer GDIa, an insulating protrusion CDIP, an insulating extension CDIB, and an insulating extension CDIE. The insulating protrusion CDIP and the insulating extension CDIE may be referred to as the first insulating protrusion and the second insulating protrusion, respectively. The insulating extensions CDIB and CDIE may surround the bit line pad BLPa.

[0133] Bit line pads (BLPa) can have a T-shaped vertical cross-section, which includes filler such as... Figure 10B and Figure 10CThe extended opening of the EOP shown is a portion of the pad extension BLPB and the filler as shown. Figure 10B and Figure 10C The extended opening POP shown is represented by the pad extension BLPE. The pad extension BLPE may protrude further in the horizontal direction than the pad extension BLPB and have a wider horizontal width than the pad extension BLPB. The insulating extension CDIB may surround the pad extension BLPB, and the insulating extension CDIE may surround the pad extension BLPE. The pillar STD may be connected to the pad extension BLPE of the bit line pad BLPa, and the channel layer CHL may be connected to the pad extension BLPB of the bit line pad BLPa.

[0134] The through-path THVa may include a through-path protrusion THBa, a through-path extension THEa, and a through-path extension THSa. The through-path protrusion THBa and the through-path extension THSa may be referred to as the first through-path protrusion and the second through-path protrusion, respectively. The through-path extension THSa may have a horizontal width greater than that of the through-path extension THEa. The through-path extension THSa may be located at the same or substantially similar vertical height as the pad extension BLPE. A post STD may be connected to the through-path extension THSa. Because the post STD is connected to the relatively wide horizontally wide pad extension BLPE of the bit line pad BLPa or the relatively wide horizontally wide through-path THVa of the through-path THVa, the connection reliability between the channel layer CHL and the bit line BL, or between the through-path THVa and the bit line BL, can be improved.

[0135] Figures 10A to 10C This is a cross-sectional view illustrating a method of manufacturing a non-volatile storage device according to an exemplary embodiment. Specifically, Figures 10A to 10C It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB. Figures 10A to 10C Shown as with Figure 4A The ENB portion is reversed.

[0136] Reference Figure 10A In formation Figure 6E Following the extended opening (EOP) shown, a sub-spacer layer (SSPC) is formed, which covers the surface of the main spacer layer (MSPC) exposed within the substrate opening (BOP) and the surface of the first substrate region (BSUB1) exposed to the inner wall of the extended opening (EOP). According to some example embodiments, the sub-spacer layer (SSPC) may comprise a material having the same or similar etch characteristics as the main spacer layer (MSPC).

[0137] Reference Figure 10BA portion of the first substrate region BSUB1 is removed from the bottom surface of the extended opening EOP by isotropic etching using an initial insulating layer PILD, a main spacer layer MSPC, and a sub-spacer layer SSPC as an etching mask, thereby forming an extended opening POP connected to the extended opening EOP. Since the extended opening POP is formed by isotropic etching, its horizontal width can be wider than that of the extended opening EOP. The extended opening POP can have a circular or annular horizontal cross-section.

[0138] Refer to together Figure 10B and Figure 10C After removing the main spacer layer MSPC and the sub-spacer layer SSPC, an etch stop sacrificial film STB is formed to fill the substrate opening BOP, the extended opening EOP, and the extended opening POP. Subsequently, refer to... Figures 6G to 6N Perform subsequent operations.

[0139] Figure 11 This is a cross-sectional view of a non-volatile storage device according to an example embodiment. Specifically, Figure 11 It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB.

[0140] Reference Figure 11 The bit line pad BLPa and the pillar STD may not be aligned in the vertical direction and may be offset. For example, the pillar STD may be offset from the bit line pad BLPa in the horizontal direction. When the pillar STD is formed to connect to the bit line pad BLPa, even if there is misalignment between the bit line pad BLPa and the pillar STD, the connection reliability between the channel layer CHL and the bit line BL can be improved because the bit line pad BLPa includes a pad extension BLPE and the pillar STD is connected to the pad extension BLPE, which has a relatively wide horizontal width.

[0141] Figure 12A and Figure 12B This is a cross-sectional view of a non-volatile storage device according to an example embodiment. Specifically, Figure 12A It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB. Figure 12B It corresponds to Figure 4A Enlarged cross-sectional view of part of ENC.

[0142] Refer to together Figure 12A and Figure 12B The channel orifice CHH may include those corresponding to Figures 13A to 13CThe extended opening POP and the base opening BOP are shown with a first extended space ESP1 and a second extended space ESP2, and can further extend from the second extended space ESP2 toward the bit line BL, corresponding to the deep extended opening DOP. The horizontal width of each of the first extended space ESP1 and the second extended space ESP2 can be greater than the horizontal width of the other part of the channel hole CHH.

[0143] The cell channel structure CHSb may include a gate insulating layer GDIb, a channel layer CHL, a buried insulating layer BIL, and a bit line pad BLPb. The gate insulating layer GDIb may have a structure including a tunneling dielectric film GDIbA, a charge storage film GDIbB, and a barrier dielectric film GDIbC. The gate insulating layer GDIb may include a main body portion of the gate insulating layer GDIb, an insulating protrusion CDIP, an insulating extension CDIB, an insulating extension CDIE, and an insulating deep extension CDID. The insulating protrusion CDIP and the insulating extension CDIE may be referred to as the first insulating protrusion and the second insulating protrusion, respectively, and the insulating extension CDIB and the insulating deep extension CDID may be referred to as the first insulating extension and the second insulating extension, respectively. The insulating extensions CDIB, CDIE, and CDID may surround the bit line pad BLPb.

[0144] Bit line pads (BLPb) can have a cross-shaped vertical cross section, which includes filler such as... Figure 13B and Figure 13C The extended opening of the EOP shown is a portion of the pad extension BLPB, filled as... Figure 13B and Figure 13C The extended opening POP pad extension BLPE shown and the filler as... Figure 13B and Figure 13C The deep extension portion (BLPD) of the pad in the deep extension opening (DOP) is shown. The pad extension portion (BLPB) and the deep extension portion (BLPD) can be referred to as the first pad extension and the second pad extension, respectively. The pad extension portion (BLPE) may protrude further in the horizontal direction than each of the pad extension portions (BLPB and BLPD) and may have a wider horizontal width than each of the pad extension portions (BLPB and BLPD). An insulating extension portion (CDIB) may surround the pad extension portion (BLPB), an insulating extension portion (CDIE) may surround the pad extension portion (BLPE), and an insulating deep extension portion (CDID) may surround the deep extension portion (BLPD). The channel layer (CHL) may be connected to the pad extension portion (BLPB) of the bit line pad (BLPb), and the pillar (STD) may be connected to the deep extension portion (BLPD) of the bit line pad (BLPb) or may be connected to both the pad extension portion (BLPE) and the deep extension portion (BLPD).

[0145] The through-path THVb may include a through-path protrusion THBb, a through-path extension THEb, a through-path extension THSb, and a through-path deep extension THDb. The through-path protrusion THBb and the through-path extension THSb may be referred to as the first through-path protrusion and the second through-path protrusion, respectively. The through-path extension THEb and the through-path deep extension THDb may be referred to as the first through-path extension and the second through-path extension, respectively. The through-path extension THSb and the through-path protrusion THBb may have a horizontal width wider than the horizontal width of the through-path extension THEb and the through-path deep extension THDb. The through-path deep extension THDb may be located at the same or substantially similar vertical height as the pad deep extension BLPD. The post STD may be connected to the through-path deep extension THDb.

[0146] Figures 13A to 13C This is a cross-sectional view illustrating a method of manufacturing a non-volatile storage device according to an exemplary embodiment. Specifically, Figures 13A to 13C It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB. Figures 13A to 13C Shown as with Figure 4A The ENB portion is reversed.

[0147] Reference Figure 13A In formation Figure 10B After the extended opening POP shown, the sub-spacer layer SSPC is removed. For example, the sub-spacer layer SSPC may include a material with different etch characteristics than the main spacer layer MSPC.

[0148] Reference Figure 13B An anisotropic etching process, using an initial insulating layer PILD and a main spacer layer MSPC as an etching mask, removes a portion of the first substrate region BSUB1 from the bottom surface (e.g., the bottom) of the extended opening POP to form a deep extended opening DOP communicating with the extended opening POP. Since the deep extended opening DOP is formed by anisotropic etching, the horizontal width of the deep extended opening DOP can be smaller than the horizontal width of the extended opening POP and is the same as or substantially similar to the horizontal width of the extended opening EOP.

[0149] Reference Figure 13C After removing the main spacer layer MSPC, an etch stop sacrificial film STB is formed, consisting of a substrate-filled opening BOP, an extended opening EOP, an extended opening POP, and a deep extended opening DOP. Subsequently, refer to... Figures 6G to 6N Perform subsequent operations.

[0150] Figure 14 This is a cross-sectional view of a non-volatile storage device according to an example embodiment. Specifically, Figure 14 It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB.

[0151] Reference Figure 14 The bit line pad BLPb and the pillar STD may not be aligned vertically and may be offset. For example, the pillar STD may be offset from the bit line pad BLPb horizontally. For example, the bit line pad BLPb may contact at least a portion of the bottom surface and a portion of the side surface of the pillar STD. For example, the pillar STD may be connected to the pad extension BLPE and the pad depth extension BLPD of the bit line pad BLPb.

[0152] Therefore, when forming the pillar STD connected to the bit line pad BLPb, even if there is a misalignment between the bit line pad BLPb and the pillar STD, the reduction in the portion of the bottom surface of the pillar STD that contacts the bit line pad BLPb is reduced or minimized by the pad extension BLPE, and the portion of the side surface of the pillar STD that contacts the bit line pad BLPb is formed by the pad deep extension BLPD, thus improving the connection reliability between the channel layer CHL and the bit line BL.

[0153] Figure 15A and Figure 15B This is a cross-sectional view of a non-volatile storage device according to an example embodiment. Specifically, Figure 15A It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB. Figure 15B It corresponds to Figure 4A Enlarged cross-sectional view of part of ENC.

[0154] Refer to together Figure 15A and Figure 15B The channel hole CHH can have a corresponding Figure 16A and Figure 16B The extended space of the extended opening BOPc is shown. The maximum horizontal width of the aforementioned extended space of the via CHH can be greater than the horizontal width of other portions of the via CHH, and the minimum horizontal width of the aforementioned extended space of the via CHH can be less than the horizontal width of other portions of the via CHH. The extended space of the via CHH can be set across the cell stack CST and the bit line routing insulation layer IMD-B. The extended space of the via CHH can have a tapered shape with a horizontal width decreasing towards the bit line BL. The portion of the cell channel structure CHSc extending from one end of the cell stack CST towards the bit line BL (e.g., the portion of the cell channel structure CHSc filling the extended space of the via CHH) can have a tapered shape with its horizontal width decreasing towards the bit line BL.

[0155] The cell channel structure CHSc may include a gate insulating layer GDIc, a channel layer CHLc, a buried insulating layer BILc, and a bit line pad BLPc. The gate insulating layer GDIc may have a structure including a tunneling dielectric film GDIcA, a charge storage film GDIcB, and a barrier dielectric film GDIcC. The gate insulating layer GDIc may include a body portion of the gate insulating layer GDIc, an insulating protrusion CDIPc, and an insulating extension CDIDc. The buried insulating layer BILc may include a body portion of the buried insulating layer BILc, a buried protrusion BILPc, and a buried extension BILDc. The channel layer CHLc may include a body portion of the channel layer CHLc, a channel protrusion CHLPc, and a channel extension CHPDc. The channel extension CHPDc may surround the buried extension BILDc, and the insulating extension CDIDc may surround the side surface of the channel extension CHPDc and the side surface of the bit line pad BLPc. The channel extension CHPDc may be connected to the bit line pad BLPc. The buried extension BILDc may have a tapered shape in which its horizontal width decreases from the buried protrusion BILPc toward the bit line BL. The bit line pad BLPc may have a tapered shape in which its horizontal width decreases from the channel layer CHLc toward the bit line BL. The insulating protrusion CDIPc may protrude horizontally from the main body of the gate insulating layer GDIc, the buried protrusion BILPc may protrude horizontally from the main body of the buried insulating layer BILc, and the channel protrusion CHLPc may protrude horizontally from the main body of the channel layer CHLc.

[0156] The through-path THVc may include a through-path protrusion THPc and a through-path extension THDc. The through-path protrusion THPc may protrude horizontally from the main body of the through-path THVc. The through-path extension THDc may have a tapered shape with a horizontal width that decreases toward the bit line BL.

[0157] Figure 16A and Figure 16B This is a cross-sectional view illustrating a method of manufacturing a non-volatile storage device according to an exemplary embodiment. Specifically, Figure 16A and Figure 16B It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB. Figure 16A and Figure 16B Shown as with Figure 4A The ENB portion is reversed.

[0158] Reference Figure 16A In formation Figure 6BAfter the initial insulating layer PILD is shown, the upper part of the first substrate region BSUB1 is removed through the initial insulating layer PILD, thereby forming a substrate opening BOPc extending from the uppermost part of the initial insulating layer PILD into the first substrate region BSUB1. The substrate opening BOPc can be formed to penetrate the initial insulating layer PILD, extending from the top surface of the first substrate region BSUB1 into the first substrate region BSUB1, or it can not penetrate the first substrate region BSUB1. According to some exemplary embodiments, the substrate opening BOPc can be formed to have a tapered shape, which has a horizontal width that decreases from the initial insulating layer PILD toward the interior of the first substrate region BSUB1. For example, the substrate opening BOPc can be formed by supplying a relatively small amount of etchant into the interior of the first substrate region BSUB1.

[0159] Reference Figure 16B An etch-stop sacrificial film (STB) is formed to fill the substrate opening (BOPc). Subsequently, refer to... Figures 6G to 6N Perform subsequent operations.

[0160] Figure 17 This is a cross-sectional view of a non-volatile storage device according to an example embodiment. Specifically, Figure 17 It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB.

[0161] Reference Figure 17 The bit line pad BLPc and the pillar STD may not be aligned vertically and may be offset. For example, the pillar STD may be offset from the bit line pad BLPc horizontally. For example, the bit line pad BLPc may contact at least a portion of the bottom surface and a portion of the side surface of the pillar STD. Therefore, when forming the pillar STD connected to the bit line pad BLPc, even when there is misalignment between the bit line pad BLPc and the pillar STD, the bit line pad BLPc contacts a portion of the side surface and a portion of the bottom surface of the pillar STD, thus improving the connection reliability between the channel layer CHLc and the bit line BL.

[0162] Figure 18A and Figure 18B This is a cross-sectional view of a non-volatile storage device according to an example embodiment. Specifically, Figure 18A It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB. Figure 18B It corresponds to Figure 4A Enlarged cross-sectional view of part of ENC.

[0163] Refer to together Figure 18A and Figure 18B The channel hole CHH can have a corresponding Figure 19A and Figure 19B The extended space of the extended opening BOPc shown and the corresponding Figure 19A and Figure 19B The extended space ESPA of the extended opening POPc shown. The maximum horizontal width of the aforementioned extended space of the via CHH can be greater than the horizontal width of other parts of the via CHH, and the minimum horizontal width of the aforementioned extended space of the via CHH can be less than the horizontal width of other parts of the via CHH. The horizontal width of the extended space ESPA of the via CHH can be greater than the minimum horizontal width of the extended space of the via CHH. The extended space of the via CHH can be set across the cell stack CST and the bit line routing insulation layer IMD-B, and the extended space ESPA can be set within the bit line routing insulation layer IMD-B. The extended space of the via CHH can have a tapered shape, which has a horizontal width that decreases towards the bit line BL.

[0164] The cell channel structure CHSd may include a gate insulating layer GDId, a channel layer CHLd, a buried insulating layer BILd, and a bit line pad BLPd. The gate insulating layer GDId may have a structure including a tunneling dielectric film GDIdA, a charge storage film GDIdB, and a barrier dielectric film GDIdC. The gate insulating layer GDId may include a main body portion of the gate insulating layer GDId, an insulating protrusion CDIPd, an insulating extension CDIDd, and an insulating extension CDIEd. The channel layer CHLd and the buried insulating layer BILd are substantially respectively connected to... Figure 15A The trench layer CHLc and buried insulating layer BILc shown are the same, therefore descriptions identical to those given above are omitted. Insulation extensions CDIDd and CDIEd may surround the bit line pad BLPd.

[0165] Bit line pads (BLPd) can have a T-shaped vertical cross-section, which includes filler such as... Figures 19A to 19C The extended opening BOPc shown is a portion of the pad extension BLPBd and the filler as shown. Figure 19A and Figure 19B The extended opening POPc is shown as a pad extension BLPEd. The pad extension BLPEd may protrude further horizontally than the pad extension BLPBd and have a wider horizontal width than the pad extension BLPBd. An insulating extension CDIDd may surround the pad extension BLPBd, and an insulating extension CDIEd may surround the pad extension BLPEd. A post STD may be connected to the pad extension BLPEd of the bit line pad BLPd.

[0166] The through-path THVd may include a through-path protrusion THPd, a through-path extension THDd, and a through-path extension THSd. The through-path protrusion THPd may protrude horizontally from the main body of the through-path THVd. The through-path extension THDd may have a tapered shape with a horizontal width decreasing towards the bit line BL. The through-path extension THSd may be located at the same or substantially similar vertical height as the pad extension BLPEd. The through-path extension THSd may protrude further horizontally than the through-path extension THDd and have a wider horizontal width than the through-path extension THDd. A post STD may be connected to the through-path extension THSd. Because the post STD is connected to the relatively wide horizontally wide pad extension BLPEd of the bit line pad BLPd or the relatively wide horizontally wide through-path extension THSd of the through-path THVd, the connection reliability between the channel layer CHLd and the bit line BL, or between the through-path THVa and the bit line BL, can be improved.

[0167] Figures 19A to 19C This is a cross-sectional view illustrating a method of manufacturing a non-volatile storage device according to an exemplary embodiment. Specifically, Figures 19A to 19C It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB. Figures 19A to 19C Shown as with Figure 4A The ENB portion is reversed.

[0168] Reference Figure 19A In formation Figure 16A Following the extended opening BOPc shown, a spacer layer SPC is formed covering the surface of the first substrate region BSUB1 exposed to the inner wall (e.g., boundary) of the extended opening BOPc. For example, the spacer layer SPC may include a nitride. Figure 19A The diagram shows a spacer layer SPC covering the surface of the first substrate region BSUB1 exposed to the inner wall (e.g., boundary) of the extended opening BOPc, but not covering the surface of the initial insulating layer PILD; however, the inventive concept is not limited thereto. For example, the spacer layer SPC may be formed to cover both the surface of the first substrate region BSUB1 exposed to the inner wall (e.g., boundary) of the extended opening BOPc and the surface of the initial insulating layer PILD.

[0169] Reference Figure 19BA portion of the first substrate region BSUB1 is removed from the bottom surface of the extended opening BOPc by isotropic etching using an initial insulating layer PILD and a spacer layer SPC as an etching mask, to form an extended opening POPc communicating with the extended opening BOPc. Since the extended opening POPc is formed by isotropic etching, the horizontal width of the extended opening POPc can be wider than the minimum horizontal width of the extended opening BOPc. The extended opening POPc can have a circular or annular horizontal cross-section.

[0170] Refer to together Figure 19B and Figure 19C After removing the spacer layer SPC, an etch stop sacrificial film STB is formed to fill the extended openings BOPc and POPc. Subsequently, refer to... Figures 6G to 6N Perform subsequent operations.

[0171] Figure 20 This is a cross-sectional view of a non-volatile storage device according to an example embodiment. Specifically, Figure 20 It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB.

[0172] Reference Figure 20 The bit line pad BLPd and the pillar STD may not be aligned in the vertical direction and may be offset. For example, the pillar STD may be offset from the bit line pad BLPd in ​​the horizontal direction. When the pillar STD is formed to connect to the bit line pad BLPd, even if there is misalignment between the bit line pad BLPd and the pillar STD, the connection reliability between the channel layer CHLd and the bit line BL can be improved because the bit line pad BLPd includes the pad extension BLPEd and the pillar STD is connected to the pad extension BLPEd, which has a relatively wide horizontal width.

[0173] Figure 21A and Figure 21B This is a cross-sectional view of a non-volatile storage device according to an example embodiment. Specifically, Figure 21A It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB. Figure 21B It corresponds to Figure 4A Enlarged cross-sectional view of part of ENC.

[0174] Refer to together Figure 21A and Figure 21B The channel orifice CHH may include corresponding to Figures 22A to 22C The extended space ESPb of the base opening BOPd shown and the corresponding Figures 22A to 22CThe extended space of the extended opening EOPd is shown. The horizontal width of the extended space ESPb can be greater than the horizontal width of other portions of the via CHH. The extended space ESPb of the via CHH can be located at the boundary between the cell stack CST and the bit line routing insulation layer IMD-B. For example, the extended space ESPb of the via CHH can be located in the portion of the bit line routing insulation layer IMD-B adjacent to the cell stack CST. The extended space of the via CHH can extend from the extended space ESPb toward the bit line BL.

[0175] The cell channel structure CHSe may include a gate insulating layer GDIe, a channel layer CHLe, a buried insulating layer BILe, and a bit line pad BLPe. The gate insulating layer GDIe may have a structure including a tunneling dielectric film GDIeA, a charge storage film GDIeB, and a barrier dielectric film GDIeC. The gate insulating layer GDIe may include a body portion of the gate insulating layer GDIe, an insulating protrusion CDIPe, and an insulating extension CDIBe. The insulating protrusion CDIPe may surround the bit line pad BLPe. Each of the channel layer CHLe and the buried insulating layer BILe may extend vertically along the channel via CHH. Each of the channel layer CHLe and the buried insulating layer BILe may have a substantially equal horizontal width in the vertical direction, or may have a horizontal width that gradually decreases towards the bit line BL.

[0176] Bit line pads BLPe can be filled with, for example... Figures 22A to 22C The portion of the substrate opening BOPd shown. The bit line pad BLPe can have a horizontal cross-section with an annular or rectangular annular shape. The bit line pad BLPe can surround the channel layer CHLe. The bit line pad BLPe can be positioned adjacent to one end of the channel layer CHLe.

[0177] The through passage THVe may include a passage protrusion THBe and a passage extension THEe. The passage protrusion THBe may have a horizontal width greater than the horizontal width of the passage extension THEe.

[0178] Figures 22A to 22C This is a cross-sectional view of a method for manufacturing a non-volatile storage device according to an example embodiment. Specifically, Figures 22A to 22C It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB. Figures 22A to 22C Shown as with Figure 4A The ENB portion is reversed.

[0179] Reference Figure 22AThe upper part of the first substrate region BSUB1 is removed to form a substrate opening BOPd, and then an etch stop sacrificial film STB is formed to fill the substrate opening BOPd. The substrate opening BOPd can be formed with a circular or rectangular horizontal cross-section.

[0180] Reference Figure 22B After alternatingly forming multiple interlayer insulating layers (ILDs) and multiple sacrificial films (STLs) on the first substrate region BSUB1 and the etch stop sacrificial film (STB), an extension opening (EOPd) is formed. The extension opening (EOPd) penetrates the multiple interlayer insulating layers (ILDs), the multiple sacrificial films (STLs) and the etch stop sacrificial film (STB) and extends into the first substrate region BSUB1.

[0181] Refer to together Figure 22B and Figure 22C After removing the etch-stop sacrificial film STB, refer to Figures 6J to 6N Perform subsequent operations.

[0182] Figure 23 This is a cross-sectional view of a non-volatile storage device according to an example embodiment. Specifically, Figure 23 It corresponds to Figure 4A Enlarged cross-sectional view of part of ENB.

[0183] Reference Figure 23 Bit line pads BLPe and pillars STD can be misaligned in the vertical direction and can be offset. For example, pillar STD can be offset from bit line pads BLPe in the horizontal direction. When forming pillar STDs connected to bit line pads BLPe, even when offset between bit line pads BLPe and pillar STD occurs, bit line pads BLPe have a relatively large horizontal width, thus improving the connection reliability between the channel layer CHLe and the bit line BL.

[0184] Figure 24 This is a schematic diagram of a storage system including a non-volatile storage device according to an example embodiment.

[0185] Reference Figure 24 The storage system 1000 may include one or more storage devices 1100 and a storage controller 1200 electrically connected to the storage devices 1100. The storage system 1000 may be, for example, a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device that includes at least one storage device 1100.

[0186] Storage device 1100 may be a non-volatile storage device. For example, storage device 1100 may include the above-mentioned references. Figures 1 to 23The described non-volatile storage device 10 is a NAND flash memory device, one or a combination thereof. Storage device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F may correspond to... Figure 2 The peripheral circuit structure shown is PS or Figure 4A The peripheral circuit area Peri is shown. Figure 1 The peripheral circuit 30 shown may include a line decoder 1110, a page buffer 1120, and a logic circuit 1130. Figure 4A The multiple peripheral circuit transistors P-TR shown can form a line decoder 1110, a page buffer 1120, and a logic circuit 1130.

[0187] The second structure 1100S can correspond to Figure 2 and Figure 3 The cell array structure CS shown, or Figure 4A The diagram shows a stacked structure comprising the first bit line region BLR1, the first cell stacking region Cell ST1, the first common source region CSL1, the lower cell junction region BPU1, the upper cell junction region BPU2, the second common source region CSL2, the second cell stacking region Cell ST2, and the second bit line region BLR2. The second structure 1100S may include multiple first memory cell strings CSTR1 and multiple second memory cell strings CSTR2. Each of the multiple first memory cell strings CSTR1 and the multiple second memory cell strings CSTR2 is positioned between the bit line BL and the common source line CSL, and can be connected to multiple bit lines BL, the common source line CSL, and multiple word lines WL. Figure 4A The plurality of cell channel structures CHS and the plurality of gate electrodes CDL shown can respectively form the plurality of first memory cell strings CSTR1 and the plurality of second memory cell strings CSTR2.

[0188] In the second structure 1100S, the plurality of first memory cell strings CSTR1 and the plurality of second memory cell strings CSTR2 may include ground selection transistors LT1 and LT2 adjacent to the common source line CSL, string selection transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the ground selection transistors LT1 and LT2 and the string selection transistors UT1 and UT2. According to the example embodiment, the number of ground selection transistors LT1 and LT2 and the number of string selection transistors UT1 and UT2 can be varied. Figure 4AOne of the plurality of cell channel structures CHS and one of the plurality of gate electrodes CDL shown can constitute one of the plurality of transistors LT1, LT2, UT1, UT2 and MCT. The common source line CSL connected to the plurality of first memory cell strings CSTR1 and the common source line CSL connected to the plurality of second memory cell strings CSTR2 can be arranged between the plurality of first memory cell strings CSTR1 and the plurality of second memory cell strings CSTR2 facing each other.

[0189] The bit line BL connected to the plurality of first storage cell strings CSTR1 may be located on the side of the plurality of first storage cell strings CSTR1 opposite to the plurality of second storage cell strings CSTR2, and the bit line BL connected to the plurality of second storage cell strings CSTR2 may be located on the side of the plurality of second storage cell strings CSTR2 opposite to the plurality of first storage cell strings CSTR1.

[0190] According to some example implementations, the first ground select line LL1 and the second ground select line LL2 can be connected to the gate electrodes of ground select transistors LT1 and LT2, respectively. The word line WL can be connected to the gate electrode of the memory cell transistor MCT. The first string select line UL1 and the second string select line UL2 can be connected to the gate electrodes of string select transistors UT1 and UT2, respectively.

[0191] The common source line CSL, ground select lines LL1 and LL2, word line WL, and first string select line UL1 and second string select line UL2 can be connected to the line decoder 1110. The bit line BL can be electrically connected to the page buffer 1120.

[0192] Storage device 1100 can communicate with storage controller 1200 via external connection pad 1101 electrically connected to logic circuit 1130. External connection pad 1101 can be electrically connected to logic circuit 1130. External connection pad 1101 can correspond to... Figure 4A The input / output pads are shown. The storage device 1100 can be electrically connected to the storage controller 1200 via connection structures such as bonding leads connected to external connection pads 1101.

[0193] The storage controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the storage system 1000 may include a plurality of storage devices 1100. In this case, the storage controller 1200 can control the plurality of storage devices 1100.

[0194] Processor 1210 can control the entire operation of storage system 1000, including storage controller 1200. Processor 1210 can operate according to specific firmware and can access storage device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface 1221 for processing communication with storage device 1100. Control commands for controlling storage device 1100, data to be written to memory cell transistors (MCTs) of storage device 1100, and data read from memory cell transistors (MCTs) of storage device 1100 can be transmitted via NAND interface 1221. Host interface 1230 provides functionality for communication between storage system 1000 and external host. When a control command is received from an external host via host interface 1230, processor 1210 can control storage device 1100 in response to the control command.

[0195] Figure 25 This is a schematic perspective view of a storage system including a non-volatile storage device according to an example embodiment.

[0196] Reference Figure 25 A memory system 2000 according to an example embodiment may include a main substrate 2001 and a memory controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the memory controller 2002 via a plurality of wiring patterns 2005 formed on the main substrate 2001.

[0197] The main substrate 2001 may include a connector 2006, which includes a plurality of pins and is configured to connect to an external host. The number and arrangement of the pins of the connector 2006 may vary depending on the communication interface between the storage system 2000 and the external host. In example embodiments, the storage system 2000 may communicate with the external host via any of the interfaces including Universal Serial Bus (USB), PCI-Express, Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Memory (UFS), etc. In some example embodiments, the storage system 2000 may operate via power supplied from the external host by the connector 2006. The storage system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the storage controller 2002 and the semiconductor package 2003.

[0198] The storage controller 2002 can write data to or read data from the semiconductor package 2003 and can improve the operating speed of the storage system 2000.

[0199] DRAM 2004 can be a buffer memory used to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. DRAM 2004 included in the storage system 2000 can also operate as a high-speed cache memory and can provide space for temporary data storage during control operations of the semiconductor package 2003. When DRAM 2004 is included in the storage system 2000, in addition to the NAND controller for controlling the semiconductor package 2003, the storage controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0200] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 on the package substrate 2100 covering the semiconductor chip 2200 and the connection structure 2400.

[0201] Each of the plurality of semiconductor chips 2200 may include the above references. Figures 1 to 23 At least one of the described non-volatile memory devices 10. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to Figure 4A The input / output pads are shown. The package substrate 2100 can be a printed circuit board including multiple package-on-pads 2130.

[0202] In some example embodiments, the connection structure 2400 may be a bonding lead that electrically connects the input / output pads 2210 and the package pads 2130. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding leads and may be electrically connected to the package pads 2130 of the package substrate 2100.

[0203] According to some example embodiments, the memory controller 2002 and the semiconductor chip 2200 may be included in a single package. According to some example embodiments, the memory controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate, different from the main substrate 2001, and the memory controller 2002 and the semiconductor chip 2200 may be interconnected by wires formed on the interposer substrate.

[0204] Figure 26 This is a schematic cross-sectional view of a semiconductor package according to an example embodiment.

[0205] Reference Figure 26 In semiconductor packaging 2003, the packaging substrate 2100 can be a printed circuit board. The packaging substrate 2100 may include a packaging substrate body 2120 and a plurality of on-package pads 2130 disposed on the top surface of the packaging substrate body 2120 (see reference). Figure 25 ), and multiple lower package pads 2125 arranged or exposed on the bottom surface of the package substrate body 2120, and upper package pads 2130 electrically connected inside the package substrate body 2120 (see reference). Figure 25 ), and multiple internal conductors 2135 of the pad 2125 under the package. For example... Figure 25 As shown, the multiple package pads 2130 can be electrically connected to multiple connection structures 2400. The package pads 2125 can be connected to multiple conductive bumps 2800. Figure 25 Wiring pattern 2005 on the main substrate 2001 of the storage system 2000 shown. Each of the plurality of semiconductor chips 2200 may include the wiring pattern shown above. Figures 1 to 23 At least one of the described non-volatile storage devices 10.

[0206] Any functional block shown in the accompanying drawings and described above can be implemented as: processing circuitry, such as hardware including logic circuitry; hardware / software combination, such as a processor executing software; or a combination thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0207] Although the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0208] This application is based on and claims priority to Korean Patent Application No. 10-2024-0131072, filed on September 26, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A non-volatile storage device, comprising: The peripheral circuit structure includes a peripheral circuit, wherein the peripheral circuit includes a plurality of peripheral circuit transistors; and A cell array structure is electrically connected to the peripheral circuit structure. The cell array structure includes a common source line layer, bit lines, a bit line wiring insulating layer surrounding the bit lines, a cell stack in a vertical direction between the common source line layer and the bit lines, and a plurality of channel structures extending through the cell stack into the bit line wiring insulating layer. The cell stack includes a plurality of alternating gate electrodes and a plurality of interlayer insulating layers in the vertical direction. Each of the plurality of channel structures includes a channel layer, a bit line pad, and a gate insulating layer. The channel layer is electrically connected to the common source line layer. The bit line pad electrically connects the channel layer to the bit line and is adjacent to one end of the channel layer facing the bit line. The gate insulating layer covers the channel layer and the bit line pad. The gate insulating layer includes an insulating protrusion at the boundary between the bit line wiring insulating layer and the cell stack, the insulating protrusion protruding further in the horizontal direction than the portion of the gate insulating layer that penetrates the cell stack.

2. The non-volatile storage device according to claim 1, wherein... The cell array structure further includes pillars that contact the bit line pads and electrically connect the bit lines to the bit line pads. The gate insulating layer is in contact with at least a portion of the side surface of the pillar.

3. The non-volatile memory device of claim 2, wherein the bit line pads have a T-shaped vertical cross-section, the T-shaped vertical cross-section including a pad extension and a pad extension, the pad extension being connected to the channel layer, and the pad extension being connected to the post and having a horizontal width wider than the horizontal width of the pad extension.

4. The non-volatile memory device of claim 2, wherein the bit line pads have a cross-shaped vertical cross-section, the cross-shaped vertical cross-section including a first pad extension, a second pad extension, and a pad extension, the first pad extension being connected to the channel layer, the second pad extension being connected to the post, the pad extension having a horizontal width wider than the horizontal width of each of the first pad extension and the second pad extension, the pad extension being located between the first pad extension and the second pad extension.

5. The non-volatile storage device of claim 2, wherein the bit line pads are in contact with a portion of the bottom surface of the pillar and a portion of the side surface of the pillar.

6. The non-volatile storage device according to claim 1, wherein, In each of the plurality of channel structures, the portion extending toward the bit line from one end of the stacked cells facing the bit line has a tapered shape in which its horizontal width decreases toward the bit line.

7. The non-volatile storage device of claim 1, wherein the channel layer includes a channel protrusion that protrudes horizontally from a portion of the channel layer that penetrates the cell stack, the channel protrusion corresponding to the insulating protrusion.

8. The non-volatile storage device according to claim 7, wherein Each of the plurality of trench structures further includes a buried insulation layer that fills the space defined by the trench layer, and The buried insulation layer includes buried protrusions that protrude horizontally from a portion of the buried insulation layer that penetrates the unit stack, the buried protrusions corresponding to the insulation protrusions and the channel protrusions.

9. The non-volatile memory device of claim 1, wherein the insulating protrusion of the gate insulating layer is located within the portion of the bit line wiring insulating layer adjacent to the cell stack.

10. The non-volatile storage device according to claim 1, wherein The cell array structure includes a first cell array structure and a second cell array structure on the first cell array structure. Each of the first cell array structure and the second cell array structure includes the common source line layer, the bit line, the bit line wiring insulation layer, the cell stack, and the plurality of channel structures. The common source line layer of the first cell array structure and the common source line layer of the second cell array structure are located between the cell stack of the first cell array structure and the cell stack of the second cell array structure.

11. A non-volatile storage device, comprising: The peripheral circuit structure includes a peripheral circuit, wherein the peripheral circuit includes a plurality of peripheral circuit transistors; A first unit array structure is electrically connected to the peripheral circuit structure. The first unit array structure includes a first bit line, a first bit line wiring insulation layer surrounding the first bit line, a first common source line layer, a first unit stack between the first bit line and the first common source line layer in the vertical direction, and a plurality of first channel structures penetrating the first unit stack and extending into the first bit line wiring insulation layer. The first unit stack includes a plurality of first gate electrodes and a plurality of first interlayer insulation layers alternating in the vertical direction. as well as A second cell array structure is electrically connected to the first cell array structure. The second cell array structure includes a second common source line layer, a second bit line, a second bit line wiring insulation layer surrounding the second bit line, a second cell stack in the vertical direction between the second common source line layer and the second bit line, and a plurality of second channel structures extending through the second cell stack into the second bit line wiring insulation layer. The second cell stack includes a plurality of alternating second gate electrodes and a plurality of second interlayer insulation layers in the vertical direction. The first common source line layer and the second common source line layer are located between the first cell stack and the second cell stack. Each of the plurality of first channel structures includes a first channel layer, a first bit line pad, and a first gate insulating layer. The first channel layer is electrically connected to the first common source line layer. The first bit line pad is electrically connected to the first channel layer and the first bit line. The first bit line pad is adjacent to the end of the first channel layer facing the first bit line. The first gate insulating layer covers the first channel layer and the first bit line pad. Each of the plurality of second-channel structures includes a second channel layer, a second bit line pad, and a second gate insulating layer. The second channel layer is electrically connected to the second common source line layer. The second bit line pad is electrically connected to the second channel layer and the second bit line. The second bit line pad is adjacent to one end of the second channel layer facing the second bit line. The second gate insulating layer covers the second channel layer and the second bit line pad. The first gate insulating layer includes a first insulating protrusion at the boundary between the first first line wiring insulating layer and the first cell stack. The first insulating protrusion protrudes further horizontally than the portion of the first gate insulating layer that penetrates the first cell stack. The second gate insulating layer includes a second insulating protrusion at the boundary between the second bit line wiring insulating layer and the second cell stack, the second insulating protrusion protruding further in the horizontal direction than the portion of the second gate insulating layer that penetrates the second cell stack.

12. The non-volatile storage device according to claim 11, wherein The first cell array structure further includes a first pillar, which contacts and electrically connects the first bit line and the first bit line pad. The second cell array structure further includes a second pillar, which contacts and electrically connects the second bit line and the second bit line pad. The first gate insulating layer contacts at least a portion of the side surface of the first pillar, and The second gate insulating layer is in contact with at least a portion of the side surface of the second pillar.

13. The non-volatile storage device according to claim 12, wherein The first bit pad contacts at least a portion of the bottom surface of the first pillar and at least a portion of the side surface of the first pillar, and The second bit pad is in contact with at least a portion of the bottom surface of the second pillar and at least a portion of the side surface of the second pillar.

14. The non-volatile storage device according to claim 12, wherein The first bit line pad includes a first pad extension and a first pad expansion, the first pad extension being connected to the first channel layer, the first pad expansion being connected to the first pillar, and the first pad expansion having a horizontal width wider than the horizontal width of the first pad extension. The second bit line pad includes a second pad extension and a second pad expansion. The second pad extension is connected to the second channel layer, and the second pad expansion is connected to the second pillar. The second pad expansion has a horizontal width that is wider than the horizontal width of the second pad extension.

15. The non-volatile storage device according to claim 12, wherein The first bit line pad includes a first pad extension, a second pad extension, and a first pad expansion. The first pad extension is connected to the first channel layer, and the second pad extension is connected to the first pillar. The first pad expansion has a horizontal width wider than the horizontal widths of the first pad extension and the second pad extension. The first pad expansion is located between the first pad extension and the second pad extension. The second bit line pad includes a third pad extension, a fourth pad extension, and a second pad extension. The third pad extension is connected to the second channel layer, and the fourth pad extension is connected to the second pillar. The second pad extension has a horizontal width that is wider than the horizontal widths of the third pad extension and the fourth pad extension, and the second pad extension is located between the third pad extension and the fourth pad extension.

16. The non-volatile storage device according to claim 11, wherein Each of the plurality of first channel structures has a portion extending toward the first bit line from one end of the first unit stack facing the first bit line, having a tapered shape in which its horizontal width decreases toward the first bit line. Each of the plurality of second channel structures has a portion extending toward the second bit line from one end of the second unit stack facing the second bit line, with its horizontal width decreasing toward the second bit line.

17. The non-volatile storage device according to claim 11, wherein The first channel layer includes a first channel protrusion corresponding to the first insulating protrusion, and The second channel layer includes a second channel protrusion corresponding to the second insulating protrusion.

18. A storage system, comprising: Non-volatile storage devices, including The peripheral circuit structure includes a peripheral circuit, which in turn includes multiple peripheral circuit transistors. The first unit array structure is located on the peripheral circuit structure. The second unit array structure, on top of the first unit array structure, and Input / output pads are disposed on the second cell array structure, wherein each of the first cell array structure and the second cell array structure includes a common source line layer, a bit line, a bit line wiring insulation layer surrounding the bit line, a cell stack between the common source line layer and the bit line in a vertical direction, and a plurality of channel structures extending through the cell stack into the bit line wiring insulation layer, the cell stack including a plurality of gate electrodes and a plurality of interlayer insulation layers alternating in the vertical direction; as well as A storage controller, electrically connected to the non-volatile storage device via the input / output pads and configured to control the non-volatile storage device, The common source line layer of the first unit array structure and the common source line layer of the second unit array structure are arranged between the unit stack of the first unit array structure and the unit stack of the second unit array structure. Each of the plurality of channel structures included in each of the first and second cell array structures includes a channel layer, a bit line pad, and a gate insulating layer. The channel layer is electrically connected to the common source line layer. The bit line pad electrically connects the channel layer to the bit line. The bit line pad is adjacent to one end of the channel layer facing the bit line. The gate insulating layer covers the channel layer and the bit line pad. The gate insulating layer included in each of the first cell array structure and the second cell array structure includes an insulating protrusion at the boundary between the bit line wiring insulating layer and the cell stack, the insulating protrusion protruding further in the horizontal direction than the portion of the gate insulating layer that penetrates the cell stack.

19. The memory system of claim 18, wherein each of the first cell array structure and the second cell array structure further comprises a post electrically connecting the bit line and the bit line pad, the post contacting the bit line pad, and at least a portion of a side surface of the post contacting the gate insulating layer.

20. The storage system of claim 18, wherein the channel layer in each of the first cell array structure and the second cell array structure includes a channel protrusion that protrudes further in the horizontal direction than a portion of the channel layer that penetrates the cell stack, the channel protrusion corresponding to the insulating protrusion.

Images