Non-volatile memory structure

Abstract

The invention discloses a non-volatile memory structure. The non-volatile memory structure comprises a substrate, a gate dielectric layer and a floating gate structure, the gate dielectric layer is located on the substrate. The floating gate structure is located on the gate dielectric layer. The floating gate structure includes a buffer polysilicon layer, a carbon-doped polysilicon layer, a doped polysilicon layer, a first nitride layer and a first oxide layer. The buffer polysilicon layer is located on the gate dielectric layer. The carbon-doped polycrystalline silicon layer is located on the buffer polycrystalline silicon layer. The doped polycrystalline silicon layer is located on the carbon-doped polycrystalline silicon layer. The first nitride layer is located between the buffer polysilicon layer and the gate dielectric layer. The first oxide layer is located between the doped polycrystalline silicon layer and the carbon-doped polycrystalline silicon layer.

Description

TECHNICAL FIELD

[0001] The present invention relates to a memory structure, and more particularly, to a non-volatile memory structure. BACKGROUND

[0002] Non-volatile memory has become a widely used memory because it can perform multiple data storage, reading and erasing operations, and has the advantages of not losing stored data when power supply is interrupted, short data access time, and low power consumption. However, how to further improve the reliability of non-volatile memory is a continuous effort. SUMMARY

[0003] The present invention provides a non-volatile memory structure that can have better reliability.

[0004] The present invention provides a non-volatile memory structure, comprising a substrate, a gate dielectric layer and a floating gate structure. The gate dielectric layer is on the substrate. The floating gate structure is on the gate dielectric layer. The floating gate structure comprises a buffer polysilicon layer, a carbon-doped polysilicon layer, a doped polysilicon layer, a first nitride layer and a first oxide layer. The buffer polysilicon layer is on the gate dielectric layer. The carbon-doped polysilicon layer is on the buffer polysilicon layer. The doped polysilicon layer is on the carbon-doped polysilicon layer. The first nitride layer is between the buffer polysilicon layer and the gate dielectric layer. The first oxide layer is between the doped polysilicon layer and the carbon-doped polysilicon layer.

[0005] According to an embodiment of the present invention, in the above-mentioned non-volatile memory structure, the dopant of the doped polysilicon layer can comprise P-type dopant or N-type dopant.

[0006] According to an embodiment of the present invention, in the above-mentioned non-volatile memory structure, the total dopant concentration of the buffer polysilicon layer can be less than the total dopant concentration of the doped polysilicon layer.

[0007] According to an embodiment of the present invention, in the above-mentioned non-volatile memory structure, the total dopant concentration of the buffer polysilicon layer can be less than the total dopant concentration of the carbon-doped polysilicon layer.

[0008] According to an embodiment of the present invention, in the above-mentioned non-volatile memory structure, the material of the buffer polysilicon layer can be undoped polysilicon.

[0009] According to an embodiment of the present invention, in the above-mentioned non-volatile memory structure, a control gate and a dielectric layer structure can also be included. The control gate is on the floating gate structure. The dielectric layer structure is between the control gate and the floating gate structure.

[0010] According to one embodiment of the present invention, in the above-described non-volatile memory structure, the material of the control gate may be doped polysilicon.

[0011] According to an embodiment of the present invention, in the above-described non-volatile memory structure, the dielectric layer structure may include a second nitride layer, a second oxide layer, a third nitride layer, and a third oxide layer. The second nitride layer is located on the floating gate structure. The second oxide layer is located on the second nitride layer. The third nitride layer is located on the second oxide layer. The third oxide layer is located on the third nitride layer.

[0012] According to one embodiment of the present invention, in the above-described non-volatile memory structure, the dielectric layer structure may further include a fourth nitride layer. The fourth nitride layer is located on the third oxide layer.

[0013] According to one embodiment of the present invention, the above-described non-volatile memory structure may further include an isolation structure. The isolation structure is located in the substrate. The isolation structure may define an active region in the substrate. A floating gate structure may be located in the active region.

[0014] Based on the above, in the non-volatile memory structure proposed in this invention, since the carbon-doped polysilicon layer contains carbon dopants, it can have a small grain size. Therefore, the durability and data retention capacity of the non-volatile memory structure can be improved, thereby enhancing its reliability. Furthermore, since the non-volatile memory structure has a buffer polysilicon layer, the sub-threshold swing can be reduced, improving the channel control capability of the floating gate structure. Additionally, the first nitride layer is located between the buffer polysilicon layer and the gate dielectric layer, thereby suppressing the diffusion of carbon dopants from the carbon-doped polysilicon layer into the gate dielectric layer, thus improving the quality of the gate dielectric layer. Furthermore, the first oxide layer is located between the doped polysilicon layer and the carbon-doped polysilicon layer, thereby suppressing the diffusion of dopants from the doped polysilicon layer into the carbon-doped polysilicon layer and the buffer polysilicon layer, thus effectively controlling the dopant concentration of the carbon-doped polysilicon layer and the buffer polysilicon layer. On the other hand, since the first oxide layer is located between the doped polysilicon layer and the carbon-doped polysilicon layer, it can suppress the diffusion of carbon dopants from the carbon-doped polysilicon layer into the doped polysilicon layer, thus effectively controlling the dopant concentration of the doped polysilicon layer.

[0015] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view of a non-volatile memory structure according to some embodiments of the present invention.

[0017] Symbol Explanation

[0018] 10: Non-volatile memory architecture

[0019] 100: Base

[0020] 102: Gate dielectric layer

[0021] 104: Floating gate structure

[0022] 106: Isolation Structure

[0023] 108: Buffered polysilicon layer

[0024] 110: Carbon-doped polycrystalline silicon layer

[0025] 112: Doped polycrystalline silicon layer

[0026] 114, 122, 126, 130: Nitride layers

[0027] 116, 124, 128: Oxide layers

[0028] 118: Control gate

[0029] 120: Dielectric layer structure

[0030] AA: Active Zone Detailed Implementation

[0031] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be increased or decreased arbitrarily for clarity of explanation.

[0032] Figure 1 This is a cross-sectional view of a non-volatile memory structure according to some embodiments of the present invention.

[0033] Please refer to Figure 1The non-volatile memory structure 10 includes a substrate 100, a gate dielectric layer 102, and a floating gate structure 104. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, the non-volatile memory structure 10 may also include an isolation structure 106. The isolation structure 106 is located within the substrate 100. The isolation structure 106 may define an active region AA within the substrate 100. In some embodiments, the material of the isolation structure 106 is, for example, silicon oxide.

[0034] The gate dielectric layer 102 is located on the substrate 100. In some embodiments, the material of the gate dielectric layer 102 is, for example, silicon oxide.

[0035] The floating gate structure 104 is located on the gate dielectric layer 102. The floating gate structure 104 may be located in the active region AA. The floating gate structure 104 includes a buffer polysilicon layer 108, a carbon-doped polysilicon layer 110, a doped polysilicon layer 112, a nitride layer 114, and an oxide layer 116.

[0036] A buffer polysilicon layer 108 is located on the gate dielectric layer 102. Because the non-volatile memory structure 10 has a buffer polysilicon layer 108, the subcritical swing can be reduced, thereby improving the ability of the floating gate structure 104 to control the channel. In some embodiments, the total dopant concentration of the buffer polysilicon layer 108 may be less than the total dopant concentration of the doped polysilicon layer 112. In some embodiments, the total dopant concentration of the buffer polysilicon layer 108 may be less than the total dopant concentration of the carbon-doped polysilicon layer 110. In some embodiments, the material of the buffer polysilicon layer 108 may be undoped polysilicon.

[0037] A carbon-doped polysilicon layer 110 is located on the buffer polysilicon layer 108. Because the carbon-doped polysilicon layer 110 contains carbon dopants, it can have a small particle size. Therefore, the durability and data retention capability of the non-volatile memory structure 10 can be improved, thereby enhancing the reliability of the non-volatile memory structure 10.

[0038] The doped polysilicon layer 112 is located on the carbon-doped polysilicon layer 110. In some embodiments, the dopant of the doped polysilicon layer 112 may include a P-type dopant or an N-type dopant.

[0039] The nitride layer 114 is located between the buffer polysilicon layer 108 and the gate dielectric layer 102, thereby suppressing the diffusion of carbon dopants from the carbon-doped polysilicon layer 110 into the gate dielectric layer 102, and thus improving the quality of the gate dielectric layer 102. In some embodiments, the material of the nitride layer 114 is, for example, silicon nitride.

[0040] The oxide layer 116 is located between the doped polysilicon layer 112 and the carbon-doped polysilicon layer 110, thereby suppressing the diffusion of dopants from the doped polysilicon layer 112 into the carbon-doped polysilicon layer 110 and the buffer polysilicon layer 108, thus effectively controlling the dopant concentration of the carbon-doped polysilicon layer 110 and the buffer polysilicon layer 108. Furthermore, since the oxide layer 116 is located between the doped polysilicon layer 112 and the carbon-doped polysilicon layer 110, it also suppresses the diffusion of carbon dopants from the carbon-doped polysilicon layer 110 into the doped polysilicon layer 112, thereby effectively controlling the dopant concentration of the doped polysilicon layer 112.

[0041] The non-volatile memory structure 10 may further include a control gate 118 and a dielectric layer structure 120. The control gate 118 is located on the floating gate structure 104. In some embodiments, the material of the control gate 118 may be doped polysilicon. In some embodiments, the dopant of the control gate 118 may include a P-type dopant or an N-type dopant.

[0042] A dielectric layer structure 120 is located between the control gate 118 and the floating gate structure 104. The dielectric layer structure 120 may also be located on the isolation structure 106. The dielectric layer structure 120 may be a single-layer structure or a multi-layer structure. In some embodiments, the dielectric layer structure 120 may include a nitride layer 122, an oxide layer 124, a nitride layer 126, and an oxide layer 128. That is, the dielectric layer structure 120 may be an oxide / nitride / oxide / nitride (ONON) composite layer. The nitride layer 122 is located on the floating gate structure 104. The nitride layer 122 can suppress the diffusion of carbon dopants from the carbon-doped polysilicon layer 110 into the control gate 118. In some embodiments, the material of the nitride layer 122 is, for example, silicon nitride. An oxide layer 124 is located on the nitride layer 122. In some embodiments, the material of the oxide layer 124 is, for example, silicon oxide. A nitride layer 126 is located on the oxide layer 124. The nitride layer 126 can suppress the diffusion of carbon dopants from the carbon-doped polysilicon layer 110 into the control gate 118. In some embodiments, the material of the nitride layer 126 is, for example, silicon nitride. An oxide layer 128 is located on the nitride layer 126. In some embodiments, the material of the oxide layer 128 is, for example, silicon oxide.

[0043] In some embodiments, the dielectric layer structure 120 may further include a nitride layer 130. That is, the dielectric layer structure 120 may be a nitride / oxide / nitride / oxide / nitride (NONON) composite layer. The nitride layer 130 is located on the oxide layer 128. The nitride layer 130 can suppress the diffusion of carbon dopants in the carbon-doped polysilicon layer 110 into the control gate 118. In some embodiments, the material of the nitride layer 130 is, for example, silicon nitride.

[0044] In some embodiments, the dielectric layer structure 120 may include an oxide layer 124, a nitride layer 126, and an oxide layer 128, but excludes nitride layers 122 and 130. That is, the dielectric layer structure 120 may be an oxide / nitride / oxide (ONO) composite layer.

[0045] Based on the above embodiments, it can be seen that in the non-volatile memory structure 10, since the carbon-doped polysilicon layer 110 can have a small particle size, the durability and data retention capability of the non-volatile memory structure 10 can be improved, thereby enhancing the reliability of the non-volatile memory structure 10. Furthermore, the buffer polysilicon layer 108 can reduce the subcritical swing, thereby improving the channel control capability of the floating gate structure 104. Additionally, the nitride layer 114 can suppress the diffusion of carbon dopants from the carbon-doped polysilicon layer 110 into the gate dielectric layer 102, thereby improving the quality of the gate dielectric layer 102. Moreover, the oxide layer 116 can effectively control the dopant concentration of the carbon-doped polysilicon layer 110, the dopant concentration of the buffer polysilicon layer 108, and the dopant concentration of the doped polysilicon layer 112.

[0046] In summary, in the non-volatile memory structure of the above embodiments, the floating gate structure includes a buffer polysilicon layer, a carbon-doped polysilicon layer, a doped polysilicon layer, a first nitride layer, and a first oxide layer. Since the carbon-doped polysilicon layer contains carbon dopants, it can have a small particle size. Therefore, the durability and data retention capability of the non-volatile memory structure can be improved, thereby enhancing its reliability. Furthermore, because the non-volatile memory structure has a buffer polysilicon layer, the subcritical swing can be reduced, improving the floating gate structure's control channel capability. Additionally, the first nitride layer is located between the buffer polysilicon layer and the gate dielectric layer, thereby suppressing the diffusion of carbon dopants from the carbon-doped polysilicon layer into the gate dielectric layer, thus improving the quality of the gate dielectric layer. Furthermore, the first oxide layer is located between the doped polysilicon layer and the carbon-doped polysilicon layer, thereby suppressing the diffusion of dopants from the doped polysilicon layer into the carbon-doped polysilicon layer and the buffer polysilicon layer, thus effectively controlling the dopant concentration of the carbon-doped polysilicon layer and the buffer polysilicon layer. On the other hand, since the first oxide layer is located between the doped polysilicon layer and the carbon-doped polysilicon layer, it can suppress the diffusion of carbon dopants from the carbon-doped polysilicon layer into the doped polysilicon layer, thus effectively controlling the dopant concentration of the doped polysilicon layer.

[0047] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. A non-volatile memory structure, comprising: Base; A gate dielectric layer is located on the substrate; as well as A floating gate structure, located on the gate dielectric layer, includes: A buffer polysilicon layer is located on the gate dielectric layer; A carbon-doped polycrystalline silicon layer is located on the buffer polycrystalline silicon layer; A doped polycrystalline silicon layer is located on the carbon-doped polycrystalline silicon layer; A first nitride layer is located between the buffer polysilicon layer and the gate dielectric layer; and The first oxide layer is located between the doped polysilicon layer and the carbon-doped polysilicon layer.

2. The non-volatile memory structure as described in claim 1, wherein the dopant of the polysilicon layer includes a P-type dopant or an N-type dopant.

3. The non-volatile memory structure as described in claim 1, wherein the total dopant concentration of the buffer polysilicon layer is less than the total dopant concentration of the doped polysilicon layer.

4. The non-volatile memory structure as described in claim 1, wherein the total dopant concentration of the buffer polysilicon layer is less than the total dopant concentration of the carbon-doped polysilicon layer.

5. The non-volatile memory structure of claim 1, wherein the material of the buffer polysilicon layer comprises undoped polysilicon.

6. The non-volatile memory structure as described in claim 1, further comprising: A control gate is located on the floating gate structure; as well as A dielectric layer structure is located between the control gate and the floating gate structure.

7. The non-volatile memory structure of claim 6, wherein the material of the control gate comprises doped polysilicon.

8. The non-volatile memory structure of claim 6, wherein the dielectric layer structure comprises: A second nitride layer is located on the floating gate structure; The second oxide layer is located on the second nitride layer; as well as The third nitride layer is located on the second oxide layer; as well as The third oxide layer is located on the third nitride layer.

9. The non-volatile memory structure of claim 8, wherein the dielectric layer structure further comprises: The fourth nitride layer is located on the third oxide layer.

10. The non-volatile memory structure as described in claim 1, further comprising: An isolation structure is located in the substrate, and an active region is defined in the substrate, wherein the floating gate structure is located in the active region.

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