Power device and preparation method thereof
By using a preset mask and adjusting the etching time during the fabrication process of FRED, a uniform voltage divider ring and spacing are formed, which solves the problem of voltage divider ring non-uniformity, improves the voltage withstand uniformity and yield, and simplifies the fabrication process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2026-03-27
AI Technical Summary
In existing technologies, the uneven width and spacing of the voltage divider rings in FREDs lead to uneven pressure resistance, resulting in low product yield and high requirements for manufacturing processes.
Wet etching is performed using a preset mask, reducing the mask pattern width and increasing the etching time to form a uniform pressure ring and uniform spacing. A buffer layer is formed by ion implantation on the surface of the epitaxial layer and back-side thinning.
It improves the voltage uniformity and product yield of power devices, simplifies the fabrication process, and reduces the requirements for etching processes.
Smart Images
Figure CN121751655A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a power device and its fabrication method. Background Technology
[0002] With the rapid development of the electronics industry, Fast Recovery Epitaxial Diode (FRED), as a semiconductor device with excellent switching characteristics and fast reverse recovery capability, is gradually becoming a key component for improving the efficiency and stability of electronic devices.
[0003] However, conventional processes often use wet etching on the control line to prepare the voltage divider rings in FREDs. This can lead to uneven width of the voltage divider rings and uneven spacing between voltage divider rings on each wafer due to excessive side etching. This results in uneven withstand voltage within each wafer and / or between wafers, leading to low product yield and high requirements for the manufacturing process. Summary of the Invention
[0004] This invention provides a power device and its fabrication method to improve the voltage uniformity of power devices within and / or between wafers, increase product yield, and simplify the fabrication process.
[0005] According to one aspect of the present invention, a method for fabricating a power device is provided, comprising:
[0006] A substrate is provided, and an epitaxial layer is formed on the surface of the substrate;
[0007] Ion implantation is performed on the surface of the epitaxial layer to form an active region;
[0008] A preset mask is attached to the surface of the epitaxial layer, and wet etching is performed for a preset etching time to form multiple voltage divider rings of target width in the epitaxial layer, with a uniform spacing between adjacent voltage divider rings.
[0009] The preset mask pattern has a preset width, which is less than an empirical value, and the preset etching duration is greater than an empirical value.
[0010] The substrate is thinned on the back side to form a buffer layer;
[0011] A back metal layer is formed on the side of the buffer layer away from the substrate.
[0012] Optionally, the empirical width value is less than the target width, and the preset width is the width obtained by reducing the empirical width value by a first preset percentage.
[0013] Optionally, the range of the first preset percentage includes 20% to 30%.
[0014] Optionally, the preset etching duration is the duration by adding a second preset percentage to the empirical value of the etching duration.
[0015] Optionally, the range of the second preset percentage includes 25% to 35%.
[0016] Optionally, the buffer layer has a first conductivity type, the epitaxial layer has a second conductivity type, the active region has a third conductivity type, and the voltage divider ring has a fourth conductivity type;
[0017] The first conductivity type is the same as the second conductivity type, the third conductivity type is the same as the fourth conductivity type, and the first conductivity type is different from the third conductivity type.
[0018] Optionally, before forming the active region, the method further includes:
[0019] Ion implantation is performed on the surface of the epitaxial layer to form a cutoff ring region; wherein the conductivity type of the cutoff ring region is the same as that of the epitaxial layer.
[0020] Optionally, forming the active region includes:
[0021] Ion implantation and high-temperature push-junction are performed on the epitaxial layer to form a well region with a first push-junction depth;
[0022] The well region is subjected to ion implantation and high-temperature push-junction to form a heavily doped region with a second push-junction depth; wherein the second push-junction depth is less than the first push-junction depth.
[0023] Optionally, after forming the voltage divider rings of multiple target widths, the method further includes:
[0024] An insulating layer is formed on the surface of the epitaxial layer; the insulating layer covers the voltage divider ring;
[0025] A field plate structure is formed on the side of the insulating layer away from the epitaxial layer; the field plate structure corresponds one-to-one with the voltage dividing ring.
[0026] A metal layer is formed on the side of the insulating layer away from the epitaxial layer; the metal layer covers the active region and the cutoff ring region.
[0027] A passivation layer is formed on the side of the field plate structure away from the insulating layer; the passivation layer covers the insulating layer, the field plate structure, and part of the metal layer.
[0028] According to another aspect of the present invention, a power device is provided, which is applicable to the power device fabrication method as described in any embodiment of the first aspect.
[0029] The power device fabrication method provided in this invention involves ion implantation onto the surface of an epitaxial layer to form an active region in a portion of the area. A preset mask is used to perform wet etching on the epitaxial layer, with a preset etching duration throughout the etching process. The preset mask has a pattern of a preset width, which is smaller than an empirical width value, and the preset etching duration is greater than an empirical etching duration value. A buffer layer is then formed on the back side of the substrate through back thinning, and a back metal layer is formed on the side of the buffer layer away from the substrate. This invention, by appropriately reducing the design width of the mask pattern and increasing the etching duration, significantly reduces the etching rate at different locations within the same wafer and at different locations on different wafers, and also significantly reduces the difference in etching rates. This results in voltage divider rings with a uniform target width and uniform spacing between adjacent voltage divider rings, which is beneficial for improving the voltage withstand uniformity of the power device, increasing product yield, and effectively reducing the requirements for the fabrication process.
[0030] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a schematic flowchart of a power device fabrication method according to an embodiment of the present invention;
[0033] Figure 2 This is a schematic diagram of the structure corresponding to each step in a power device fabrication method provided by an embodiment of the present invention;
[0034] Figure 3 This is a schematic diagram of the etching structure of a power device provided by existing technology;
[0035] Figure 4 This is a schematic diagram of the etching structure of a power device according to an embodiment of the present invention;
[0036] Figure 5 This is a schematic flowchart of another power device fabrication method provided by an embodiment of the present invention;
[0037] Figure 6 This is a schematic diagram of the structure corresponding to each step in another power device fabrication method provided according to an embodiment of the present invention;
[0038] Figure 7 This is a schematic diagram of the structure of a power device fabricated using a power device fabrication method according to an embodiment of the present invention. Detailed Implementation
[0039] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0041] This invention provides a method for fabricating a power device. Figure 1 This is a schematic flowchart of a power device fabrication method provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure corresponding to each step in a power device fabrication method provided by an embodiment of the present invention. Combined with... Figure 1 and Figure 2 The method for fabricating this power device specifically includes the following steps:
[0042] S110. A substrate is provided, and an epitaxial layer 10 is formed on the surface of the substrate.
[0043] For example, the epitaxial layer is a lightly doped silicon material layer epitaxially grown on the surface of a substrate. The substrate can be N-type polycrystalline silicon, and is not limited thereto.
[0044] S120. Ion implantation is performed on the surface of the epitaxial layer 10 to form an active region 31.
[0045] For example, in a certain region on the surface of the epitaxial layer, ions are implanted from the surface into the interior of the epitaxial layer to form an active region of a certain depth, so that the active region and the epitaxial layer form a PN junction.
[0046] S130. A preset mask is attached to the surface of the epitaxial layer 10, and wet etching is performed for a preset etching time to form multiple voltage divider rings 32 with target widths in the epitaxial layer 10, and the adjacent voltage divider rings 32 have a uniform spacing; wherein, the pattern of the preset mask has a preset width, the preset width is less than the width empirical value, and the preset etching time is greater than the etching time empirical value.
[0047] For example, the voltage divider ring is arranged in a complete ring around the active region. A wet etching method is used to fabricate the voltage divider ring, i.e., a mask is attached to the surface of the epitaxial layer to shield the parts of the epitaxial layer that do not need etching, exposing the surface of the epitaxial layer that needs to be etched according to the pattern on the mask. The wafer with the mask attached is immersed in an etching solution to etch the pattern corresponding to the mask into the epitaxial layer. During the etching process, the etching process can be controlled by designing the pattern size of the mask and combining it with the etching time, based on factors such as the thickness of the oxide layer in the epitaxial layer and the concentration of the etching solution, thereby forming a voltage divider ring of a certain width in the epitaxial layer.
[0048] However, in the process of controlling the etching effect using related technologies, there are many factors that affect the etching effect. For example, the thickness of the oxide layer of the epitaxial layer formed on different wafers may vary, the concentration of the etching solution used may change during use, and the time that different pressure dividing rings in the wafer come into contact with the etching solution may vary during the etching process of gradually immersing the wafer plane vertically downwards into the etching solution. Figure 3 This is a schematic diagram of the etched structure of a power device provided by existing technology. See also... Figure 3 All of the above factors can lead to different etching rates at different etching locations within the same wafer and between different wafers, resulting in excessive side etching. Figure 3 The red dashed box in the figure shows the width of the voltage divider ring 01 formed when it is actually etched at different positions. It can be clearly seen that the width of the voltage divider rings and the spacing between the voltage divider rings are not uniform, which leads to poor voltage withstand uniformity, low yield and high manufacturing cost of the power device.
[0049] In this embodiment of the invention, a preset mask with a preset width pattern is used, wherein the preset width is less than an empirical width value; and the wafer with the preset mask attached is immersed in an etching solution for a preset etching time to obtain multiple voltage divider rings with uniform width and spacing; wherein the preset etching time is greater than an empirical etching time value. It should be noted that the empirical width value is the width value obtained by designing the mask pattern width according to the target width of the voltage divider rings and the control of the etching time in related technologies; the empirical etching time value is the time required to obtain voltage divider rings with the target width when using a mask with the empirical width value for etching. In other words, this embodiment of the invention uses a preset mask with an appropriately reduced empirical width value and increases the etching time compared to the empirical etching time value. For wafers with the same oxide layer thickness as in related technologies, this significantly reduces the etching rate of the oxide layer after the preset etching time in the etching solution, and also significantly reduces the difference in etching rate at different etching positions. Figure 4 This is a schematic diagram of the etching structure of a power device provided in an embodiment of the present invention. See also... Figure 4 The red dashed box indicates the actual width of the voltage divider rings formed by etching at different locations. This allows different etching locations within the same wafer to obtain voltage divider rings with the target width, ensuring uniform spacing between adjacent voltage divider rings. Furthermore, it enables voltage divider rings across different wafers to have a uniform target width and uniform spacing, thereby improving the voltage withstand uniformity of power devices within the same wafer and across different wafers, increasing product yield, and effectively reducing the requirements for the fabrication process.
[0050] S140. Thin the back side of the substrate to form a buffer layer 20.
[0051] For example, the back side of the substrate is thinned and phosphorus impurities are implanted from the back side of the substrate inwards at a high concentration to form a heavily doped buffer layer.
[0052] S150, A back metal layer 30 is formed on the side of the buffer layer 20 away from the substrate.
[0053] For example, metal is deposited on the surface of the buffer layer away from the substrate to form a back metal layer.
[0054] The power device fabrication method provided in this invention involves ion implantation onto the surface of an epitaxial layer to form an active region in a portion of the area. A preset mask is used to perform wet etching on the epitaxial layer, with a preset etching duration throughout the etching process. The preset mask has a pattern of a preset width, which is smaller than an empirical width value, and the preset etching duration is greater than an empirical etching duration value. A buffer layer is then formed on the back side of the substrate through back thinning, and a back metal layer is formed on the side of the buffer layer away from the substrate. This invention, by appropriately reducing the design width of the mask pattern and increasing the etching duration, significantly reduces the etching rate at different locations within the same wafer and at different locations on different wafers, and also significantly reduces the difference in etching rates. This results in voltage divider rings with a uniform target width and uniform spacing between adjacent voltage divider rings, which is beneficial for improving the voltage withstand uniformity of the power device, increasing product yield, and effectively reducing the requirements for the fabrication process.
[0055] Optionally, based on the above embodiments, if the empirical width value is less than the target width, the preset width is the width obtained by reducing the empirical width value by a first preset percentage.
[0056] For example, during the etching process to form the voltage divider ring, the etching solution, upon contact with the exposed epitaxial layer surface of the mask, etches along the depth direction of the epitaxial layer and laterally, resulting in lateral etching exceeding the width of the mask pattern. Therefore, when designing the mask pattern, the width needs to be appropriately reduced based on the target width to determine an empirical value for the mask width. In this embodiment, due to the increased etching time, the width needs to be further reduced by a first preset percentage based on the empirical width value to determine the preset width of the preset mask, ultimately etching to obtain a voltage divider ring with the target width. For example, the range of the first preset percentage includes 20% to 30%; preferably, the preset width of the preset mask is determined by reducing the empirical width value by 30%.
[0057] Optionally, based on the above embodiments, the preset etching time is the time by adding a second preset percentage to the empirical value of the etching time.
[0058] For example, to minimize the etching rate at different locations on the same wafer or when etching rings of different wafer compositions, and to reduce the differences in etching rates, the etching time needs to be extended. The etching time is related to the thickness of the oxide layer in the epitaxial layer, the concentration of the etching solution, etc., and can be set according to actual conditions; no limitation is imposed here. For example, the preset etching time is increased by a second preset percentage compared to an empirical value for etching time. The range of the second preset percentage includes 25% to 35%; preferably, the preset etching time is determined by increasing the empirical value for etching time by 35%.
[0059] One feasible embodiment is that, for an epitaxial layer oxide layer thickness of... Furthermore, to obtain a voltage divider ring with a target width of 11 μm through etching, the fabrication methods can be compared as follows:
[0060] The empirical value for the width of the mask pattern in the related technology design is 7μm, and the empirical value for the etching time is set to 1700s. This can obtain a voltage divider ring with a target width of 11μm. However, the etching process has high requirements and poor stability. The uniformity of the width of the voltage divider ring and the uniformity of the spacing between the voltage divider rings are poor and difficult to control.
[0061] The power device fabrication method provided in this embodiment of the invention has a preset mask pattern width of 3μm and a preset etching time of 2200s, which can also obtain a voltage divider ring with a target width of 11μm. The voltage divider ring has good uniformity in width and spacing, has low requirements for etching process, is easy to control, and has good stability.
[0062] In comparison, the voltage divider ring formed by etching using the power device fabrication method provided in this embodiment of the invention is easier to obtain voltage divider rings with uniform width and spacing, which is beneficial to improving the voltage withstand uniformity of power devices, increasing product yield, and simplifying the fabrication process.
[0063] Optionally, based on the above embodiments, see below. Figure 2 The buffer layer 20 has a first conductivity type, the epitaxial layer 10 has a second conductivity type, the active region 31 has a third conductivity type, and the voltage divider ring 32 has a fourth conductivity type; the first conductivity type is the same as the second conductivity type, the third conductivity type is the same as the fourth conductivity type, and the first conductivity type is different from the third conductivity type.
[0064] Specifically, the epitaxial layer 10 and the buffer layer 20 have the same conductivity type, the active region 31 and the voltage divider ring 32 have the same conductivity type, while the conductivity type of the active region 31 is different from that of the epitaxial layer 10, thereby forming a PN junction. For example, the first and second conductivity types can be N-type, then the third and fourth conductivity types are P-type; or, the first and second conductivity types can also be P-type, then the third and fourth conductivity types are N-type, without limitation.
[0065] Optionally, Figure 5 This is a schematic flowchart of another power device fabrication method provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the structure corresponding to each step in another power device fabrication method provided by an embodiment of the present invention. Based on the above embodiments, see... Figure 5 and Figure 6 The method for fabricating this power device includes:
[0066] S201. A substrate is provided, and an epitaxial layer 10 is formed on the surface of the substrate.
[0067] S202. Ion implantation is performed on the surface of the epitaxial layer 10 to form a cutoff ring region 33; wherein the conductivity type of the cutoff ring region 33 is the same as that of the epitaxial layer 10.
[0068] For example, for high-voltage power devices, a cutoff loop region is necessary. See [link to relevant documentation]. Figure 4 The attached diagram corresponding to step S202 shows that the cutoff ring region is set around the periphery of the voltage divider ring. A certain amount of phosphorus impurities are implanted into the surface of the epitaxial layer to form a cutoff ring region with a certain depth.
[0069] S203. Ion implantation is performed on the surface of the epitaxial layer 10 to form an active region 31.
[0070] S204. A preset mask is attached to the surface of the epitaxial layer 10, and wet etching is performed for a preset etching time to form multiple voltage divider rings 32 with target widths in the epitaxial layer 10, and the adjacent voltage divider rings 32 have a uniform spacing; wherein, the pattern of the preset mask has a preset width, the preset width is less than the empirical value of the width, and the preset etching time is greater than the empirical value of the etching time.
[0071] S205. Thin the back side of the substrate to form a buffer layer 20.
[0072] S206. A back metal layer 30 is formed on the side of the buffer layer 20 away from the substrate.
[0073] Optionally, based on the above embodiments, the formation of the active region in step S205 specifically includes the following steps:
[0074] Ion implantation and high-temperature push-junction are performed on the epitaxial layer to form a well region with a first push-junction depth.
[0075] For example, taking the active region as P-type as an example, a certain dose of boron ions is implanted into the epitaxial layer and high-temperature push junction is performed to form a P-type well region with a first push junction depth inside the epitaxial layer.
[0076] Ion implantation and high-temperature push-junction are performed on the well region to form a heavily doped region with a second push-junction depth; wherein the second push-junction depth is less than the first push-junction depth.
[0077] For example, a large dose of boron ions is implanted into the P-type well region of the epitaxial layer, followed by high-temperature push-junction, to form a heavily doped P-type region with a second push-junction depth within the P-type well region. Since the second push-junction depth is less than the first push-junction depth, the P-type well region surrounds the heavily doped P-type region.
[0078] Optionally, Figure 7This is a schematic diagram of the structure of a power device fabricated using a power device fabrication method according to an embodiment of the present invention. Based on the above embodiments, see... Figure 5 and Figure 7 After forming multiple voltage divider rings of target width in step S206, the following steps are also included:
[0079] S207. An insulating layer 40 is formed on the surface of the epitaxial layer 10; the insulating layer 40 covers the voltage divider ring 32.
[0080] For example, an insulating layer is formed on the surface of the epitaxial layer, such that the insulating layer completely covers the voltage divider ring, thereby insulating the voltage divider ring.
[0081] S208. A field plate structure 50 is formed on the side of the insulating layer 40 away from the epitaxial layer 10; the field plate structure 50 corresponds one-to-one with the voltage dividing ring 32.
[0082] For example, multiple field plate structures are formed using polycrystalline silicon material at positions on the surface of the insulating layer that correspond one-to-one with each voltage divider ring.
[0083] S209. A metal layer 60 is formed on the side of the insulating layer 40 away from the epitaxial layer 10; the metal layer 60 covers the active region 31 and the cutoff ring region 33.
[0084] For example, a metal layer is formed on the surface of the epitaxial layer such that the metal layer covers the active region and the cutoff ring region, and the edge of the metal layer covers the edge of the insulating layer.
[0085] S210, A passivation layer 70 is formed on the side of the field plate structure 50 away from the insulating layer 40; the passivation layer 70 covers the insulating layer 40, the field plate structure 50 and part of the metal layer 60.
[0086] For example, an insulating material is used to form a flat passivation layer on the surface of the field plate structure, such that the passivation layer covers the edges of the insulating layer, the field plate structure and the metal layer, and flattens the surface of the power device.
[0087] This invention also provides a power device. This power device is applicable to the power device fabrication method provided in any of the above embodiments and possesses the same beneficial effects as the power device fabrication method. Specifically, a preset mask is used to perform wet etching on the surface of the epitaxial layer, and etching is performed continuously for a preset etching time. The preset mask pattern has a preset width, which is smaller than an empirical width value, and the preset etching time is greater than an empirical etching time value. By appropriately reducing the design width of the mask pattern and increasing the etching time, the etching rate at different locations on the same wafer and at different locations on different wafers is significantly reduced, and the difference in etching rate is also significantly reduced. This results in voltage divider rings with a uniform target width and uniform spacing between adjacent voltage divider rings, which is beneficial for improving the voltage withstand uniformity of the power device, increasing product yield, and effectively reducing the requirements for the fabrication process.
[0088] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A method of fabricating a power device, the method comprising: The application relates to a power device manufacturing method, comprising the following steps: providing a substrate, and forming an epitaxial layer on the surface of the substrate; carrying out ion implantation on the surface of the epitaxial layer to form an active region; attaching a preset mask to the surface of the epitaxial layer, and continuously carrying out wet etching for a preset etching duration to form a plurality of target-width voltage division rings on the epitaxial layer, and the adjacent voltage division rings have a uniform interval; wherein the pattern of the preset mask has a preset width, the preset width is smaller than a width empirical value, and the preset etching duration is longer than an etching duration empirical value; carrying out back thinning on the substrate to form a buffer layer; forming a back metal layer on the side of the buffer layer away from the substrate.
2. The method of claim 1, wherein The width empirical value is smaller than the target width, and the preset width is a width reduced by a first preset percentage from the width empirical value.
3. The method for fabricating a power device according to claim 2, characterized in that, The first preset percentage ranges from 20% to 30%.
4. The method of claim 1, wherein The preset etching duration is a duration increased by a second preset percentage from the etching duration empirical value.
5. The method of claim 4, wherein The second preset percentage ranges from 25% to 35%.
6. The method of claim 1, wherein The buffer layer has a first conductivity type, the epitaxial layer has a second conductivity type, the active region has a third conductivity type, and the voltage division rings have a fourth conductivity type; the first conductivity type is the same as the second conductivity type, the third conductivity type is the same as the fourth conductivity type, and the first conductivity type is different from the third conductivity type.
7. The method for fabricating a power device according to claim 6, characterized in that, Before the step of forming the active region, the method further comprises the following steps: carrying out ion implantation on the surface of the epitaxial layer to form a cutoff ring region; wherein the conductivity type of the cutoff ring region is the same as that of the epitaxial layer.
8. The method of claim 1, wherein The step of forming the active region comprises the following steps: carrying out ion implantation and high-temperature push junction on the epitaxial layer to form a well region with a first push junction depth; carrying out ion implantation and high-temperature push junction on the well region to form a heavily doped region with a second push junction depth; wherein the second push junction depth is smaller than the first push junction depth.
9. The method for fabricating a power device according to claim 7, characterized in that, After the step of forming the plurality of target-width voltage division rings, the method further comprises the following steps: forming an insulating layer on the surface of the epitaxial layer; the insulating layer covers the voltage division rings; forming a field plate structure on the side of the insulating layer away from the epitaxial layer; the field plate structure corresponds to the voltage division rings one by one; forming a metal layer on the side of the insulating layer away from the epitaxial layer; the metal layer covers the active region and the cutoff ring region; forming a passivation layer on the side of the field plate structure away from the insulating layer; the passivation layer covers the insulating layer, the field plate structure and part of the metal layer.
10. A power device, characterized by The application is suitable for the power device manufacturing method as claimed in any one of claims 1 to 9.