Selective nanobelt removal and thinning for wide band-to-band spaced transistors

Abstract

Described herein are devices, transistor structures, systems, and techniques relating to gate-all-around field effect transistors having selectively removed nanobelts to achieve thicker gate dielectric materials. In forming an alternating stack of semiconductor layers and sacrificial layers, a cladding layer is applied to those semiconductor layers to be removed during nanobelt release. Before the nanobelt is released, the atoms of the cladding layer diffuse only into those semiconductor layers with the cladding body. During the nanobelt release etch, the sacrificial layer and those semiconductor layers having diffused atoms therein are removed while retaining the semiconductor layer without the cladding. By removing the nanobelt, an increased band-to-band spacing is obtained for the application of thicker gate dielectric material in gate-all-around field effect transistors.

Description

BACKGROUND

[0001] Higher performance, lower cost, increasing miniaturization, and greater density of integrated circuits (ICs) are continuing goals of the electronics industry. To keep pace with the increasing speed of improving transistor performance, for example, multiple-gate transistors such as gate-all-around (GAA) or nanoribbon transistors are being deployed. In such devices, a gate structure including a gate dielectric and a gate electrode surrounds a channel region on all sides of each nanoribbon or nanowire of semiconductor material to improve drive current, device control, and other advantages. The nanoribbons are contacted on opposite sides by source and drain structures, which can be epitaxially grown material.

[0002] Currently, these transistors have difficulty with narrow ribbon-to-ribbon spacing, particularly in applications requiring thick gate dielectrics, such as high voltage transistors. High voltage transistors are used in input / output (I / O) circuitry and other circuits of IC dies, and high voltage transistors need to have high on-voltage and need to withstand high breakdown voltage. However, narrow ribbon-to-ribbon spacing in a ribbon field effect transistor (FET) architecture creates limitations for applications requiring thick gate dielectric deposition and / or requiring free use of work function metal thickness for threshold voltage tuning. Prior art for increasing ribbon-to-ribbon spacing includes increasing the space between semiconductor (e.g., silicon) layers in a stack of interleaved semiconductor and sacrificial material (e.g., silicon germanium) during superlattice formation (i.e., increasing the sacrificial material layer thickness), and trimming the thickness of the semiconductor layers after nanoribbon release (i.e., after removal of the sacrificial material layers). However, increasing the space between semiconductor layers disadvantageously increases capacitance and reduces transistor performance, and trimming the thickness of the semiconductor layers, particularly in thick gate dielectric applications using longer nanoribbon lengths, causes physical bending and failure of the nanoribbons, resulting in reduced yield and transistor performance.

[0003] It is with respect to these and other considerations that the present improvements have been needed. As the desirability of deploying multiple-gate transistor structures such as ribbon field effect transistors becomes more widespread, such improvements can become critical. BRIEF DESCRIPTION OF DRAWINGS

[0004] The materials described herein are illustrated by way of example and not limitation in the accompanying drawings. The elements in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the materials. For example, some elements can be exaggerated relative to others in order to more clearly demonstrate certain principles of the materials. Further, in the figures, like reference numerals are used across different views to indicate like elements. In the drawings:

[0005] Figure 1is a flowchart showing an exemplary method for forming an integrated circuit structure having thin gate dielectric gate-all-around transistors integrated with thick gate dielectric gate-all-around transistors enabled by nanobelt removal;

[0006] Figure 2 、 3 , 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and Figure 15 is a cross-sectional side view of an exemplary integrated circuit structure when performing certain fabrication operations of the method of Figure 1 ;

[0007] Figure 16 is a cross-sectional side view of a multi-layer integrated circuit device structure incorporating thin gate dielectric transistor structures and thick gate dielectric transistor structures of the integrated circuit structure of Figure 15 ;

[0008] Figure 17 exemplary systems employing integrated circuit assemblies including integrated circuit dies having thin gate dielectric transistor structures integrated with thick gate dielectric transistor structures; and

[0009] Figure 18 is a functional block diagram of an electronic computing device in accordance with at least some embodiments of the present disclosure. DETAILED DESCRIPTION

[0010] One or more embodiments or implementations will now be described with reference to the attached drawings. While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements can be employed without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and / or arrangements described herein can also be employed in a variety of other systems and applications other than what is described herein.

[0011] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, in which like numerals can refer to like parts throughout the view s and can indicate cor responding or like elements. It is to be understood that other embodiments can be taken without departing from the scope of the claimed subject matter, and that structural and / or logical changes can be made without departing from the scope of the claimed subject matter. It should further be noted that directions and references, for example, up, down, top, bottom, above, below, etc., can be used in the discussion of the drawings and embodiments to facilitate discussion, and are not intended to limit the application of the claimed subject matter. Thus, the following detailed description is not to be taken as limiting the claimed subject matter and the scope thereof is defined by the appended claims and their equivalents.

[0012] In the following description, numerous specific details are set forth. However, it is understood that the application can be practiced without these specific details. In some instances, well-known methods and devices are not described in detail in order not to obscure the application. References can be made throughout this specification to "an embodiment" or "one embodiment," meaning that a particular feature, structure, function, or characteristic is included in at least one embodiment of the present application. Thus, the appearing of the phrases "in an embodiment" or "in one embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the application, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. Moreover, particular features, structures, functions, or characteristics can be combined in any suitable manner in one or more embodiments. For example, a first embodiment can be combined with a second embodiment in any case where the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive of each other.

[0013] As used in the description of the application and the appended claims, the singular forms “a,” “an,” and “the” are intended to include plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and / or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. In this document, the term “majority” indicates not less than 50% of a particular material or ingredient, the term “substantially pure” indicates not less than 99% of a particular material or ingredient, and the term “pure” indicates not less than 99.9% of a particular material or ingredient. Such material percentages are based on atomic percentages, unless otherwise specified. In this document, the term concentration can be used interchangeably with material percentage, and also indicates atomic percentage, unless otherwise specified.

[0014] The terms“coupled” and“connected,” along with their derivatives, can be used herein to describe structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments,“connected” can be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” can be used to indicate that two or more elements are in either direct physical or electrical contact with each other, or that two or more elements are not in direct contact with each other, but yet still cooperate or interact with each other (e.g., as in a causal relationship, as in a

[0015] As used herein, the terms“over,”“under,”“between,”“on,” and the like, refer to a relative positioning between layers or components. For example, a layer disposed over or under another layer can be directly in contact with the other layer, or one or more intervening layers can also be present. Moreover, a layer disposed between two layers can be directly in contact with the two layers, or one or more intervening layers can also be present. In contrast, a first layer“on” a second layer is in direct contact with that second layer. Similarly, unless otherwise explicitly specified, a feature disposed“between” two features can be directly in contact with the adjacent features, or one or more intervening features can also be present. In

[0016] Described herein are devices, transistor structures, integrated circuit dies, apparatuses, systems, and techniques involving selectively removing nanoribbons of a gate-all-around field effect transistor (GAA-FET) using a cladding body and diffusion to modify those semiconductor materials to be removed prior to release of the nanoribbons.

[0017] As discussed, multi-gate transistors, such as gate-all-around (GAA) or nanoribbon transistors, are deployed in advanced integrated circuit devices. As used herein, the terms nanowire, nanoribbon, stacked semiconductor structure, and similar terms are largely used interchangeably to refer to a semiconductor material extending from the source to the drain such that the semiconductor material is enclosed by the gate structure. If multiple such semiconductor materials are used, they are separated by the gate structure and vertically aligned. One or more semiconductor material structures are each coupled to the same source and drain and are vertically separated by the gate structure, which includes the gate dielectric and the gate electrode.

[0018] Therefore, a field-effect transistor or device includes a source, a drain, and one or more semiconductor structures extending between the source and drain. The source and drain are epitaxial relative to the semiconductor structure. As used herein, the term epitaxial or similar terminology indicates that the materials are substantially lattice-matched. The stack of semiconductor structures (e.g., one to eight semiconductor structures) is controlled by the same gate electrode and works together as the channel of the device. As used herein, the term channel region of a semiconductor structure refers to a region of a material layer adjacent to the gate dielectric and the gate electrode that will be controlled by the gate electrode to switch the transistor structure in operation. It is noteworthy that the region of the material layer does not need to be characterized as a channel region, channel material, etc., in operation. The term semiconductor structure is widely used to include nanowires, nanoribbons, and similar terms.

[0019] Current GAA-FETs face challenges in terms of narrow band-to-band spacing, particularly in applications requiring thick gate dielectrics, such as high-voltage transistors. High-voltage transistors are used in power-regulated input / output (I / O) circuit systems and other circuits in IC dies. High-voltage transistors require high turn-on voltages and need to withstand high breakdown voltages. However, the narrow band-to-band spacing in the strip-effect transistor (FET) architecture limits applications requiring thick gate dielectric deposition and / or the ability to freely adjust the threshold voltage using work function metal thickness. In some embodiments, relatively thick gate dielectric GAA-FETs are fabricated by selectively removing nanoribbons by diffusing atoms from the cladding into the semiconductor material during nanoribbon release. For example, a germanium cladding can be formed on those silicon semiconductor layers to be removed, while the silicon semiconductor layers to be retained do not contain germanium. The cladding and uncladding layers are interleaved with the silicon-germanium sacrificial layers removed during nanoribbon release.

[0020] In some embodiments, a relatively thick gate dielectric layer transistor is integrated with a relatively thin gate dielectric layer transistor. As used herein, the terms relatively thick and relatively thin, or similarly thick and similarly thin, are relative to other similar features across the transistor. In some embodiments, the thick layer is at least 50% thicker than the thin layer, at least twice the thickness of the thin layer, at least three times the thickness of the thin layer, etc. Furthermore, the thick gate dielectric layer is achieved through nanoribbon removal, and therefore the thick gate dielectric layer transistor has fewer nanoribbons than the thin gate dielectric layer transistor. Notably, each nanoribbon in the thick gate dielectric layer transistor is coplanar with the nanoribbons in the thin gate dielectric layer transistor. However, some nanoribbons in the thin gate dielectric layer transistor do not have coplanar nanoribbons in the thick gate dielectric layer transistor because they are removed during nanoribbon release.

[0021] Figure 1 This is a flowchart illustrating an exemplary method 100 for forming an integrated circuit structure arranged according to at least some embodiments of the present disclosure, the integrated circuit structure having a thin-gate dielectric full-around gate transistor integrated with a thick-gate dielectric full-around gate transistor achieved by nanoribbon removal. For example, method 100 can be implemented to fabricate integrated circuit (IC) structures 1400, 1500, multilayer IC device structures 1600, or any other transistor or IC structure discussed herein. In the illustrated embodiments, method 100 may include one or more operations as shown in operations 101-112. However, embodiments herein may include additional operations, certain operations may be omitted, or operations may not be performed in the provided order.

[0022] Figure 2 , 3 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 and Figure 15 This is a cross-sectional side view of an example integrated circuit structure arranged according to at least some embodiments of the present disclosure when performing a specific manufacturing operation of method 100. Figure 16 It is incorporated into the structure of multilayer integrated circuit devices. Figure 15 A cross-sectional side view of an integrated circuit structure. Although it is relative to... Figure 15 The integrated circuit structure shown herein can be deployed in any transistor structure discussed herein. Figure 16 In the context of multilayer integrated circuit device structures.

[0023] Processing begins at operation 101, where a workpiece, such as a substrate, is received for processing. The substrate may include any suitable substrate as discussed herein, such as a silicon wafer. In some embodiments, the substrate includes underlying devices or electrical interconnects. Processing continues at operation 102, where alternating layers of semiconductor material layers and sacrificial layers are formed over the workpiece or substrate, such that an cladding is applied to those semiconductor material layers that will later be selectively removed in the processing.

[0024] For example, the techniques discussed in this paper can utilize high germanium (Ge) etching selectivity against silicon (Si) during nanoribbon or nanowire release. During superlattice deposition, a cladding layer with high or even higher germanium concentrations is deposited on those silicon semiconductor material layers to be removed. The silicon nanoribbons or nanowires can be selectively controlled by controlling the sequence of nanoribbon or nanowire release and germanium diffusion annealing. Such techniques offer flexibility in controlling the space between Si nanoribbons. Transistor structures or devices with different band spaces can be fabricated in the same integration process, enabling the application of thick-gate devices and threshold voltage regulation using work function metal thickness.

[0025] Figure 2 This is a cross-sectional side view of an example IC structure 200 after an alternating stack 205 of semiconductor material layers 202 and sacrificial material layers 203 grown on a substrate 201, wherein selected semiconductor material layers in the semiconductor material layers 202 have a cladding layer 204 on each of their sides. The substrate 201 may comprise any suitable one or more materials, and in some embodiments, the substrate 201 comprises one or more materials having the same or similar composition relative to the semiconductor material layers 202. In some embodiments, the substrate 201 and semiconductor material layers 202 comprise group IV materials (e.g., silicon). In some embodiments, the substrate 201 and semiconductor material layers 202 comprise substantially single-crystal materials. In some embodiments, the substrate 201 comprises, for example, a semiconductor-on-insulator (SOI) substrate and / or a buried insulating layer (e.g., SiO2) isolating an insulating region.

[0026] A thin-gate dielectric transistor structure 220 is fabricated in a first region of substrate 201, and a thick-gate dielectric transistor structure 210 is fabricated in a second region of substrate 201. For example, the thin-gate dielectric transistor structure 220 and the thick-gate dielectric transistor structure 210 are integrated into an IC die. Besides the difference in dielectric material thickness, the thin-gate dielectric transistor structure 220 has more nanoribbons than the thick-gate dielectric transistor structure 210 due to the removal of those nanoribbons coated by the cladding layer 204, as discussed further herein. Furthermore, different dielectric materials and / or electrode materials can be used.

[0027] Semiconductor material layers 202 may include any number of layers, such as three, four, five, six, seven, eight, or more, for forming semiconductor structures, channel semiconductors, nanoribbons, or nanowires on the substrate 201, typically deploying an even number of semiconductor material layers 202. Although shown as three semiconductor material layers 202 with cladding layers 204 on each surface of two of them (top and bottom), any number of semiconductor material layers 202 and cladding combinations can be used. In some embodiments, for example, every other semiconductor material layer 202 has a cladding layer 204. Thus, the process in question can leave any number of remaining nanoribbons in the thick gate dielectric transistor structure 210. In the example shown, a single nanoribbon is retained. However, multiple nanoribbons (i.e., a stack of vertically aligned nanoribbons) can be retained. In some embodiments, every other nanoribbon is removed, such that the thin gate dielectric transistor structure 220 has more than twice the number of nanoribbons as the thick gate dielectric transistor structure 210.

[0028] Semiconductor material layer 202 (with or without cladding layer 204) is separated from and interleaved with sacrificial material layer 203. During the first nanoribbon release, sacrificial material layer 203 and cladding layer 204 are removed from thin gate dielectric transistor structure 220. Furthermore, after annealing, during subsequent nanoribbon release, sacrificial material layer 203, cladding layer 204, and those semiconductor material layers 202 having cladding layer 204 (due to diffusion into semiconductor material layer 202) are removed from thick gate dielectric transistor structure 210.

[0029] In some embodiments, the semiconductor material layer 202 is substantially pure silicon or pure silicon, such as substantially pure monocrystalline silicon or pure monocrystalline silicon; the sacrificial material layer 203 is silicon-germanium, such as monocrystalline silicon-germanium; and the cladding layer 204 is substantially pure germanium or pure germanium, such as substantially pure monocrystalline germanium or pure monocrystalline germanium. However, other material systems may be used. Any suitable one or more techniques, such as epitaxial growth techniques, may be used to form the staggered stack 205. The semiconductor material layer 202, the sacrificial material layer 203, and the cladding layer 204 may have any suitable thickness (i.e., measured in the z-axis), for example, a thickness in the range of about 4 nm to 12 nm.

[0030] return Figure 1The process continues at operation 103, where fins or fin structures are patterned from the staggered stacks formed at operation 102, and then nanoribbon structures are patterned from the fins. Any suitable one or more techniques can be used to pattern the fins or fin structures. In some embodiments, a mask structure is formed using photolithography etching, such that the mask defines rows of fins or fin structures, and subsequent etching forms the fins or fin structures. Orthogonal dummy gates and gate spacers can then be patterned over the fins. Etching then forms nanoribbons or channel structures from the fins.

[0031] Figure 3 This is a cross-sectional side view of an example IC structure 300, similar to IC structure 200, after the fins 305 have been patterned from the staggered stack 205 and after the dummy gate structure 302 and spacer 301 have been formed. In some embodiments, the staggered stack 205 is first etched using photolithography and etching techniques to define fins extending in the x-axis. The dummy gate structure 302 extending in the y-axis can then be formed and patterned (i.e., by volume deposition and patterning using photolithography and etching), and the spacer 301 can then be formed using conformal deposition and anisotropic etching. The dummy gate structure 302 can be any suitable material such as polysilicon. The spacer 301 can be any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0032] Figure 4This is a cross-sectional side view of an example IC structure 400, similar to IC structure 300, after the fins 305 are etched downwards to form a patterned stack 415 including patterned semiconductor layers 401a-f, a patterned sacrificial layer 431, and a patterned overlay layer 432. As discussed below, all patterned semiconductor layers 401a, 401b, 40c will be released to form a stack of vertically aligned semiconductor structures 411 for a thin gate dielectric transistor structure 220. However, only a portion of the stack of vertically aligned semiconductor structures 412 will be released to form a nanoribbon or a stack of vertically aligned nanoribbons for a thick gate dielectric transistor structure 210. Also as shown, the individual semiconductor structures in the stacks of vertically aligned semiconductor structures 411 and 412 are coplanar, as shown with respect to exemplary planes 421, 422. For example, patterned semiconductor layers 401a and 401d are coplanar on plane 421, patterned semiconductor layers 401b and 401e are coplanar on plane 422, patterned semiconductor layers 401c and 401f are coplanar on an unmarked plane, and so on. As used herein, coplanarity indicates that at least a portion of each component is aligned in the same plane. In some embodiments, the centerlines of each of the patterned semiconductor layers 401a, 401d, 401b, 401e, etc., are coplanar. In some embodiments, a recess 418 is etched in the substrate 201 during the etching of fin 305.

[0033] return Figure 1 The process continues at operation 104, where a recess etching is performed to recess the sacrificial and overlay materials. The recesses are then backfilled to form spacers of dielectric material. The recess etching can be performed using any suitable technique or technique (e.g., selective etching that selectively etches the germanium content of the sacrificial and overlay materials relative to the pure silicon content of the semiconductor layer). The spacers of dielectric material can then be formed using any suitable technique or technique, such as material deposition followed by anisotropic etching. The spacers can be any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, with silicon oxynitride being particularly advantageous. For example, the spacers can comprise silicon, oxygen, and nitrogen.

[0034] Figure 5This is a cross-sectional side view of an example IC structure 500, similar to IC structure 400, after a portion of the patterned sacrificial layer 431 and patterned cladding layer 432 have been patterned in recess etch 501. As shown, due to etching selectivity, the patterned cladding layer 432, with a high germanium content or pure germanium content, is etched faster than the patterned sacrificial layer 431. This is evident in the case where the recess 502 of the patterned cladding layer 432 is deeper than the recess 503 of the patterned sacrificial layer 431. As discussed further below, the resulting dielectric spacers on and adjacent to the patterned sacrificial layer 431 and patterned cladding layer 432 thus have a larger width on those patterned semiconductor layers 401a, 401c, 401d, 401f with claddings compared to those patterned semiconductor layers 401b, 401e without claddings.

[0035] Figure 6 This is a cross-sectional side view of an example IC structure 600, similar to IC structure 500, after the dielectric spacer 601 has been formed in the recessed region. The dielectric spacer 601 can then be formed using material deposition and anisotropic etching techniques, and the dielectric spacer 601 can be any suitable dielectric material, such as silicon oxide (i.e., comprising silicon and oxygen), silicon nitride (i.e., comprising silicon and nitrogen), or silicon oxynitride (i.e., comprising silicon, oxygen, and nitrogen). As shown, the dielectric spacers 601a, 601b, 601c, and 601d each have a cross-sectional shape with a larger width on and near the patterned semiconductor layers 401a, 401c, 401d, and 401f having a patterned cladding layer 432, and a smaller width on the patterned semiconductor layers 401b and 401e without a cladding layer. In some embodiments, the larger width is at least 10%, at least 20%, at least 25%, at least 40%, or more greater than the smaller width.

[0036] return Figure 1 The process continues at operation 105, where epitaxial source and drain materials are grown or deposited via exposed ends of staggered semiconductor material layers. In some embodiments, an epitaxial nucleation layer may be deposited followed by bulk deposition. In some embodiments, the epitaxial nucleation layer and the epitaxial material are deposited in the same processing chamber using different deposition parameters. The source and drain materials can be any suitable materials, such as doped silicon, doped silicon-germanium, etc. The epitaxial source and drain materials can be deposited using any suitable one or more techniques, such as chemical vapor deposition (CVD) including in-situ deposition of dopant materials.

[0037] Figure 7This is a cross-sectional side view of an example IC structure 700, similar to IC structure 600, after epitaxial growth of source and drain structures 701, 702. The source and drain structures 701, 702 can be a single material (as shown), or they can include an epitaxial nucleation layer and an external epitaxial material. The source and drain structures 701, 702 can be fabricated using CVD or other epitaxial deposition techniques. The source and drain structures 701, 702 are epitaxial with respect to the exposed ends of the patterned semiconductor layer 401, and the source and drain structures 701, 702 can be doped epitaxial silicon or doped epitaxial silicon and germanium (SiGe). In some embodiments, the dopant is boron or gallium for PMOS devices and phosphorus or arsenic for NMOS devices, but other suitable dopant can be used.

[0038] return Figure 1 The process continues at operation 106, where a selective etching technique (e.g., wet etching) is used in the thin gate dielectric transistor region to remove the sacrificial material layer and cladding to release the nanoribbon or semiconductor structure. For example, the nanoribbon is released by utilizing the etch selectivity between the silicon semiconductor material and the silicon-germanium sacrificial material layer and germanium cladding, which is due to the different materials deployed (i.e., etching germanium-containing or germanium-rich materials while retaining pure or substantially pure silicon). In some embodiments, photoresist or other masking materials are used to mask the thick gate dielectric transistor region during this process. In some embodiments, selective etching removes the sacrificial material layer and cladding to release the nanoribbon corresponding to each semiconductor material layer grown in operation 102 (i.e., those semiconductor material layers with or without cladding). The released nanoribbon is structurally supported by the source and drain structures formed at operation 105.

[0039] Figure 8 This is a cross-sectional side view of an example IC structure 800, similar to IC structure 700, after forming dielectric layer 801, patterning mask layer 802, and removing dummy gate structure 302 of thin gate dielectric transistor structure 220 to expose patterned sacrificial layer 431 and patterned cladding layer 432. Dielectric layer 801 can be formed using any suitable technique or one or more, such as bulk deposition followed by planarization, and can be any suitable dielectric material, such as silicon oxide. Patterned mask layer 802 can be any suitable material that will block areas of thick gate dielectric transistor structure 210 during processing, such as photoresist, hard mask, or similar materials. The dummy gate structure 302 of thin gate dielectric transistor structure 220 can then be removed using, for example, selective etching techniques.

[0040] Figure 9This is a cross-sectional side view of an example IC structure 900, similar to IC structure 800, after the patterned sacrificial layer 431 and patterned cladding layer 432 of the thin gate dielectric transistor structure 220 have been removed to form an opening 902. Furthermore, this process releases a stack of vertically aligned semiconductor structures 411 anchored by source and drain structures 701 and dielectric spacers 601 (e.g., dielectric spacers 601a, 601b). The patterned sacrificial layer 431 and patterned cladding layer 432 are removed using a selective etching technique. Notably, this etching process is highly selective for germanium content, and the patterned sacrificial layer 431 (e.g., silicon-germanium) and patterned cladding layer 432 (e.g., germanium) are removed, while semiconductor structures 901 such as 901a, 901b, 901c are retained and released as nanowires, nanoribbons, or semiconductor structures 901 of the resulting transistor device. For example, the semiconductor structure 901 has the same number of semiconductor structures 901 as the number of semiconductor material layers 202 formed at operation 102.

[0041] return Figure 1 The process continues at operation 107, where annealing is performed to diffuse atoms (e.g., germanium atoms) from the cladding layer formed at operation 102 into the semiconductor layer on which the cladding layer is applied, only in thick dielectric transistor structures where the cladding remains. For example, the cladding layer in a thin dielectric transistor structure is removed at operation 106, and the remaining cladding layer can be used to selectively remove the semiconductor layer in a thick dielectric transistor structure. The annealing process can be performed using any suitable one or more techniques, such as rapid thermal annealing at any suitable temperature and duration, to diffuse germanium atoms into the semiconductor layer to the level required for removal of germanium atoms in subsequent etching processes.

[0042] Figure 10 It is from the remaining patterned covering layer 432 (see Figure 9The diffusion process is illustrated in the cross-sectional side view of an exemplary IC structure 1000, similar to IC structure 900, after diffusion into those patterned semiconductor layers (e.g., patterned semiconductor layers 401d, 401f, which still have patterned cladding layers 432 to form the diffused material structure 1001). The diffused material structure 1001 is silicon-germanium and will be removed by a subsequent etching process. As shown, in some embodiments, the ends of the patterned semiconductor layers 401d, 401f do not include germanium diffusion and may be retained after nanoribbon release. However, as shown in the following figures, in some embodiments, the diffusion process in question forms the diffused material structure 1001 throughout the patterned semiconductor layers 401d, 401f, and the entire patterned semiconductor layers 401d, 401f are removed during a selective etching process for nanowire or nanoribbon release.

[0043] return Figure 1 The process continues at operation 108, where a selective etching technique (e.g., wet etching) is used in the thick gate dielectric transistor region to remove the sacrificial material layer and the diffusion region (formed at operation 107) to release nanoribbons or semiconductor structures. In the context of operation 108, the etch selectivity between the silicon semiconductor material and the silicon-germanium sacrificial material layer, as well as the silicon-germanium diffusion regions of those semiconductor material layers having cladding thereon, is used to release the remaining semiconductor structure (e.g., substantially pure silicon or pure silicon) that does not contain germanium. In some embodiments, a thin gate dielectric transistor region is masked during this process using a photoresist or similar material. In some embodiments, selective etching removes the sacrificial material layer and the previously clad semiconductor structure to release nanoribbons corresponding to each semiconductor material layer without cladding grown at operation 102.

[0044] Figure 11 The mask layer 1103 is patterned, the 302-thick gate dielectric transistor structure 210 is removed, and the patterned sacrificial layer 431 and diffusion material structure 1001 (including the end of the semiconductor layer, see below) of the thick gate dielectric transistor structure 210 are removed. Figure 10The image shows a cross-sectional side view of an example IC structure 1100, similar to IC structure 1000, after the opening 1102 is formed. This process releases one or more vertically aligned semiconductor structures 1111 (i.e., stacks), which are anchored by source and drain structures 702 and dielectric spacers 601 (e.g., dielectric spacers 601c, 601d). Although shown relative to one semiconductor structure 1101e, the stacks of vertically aligned semiconductor structures 1111 can include any number of semiconductor structures 1101, such as two, three, four, or more. In some embodiments, the stacks of vertically aligned semiconductor structures 1111 have half the semiconductor structure of a stack of vertically aligned semiconductor structures 411.

[0045] The dummy gate structure 302 of the thick gate dielectric transistor structure 210 can be removed using any suitable technique or one or more techniques such as selective etching. The patterned sacrificial layer 431 and the diffused material structure 1001 are then removed using selective etching. As discussed, this etching process is highly selective for germanium content, and the patterned sacrificial layer 431 (e.g., silicon-germanium) and the diffused material structure 1001 (e.g., silicon-germanium due to germanium diffusion) are removed, while semiconductor structures 1101, such as 1101e, are retained and released as nanowires, nanoribbons, or semiconductor structures 1101 of the resulting transistor device.

[0046] As discussed, the technique described herein utilizes high Ge-to-Si etch selectivity during nanowire or nanoribbon release, such as a dry etching process with high etch rates for Ge and SiGe and very low etch rates for Si. In this paper, an additional layer with a high Ge concentration is inserted next to the Si layer to be removed during nanowire or nanoribbon release. Ge is then diffused into the adjacent Si ribbon using a Ge cladding layer to facilitate etching of the ribbon during the nanowire or nanoribbon release process. By controlling the sequence of Ge diffusion annealing and nanowire or nanoribbon release steps, control over the removal of the Ge-clad or unclad Si ribbon can be utilized to form transistors with different numbers of nanowires or nanoribbons and different gate dielectric thicknesses within IC devices for different applications.

[0047] return Figure 1The process continues at operation 109, wherein a gate structure (comprising a relatively thick gate dielectric material on at least a portion of a semiconductor structure (i.e., nanoribbon)) and a gate electrode (e.g., gate metal) on the gate dielectric material are formed in the thick dielectric material transistor structure. Any suitable one or more techniques can be used to form the gate structure. In some embodiments, a conformal deposition process is used to form the gate dielectric material, and the gate electrode is formed by conformal deposition of a work function metal followed by metal filling. However, other fabrication techniques can be used.

[0048] Figure 12 This is a cross-sectional side view of an example IC structure 1200, similar to IC structure 1100, after forming a gate structure 1201 including a gate dielectric layer 1203 and a gate electrode 1202. The gate structure 1201 can be formed by conformally depositing the gate dielectric layer 1203, then conformally depositing a work function metal of the gate electrode 1202, and then filling the remaining portion of the gate electrode 1202 with the metal. The formation of the gate structure 1201 may include the formation of a dielectric material 1207. As shown, in some embodiments, the gate dielectric layer 1203 includes a portion 1204 located on the dielectric spacer 601 and extending to contact the source and drain structures 702. This portion 1204 of the gate dielectric layer 1203 is due to... Figure 11 The etching under discussion.

[0049] In some embodiments, removing the semiconductor structure allows the thicker gate dielectric layer 1203 to have a thickness t1 on a semiconductor structure 1101 such as 1101e. In some embodiments, the thickness t1 is not less than 3 nm. In some embodiments, the thickness t1 is not less than 4 nm. In some embodiments, the thickness t1 is not less than 5 nm. Other thicknesses may be used. In some embodiments, the gate dielectric layer 1203 is or includes aluminum oxide, hafnium oxide, zirconium oxide, titanium silicon oxide, hafnium silicon oxide, silicon oxide, or silicon nitride. For example, the gate dielectric layer 1203 may include aluminum and oxygen; hafnium and oxygen; zirconium and oxygen; titanium, silicon, and oxygen; hafnium, silicon, and oxygen; silicon and oxygen; or silicon and nitrogen. In some embodiments, the gate electrode 1202 includes a work function layer of platinum, nickel, titanium nitride, or tantalum nitride and a filler metal such as tungsten. However, other material systems may be used.

[0050] In some embodiments, compared to the thin gate dielectric transistor structure 220, the thick gate dielectric transistor structure 210 utilizes a different gate dielectric layer 1203, in addition to having a thicker gate dielectric layer 1203 and fewer semiconductor structures 1101. In some embodiments, the gate dielectric layer 1203 is silicon oxide (i.e., comprising silicon and oxygen), and the gate dielectric layer of the thin gate dielectric transistor structure 220 is not silicon oxide, but rather a high-k gate dielectric material.

[0051] As shown in the figure, the thick gate dielectric transistor structure 210 includes at least one semiconductor structure 1101e laterally located between and coupled to the source and drain structures 702. The gate structure 1201 includes a gate dielectric layer 1203 (e.g., a gate dielectric) located on and surrounding the channel region of the semiconductor structure 1101e, and a gate electrode 1202 (e.g., a gate metal) surrounding the gate dielectric layer 1203. Dielectric spacers 601, such as dielectric spacers 601c and 601d, are laterally located between one or both of the source and drain structures 702 and the gate structure 1201, and on one or both of the source and drain structures 702 and the gate structure 1201. As shown with respect to illustration 1210, the dielectric spacers 601 are adjacent to the channel region 1211 on the semiconductor structure 1101e (i.e., the portion of the semiconductor structure 1101e adjacent to and controlled by the gate structure 1201). The dielectric spacer 601 has a first width w1 and a second width w2, each width extending between the gate structure 1201 and the source or drain structure 702, such that the first width w1 is adjacent to the semiconductor structure 1101e, and the second width w2 is distant from the semiconductor structure 1101e and is at least ten percent larger than the first width w1. As discussed, due to the etched patterned cladding layer 432 (see...) Figure 4 The second width w2 is greater than the first width w1. In some embodiments, the second width w2 is at least 20% larger than the first width w1. In some embodiments, the second width w2 is at least 25% larger than the first width w1. In some embodiments, the second width w2 is at least 50% larger than the first width w1. The first width w1 can be any suitable width, such as not less than 1 nm, not less than 2 nm, not less than 5 nm, etc.

[0052] As also shown, a portion 1204 of the gate dielectric layer 1203 is on the dielectric spacer 601 and contacts the source or drain structure 702. In some embodiments, the dielectric spacer 601 is silicon oxynitride (i.e., comprising silicon, oxygen, and nitrogen), and the gate dielectric layer 1203 is silicon oxide (i.e., comprising silicon and oxygen). However, the gate dielectric layer 1203 can be any material discussed above.

[0053] return Figure 1The process continues at operation 110, wherein a gate structure (including a relatively thin gate dielectric material on at least a portion of a semiconductor structure (i.e., nanoribbon) and a gate electrode (e.g., gate metal) on the gate dielectric material) is formed in a thin dielectric material transistor structure. In some embodiments, the gate dielectric material is formed using a conformal deposition process, and the gate electrode is formed by conformally depositing a work function metal followed by metal filling. However, other fabrication techniques may be used. In some embodiments, a thick dielectric material transistor structure is masked during such a process.

[0054] Figure 13 This is a cross-sectional side view of an example IC structure 1300, similar to IC structure 1200, after patterning the mask layer 1305 and forming the gate structure 1301, which includes a gate dielectric layer 1303 and a gate electrode 1302. The gate structure 1301 can be formed by conformally depositing the gate dielectric layer 1303, conformally depositing the work function metal of the gate electrode 1302, and filling the remaining portion of the gate electrode 1302 with metal. The formation of the gate structure 1301 may include the formation of a dielectric material 1304.

[0055] As discussed, the semiconductor structure is removed to implement a thicker gate dielectric layer 1203 for the thick gate dielectric transistor structure 210. In contrast, the gate dielectric layer 1303 of the thin gate dielectric transistor structure 220 has a smaller thickness t2 relative to the thickness t1 of the gate dielectric layer 1203 of the thick gate dielectric transistor structure 210. In some embodiments, the thickness t2 is no greater than half the thickness t1. In some embodiments, the thickness t2 is no greater than 75% of the thickness t1. In some embodiments, the thickness t2 is no greater than 40% of the thickness t1. In some embodiments, the thickness t2 is no greater than 25% of the thickness t1. The thickness t2 can be any suitable thickness for each semiconductor structure 901, for example, a thickness not exceeding 3 nm, 2 nm, or 1 nm. Other thicknesses can be used. In some embodiments, the gate dielectric layer 1303 is or includes aluminum oxide, hafnium oxide, zirconium oxide, titanium silicon oxide, hafnium silicon oxide, silicon oxide, or silicon nitride. For example, gate dielectric layer 1303 may comprise aluminum and oxygen; hafnium and oxygen; zirconium and oxygen; titanium, silicon and oxygen; hafnium, silicon and oxygen; silicon and oxygen; or silicon and nitrogen. In some embodiments, gate electrode 1302 comprises a work function layer of platinum, nickel, titanium nitride, or tantalum nitride and a filler metal such as tungsten. However, other material systems may be used. As discussed, in some embodiments, gate dielectric layer 1203 and gate dielectric layer 1303 are different materials. In some embodiments, gate dielectric layer 1203 is silicon oxide (i.e., comprising silicon and oxygen), and gate dielectric layer 1303 is one of aluminum oxide (i.e., comprising aluminum and oxygen), hafnium oxide (i.e., comprising hafnium and oxygen), zirconium oxide (i.e., comprising zirconium and oxygen), titanium silicon oxide (i.e., comprising titanium, silicon, and oxygen), or hafnium silicon oxide (i.e., comprising hafnium, silicon, and oxygen).

[0056] As shown, the thin gate dielectric transistor structure 220 includes any number of semiconductor structures 901 laterally located between and coupled to the source and drain structures 701. The gate structure 1301 includes a gate dielectric layer 1303 (e.g., a gate dielectric) located on and surrounding the channel region of each semiconductor structure 901, and a gate electrode 1302 (e.g., a gate metal) surrounding the gate dielectric layer 1303. Dielectric spacers 601, such as dielectric spacers 601a and 601b, are laterally located between one or both of the source and drain structures 701 and the gate structure 1301, and on one or both of the source and drain structures 701 and the gate structure 1301. As shown with respect to illustration 1310, the dielectric spacer 601 is adjacent to the channel region 1311 on the semiconductor structure 901c (i.e., the portion of the semiconductor structure 901c adjacent to and controlled by the gate structure 1301). As previously described, the dielectric spacer 601 may have a first width w1 and a second width w2, each width extending between the gate structure 1301 and the source or drain structure 701, such that the first width w1 is adjacent to the semiconductor structure 901c (i.e., the semiconductor structure with an cladding), and the second width w2 is away from the semiconductor structure 901c and adjacent to the semiconductor structure 901b (i.e., the semiconductor structure without an cladding). The second width w2 is greater than the first width w1, and the widths w1 and w2 may have any of the values ​​or relationships discussed above.

[0057] return Figure 1 The process continues at operation 111, where front-side metal contacts and metallization are formed over the transistor structure. Any suitable technique or one or more can be used to form such contacts, such as patterning to form openings in the dielectric material, bulk metal deposition, and CMP processing to remove the overlay. For example, front-side contacts can be formed for any one or more of the three terminals (source, drain, and gate) of the transistor structure being manufactured. The front-side contacts are then interconnected via a metallization layer over the front-side contacts. In some embodiments, the gate and drain of the transistor structure are contacted from the front side to provide signal transmission, and the source of the transistor structure is contacted from the back side to provide power delivery. However, any interconnection route can be used. In some embodiments, only front-side contacts and metallization are used.

[0058] Figure 14This is a cross-sectional side view of an example IC structure 1400, similar to IC structure 1300, after the formation of the front source contact 1401, front gate contact 1402, and front drain contact 1403 of the thin gate dielectric transistor structure 220, and the front source contact 1404, front gate contact 1405, and front drain contact 1406 of the thick gate dielectric transistor structure 210. The front contacts 1401-1406 can be formed using operations known in the art, such as photolithographic patterning of openings or vias, and via metal filling and optional planarization. Such components can include any suitable material. For example, the front contacts 1401-1406 can include a substrate material such as titanium nitride and a fill metal such as tungsten. However, other material systems can be used. On top of IC structure 1400, any suitable one or more techniques such as dual damascene technology, single damascene technology, subtractive metallization patterning technology, etc., can be used to form a front metallization layer. The following sections discuss… Figure 16 The front metallization layer is shown. It is worth noting that the front metallization layer can be formed before the IC structure 1400 is mounted to the carrier wafer and the back-side processing described below is performed.

[0059] return Figure 1 The process continues at operation 112, where optional back-side metal contacts for the transistor structure are formed, and the workpiece is further processed and output. In some embodiments, the back-side metal contacts are fabricated for the source structure of the transistor structure. The back-side metal contacts can be fabricated using any suitable one or more techniques known in the art (e.g., patterning, metal deposition, and CMP processing). The back-side contacts are then interconnected via a metallization layer over the back-side contacts. In some embodiments, the gate and drain of the transistor structure are contacted from the front side to provide signal transmission, and the source of the transistor structure is contacted from the back side to provide power delivery. However, any interconnect route can be used. Subsequently, a metallization layer is formed over the back-side contacts, additional manufacturing processes can be completed, and the resulting structure can be output. Such processing can include back-end processing, dicing, packaging, assembly, etc. The resulting device (e.g., an integrated circuit die) can then be implemented in any device of suitable form factor, such as laptops, netbooks, notebooks, ultrabooks, smartphones, tablets, personal digital assistants, ultra-mobile PCs, mobile phones, desktop computers, servers, printers, scanners, monitors, set-top boxes, entertainment control units, digital cameras, portable music players, digital video recorders, etc.

[0060] Figure 15This is a cross-sectional side view of an example IC structure 1500, similar to IC structure 1400, after the formation of back-side source contacts 1501, 1502 embedded in dielectric layer 1503. The back-side source contacts 1501, 1502 can be formed using any suitable technique or combination of methods, such as patterning openings in dielectric layer 1503, depositing metal, and planarization operations. In some embodiments, a back-side exposure process is used to remove substrate 201, and dielectric layer 1503 is formed using bulk deposition techniques. In some embodiments, back-side source contacts 1501, 1502 comprise a substrate material such as titanium nitride and a filler metal such as tungsten. However, other materials can be used. As discussed, back-side source contacts 1501, 1502 can provide power delivery for thin-gate dielectric transistor structure 220 and thick-gate dielectric transistor structure 210.

[0061] As discussed, the process continues, wherein optional back-side metallization is formed over the back-side contacts, which can complete additional manufacturing processes and output the resulting structure.

[0062] Figure 16 This is a cross-sectional side view of a multilayer integrated circuit device structure 1600 incorporating a thin-gate dielectric transistor structure 220 and a thick-gate dielectric transistor structure 210 into an integrated circuit structure 1500 according to at least some embodiments of the present disclosure. Although relative to... Figure 15 The IC structure 1500 is shown and discussed, but any IC structure discussed herein (e.g., Figure 14 The IC structure 1400 can be deployed within the context of the multilayer integrated circuit device structure 1600. As shown, the multilayer integrated circuit device structure 1600 is incorporated into the integrated circuit (IC) die 1607, such that the multilayer integrated circuit device structure 1600 includes a front metallization layer 1601 (or a front interconnect layer) and a back metallization layer 1602 (or a back interconnect layer). The front metallization layer 1601 and the back metallization layer 1602 can be formed using any suitable technique or one or more techniques such as dual damascene, single damascene, subtractive metallization patterning, etc.

[0063] For example, interconnectivity, signal transmission, power delivery, etc., can be provided through the front metallization layer 1601. Adjacent metallization layers (e.g., metallization interconnect 1610) are interconnected vias (e.g., vias 1603), which can be characterized as part of a metallization layer or between metallization layers. As shown, in some embodiments, the front metallization layer 1601 is formed on and adjacent to the thin gate dielectric transistor structure 220 and the thick gate dielectric transistor structure 210. In the example shown, the front metallization layer 1601 includes M0, V0, M1, M2 / V1, M3 / V2, and M4 / V3. However, the front metallization layer 1601 can include any number of metallization layers, such as six, eight, or more metallization layers.

[0064] Similarly, the back metallization layer 1602 can be used for interconnectivity, signal transmission, power delivery, and any other suitable electrical connections. In some embodiments, the front metallization layer 1601 is dedicated to signal transmission, and the back metallization layer 1602 is dedicated to power delivery. However, any interconnect architecture can be used. In the example shown, package-level interconnects 1611 are disposed on or above the device back side as bumps above the passivation layer 1605. However, any suitable interconnect structure such as bonding pads, solder bumps, etc., can be used to provide package-level interconnects 1611. As shown, in some embodiments, the back metallization layer 1602 is formed such that a device layer 1604 including a thin gate dielectric transistor structure 220 and a thick gate dielectric transistor structure 210 is located between the front metallization layer 1601 and the back metallization layer 1602. In the example shown, the back metallization layer 1602 includes BMO, BM1, and BM2 with intermediate via layers. However, the back metallization layer 1602 may include any number of metallization layers, such as three, four or more metallization layers.

[0065] In some embodiments, a thin-gate dielectric transistor structure 220 and a thick-gate dielectric transistor structure 210 are deployed in a monolithic integrated circuit (IC) die 1607, which includes an all-around gate field-effect transistor structure (e.g., GAA-FET) having any of the components and characteristics discussed herein. As shown, a power supply 1606 may be coupled to the IC die 1607 such that the power supply 1606 may include a battery, a voltage converter, a power supply circuit system, etc.

[0066] Figure 17Exemplary systems employing integrated circuit assemblies including an integrated circuit die having a thin gate dielectric transistor structure integrated with a thick gate dielectric transistor structure are illustrated according to some embodiments. For example, the system could be a mobile computing platform 1705 and / or a data server machine 1706. Either can employ a component assembly including an IC die having a thin gate dielectric transistor structure integrated with a thick gate dielectric transistor structure, as described elsewhere herein. Server machine 1706 can be any commercial server, such as any number of high-performance computing platforms rack-mounted and networked together for electronic data processing, which in exemplary embodiments includes an IC die assembly 1750 having an IC die having a thin gate dielectric transistor structure integrated with a thick gate dielectric transistor structure, as described elsewhere herein. Mobile computing platform 1705 can be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, etc. For example, mobile computing platform 1705 can be any of a tablet, smartphone, laptop, etc., and can include a display (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 1710, and a battery 1715. Although shown relative to mobile computing platform 1705, in other examples, chip-level or package-level integrated system 1710 and battery 1715 can be implemented in desktop computing platforms, automotive computing platforms, Internet of Things platforms, etc. As described below, in some examples, the disclosed system may include a subsystem 1760, such as a system-on-a-chip (SoC) or an integrated system of multiple ICs, shown relative to mobile computing platform 1705.

[0067] Whether located within the integrated system 1710 shown in extended view 1720 or as a stand-alone packaged device within a data server machine 1706, subsystem 1760 may include a memory circuitry and / or a processor circuitry 1740 (e.g., RAM, microprocessor, multi-core microprocessor, graphics processor, etc.), a power management integrated circuit (PMIC) 1730, a controller 1735, and a radio frequency integrated circuit (RFIC) 1725 (e.g., including a broadband RF transmitter and / or receiver (TX / RX)). As shown, one or more IC dies (e.g., the memory circuitry and / or processor circuitry 1740) may be assembled and implemented such that one or more IC dies have a thin-gate dielectric transistor structure integrated with a thick-gate dielectric transistor structure as described herein. In some embodiments, RFIC 1725 includes a digital baseband and an analog front-end module, the analog front-end module further including a power amplifier on the transmit path and a low-noise amplifier on the receive path. Functionally, the PMIC 1730 can perform battery power regulation, DC-DC conversion, etc., and therefore has an input coupled to the battery 1715 and an output that provides current to other functional modules. For example... Figure 17 As further illustrated, in an exemplary embodiment, RFIC 1725 has an output coupled to an antenna (not shown) to implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and above. Memory circuitry and / or processor circuitry 1740 can provide memory functionality for subsystem 1760, and provide advanced control, data processing, etc., for subsystem 1760. In an alternative embodiment, each SOC module can be integrated onto a separate IC coupled to a package substrate, interposer, or board.

[0068] Figure 18This is a functional block diagram of an electronic computing device 1800 according to some embodiments. For example, according to any embodiment described elsewhere herein, device 1800 may have a thin-gate dielectric transistor structure integrated with a thick-gate dielectric transistor structure via any suitable component therein. Device 1800 also includes a motherboard or package substrate 1802 hosting several components (e.g., but not limited to a processor 1804, such as an application processor). Processor 1804 may be physically and / or electrically coupled to package substrate 1802. In some examples, processor 1804 is within an IC assembly that includes an IC die having a thin-gate dielectric transistor structure integrated with a thick-gate dielectric transistor structure as described elsewhere herein. Generally, the terms "processor" or "microprocessor" can refer to any device or part of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be further stored in registers and / or memory.

[0069] In various examples, one or more communication chips 1806 may also be physically and / or electrically coupled to the package substrate 1802. In a further embodiment, the communication chip 1806 may be part of a processor 1804. Depending on its application, the computing device 1800 may include other components that may or may not be physically and electrically coupled to the package substrate 1802. These other components include, but are not limited to, volatile memory (e.g., DRAM 1832), non-volatile memory (e.g., ROM 1835), flash memory (e.g., NAND or NOR), magnetic storage (MRAM 1830), graphics processor 1822, digital signal processor, cryptographic processor, chipset 1812, antenna 1825, touch screen display 1815, touch screen controller 1865, battery 1816, audio codec, video codec, power amplifier 1821, global positioning system (GPS) device 1840, compass 1845, accelerometer, gyroscope, speaker 1820, camera 1841, and mass storage devices (e.g., hard disk drive, solid-state drive (SSD), compact optical disc (CD), digital multifunction disc (DVD), etc.).

[0070] Communication chip 1806 enables wireless communication for transmitting data to and from computing device 1800. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data via a non-solid medium using modulated electromagnetic radiation. This term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires. Communication chip 1806 can implement any of a variety of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 1800 may include multiple communication chips 1806. For example, a first communication chip may be dedicated to shorter-range wireless communication such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0071] While certain features set forth herein have been described with reference to various embodiments, this description is not intended to be interpreted in a limiting sense. Therefore, various modifications to the embodiments described herein, as well as other embodiments that will be apparent to those skilled in the art to which this disclosure pertains, are considered to be within the spirit and scope of this disclosure.

[0072] It will be appreciated that the invention is not limited to the embodiments described herein, but can be practiced with modifications and variations without departing from the scope of the appended claims. For example, the above embodiments may include specific combinations of features further provided below.

[0073] The following describes exemplary embodiments.

[0074] In one or more first embodiments, an apparatus includes: at least one semiconductor structure laterally located between and coupled to a source structure and a drain structure; a gate structure including a gate dielectric on and surrounding the channel region of the semiconductor structure and a gate electrode surrounding the gate dielectric; and a dielectric spacer laterally located between the gate structure and one of the source structure or the drain structure and the gate structure, the dielectric spacer being adjacent to the channel region on the at least one semiconductor structure such that the dielectric spacer has a first width and a second width extending between the gate structure and the source structure or the drain structure, the first width being adjacent to the semiconductor structure and the second width being away from the semiconductor structure and at least 10 percent larger than the first width.

[0075] In one or more second embodiments, further for the first embodiment, a portion of the gate dielectric is on the dielectric spacer and in contact with the source structure or the drain structure.

[0076] In one or more third embodiments, further for the first or second embodiments, the dielectric spacer comprises silicon, oxygen, and nitrogen, and the gate dielectric comprises silicon and oxygen.

[0077] In one or more fourth embodiments, further for the first to third embodiments, the dielectric spacer is a first dielectric spacer, and the second dielectric spacer is on the portion of the gate dielectric above the first dielectric spacer.

[0078] In one or more fifth embodiments, further for the first to fourth embodiments, the semiconductor structure is a first semiconductor structure, and the device further includes a plurality of vertically aligned second semiconductor structures, each second semiconductor structure being laterally located between the second source structure and the second drain structure and coupled to the second source structure and the second drain structure, such that the first second semiconductor structure in the second semiconductor structure is coplanar with the first semiconductor structure, and the second second semiconductor structure in the second semiconductor structure is coplanar with a portion of the gate dielectric.

[0079] In one or more sixth embodiments, and further for the first to fifth embodiments, the gate dielectric is a first gate dielectric, and the device further includes a second gate dielectric on the second semiconductor structure, such that the first gate dielectric comprises silicon and oxygen, and the second dielectric comprises one of hafnium, aluminum, zirconium or titanium and oxygen.

[0080] In one or more seventh embodiments, and further for the first to sixth embodiments, the first gate dielectric has a first thickness in the channel region, and the second dielectric has a second thickness in the second semiconductor structure that is not greater than half of the first thickness.

[0081] In one or more eighth embodiments, and further for the first to seventh embodiments, the second width is at least 25% larger than the first width.

[0082] In one or more ninth embodiments, and further for the first to eighth embodiments, the apparatus further includes: an integrated circuit (IC) die including the semiconductor structure, the source structure, the drain structure, the gate structure and the dielectric spacer; and a power supply coupled to the IC die.

[0083] In one or more tenth embodiments, a system includes an IC die of any of the devices according to the first to eighth embodiments, and a display and / or power supply coupled to the IC die.

[0084] In one or more eleventh embodiments, at least one semiconductor structure is laterally located between and coupled to the source and drain structures, and the gate structure includes a gate dielectric on and surrounding the channel region of the semiconductor structure and a gate electrode surrounding the gate dielectric, and a dielectric spacer laterally located between the source or drain structure and the gate structure and the gate structure, the dielectric spacer being adjacent to the channel region on the at least one semiconductor structure such that a portion of the gate dielectric is on the dielectric spacer and in contact with the source or drain structure.

[0085] In one or more twelfth embodiments, and further for an eleventh embodiment, the dielectric spacer is a first dielectric spacer, and the second dielectric spacer is on the portion of the gate dielectric above the first dielectric spacer.

[0086] In one or more thirteenth embodiments, and further for the eleventh or twelfth embodiment, the second dielectric spacer has a first width and a second width extending between the gate structure and the source structure or the drain structure, the first width being adjacent to the portion of the gate dielectric, and the second width being away from the portion of the gate dielectric and at least 10 percent smaller than the first width.

[0087] In one or more of the fourteenth embodiments, and further for the eleventh to thirteenth embodiments, the semiconductor structure is a first semiconductor structure, and the device further includes a plurality of vertically aligned second semiconductor structures, each second semiconductor structure being laterally located between the second source structure and the second drain structure and coupled to the second source structure and the second drain structure, such that the first second semiconductor structure in the second semiconductor structure is coplanar with the first semiconductor structure, and the second second semiconductor structure in the second semiconductor structure is coplanar with a portion of the gate dielectric.

[0088] In one or more fifteenth embodiments, and further for eleventh to fourteenth embodiments, the gate dielectric is a first gate dielectric, and the device further includes a second gate dielectric on the second semiconductor structure, such that the first gate dielectric has a first thickness on the channel region and comprises silicon and oxygen, the second dielectric has a second thickness on the second semiconductor structure and comprises one of hafnium, aluminum, zirconium or titanium and oxygen, and the second thickness is not greater than half of the first thickness.

[0089] In one or more sixteenth embodiments, and further for eleventh to fifteenth embodiments, the dielectric spacer comprises silicon, oxygen, and nitrogen, and the gate dielectric comprises silicon and oxygen.

[0090] In one or more of the seventeenth embodiments, and further for the eleventh to sixteenth embodiments, the apparatus further includes: an integrated circuit (IC) die including the semiconductor structure, the source structure, the drain structure, the gate structure, and the dielectric spacer; and a power supply coupled to the IC die.

[0091] In one or more of the eighteenth embodiments, a system includes an IC die of any of the devices according to the eleventh to sixteenth embodiments, and a display and / or power supply coupled to the IC die.

[0092] In one or more nineteenth embodiments, an apparatus includes: a plurality of vertically aligned first nanoribbons, each first nanoribbon laterally located between and coupled to the first source structure and the first drain structure; a first gate structure coupled to each of the first nanoribbons; a plurality of vertically aligned second nanoribbons, each second nanoribbon laterally located between and coupled to the second source structure and the second drain structure; and a second gate structure coupled to each of the first nanoribbons such that the first nanoribbons in the first nanoribbons are coplanar with the first nanoribbons in the second nanoribbons, and the first nanoribbons have more nanoribbons than the second nanoribbons.

[0093] In one or more twentieth embodiments, and further for the nineteenth embodiment, the first gate structure includes a first gate dielectric having a first thickness, and the second gate structure includes a second gate dielectric having a second thickness not less than twice the first thickness.

[0094] In one or more twenty-first embodiments, and further for the nineteenth or twentieth embodiment, the first gate dielectric comprises one of hafnium, aluminum, zirconium or titanium and oxygen, and the second gate dielectric comprises silicon and oxygen.

[0095] In one or more twenty-second embodiments, and further for the nineteenth to twenty-first embodiments, the apparatus further includes: an integrated circuit (IC) die including the first nanoribbon, the first source structure, the first drain structure, the first gate structure, the second nanoribbon, the second source structure, the second drain structure, and the second gate structure; and a power supply coupled to the IC die.

[0096] In one or more twenty-third embodiments, a system includes an IC die of any of the devices according to the nineteenth to twenty-first embodiments, and a display and / or power supply coupled to the IC die.

[0097] It will be appreciated that the invention is not limited to the embodiments described herein, but can be practiced with modifications and variations without departing from the scope of the appended claims. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limited in this respect, and in various implementations, the above embodiments may include only a subset of such features, different orders of such features, different combinations of such features, and / or additional features different from those expressly listed. Therefore, the scope of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. An apparatus comprising: At least one semiconductor structure, the at least one semiconductor structure being laterally located between a source structure and a drain structure and coupled to the source structure and the drain structure; A gate structure, the gate structure including a gate dielectric located on and surrounding a channel region of the semiconductor structure and a gate electrode surrounding the gate dielectric; as well as A dielectric spacer is laterally located between one of the source structure or the drain structure and the gate structure, and on both the source structure or the drain structure and the gate structure. The dielectric spacer is adjacent to the channel region on the at least one semiconductor structure. The dielectric spacer has a first width and a second width extending between the gate structure and the source structure or the drain structure, the first width being adjacent to the semiconductor structure and the second width being away from the semiconductor structure and at least 10 percent larger than the first width.

2. The apparatus according to claim 1, wherein, A portion of the gate dielectric is on the dielectric spacer and is in contact with the source structure or the drain structure.

3. The apparatus according to claim 2, wherein, The dielectric spacer comprises silicon, oxygen, and nitrogen, and wherein the gate dielectric comprises silicon and oxygen.

4. The apparatus according to claim 2, wherein, The dielectric spacer is a first dielectric spacer, and wherein the second dielectric spacer is on the portion of the gate dielectric above the first dielectric spacer.

5. The apparatus according to any one of claims 1 to 4, wherein, The semiconductor structure is a first semiconductor structure, and the device further includes: A plurality of vertically aligned second semiconductor structures, each second semiconductor structure being laterally located between and coupled to the second source structure and the second drain structure, wherein the first second semiconductor structure is coplanar with the first semiconductor structure, and wherein the second second semiconductor structure is coplanar with the portion of the gate dielectric.

6. The apparatus according to claim 5, wherein, The gate dielectric is a first gate dielectric, and the device further includes a second gate dielectric on the second semiconductor structure, wherein the first gate dielectric comprises silicon and oxygen, and wherein the second dielectric comprises one of hafnium, aluminum, zirconium or titanium and oxygen.

7. The apparatus according to claim 6, wherein, The first gate dielectric has a first thickness in the channel region, and the second dielectric has a second thickness in the second semiconductor structure that is no more than half the first thickness.

8. The apparatus according to any one of claims 1 to 4, wherein, The second width is at least 25% larger than the first width.

9. A system comprising: Integrated circuit (IC) die, the integrated circuit die comprising: At least one semiconductor structure, the at least one semiconductor structure being laterally located between a source structure and a drain structure and coupled to the source structure and the drain structure; A gate structure, the gate structure including a gate dielectric located on and surrounding a channel region of the semiconductor structure and a gate electrode surrounding the gate dielectric; and A dielectric spacer, the dielectric spacer being laterally located between one of the source structure or the drain structure and the gate structure, and on both the source structure or the drain structure and the gate structure, the dielectric spacer being adjacent to the channel region on the at least one semiconductor structure, wherein the dielectric spacer has a first width and a second width extending between the gate structure and the source structure or the drain structure, the first width being adjacent to the semiconductor structure, and the second width being distal to the semiconductor structure and at least 10 percent larger than the first width; and A power supply, which is coupled to the IC die.

10. The system according to claim 9, wherein, A portion of the gate dielectric is on the dielectric spacer and is in contact with the source structure or the drain structure.

11. The system according to claim 10, wherein, The dielectric spacer comprises silicon, oxygen, and nitrogen, and wherein the gate dielectric comprises silicon and oxygen.

12. The system according to claim 10, wherein, The dielectric spacer is a first dielectric spacer, and wherein the second dielectric spacer is on the portion of the gate dielectric above the first dielectric spacer.

13. The system according to any one of claims 9 to 12, wherein, The semiconductor structure is a first semiconductor structure, and the system further includes: A plurality of vertically aligned second semiconductor structures, each second semiconductor structure being laterally located between and coupled to the second source structure and the second drain structure, wherein the first second semiconductor structure is coplanar with the first semiconductor structure, and wherein the second second semiconductor structure is coplanar with the portion of the gate dielectric.

14. The system according to claim 13, wherein, The gate dielectric is a first gate dielectric, and the system further includes a second gate dielectric on the second semiconductor structure, wherein the first gate dielectric comprises silicon and oxygen, and wherein the second dielectric comprises one of hafnium, aluminum, zirconium or titanium and oxygen.

15. The system according to claim 14, wherein, The first gate dielectric has a first thickness in the channel region, and the second dielectric has a second thickness in the second semiconductor structure that is no more than half the first thickness.

16. The system according to any one of claims 9 to 12, wherein, The second width is at least 25% larger than the first width.

17. A method comprising: At least one semiconductor structure is formed, the at least one semiconductor structure being laterally located between the source structure and the drain structure and coupled to the source structure and the drain structure; A gate structure is formed, the gate structure including a gate dielectric located on and surrounding the channel region of the semiconductor structure and a gate electrode surrounding the gate dielectric; as well as A dielectric spacer is formed, the dielectric spacer being laterally located between one of the source structure or the drain structure and the gate structure and on the one of the source structure or the drain structure and the gate structure, the dielectric spacer being adjacent to the channel region on the at least one semiconductor structure, wherein the dielectric spacer has a first width and a second width extending between the gate structure and the source structure or the drain structure, the first width being adjacent to the semiconductor structure and the second width being away from the semiconductor structure and being at least 10 percent larger than the first width.

18. The method according to claim 17, wherein, A portion of the gate dielectric is on the dielectric spacer and is in contact with the source structure or the drain structure.

19. The method according to claim 18, wherein, The dielectric spacer comprises silicon, oxygen, and nitrogen, and wherein the gate dielectric comprises silicon and oxygen.

20. The method according to claim 18, wherein, The dielectric spacer is a first dielectric spacer, and wherein the second dielectric spacer is on the portion of the gate dielectric above the first dielectric spacer.

21. The method according to any one of claims 17 to 20, wherein, The semiconductor structure is a first semiconductor structure, and the method further includes: A plurality of vertically aligned second semiconductor structures are formed, each second semiconductor structure being laterally located between and coupled to the second source structure and the second drain structure, wherein the first second semiconductor structure is coplanar with the first semiconductor structure, and wherein the second second semiconductor structure is coplanar with the portion of the gate dielectric.

22. The method according to claim 21, wherein, The gate dielectric is a first gate dielectric, and the method further includes: A second gate dielectric is formed on the second semiconductor structure, wherein the first gate dielectric comprises silicon and oxygen, and wherein the second dielectric comprises one of hafnium, aluminum, zirconium or titanium and oxygen.

23. The method according to claim 22, wherein, The first gate dielectric has a first thickness in the channel region, and the second dielectric has a second thickness in the second semiconductor structure that is no more than half the first thickness.

24. The method according to any one of claims 17 to 20, wherein, The second width is at least 25% larger than the first width.

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