Construction method of field effect transistor with high electrical performance

Abstract

The invention discloses a construction method of a field effect transistor with high electrical properties. The construction method comprises the following steps: (1) forming a selenide channel layer on a substrate by using a mechanical stripping method and a dry method transfer device; (2) laminating a prefabricated metal electrode layer on the selenide channel layer to obtain an initial device; and (3) spin-coating a polymer protective layer on the initial device, and then carrying out nanoimprint processing to obtain the field effect transistor after imprint. The electrical performance of the transistor is effectively improved through the nanoimprint technology, the saturation current density of the transistor is improved by more than 200% and can reach 2358%, and the carrier mobility is improved by more than 200% and can reach 2704%.

Description

Technical Field

[0001] This invention relates to a method for constructing a high-performance field-effect transistor. Background Technology

[0002] In the fabrication of two-dimensional field-effect transistors (FETs), vapor deposition, chemical deposition, or physical transfer methods are commonly used. Vapor deposition and chemical deposition methods are prone to disrupting lattice integrity and introducing interface defects, leading to a significant reduction in carrier mobility. While physical transfer methods avoid channel layer loss and create a clean interface, they achieve Schottky contacts. The interface between the metal electrode and the two-dimensional channel material suffers from bandgap states, such as metal-induced bandgap states (MIGS) and disorder-induced bandgap states (DIGS). These bandgap states cause Fermi level pinning, making it difficult to adjust the Schottky barrier height using the metal work function. This results in low saturation current density and low carrier mobility in the transistor's electrical performance. Summary of the Invention

[0003] Purpose of the invention: The purpose of this invention is to provide a method for significantly improving the electrical performance of field-effect transistors by effectively improving the interface contact between metal and semiconductor (two-dimensional channel layer).

[0004] Technical solution: The method for constructing a high-performance field-effect transistor according to the present invention includes the following steps: (1) A selenide channel layer is formed on the substrate using mechanical stripping and dry transfer equipment; (2) The pre-fabricated metal electrode is laminated onto the selenide channel layer to obtain the initial device; (3) After spin-coating a polymer protective layer on the initial device, nanoimprinting is performed to obtain a field-effect transistor.

[0005] In step (1), the substrate is an n-type doped single-sided polished silicon dioxide substrate with a thickness of 300 nm. The length of the selenide channel layer is 5~10 μm and the width is 0.5~10 μm; the selenide channel layer is a tungsten selenide channel layer or a platinum selenide channel layer.

[0006] In step (2), the prefabricated metal electrode is obtained by photolithography, vapor deposition, and spin coating of PVA; the metal electrode is an Au electrode; the thickness of the electrode is 50~55nm.

[0007] The prefabricated metal electrode is prepared by the following method: an Au electrode is photolithographically etched and deposited on a Si sacrificial substrate with a thickness of 50 nm; a PVA solution is spin-coated onto the Si sacrificial substrate and heated at 70 °C for 3 min. The spin-coating and heating operations are repeated 4 to 5 times, and the prefabricated metal electrode is then peeled off.

[0008] In step (2), the pre-fabricated metal electrode is physically laminated onto the selenide channel layer, a pressure of about 0.4~0.5MPa is applied, and the electrode is heated at 70~80℃ for 4~7 minutes before being released.

[0009] In step (3), the polymer protective layer is positive electron beam photoresist 950 PMMA. After spin coating the polymer protective layer and heating and drying it, nanoimprinting is performed. The heating temperature is 150~155℃ and the heating time is 2~2.5min, so that PMMA is cured to achieve the purpose of protecting the electrode. The nanoimprinting temperature is 40~100℃, the pressure is 11bar~30bar and the time is 300~320s. Applying a certain pressure and time at a suitable temperature can improve the interface contact of metal-semiconductor (two-dimensional channel layer), thereby greatly improving the electrical performance of field-effect transistor.

[0010] Heating during nanoimprinting avoids thermal decomposition of the material and promotes interfacial atomic diffusion, weakening the contact barrier. Applying pressure physically compresses van der Waals gaps or micro-voids at the metal-semiconductor interface, enhancing the overlap of their electronic wave functions while suppressing interfacial bubbles / impurities, significantly reducing carrier transport resistance. Maintaining pressure for a certain period ensures sufficient interface optimization and improves contact stability. The method of this invention significantly improves the saturation current density of the field-effect transistor while also significantly increasing the carrier concentration.

[0011] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: The method of the present invention effectively improves the electrical performance of transistors, increasing the saturation current density of transistors by more than 200%, up to 2358%, and increasing the carrier mobility by more than 200%, up to 2704%. Attached Figure Description

[0012] Figure 1 Electrical characteristic curves of the field-effect transistor before and after nanoimprinting constructed in Example 1; Figure 2 Electrical characteristic curves of the field-effect transistor before and after nanoimprinting constructed in Example 2; Figure 3 Electrical characteristic curves of the field-effect transistor before and after nanoimprinting constructed in Example 3; Figure 4 The electrical characteristic curves of the field-effect transistor before and after nanoimprinting constructed in Example 4 are shown. Figure 5 Electrical characteristic curves of the field-effect transistor before and after nanoimprinting constructed in Example 5; Figure 6 Electrical characteristic curves of the field-effect transistor before and after nanoimprinting, for Comparative Example 1. Figure 7 Electrical characteristic curves of the field-effect transistors before and after nanoimprinting, for Comparative Example 2. Figure 8 Electrical characteristic curves of the field-effect transistors before and after nanoimprinting, for Comparative Example 3. Figure 9 Here are schematic diagrams of the structure and electrode patterns of a field-effect transistor constructed based on the method of this invention; Figure 10 Raman spectra of WSe2 materials after nanoimprinting under different pressures. Detailed Implementation

[0013] Example 1 The method for constructing a high-performance field-effect transistor according to the present invention specifically includes the following steps: (1) Few-layer tungsten selenide channel material was prepared by mechanical exfoliation. The thickness of the channel material was 2~4 nm, the length was 8.64 μm, and the width was 3.38 μm. (2) Use a dry transfer apparatus to transfer tungsten selenide thin films onto an n-type doped 300nm single-polished silicon dioxide wafer substrate; (3) Au electrodes are photolithographically etched and deposited on a Si sacrificial substrate, with the electrode pattern as shown in the figure. Figure 9 As shown in (b), the electrode thickness is 50 nm; (4) Spin-coat PVA solution onto Si sacrificial substrate and heat at 70°C for 3 min. Repeat the spin-coating and heating operation 4 to 5 times, and peel it off to obtain the pre-fabricated metal electrode. (5) Physically laminate the pre-fabricated electrode onto the tungsten selenide channel layer of the silicon oxide substrate, apply a pressure of 0.4~0.5MPa, heat at 70~80℃ for 4~7min and release, and soak in deionized water for about 2h to remove PVA to obtain the transfer electrode device; (6) Spin-coat the device with positive electron beam photoresist 950 PMMA, and heat at 150°C for 2 min after spin coating; (7) Place the device at the bottom of the nanoimprint stage, heat the nanoimprint stage to 100°C, apply a pressure of 11 bar at this temperature, and cool it to room temperature after 300 s to obtain a field-effect transistor, the structure of which is as follows. Figure 9 As shown in (a).

[0014] The transfer characteristic curves and output characteristic curves of the field-effect transistor constructed in Example 1 were tested using a semiconductor tester, and the results are as follows: Figure 1 As shown, the field-effect transistor constructed in Example 1 is a p-type field-effect transistor. Testing revealed that, before nanoimprinting (transfer electrode device), the transistor's saturation current density was 1.45 μA / μm, and its hole mobility was 25.6 cm⁻¹. 2 The saturation current density of the transistor after nanoimprinting is 5.15 μA / μm, and the hole mobility is 58.9 cm⁻¹. 2 / V·s, which is 355% higher than the saturated current density before nanoimprinting and 230% higher hole mobility.

[0015] Example 2 The method for constructing a high-performance field-effect transistor according to the present invention specifically includes the following steps: (1) Few-layer tungsten selenide channel material was prepared by mechanical exfoliation. The thickness of the channel material was 2~4 nm, the length was 6.03 μm, and the width was 9.48 μm. (2) Use a dry transfer apparatus to transfer tungsten selenide thin films onto an n-type doped 300nm single-polished silicon dioxide wafer substrate; (3) Au electrodes are photolithographically etched and deposited on a Si sacrificial substrate, with the electrode pattern as shown in the figure. Figure 9 As shown in (b), the electrode thickness is 50 nm; (4) Spin-coat PVA solution onto Si sacrificial substrate and heat at 70°C for 3 min. Repeat the spin-coating and heating operation 4 to 5 times, and peel it off to obtain the pre-fabricated electrode. (5) Physically laminate the pre-fabricated electrode onto the tungsten selenide channel layer of the silicon oxide substrate, apply a pressure of 0.4~0.5MPa, heat at 70~80℃ for 4~7min and release, and soak in deionized water for about 2h to remove PVA to obtain the transfer electrode device. (6) Spin-coat the device with positive electron beam photoresist 950 PMMA, and heat at 150°C for 2 min after spin coating; (7) Place the device at the bottom of the nanoimprint stage, heat the nanoimprint stage to 100°C, apply a pressure of 15 bar at this temperature, and cool it to room temperature after 300 s to obtain a field-effect transistor, the structure of which is as follows. Figure 9 As shown in (a).

[0016] The transfer characteristic curves and output characteristic curves of the field-effect transistor constructed in Example 2 were tested using a semiconductor tester, and the results are as follows: Figure 2As shown, the field-effect transistor constructed in Example 2 is a p-type field-effect transistor. Testing revealed that the saturation current density of this transistor before nanoimprinting was 1.6 μA / μm, and the hole mobility was 17.3 cm⁻¹. 2 The saturation current density of the transistor after nanoimprinting is 4.89 μA / μm, and the hole mobility is 56.7 cm⁻¹. 2 / V·s, which is 305% higher than the saturated current density before nanoimprinting and 328% higher hole mobility.

[0017] Example 3 The method for constructing a high-performance field-effect transistor according to the present invention specifically includes the following steps: (1) Few-layer tungsten selenide channel material was prepared by mechanical exfoliation. The thickness of the channel material was 2~4 nm, the length was 6.73 μm, and the width was 0.62 μm. (2) Use a dry transfer apparatus to transfer tungsten selenide thin films onto an n-type doped 300nm single-polished silicon dioxide wafer substrate; (3) Au electrodes are photolithographically etched and deposited on a Si sacrificial substrate, with the electrode pattern as shown in the figure. Figure 9 As shown in (b), the electrode thickness is 50 nm; (4) Spin-coat PVA solution onto Si sacrificial substrate and heat at 70°C for 3 min. Repeat the spin-coating and heating operation 4 to 5 times, and peel it off to obtain the pre-fabricated electrode. (5) Physically laminate the pre-fabricated electrode onto the tungsten selenide channel layer of the silicon oxide substrate, apply a pressure of 0.4~0.5MPa, heat at 70~80℃ for 4~7min and release, and soak in deionized water for about 2h to remove PVA to obtain the transfer electrode device. (6) Spin-coat the device with positive electron beam photoresist 950 PMMA, and heat at 150°C for 2 min after spin coating; (7) Place the device at the bottom of the nanoimprint stage, heat the nanoimprint stage to 100°C, apply a pressure of 20 bar at this temperature, and cool it to room temperature after 300 s to obtain a field-effect transistor, the structure of which is as follows. Figure 9 As shown in (a).

[0018] The transfer characteristic curves and output characteristic curves of the field-effect transistor constructed in Example 3 were tested using a semiconductor tester, and the results are as follows: Figure 3 As shown, the field-effect transistor constructed in Example 3 is a p-type field-effect transistor. Testing revealed that the saturation current density of this transistor before nanoimprinting was 5.64 μA / μm, and the hole mobility was 78 cm⁻¹. 2 The saturation current density of the transistor after nanoimprinting is 13.7 μA / μm, and the hole mobility is 159 cm⁻¹.2 / V·s, which is 243% higher than the saturated current density before nanoimprinting and 204% higher hole mobility.

[0019] Example 4 The method for constructing a high-performance field-effect transistor according to the present invention specifically includes the following steps: (1) Few-layer tungsten selenide channel material was prepared by mechanical exfoliation. The thickness of the channel material was 2~4 nm, the length was 5.97 μm, and the width was 6.12 μm. (2) Use a dry transfer apparatus to transfer tungsten selenide thin films onto an n-type doped 300nm single-polished silicon dioxide wafer substrate; (3) Au electrodes are photolithographically etched and deposited on a Si sacrificial substrate, with the electrode pattern as shown in the figure. Figure 9 As shown in (b), the electrode thickness is 50 nm; (4) Spin-coat PVA solution onto Si sacrificial substrate and heat at 70°C for 3 min. Repeat the spin-coating and heating operation 4 to 5 times, and peel it off to obtain the pre-fabricated electrode. (5) Physically laminate the pre-fabricated electrode onto the tungsten selenide channel layer of the silicon oxide substrate, apply a pressure of 0.4~0.5MPa, heat at 70~80℃ for 4~7min and release, and soak in deionized water for about 2h to remove PVA to obtain the transfer electrode device. (6) Spin-coat the device with positive electron beam photoresist 950 PMMA, and heat at 150°C for 2 min after spin coating; (7) Place the device at the bottom of the nanoimprint stage, heat the nanoimprint stage to 60°C, apply a pressure of 15 bar at this temperature, and cool it to room temperature after 300 s to obtain a field-effect transistor, the structure of which is as follows. Figure 9 As shown in (a).

[0020] The transfer characteristic curves and output characteristic curves of the field-effect transistor constructed in Example 4 were tested using a semiconductor tester, and the results are as follows: Figure 4 As shown, the field-effect transistor constructed in Example 4 is a p-type field-effect transistor. Testing revealed that the saturation current density of this transistor before nanoimprinting was 0.67 μA / μm, and the hole mobility was 6.9 cm⁻¹. 2 The saturation current density of this transistor after nanoimprinting is 15.8 μA / μm, and the hole mobility is 186.6 cm⁻¹. 2 / V·s, which is 2358% higher than the saturated current density before nanoimprinting and 2704% higher hole mobility.

[0021] Example 5 The method for constructing a high-performance field-effect transistor according to the present invention specifically includes the following steps: (1) Few-layer tungsten selenide channel material was prepared by mechanical exfoliation. The thickness of the channel material was 2~4 nm, the length was 6.46 μm, and the width was 2.54 μm. (2) Use a dry transfer apparatus to transfer tungsten selenide thin films onto an n-type doped 300nm single-polished silicon dioxide wafer substrate; (3) Au electrodes are photolithographically etched and deposited on a Si sacrificial substrate, with the electrode pattern as shown in the figure. Figure 9 As shown in (b), the electrode thickness is 50 nm; (4) Spin-coat PVA solution onto Si sacrificial substrate and heat at 70°C for 3 min. Repeat the spin-coating and heating operation 4 to 5 times, and peel it off to obtain the pre-fabricated electrode. (5) Physically laminate the pre-fabricated electrode onto the tungsten selenide channel layer of the silicon oxide substrate, apply a pressure of 0.4~0.5MPa, heat at 70~80℃ for 4~7min and release, and soak in deionized water for about 2h to remove PVA to obtain the transfer electrode device. (6) Spin-coat the device with positive electron beam photoresist 950 PMMA, and heat at 150°C for 2 min after spin coating; (7) Place the device at the bottom of the nanoimprint stage, heat the nanoimprint stage to 40°C, apply a pressure of 15 bar at this temperature, and cool it to room temperature after 300 s to obtain a field-effect transistor, the structure of which is as follows. Figure 9 As shown in (a).

[0022] The transfer characteristic curves and output characteristic curves of the field-effect transistor constructed in Example 5 were tested using a semiconductor tester, and the results are as follows: Figure 5 As shown, the field-effect transistor constructed in Example 5 is a p-type field-effect transistor. Testing revealed that the saturation current density of this transistor before nanoimprinting was 1.46 μA / μm, and the hole mobility was 14.8 cm⁻¹. 2 The saturation current density of this transistor after nanoimprinting is 12.6 μA / μm, and the hole mobility is 175.5 cm⁻¹. 2 / V·s, which is 863% higher than the saturation current density before nanoimprinting and 1186% higher hole mobility.

[0023] Comparative Example 1 A method for constructing a field-effect transistor specifically includes the following steps: (1) Few-layer tungsten selenide channel material was prepared by mechanical exfoliation. The thickness of the channel material was 2~4 nm, the length was 6.07 μm, and the width was 3.95 μm. (2) Use a dry transfer apparatus to transfer tungsten selenide thin films onto an n-type doped 300nm single-polished silicon dioxide wafer substrate; (3) Au electrodes are photolithographically etched and deposited on a Si sacrificial substrate, with the electrode pattern as shown in the figure. Figure 9 As shown in (b), the electrode thickness is 50 nm; (4) Spin-coat PVA solution onto Si sacrificial substrate and heat at 70°C for 3 min. Repeat the spin-coating and heating operation 4 to 5 times, and peel it off to obtain the pre-fabricated electrode. (5) Physically laminate the pre-fabricated electrode onto the tungsten selenide channel layer of the silicon oxide substrate, apply a pressure of 0.4~0.5MPa, heat at 70~80℃ for 4~7min and release, and soak in deionized water for about 2h to remove PVA to obtain the transfer electrode device. (6) Spin-coat the device with positive electron beam photoresist 950 PMMA, and heat at 150°C for 2 min after spin coating; (7) Place the device at the bottom of the nanoimprint stage, heat the nanoimprint stage to 100°C, apply a pressure of 30 bar at this temperature, and cool it to room temperature after 300 s to obtain a field-effect transistor, the structure of which is as follows. Figure 9 As shown in (a).

[0024] The transfer characteristic curves and output characteristic curves of the field-effect transistor constructed in Comparative Example 1 were tested using a semiconductor tester, and the results are as follows: Figure 6 As shown, the field-effect transistor constructed in Comparative Example 1 is a p-type field-effect transistor. Tests showed that the saturation current density of this transistor before nanoimprinting was 0.83 μA / μm, and the hole mobility was 21.5 μm. 2 The saturation current density of the transistor after nanoimprinting is 0.84 μA / μm, and the hole mobility is 24.0 cm⁻¹. 2 / V·s.

[0025] Comparative Example 2 A method for constructing a field-effect transistor specifically includes the following steps: (1) Few-layer tungsten selenide channel material was prepared by mechanical exfoliation. The thickness of the channel material was 2~4 nm, the length was 5.79 μm, and the width was 6.71 μm. (2) Use a dry transfer apparatus to transfer tungsten selenide thin films onto an n-type doped 300nm single-polished silicon dioxide wafer substrate; (3) Au electrodes are photolithographically etched and deposited on a Si sacrificial substrate, with the electrode pattern as shown in the figure. Figure 9 As shown in (b), the electrode thickness is 50~55nm; (4) Spin-coat PVA solution onto Si sacrificial substrate and heat at 70°C for 3 min. Repeat the spin-coating and heating operation 4 to 5 times, and peel it off to obtain the pre-fabricated electrode. (5) Physically laminate the pre-fabricated electrode onto the tungsten selenide channel layer of the silicon oxide substrate, apply a pressure of 0.4~0.5MPa, heat at 70~80℃ for 4~7min and release, and soak in deionized water for about 2h to remove PVA to obtain the transfer electrode device. (6) Spin-coat the device with positive electron beam photoresist 950 PMMA, and heat at 150°C for 2 min after spin coating; (7) Place the device at the bottom of the nanoimprint stage, heat the nanoimprint stage to 100°C, apply a pressure of 15 bar at this temperature, and cool it to room temperature after 180 s to obtain a field-effect transistor, the structure of which is as follows. Figure 9 As shown in (a).

[0026] The transfer characteristic curves and output characteristic curves of the field-effect transistor constructed in Comparative Example 2 were tested using a semiconductor tester, and the results are as follows. Figure 7 As shown, the field-effect transistor constructed in Comparative Example 2 is a p-type field-effect transistor. Tests showed that the saturation current density of this transistor before nanoimprinting was 1.0 μA / μm, and the hole mobility was 20.4 m. 2 The saturation current density of this transistor after nanoimprinting is 1.23 μA / μm, and the hole mobility is 28.0 cm⁻¹. 2 / V·s.

[0027] Comparative Example 3 A method for constructing a field-effect transistor specifically includes the following steps: (1) Few-layer tungsten selenide channel material was prepared by mechanical exfoliation. The thickness of the channel material was 2~4 nm, the length was 6.03 μm, and the width was 9.71 μm. (2) Use a dry transfer apparatus to transfer tungsten selenide thin films onto an n-type doped 300nm single-polished silicon dioxide wafer substrate; (3) Au electrodes are photolithographically etched and deposited on a Si sacrificial substrate, with the electrode pattern as shown in the figure. Figure 9 As shown in (b), the electrode thickness is 50 nm; (4) Spin-coat PVA solution onto Si sacrificial substrate and heat at 70°C for 3 min. Repeat the spin-coating and heating operation 4 to 5 times, and peel it off to obtain the pre-fabricated electrode. (5) The pre-fabricated electrode is physically laminated onto the tungsten selenide channel layer on the silicon oxide substrate. A pressure of 0.4~0.5MPa is applied, and the electrode is heated at 70~80℃ for 4~7min before being released. The electrode is then soaked in deionized water for about 2h to remove PVA, resulting in the transfer electrode device, the structure of which is as follows. Figure 9 As shown in (a).

[0028] The transfer and output characteristics of the field-effect transistor constructed in Comparative Example 3 were tested using a semiconductor tester, and the results are as follows: Figure 8 As shown, the field-effect transistor constructed in Comparative Example 3 is a p-type field-effect transistor. Tests revealed that this transistor has a saturation current density of 0.69 μA / μm and a hole mobility of 8.3 m. 2 / V·s.

[0029] pass Figure 10 The results show that the characteristic peaks of tungsten selenide did not change significantly before and after nanoimprinting, indicating that the nanoimprinting operation provides high fidelity for WSe2. This invention utilizes a transfer electrode method to construct the initial device, spin-coates a polymer protective layer, and then uses nanoimprinting technology to modify the van der Waals gap at the interface between the metal electrode and the two-dimensional channel material, thereby achieving NIL-controlled van der Waals gap regulation and improving the electrical output performance of the transistor device.

Claims

1. A method for constructing a high-performance field-effect transistor, characterized in that, The method comprises the following steps: (1) forming a selenide channel layer on a substrate by mechanical exfoliation and dry transfer device; (2) laminating a prefabricated metal electrode on the selenide channel layer to obtain an initial device; (3) spin-coating a polymer protective layer on the initial device and then performing nano-imprinting treatment, and obtaining a field effect transistor after the nano-imprinting.

2. The construction method according to claim 1, characterized in that: In step (1), the substrate is an n-type doped single-polished double-oxide silicon substrate with a thickness of 300-320 nm.

3. The construction method of claim 1, wherein: In step (1), the length of the selenide channel layer is 5-10 μm, the width is 0.5-10 μm, and the thickness is 2-4 nm.

4. The construction method according to claim 3, characterized in that: The selenide channel layer is a tungsten selenide channel layer or a platinum selenide channel layer.

5. The construction method of claim 1, wherein: In step (2), the metal electrode is an Au electrode, and the thickness of the electrode is 50-55 nm.

6. The construction method of claim 1, wherein: In step (2), the prefabricated metal electrode is physically laminated on the selenide channel layer, and the pressure applied during the physical lamination process is 0.4-0.5 MPa.

7. The construction method according to claim 6, characterized in that: During the physical lamination process, the heating temperature is 70-80℃, and the pressure is released after heating for 4-7 min.

8. The construction method of claim 1, wherein: In step (3), the polymer protective layer is a positive electron beam resist 950 PMMA photoresist, and after spin-coating the polymer protective layer and heating and drying, nano-imprinting treatment is performed.

9. The construction method of claim 8, wherein: The heating temperature is 150-155℃, and the heating time is 2-2.5 min.

10. The construction method of claim 8, wherein: The temperature of the nano-imprinting is 40-100℃, the pressure is 11 bar-30 bar, and the time is 300-320 s.

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