Semiconductor device with thickened layer and method of manufacturing same

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate including a source region and a drain region; a wordline structure comprising a wordline dielectric layer within the substrate and comprising a U-shaped profile, a wordline conductive layer on the wordline dielectric layer and in the substrate, and a wordline cap layer on the wordline conductive layer; a top thickening layer including a U-shaped profile between the word line conductive layer and the word line cap layer and between the word line dielectric layer and the word line cap layer; a bottom cap layer on the substrate and adjacent to the word line dielectric layer; a top cap layer covering the bottom cap layer and the word line structure; a bit line passing through the top cap layer and the bottom cap layer and extending into the source region; and a cell contact passing through the top cap layer and the bottom cap layer and extending into the drain region. The top surface of the top thickening layer is coplanar with the top surface of the word line dielectric layer and is higher than the top surface of the substrate.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 897,214 (i.e., priority date "September 26, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to a semiconductor device having a thickened layer and a method for manufacturing a semiconductor device having a thickened layer. Background Technology

[0003] Semiconductor devices are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. To meet the ever-increasing demand for computing power, the size of semiconductor devices continues to shrink. However, various problems arise during the shrinking process, and the number and severity of these problems continue to increase. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of the "prior art" in this case. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device comprising a substrate including a source region and a drain region; a word line structure including a word line dielectric layer located within the substrate and having a U-shaped cross-sectional profile, a word line conductive layer located on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer having a U-shaped cross-sectional profile located between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer located on the substrate and adjacent to the word line dielectric layer; a top capping layer covering the bottom capping layer and the word line structure; a bit line passing through the top capping layer and the bottom capping layer and extending into the source region; and a cell contact passing through the top capping layer and the bottom capping layer and extending into the drain region. The top surface of the top thickening layer is substantially coplanar with the top surface of the character line dielectric layer, and the vertical height of the top surface of the layer is higher than the vertical height of the top surface of the substrate.

[0006] One aspect of the present disclosure provides a semiconductor device, comprising a substrate including a source region and a drain region; a word line structure including a word line dielectric layer having a U-shaped cross-sectional profile, a word line conductive layer including a bottom conductive portion on the word line dielectric layer and in the substrate, and a top conductive portion on the bottom conductive portion and in the substrate, and a word line cap layer on the word line conductive layer; a bottom thickening layer including a U-shaped cross-sectional profile between the bottom conductive portion and the top conductive portion, between the top conductive portion and the word line dielectric layer, and between the word line cap layer and the word line dielectric layer; a bottom cap layer on the substrate and adjacent to the word line dielectric layer; a top cap layer covering the bottom cap layer and the word line structure; a bit line through the top cap layer and the bottom cap layer and extending into the source region; and a cell contact through the top cap layer and the bottom cap layer and extending into the drain region. A top surface of the bottom thickening layer is substantially coplanar with a top surface of the word line dielectric layer, and a vertical height thereof is higher than a vertical height of a top surface of the substrate.

[0007] Another aspect of the present disclosure provides a method of manufacturing a semiconductor device, comprising providing a substrate having a source region and a drain region, forming a bottom cap layer on the substrate, and forming a word line trench through the bottom cap layer and extending to the substrate; conformally forming a word line dielectric layer on the word line trench; forming a bottom conductive portion on the word line dielectric layer and in the word line trench; conformally forming a first thickening material layer on the bottom conductive portion, the word line dielectric layer, and the bottom cap layer; forming a top conductive portion on the first thickening material layer and in the word line trench; conformally forming a second thickening material layer on the top conductive portion and the first thickening material layer; forming a top insulating material layer on the second thickening material layer and completely filling the word line trench; removing portions of the second thickening material layer, the first thickening material layer, and the top insulating material layer to form a top thickening layer, a bottom thickening layer, and a word line cap layer, respectively, and simultaneously recessing the word line dielectric layer; forming a top cap layer covering the bottom cap layer, the word line dielectric layer, the word line cap layer, the bottom thickening layer, and the top thickening layer; forming a bit line through the top cap layer and the bottom cap layer and extending into the source region in correspondence with the source region; and forming a cell contact through the top cap layer and the bottom cap layer and extending into the drain region in correspondence with the drain region.

[0008] Due to the design of the semiconductor device of the present disclosure, the thickness of the word line dielectric layer is increased by adding a bottom thickening layer and / or a top thickening layer to effectively reduce the problem of gate-induced drain leakage current, thereby improving the performance of the semiconductor device. In addition, the top cap layer shields the word line dielectric layer, the bottom thickening layer and the top thickening layer during the etching and cleaning processes. Such shielding can avoid the recess of the word line dielectric layer, the bottom thickening layer and the top thickening layer, and avoid potentially exposing the drain region and the source region, thereby preventing short circuits that can occur due to such exposure.

[0009] The foregoing has outlined rather broadly the technical features of the present disclosure in order that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described hereinafter that form the subject of the claims of the present disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed can be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0010] The disclosure will be more fully understood with reference to the implementation and claims considered together with the accompanying drawings. It should be noted that the various features are not drawn to scale, according to standard practice in the industry. Indeed, the dimensions of the various features can be arbitrarily inflated or deflated for the sake of clarity in the discussion.

[0011] According to an embodiment of the present disclosure, Figure 1 A method for manufacturing a semiconductor device is shown in the form of a flowchart.

[0012] According to an embodiment of the present disclosure, Figures 2 to 19 A cross-sectional schematic diagram showing the flow of manufacturing a semiconductor device is shown.

[0013] According to some embodiments of the present disclosure, Figures 20 to 22 A cross-sectional schematic diagram of a semiconductor device is shown.

[0014] In which the reference signs are explained as follows:

[0015] 1A: Semiconductor device

[0016] 1B: Semiconductor device

[0017] 1C: Semiconductor device

[0018] 1D: Semiconductor device

[0019] 10: Method

[0020] 101: Substrate

[0021] 101 TS: top surface

[0022] 103: isolation layer

[0023] 105: impurity region

[0024] 105D: drain region

[0025] 105S: source region

[0026] 111: bottom cap layer

[0027] 111 TS: top surface

[0028] 113: top cap layer

[0029] 200: wordline structure

[0030] 210: wordline dielectric layer

[0031] 210 TS: top surface

[0032] 220: wordline conductive layer

[0033] 221: bottom conductive portion

[0034] 221 TS: top surface

[0035] 223: top conductive portion

[0036] 230: wordline cap layer

[0037] 230P: segment

[0038] 230 TS: top surface

[0039] 301: bottom barrier layer

[0040] 301 TS: top surface

[0041] 303: middle barrier layer

[0042] 303 TS: top surface

[0043] 401: bottom thickening layer

[0044] 401 TS: top surface

[0045] 403: top thickening layer

[0046] 403 TS: top surface

[0047] 511: first insulative material layer

[0048] 513: top insulative material layer

[0049] 521: first barrier material layer

[0050] 531: first conductive material layer

[0051] 533: second conductive material layer

[0052] 541: first thickening material layer

[0053] 543: second thickening material layer

[0054] 601: bit line

[0055] 601O: bit line opening

[0056] 603: cell contact

[0057] 701: first mask layer

[0058] 6011: bit line contact

[0059] 6013: bit line bottom electrode

[0060] 6015: bit line top electrode

[0061] 6017: bit line mask pattern

[0062] 6019: bit line spacer

[0063] 6031: lower portion

[0064] 6032: surrounding surface

[0065] 6033: upper portion

[0066] 6034: surrounding surface

[0067] AA: active area

[0068] CD1: first critical dimension

[0069] CD2: second critical dimension

[0070] S11: step

[0071] S13: step

[0072] S15: step

[0073] S17: step

[0074] S19: step

[0075] S21: step

[0076] T1: thickness

[0077] T2: thickness

[0078] T3: thickness

[0079] T4: thickness

[0080] T5: thickness

[0081] T6: thickness

[0082] TR: word line trench

[0083] VL1: vertical height

[0084] VL2: vertical height

[0085] VL3: vertical height

[0086] Z: direction DETAILED DESCRIPTION

[0087] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided technology. For simplicity, the following description of a concrete example of components and arrangements is presented. Of course, this is merely an example and is not intended to limit the scope of the present disclosure. For example, when a first feature is described as being formed over or on a second feature, this can include embodiments where the first feature is in direct contact with the second feature, and can also include embodiments where additional features are formed between the first feature and the second feature such that the first feature is not in direct contact with the second feature. Furthermore, the present disclosure can refer to a number of different embodiments using the same reference numerals and / or letters. This repetition is for the purpose of simplicity and clarity and does not necessarily dictate a corresponding relationship between the various embodiments and / or configurations discussed.

[0088] Also, spatially relative terms, such as "beneath", "below", "lower", "on", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0089] It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers can be present.

[0090] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are only used to distinguish one element or component from another. Thus, a first element, component, or section discussed below could be termed a second element, component or section without departing from the teachings of the present disclosure.

[0091] Unless otherwise noted, the terms "same," "equal," "planar" or "co-planar" as used herein, when referring to orientation, layout, position, shape, size, number or other metric, do not necessarily mean exactly the same orientation, layout, position, shape, size, number or other metric, but rather mean that the orientation, layout, position, shape, size, number or other metric are nearly the same within an acceptable range of variation, which can be due to manufacturing processes, for example. The term "substantially" can be used herein to express such a meaning. For example, items described as "substantially the same," "substantially equal" or "substantially planar" can be exactly the same, equal or planar, or can be the same, equal or planar within an acceptable range of variation, which can be due to manufacturing processes.

[0092] In the present disclosure, a semiconductor device generally refers to a device that can operate using a semiconductor characteristic, and a photoelectric device, a light emitting display device, a semiconductor circuit, and an electronic device all fall within the category of a semiconductor device.

[0093] It should be noted that, in the description of the present disclosure, "on" (or above) corresponds to the direction of the Z-direction arrow, and "under" (or below) corresponds to the opposite direction of the Z-direction arrow.

[0094] According to an embodiment of the present disclosure, Figure 1 A manufacturing method 10 of a semiconductor device 1A is shown in the form of a flowchart. According to an embodiment of the present disclosure, Figures 2 to 19 A cross-sectional schematic view showing the flow of manufacturing the semiconductor device 1A is shown.

[0095] Referring to Figures 1 to 3 In step S11, a substrate 101 having a source region 105S and a drain region 105D is provided, a bottom cap layer 111 is formed on the substrate 101, and a plurality of word line trenches TR extending through the bottom cap layer 111 and into the substrate 101 are formed.

[0096] Referring to Figure 2 The substrate 101 can include a bulk semiconductor substrate. For example, the bulk semiconductor substrate can be formed of an elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductor or II-VI compound semiconductor; or a combination thereof.

[0097] Referring to Figure 2An isolation layer 103 is formed within the substrate 101. A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. An optical lithography process and a subsequent etching process, such as an anisotropic dry etching process, can be performed to form a trench through the pad oxide layer and the pad nitride layer and extending to the top surface 101TS of the substrate 101. An insulating material can be deposited within the trench, and a planarization process, such as a chemical mechanical polishing process, can be subsequently performed until the top surface 101TS of the substrate 101 is exposed to remove excess fill material, to provide a substantially planar surface for subsequent process steps, and to form the isolation layer 103. The insulating material can be, for example, silicon oxide or other suitable insulating material. In some embodiments, the isolation layer 103 can define an active area AA within the substrate 101.

[0098] Referring to Figure 2 An impurity region 105 is formed within the active area AA. In some embodiments, the impurity region 105 can be formed by an implantation process using P-type dopants or N-type dopants. The term "P-type dopants" refers to impurities that, when added to a intrinsic semiconductor material, create a positive electron vacancy. Examples of P-type dopants in silicon-containing semiconductor materials include, but are not limited to, boron, aluminum, gallium, and indium. The term "N-type dopants" refers to impurities that, when added to an intrinsic semiconductor material, contribute free electrons to the intrinsic semiconductor material. Examples of N-type dopants in silicon-containing materials include, but are not limited to, antimony, arsenic, and phosphorus.

[0099] Referring to Figure 2 A bottom cap layer 111 is formed on the substrate 101 to completely cover the impurity region 105 and the isolation layer 103. In some embodiments, the bottom cap layer 111 can be formed of a material that is etch-selective to the substrate 101 and the isolation layer 103. In some embodiments, the bottom cap layer 111 can be formed, for example, of silicon nitride, boron nitride, silicon boron nitride, phosphorus boron nitride, boron carbon silicon nitride, or a combination thereof. In some embodiments, the bottom cap layer 111 can be formed, for example, by chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0100] Referring to Figure 2 A first mask layer 701 is formed on the bottom cap layer 111. In some embodiments, the first mask layer 701 can be a photoresist layer and can include a pattern of the plurality of wordline trenches TR.

[0101] Referring to Figure 3The first mask layer 701 is used as a mask to perform a trench etching process to remove portions of the bottom cap layer 111, the impurity region 105, and the substrate 101, and simultaneously form a plurality of word line trenches TR. After the plurality of word line trenches TR are formed, the first mask layer 701 can be removed. The impurity region 105 can be divided into a plurality of sections. The section disposed between the isolation layer 103 and the word line trench TR can be referred to as a drain region 105D. The section disposed between two adjacent word line trenches TR can be referred to as a source region 105S. As shown in the cross-sectional view, the bottom cap layer 111 can be divided into a plurality of sections.

[0102] Referring to Figure 1 and Figures 4 to 6 In step S13, a plurality of word line dielectric layers 210 can be conformally formed on the plurality of word line trenches TR, and a plurality of bottom conductive portions 221 can be formed on the plurality of word line dielectric layers 210.

[0103] Referring to Figure 4 A first insulating material layer 511 is conformally formed on the bottom cap layer 111 and on the plurality of word line trenches TR. The first insulating material layer 511 can have a U-shaped cross-sectional profile in the plurality of word line trenches TR. That is, the first insulating material layer 511 can be conformally formed along the surfaces of the plurality of word line trenches TR. In some embodiments, the first insulating material layer 511 can have a thickness in a range from about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0104] In some embodiments, the first insulating material layer 511 can be formed by a thermal oxidation process. For example, the first insulating material layer 511 can be formed by oxidizing the surfaces of the plurality of word line trenches TR. In some embodiments, the first insulating material layer 511 can be formed by a deposition process such as chemical vapor deposition or atomic layer deposition. In some embodiments, after a polysilicon layer (not shown for clarity) is deposited, the first insulating material layer 511 can be formed by radical oxidation of the polysilicon layer. In some embodiments, after a silicon nitride layer (not shown for clarity) is deposited, the first insulating material layer 511 can be formed by radical oxidation of the silicon nitride layer. In some embodiments, the first insulating material layer 511 can include a material that is etch-selective to the bottom cap layer 111 and the substrate 101. In some embodiments, the first insulating material layer 511 can include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof.

[0105] In some embodiments, the high dielectric constant dielectric material may comprise a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, or a combination thereof. In some embodiments, the high dielectric constant dielectric material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon nitride, aluminum oxide, or a combination thereof.

[0106] See Figure 5 A first barrier material layer 521 is compliantly formed on the first insulating material layer 511. In some embodiments, the first barrier material layer 521 may be, for example, titanium nitride, titanium, or a combination thereof. In some embodiments, the first barrier material layer 521 may be, for example, titanium nitride. In some embodiments, the first barrier material layer 521 may be formed, for example, by atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other suitable deposition processes.

[0107] See Figure 5 A first conductive material layer 531 is formed on the first barrier material layer 521, completely filling the plurality of character line trenches TR. In some embodiments, the first conductive material layer 531 may be, for example, tungsten, cobalt, zirconium, tantalum, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), transition metal aluminum compounds, or combinations thereof. In some embodiments, the first conductive material layer 531 may be, for example, tungsten. In some embodiments, the first conductive material layer 531 may be formed, for example, by physical vapor deposition, sputtering, electroplating, electroless plating, chemical vapor deposition, or other suitable deposition processes.

[0108] See Figure 6 A planarization process, such as chemical mechanical polishing, is performed until the top surface 111TS of the bottom cap layer 111 is exposed to remove excess material, provide a generally flat surface for subsequent process steps, and transform the first insulating material layer 511 into a plurality of word line dielectric layers 210. The plurality of word line dielectric layers 210 may be formed respectively and correspondingly on a plurality of word line trenches TR.

[0109] See Figure 6 An etch-back process is performed to remove portions of the first barrier material layer 521 and the first conductive material layer 531. After the etch-back process, the first barrier material layer 521 is transformed into a plurality of bottom barrier layers 301, respectively and correspondingly on the plurality of character line dielectric layers 210. The first conductive material layer 531 is transformed into a plurality of bottom conductive portions 221, respectively and correspondingly on the plurality of bottom barrier layers 301.

[0110] For the sake of brevity, clarity and ease of description, only a character line dielectric layer 210, a bottom barrier layer 301 and a bottom conductive portion 221 are described.

[0111] See Figure 6In some embodiments, the top surface 210TS of the character line dielectric layer 210 and the top surface 111TS of the bottom capping layer 111 may be substantially coplanar. In some embodiments, the top surface 221TS of the bottom conductive portion 221 and the top surface 301TS of the bottom barrier layer 301 may be substantially coplanar. In some embodiments, the top surface 221TS of the bottom conductive portion 221 and the top surface 301TS of the bottom barrier layer 301 may be at different vertical heights (not shown).

[0112] In some embodiments, the upper segment of the word line dielectric layer 210 may have reduced thickness due to consumption during the etch-back process and / or the post-etch cleaning process. Therefore, the upper segment of the word line dielectric layer 210 is thinner than the lower segment. For illustration, the thickness T1 of the upper segment of the word line dielectric layer 210 may be less than the thickness T2 of the lower segment. In some embodiments, the thickness T1 of the upper segment of the word line dielectric layer 210 may begin from the top surface 210TS of the word line dielectric layer 210 and gradually increase as the distance from the substrate 101 decreases.

[0113] See Figure 1 , Figure 7 and Figure 8 In step S15, a plurality of intermediate barrier layers 303 are formed on a plurality of bottom conductive portions 221, and a first thickening material layer 541 is compliantly formed on the bottom cap layer 111, the plurality of character line dielectric layers 210 and the plurality of intermediate barrier layers 303.

[0114] See Figure 7 Multiple intermediate barrier layers 303 are formed respectively and correspondingly on multiple bottom conductive portions 221. For simplicity, clarity, and ease of description, only one intermediate barrier layer 303 is described. The intermediate barrier layer 303 may be formed in the character line trench TR, and the intermediate barrier layer 303 may also cover the bottom barrier layer 301. That is, as shown in the cross-sectional view, the bottom conductive portion 221 may be surrounded by the bottom barrier layer 301 and the intermediate barrier layer 303. In some embodiments, the intermediate barrier layer 303 may be formed, for example, of titanium nitride, titanium, or a combination thereof. In some embodiments, the intermediate barrier layer 303 may be formed, for example, of titanium nitride. In some embodiments, the intermediate barrier layer 303 may be formed of the same material as the bottom barrier layer 301. In some embodiments, the intermediate barrier layer 303 may be formed, for example, by radio frequency physical vapor deposition or other suitable deposition methods. In some embodiments, the thickness T3 of the bottom barrier layer 301 and the thickness T4 of the intermediate barrier layer 303 may be substantially the same. In some embodiments, the thickness T3 of the bottom barrier layer 301 may be different from the thickness T4 of the middle barrier layer 303.

[0115] It should be noted that the intermediate barrier layer 303 may be selectively formed on the bottom conductive portion 221 and the bottom barrier layer 301. The intermediate barrier layer 303 is not observable on the inner surface of the character line dielectric layer 210.

[0116] See Figure 8 A first thickening material layer 541 is compliantly formed on the bottom capping layer 111, the plurality of word line dielectric layers 210, and the plurality of intermediate barrier layers 303. In some embodiments, the first thickening material layer 541 formed in the word line trench TR may have a U-shaped profile because it conforms to the inner surface of the word line dielectric layer 210 and the top surface 303TS of the intermediate barrier layer 303. In some embodiments, the first thickening material layer 541 formed on the inner surface of the word line dielectric layer 210 may be tapered because it conforms to the inner surface of the word line dielectric layer 210. In some embodiments, the first thickening material layer 541 may be, for example, a material that has etch selectivity to the bottom capping layer 111. In some embodiments, the first thickening material layer 541 may be, for example, silicon oxide. In some embodiments, the first thickening material layer 541 may be formed, for example, by atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0117] See Figure 1 and Figures 9 to 11 In step S17, a plurality of top conductive portions 223 are formed on the first thickened material layer 541, and a second thickened material layer 543 is compliantly formed on the plurality of top conductive portions 223 and the first thickened material layer 541.

[0118] See Figure 9 A second conductive material layer 533, fully filling the character line trench TR, is formed on the first thickened material layer 541. In some embodiments, the second conductive material layer 533 may be, for example, polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or a combination thereof. In some embodiments, the second conductive material layer 533 may be doped with a P-type dopant or an N-type dopant. In some embodiments, the second conductive material layer 533 may be formed, for example, by chemical vapor deposition or other suitable deposition processes. In some embodiments, doping may be achieved by performing a placement process after the deposition process. In some embodiments, doping may be achieved by incorporating a dopant during the deposition process.

[0119] See Figure 10A subsequent etch-back process is performed to remove portions of the second conductive material layer 533 to form multiple top conductive portions 223. For simplicity, clarity, and ease of description, only one top conductive portion 223 is described. The top conductive portion 223 can be formed on the first thickened material layer 541 and in the character line trench TR. The bottom conductive portion 221 and the top conductive portion 223 together constitute the character line conductive layer 220.

[0120] In some embodiments, the upper segment of the first thickening material layer 541 formed on the word line dielectric layer 210 may be consumed during the etch-back process or during the post-cleaning process after the etch-back process. That is, the thickness of the aforementioned upper segment is reduced or the aforementioned upper segment is completely consumed, so that the upper segment of the word line dielectric layer 210 is partially exposed (not shown).

[0121] See Figure 11 A second thickened material layer 543 is compliantly formed on the first thickened material layer 541 and the plurality of top conductive portions 223. In some embodiments, because the second thickened material layer 543 conforms to the first thickened material layer 541, the second thickened material layer 543 formed in the character line trench TR may have a U-shaped cross-sectional profile. In some embodiments, a portion of the second thickened material layer 543 formed in the character line trench TR may be tapered. In some embodiments, the second thickened material layer 543 may be, for example, a material that has etch selectivity for the bottom capping layer 111. In some embodiments, the second thickened material layer 543 may be the same material as the first thickened material layer 541. In some embodiments, the second thickened material layer 543 may be, for example, silicon oxide. In some embodiments, the second thickened material layer 543 may be formed, for example, by atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0122] See Figure 12 A top insulating material layer 513 is formed on the second thickened material layer 543, completely filling the plurality of character line trenches TR. In some embodiments, the top insulating material layer 513 may be, for example, a material that has etch selectivity for the character line dielectric layer 210, the first thickened material layer 541, and the second thickened material layer 543. In some embodiments, the top insulating material layer 513 may be, for example, silicon nitride, boron nitride, boron phosphorus nitride, silicon carbide nitride, or a combination thereof. In some embodiments, the top insulating material layer 513 may be, for example, silicon nitride. In some embodiments, the top insulating material layer 513 may be formed, for example, by chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0123] See Figure 1 and Figures 13 to 15In step S19, a recessing process is performed to remove portions of the top insulating material layer 513, the second thickening material layer 543, and the first thickening material layer 541 to form a plurality of character line cover layers 230, a plurality of top thickening layers 403, and a plurality of bottom thickening layers 401.

[0124] In some embodiments, the recessing process can be a multi-stage etching process. For example, the recessing process can be a three-stage etching process. The etching chemicals in each stage can be different to provide different etching selectivity. In some embodiments, the recessing process can use phosphoric acid and diluted hydrofluoric acid alternately to selectively remove nitrides and oxides, respectively. In some embodiments, the recessing process can include gaseous hydrofluoric acid and ammonia. By adjusting the ratio of the amount of gaseous hydrofluoric acid and ammonia used in the recessing process, nitrides or oxides can be selectively etched.

[0125] See Figure 13 During the first stage of the recess process, the top insulating material layer 513 is selectively removed. A stop point can be established by detecting the second thickening material layer 543 and / or the first thickening material layer 541. In some embodiments, the first stage of the recess process may include using phosphoric acid to selectively remove the top insulating material layer 513 containing silicon nitride. After the first stage of the recess process, the remaining portion of the top insulating material layer 513 may be referred to as a plurality of word line capping layers 230. The word line dielectric layer 210, the word line conductive layer 220, and the word line capping layers 230 together constitute the word line structure 200.

[0126] See Figure 14 During the second stage of the recessing process, a first thickening material layer 541 and a second thickening material layer 543 formed on the bottom capping layer 111 are selectively removed. A stop point can be established by detecting the bottom capping layer 111. In some embodiments, the second stage of the recessing process may include using diluted hydrofluoric acid to selectively remove the first thickening material layer 541 and the second thickening material layer 543, which comprise silicon oxide. After performing the second stage of the recessing process, the remaining portion of the second thickening material layer 543 may be converted into the top thickening layer 403, while the remaining portion of the first thickening material layer 541 may be converted into the bottom thickening layer 401. In some embodiments, the thickness T5 of the bottom thickening layer 401 and the thickness T6 of the top thickening layer 403 may be substantially the same. In some embodiments, the thickness T5 of the bottom thickening layer 401 and the thickness T6 of the top thickening layer 403 may be different.

[0127] At the current stage, the vertical height of the top surface 230TS of the character line capping layer 230 can be higher than the vertical height of the top surface 401TS of the bottom thickening layer 401, or the vertical height of the top surface 403TS of the top thickening layer 403. The section of the character line capping layer 230 that is higher than the top surface 401TS of the bottom thickening layer 401 or the top surface 403TS of the top thickening layer 403 can be referred to as the protruding section 230P of the character line capping layer 230.

[0128] See Figure 15 During the third stage of the recessing process, protruding segments 230P of the character line capping layer 230 are selectively removed. The third stage may be implemented at predetermined time intervals. In some embodiments, the third stage of the recessing process may include using phosphoric acid to selectively remove the protruding segments 230P of the character line capping layer 230. In some embodiments, during the third stage of the recessing process, the character line dielectric layer 210, the bottom thickening layer 401, and the top thickening layer 403 may be slightly consumed, such that the top surfaces 210TS, 401TS, and 403TS of the character line dielectric layer 210, the bottom thickening layer 401, and the top thickening layer 403 are also recessed. In some embodiments, the character line dielectric layer 210, the bottom thickening layer 401, and the top thickening layer 403 may be slightly consumed during a cleaning process performed after the third stage of the recessing process.

[0129] In some embodiments, the top surfaces 210TS, 401TS, and 403TS of the character line dielectric layer 210, the bottom thickening layer 401, and the top thickening layer 403 may be substantially coplanar. In some embodiments, the top surface 111TS of the bottom capping layer 111 and the top surface 230TS of the character line capping layer 230 may be substantially coplanar. In some embodiments, the vertical height VL1 of the top surfaces 210TS, 401TS, and 403TS of the character line dielectric layer 210, the bottom thickening layer 401, and the top thickening layer 403 may be lower than the vertical height VL2 of the top surface 230TS of the character line capping layer 230. In some embodiments, the vertical height VL1 of the top surfaces 210TS, 401TS, and 403TS of the character line dielectric layer 210, the bottom thickening layer 401, and the top thickening layer 403 may be higher than the vertical height VL3 of the top surface 101TS of the substrate 101.

[0130] In some embodiments, the top surface 111TS of the bottom capping layer 111 and the top surface 230TS of the character line capping layer 230 may be at different vertical heights (not shown). However, the top surface 111TS of the bottom capping layer 111 and the top surface 230TS of the character line capping layer 230 are both at higher vertical heights than the top surfaces 210TS, 401TS, and 403TS of the character line dielectric layer 210, the bottom thickening layer 401, and the top thickening layer 403.

[0131] In some embodiments, the top surfaces 210TS, 401TS, and 403TS of the character line dielectric layer 210, the bottom thickening layer 401, and the top thickening layer 403 may be at different vertical heights (not shown). However, the vertical height of the top surfaces 210TS, 401TS, and 403TS of the character line dielectric layer 210, the bottom thickening layer 401, and the top thickening layer 403 is higher than the top surface 101TS of the substrate 101.

[0132] In some embodiments, the top surface 230TS of the character line capping layer 230 may be curved. In other words, the character line capping layer 230 may have an arc-shaped top surface 230TS. More specifically, the top surface 230TS of the character line capping layer 230 may include a flat section parallel to the top surface 101TS of the substrate 101, and both ends of this flat section smoothly transition to curved surfaces.

[0133] In some embodiments, the top surface 111TS of the bottom cover layer 111 is curved. In other words, the bottom cover layer 111 may have an arc-shaped top surface 111TS. More specifically, the top surface 111TS of the bottom cover layer 111 may include a flat section parallel to the top surface 101TS of the substrate 101, and its ends smoothly transition to curved surfaces.

[0134] In some prior art embodiments, reducing the thickness of the upper segment of the word line dielectric layer 210 during processes such as etch-back or cleaning can lead to gate-induced drain current. In contrast, in embodiments of this disclosure, the thickness of the word line dielectric layer 210 is increased by a bottom thickening layer 401 and a top thickening layer 403, thereby improving the insulation capability of the word line dielectric layer 210. This method effectively mitigates the problem of gate-induced drain current, thereby improving the performance of the semiconductor device 1A.

[0135] See Figure 1 and Figures 16 to 19 In step S21, a top cover layer 113 is formed on the substrate 101, and bit lines 601 and a plurality of unit contacts 603 are formed on the substrate 101.

[0136] See Figure 16A top capping layer 113 is formed on a substrate 101, covering a bottom capping layer 111, a word line dielectric layer 210, a bottom thickening layer 401, a top thickening layer 403, and a word line capping layer 230. In some embodiments, the top capping layer 113 may be formed, for example, of a material having etch selectivity for the word line dielectric layer 210, the bottom thickening layer 401, and the top thickening layer 403. In some embodiments, the top capping layer 113 may be formed, for example, of silicon nitride, boron nitride, boron phosphorus nitride, silicon borocarbon nitride, or a combination thereof. In some embodiments, the top capping layer 113 may be formed, for example, of silicon nitride. In some embodiments, the top capping layer 113 may be formed of the same material as the bottom capping layer 111. In some embodiments, the top capping layer 113 may be formed, for example, by chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. Planarization processes such as chemical mechanical polishing can be implemented to remove excess material and provide a generally flat surface for subsequent process steps.

[0137] See Figure 17 A bit line opening 601O is formed, passing through the top capping layer 113 and the bottom capping layer 111 and extending into the source region 105S. After forming the bit line opening 601O, a cleaning process can be performed to remove any residue remaining in the bit line opening 601O. In a comparative embodiment, without the top capping layer 113, the cleaning process may erode the word line dielectric layer 210, the bottom thickening layer 401, and the top thickening layer 403. Such erosion would create a risk of exposing the source region 105S and / or the drain region 105D. Therefore, a short circuit may occur when conductive material is deposited to form the bit line contact. In contrast, in this embodiment, the presence of the top capping layer 113 protects the word line dielectric layer 210, the bottom thickening layer 401, and the top thickening layer 403 during the cleaning process, thereby preventing short circuits.

[0138] See Figure 18A bit line 601 electrically connected to the source region 105S is formed within a bit line opening 601O. The bit line 601 may include a bit line contact 6011, a bit line bottom electrode 6013, a bit line top electrode 6015, a bit line masking pattern 6017, and a bit line spacer 6019. The bit line contact 6011 may be formed within the bit line opening 601O and on the source region 105S. The sidewalls of the bit line contact 6011 may be separable from the bottom capping layer 111 and the top capping layer 113. In some embodiments, the bit line contact 6011 may be formed of a conductive material such as doped polysilicon, metal, metal nitride, or metal silicide. The bit line bottom electrode 6013 may be formed on the bit line contact 6011. In some embodiments, the bit line bottom electrode 6013 may include doped polysilicon. A top electrode 6015 for a bitline may be formed on a bottom electrode 6013 for a bitline. In some embodiments, the top electrode 6015 may comprise a conductive material such as tungsten, aluminum, copper, nickel, or cobalt. A bitline masking pattern 6017 may be formed on the top electrode 6015. In some embodiments, the bitline masking pattern 6017 may comprise silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Bitline spacers 6019 may cover the sidewalls of the bitline masking pattern 6017, the sidewalls of the top electrode 6015, the sidewalls of the bottom electrode 6013, and the sidewalls of the bitline contact 6011. The sidewalls of the bitline spacers 6019, opposite to the sidewalls of the bitline contact 6011, may directly contact the bottom capping layer 111 and the top capping layer 113. Multiple bitline spacers 6019 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide.

[0139] See Figure 19 A plurality of unit contacts 603 are formed, passing through the top capping layer 113 and the bottom capping layer 111 and extending into the corresponding drain region 105D. Each unit contact 603 includes a lower portion 6031 protruding into the corresponding drain region 105D and an upper portion 6033 passing through the bottom capping layer 111 and the top capping layer 113 and formed on the top surface 101TS of the substrate 101. The lower portion 6031 of the unit contact 603 protruding into the substrate 101 increases the contact area between the unit contact 603 and the substrate 101. As a result, the contact resistance can be effectively reduced. A plurality of unit contacts 603 can be formed on the plurality of drain regions 105D respectively and correspondingly. In some embodiments, the plurality of unit contacts 603 may be formed, for example, of tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof. Multiple unit contacts 603 can be electrically connected to multiple drain regions 105D respectively and accordingly.

[0140] The lower portion 6031 of the unit contact 603 below the top surface 101TS of the substrate 101 may have a first critical dimension CD1, while the upper portion 6033 of the unit contact 603 above the top surface 101TS of the substrate 101 may have a second critical dimension CD2, and the second critical dimension CD2 is larger than the first critical dimension CD1. In some embodiments, the first critical dimension CD1 gradually decreases with increasing distance from the top surface 101TS of the substrate 101, while the second critical dimension CD2 remains constant. In particular, the surrounding surface 6032 of the lower portion 6031 of the unit contact 603 is discontinuous with the surrounding surface 6034 of the upper portion 6033 of the unit contact 603. It is worth noting that the lower portion 6031 and the upper portion 6033 of the unit contact 603 are formed integrally and contain polysilicon.

[0141] According to some embodiments of this disclosure Figures 20 to 22 Showing cross-sectional schematic diagrams of semiconductor devices 1B, 1C, and 1D.

[0142] See Figure 20 Semiconductor device 1B has the same characteristics as... Figure 19 Similar structures. Figure 20 Zhongyu Figure 19 Identical or similar elements are marked with similar reference symbols, and repeated descriptions are omitted.

[0143] See Figure 20 Only the top thickening layer 403 exists. The top conductive portion 223 may be disposed on the intermediate barrier layer 303. The character line cover layer 230 may be disposed on the top conductive portion 223. The top thickening layer 403 may be disposed between the top conductive portion 223 and the character line cover layer 230, and between the character line dielectric layer 210 and the character line cover layer 230.

[0144] See Figure 21 Semiconductor device 1C has the same characteristics as Figure 19 Similar structures. Figure 21 Zhongyu Figure 19 Identical or similar elements are marked with similar reference symbols, and repeated descriptions are omitted.

[0145] See Figure 21 Only the bottom thickening layer 401 exists. The character line cover layer 230 can be disposed on the top conductive portion 223. The bottom thickening layer 401 can be disposed between the intermediate barrier layer 303 and the top conductive portion 223, between the top conductive portion 223 and the character line dielectric layer 210, and between the character line cover layer 230 and the character line dielectric layer 210.

[0146] See Figure 22 Semiconductor device 1D has the same characteristics as Figure 19 Similar structures. Figure 22 ZhongyuFigure 19 Identical or similar elements are marked with similar reference symbols, and repeated descriptions are omitted.

[0147] In semiconductor device 1D, the upper segment of word line dielectric layer 210 is formed before the bottom thickening layer 401 and the top thickening layer 403 (e.g., in...). Figure 6 During the etch-back process shown, the source region 105S and drain region 105D are completely consumed, exposing the bottom thickening layer 401 during its formation. Therefore, the bottom thickening layer 401 can be disposed between the intermediate barrier layer 303 and the top conductive portion 223, between the lower segment of the word line dielectric layer 210 and the top conductive portion 223, and between the top thickening layer 403 and the source region 105S (and drain region 105D).

[0148] One aspect of this disclosure provides a semiconductor device comprising a substrate including a source region and a drain region; a word line structure including a word line dielectric layer located within the substrate and having a U-shaped cross-sectional profile, a word line conductive layer located on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer having a U-shaped cross-sectional profile located between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer located on the substrate and adjacent to the word line dielectric layer; a top capping layer covering the bottom capping layer and the word line structure; a bit line passing through the top capping layer and the bottom capping layer and extending into the source region; and a cell contact passing through the top capping layer and the bottom capping layer and extending into the drain region. The top surface of the top thickening layer is substantially coplanar with the top surface of the character line dielectric layer, and the vertical height of the top surface of the layer is higher than the vertical height of the top surface of the substrate.

[0149] One aspect of this disclosure provides a semiconductor device comprising a substrate including a source region and a drain region; a word line structure including a word line dielectric layer located within the substrate and having a U-shaped cross-sectional profile; a word line conductive layer including a bottom conductive portion located on the word line dielectric layer and within the substrate, and a top conductive portion located on the bottom conductive portion and within the substrate; and a word line capping layer located on the word line conductive layer; and a bottom thickening layer including a U-shaped cross-section. The substrate includes a bottom conductive layer located between the bottom conductive layer and the top conductive layer, between the top conductive layer and the character line dielectric layer, and between the character line capping layer and the character line dielectric layer; a bottom capping layer located on the substrate and adjacent to the character line dielectric layer; a top capping layer covering the bottom capping layer and the character line structure; a character line passing through the top and bottom capping layers and extending into the source region; and a cell contact passing through the top and bottom capping layers and extending into the drain region. A top surface of the bottom thickened layer is substantially coplanar with a top surface of the character line dielectric layer, and its vertical height is higher than a vertical height of a top surface of the substrate.

[0150] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising providing a substrate having a source region and a drain region, forming a bottom capping layer on the substrate, and forming a word line trench that extends through the bottom capping layer and protrudes into the substrate; conformally forming a word line dielectric layer on the word line trench; forming a bottom conductive portion on the word line dielectric layer and in the word line trench; conformally forming a first thickening material layer on the bottom conductive portion, the word line dielectric layer, and the bottom capping layer; forming a top conductive portion on the first thickening material layer and in the word line trench; and conformally forming a second thickening material layer on the top conductive portion and the first thickening material layer. Material layer; a top insulating material layer is formed on the second thickened material layer to completely fill the character line trench; portions of the second thickened material layer, the first thickened material layer, and the top insulating material layer are removed to form a top thickened layer, a bottom thickened layer, and a character line capping layer, respectively, while the character line dielectric layer is recessed; a top capping layer is formed covering the bottom capping layer, the character line dielectric layer, the character line capping layer, the bottom thickened layer, and the top thickened layer; a character line is formed corresponding to the source region, passing through the top capping layer and the bottom capping layer and extending into the source region; and a cell contact is formed corresponding to the drain region, passing through the top capping layer and the bottom capping layer and extending into the drain region.

[0151] Due to the design of the semiconductor device disclosed herein, the thickness of the word line dielectric layer is increased by adding a bottom thickening layer and / or a top thickening layer to effectively mitigate the problem of gate-induced drain leakage current, thereby improving the performance of the semiconductor device. Furthermore, the top cap layer masks the word line dielectric layer, the bottom thickening layer, and the top thickening layer during etching and / or cleaning processes. This masking avoids recessing the word line dielectric layer, the bottom thickening layer, and the top thickening layer, and avoids potential exposure of the drain and source regions, thereby preventing short circuits that may occur due to such exposure.

[0152] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0153] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device, comprising: A substrate, comprising a source region and a drain region; A single-character line structure includes: A single-character line dielectric layer is located within the substrate and includes a U-shaped cross-sectional profile. A word line conductive layer, located on the word line dielectric layer and in the substrate; and A character line capping layer is located on the conductive layer of the character line; A top thickening layer, including a U-shaped profile, is located between the character line conductive layer and the character line capping layer, and between the character line dielectric layer and the character line capping layer. A bottom cap layer is located on the substrate and adjacent to the character line dielectric layer; A top capping layer that covers the bottom capping layer and the character line structure; A source line passes through the top capping layer and the bottom capping layer, and extends into the source region; and A unit contact extends through the top cap layer and the bottom cap layer and into the drain region, wherein a top surface of the top thickened layer is substantially coplanar with a top surface of the character line dielectric layer and is at a vertical height higher than a vertical height of a top surface of the substrate.

2. The semiconductor device of claim 1, wherein a vertical height of a top surface of the character line capping layer is higher than the vertical height of the top surface of the top thickening layer.

3. The semiconductor device of claim 2, wherein the top surface of the character line capping layer is curved.

4. The semiconductor device of claim 1, wherein a vertical height of the top surface of the bottom cap layer is higher than the vertical height of the top surface of the top thickening layer.

5. The semiconductor device of claim 4, wherein the top surface of the bottom cap layer and a top surface of the character line cap layer are substantially coplanar.

6. The semiconductor device of claim 4, wherein the top surface of the bottom cap layer is curved.

7. The semiconductor device of claim 1, further comprising a bottom barrier layer located between the word line conductive layer and the word line dielectric layer.

8. The semiconductor device of claim 1, wherein the character line conductive layer comprises: A bottom conductive portion is located on the character line dielectric layer and in the substrate; as well as A top conductive portion is located on the bottom conductive portion and within the substrate. The top thickening layer is located between the top conductive portion and the character line cover layer.

9. The semiconductor device of claim 8, further comprising an intermediate barrier layer located between the bottom conductive portion and the top conductive portion.

10. The semiconductor device of claim 8, wherein the bottom conductive portion comprises tungsten, cobalt, zirconium, tantalum, aluminum, ruthenium, copper, metal carbides, transition metal aluminum dies, or combinations thereof.

11. The semiconductor device of claim 8, wherein the top conductive portion comprises polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or a combination thereof.

12. The semiconductor device of claim 9, wherein the intermediate barrier layer comprises titanium nitride, titanium, or a combination thereof.

13. The semiconductor device of claim 1, wherein the bit line comprises: One-element line contact; One-element line bottom electrode; Top electrode of a single-element line; One-dimensional line masking pattern; and One-dimensional gap material, The bit line contact is disposed on the source region. The sidewall of the bit line contact is separated from the bottom capping layer and the top capping layer. The bottom electrode of the bit line is disposed on the bit line contact. The top electrode of the bit line is disposed on the bottom electrode of the bit line. The bit line masking pattern is disposed on the top electrode of the bit line. The bit line spacer covers the sidewalls of the bit line masking pattern, the sidewalls of the top electrode, the sidewalls of the bottom electrode, and the sidewalls of the bit line contact. The sidewall of the bit line spacer, which is opposite to the sidewalls of the bit line contact, contacts the bottom capping layer and the top capping layer.

14. The semiconductor device of claim 13, wherein the bit line contact is formed of a conductive material, such as doped polysilicon, metal, metal nitride, or metal silicide.

15. The semiconductor device of claim 13, wherein the bottom electrode of the bit line is formed of doped polycrystalline silicon.

16. The semiconductor device of claim 13, wherein the top electrode of the bit line is formed of a conductive material, such as tungsten, aluminum, copper, nickel, or cobalt.

17. The semiconductor device of claim 13, wherein the bit line mask pattern is formed of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride.

18. The semiconductor device of claim 13, wherein the bit line interstitial material is formed of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride.

19. The semiconductor device of claim 1, wherein the cell contact includes a lower portion protruding into the corresponding drain region and an upper portion extending through the bottom capping layer and the top capping layer.

20. The semiconductor device of claim 19, wherein the lower portion of the unit contact has a first critical dimension, and the upper portion of the unit contact has a second critical dimension larger than the first critical dimension.

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