Shield gate trench device and manufacturing method thereof

Abstract

The invention provides a shield gate trench device and a manufacturing method thereof, and the method comprises the steps: after a composite dielectric layer is etched back through wet etching, an adjustment dielectric layer is formed firstly, the adjustment dielectric layer at least covers the etched composite dielectric layer, the lowest point of the top surface of the adjustment dielectric layer is higher than the top surface of a first dielectric layer, and then the adjustment dielectric layer is etched back to obtain a dielectric layer with the flush top surface; the subsequently formed control gate layer is positioned above the shield gate layer or on two sides of the shield gate layer and is provided with a flush bottom surface. According to the manufacturing method of the shield gate trench device, a deposition and etch-back process for adjusting the dielectric layer is added after etch-back of the composite dielectric layer and before manufacturing of the control gate layer, due to the fact that the etching rate of the same material is the same and the top surface of the dielectric layer obtained after etching is completed is flush, beveled edges of the subsequent control gate layer can be avoided, stray capacitance is reduced, and the performance of the shield gate trench device is improved. And the process does not need to add a photomask, so that the production cost is reduced and the reliability risk is avoided. The shield gate trench device obtained by the invention has lower parasitic capacitance and higher reliability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a shielded gate trench device and its fabrication method. Background Technology

[0002] The Shielded Gate Trench (SGT) structure is an advanced MOSFET technology that uses a deep trench process to add a shielding electrode below the gate electrode, connected to the source electrode, to shield the gate and drift region, thereby reducing Miller capacitance and gate charge, accelerating switching speed, and reducing switching losses.

[0003] Compared to schemes using a single-material dielectric layer for the shielding gate dielectric layer, using a composite material for the shielding gate dielectric layer introduces a material with a high dielectric constant (high k), which is beneficial for improving the breakdown voltage (BV) and reducing the gate leakage current (Ig). However, due to the fact that the insulating layer is made of composite material, the etching process of the composite layer in the current process results in unevenness at the top of the composite layer because the etching solution etches at different rates on each layer of the composite layer. This causes a bevel at the bottom of the subsequently deposited gate electrode, which increases the gate leakage capacitance (Cgd) of the device and leads to device performance degradation.

[0004] To avoid the above situation, an additional photomask is needed for etching to make the top of the composite dielectric layer flat and avoid the bottom of the gate electrode formed later having a bevel. However, this will increase the cost and increase the risk to device reliability.

[0005] Therefore, how to improve the fabrication process of shielded gate trench devices to reduce the parasitic capacitance of the final SGT and improve device reliability has become an important technical problem that needs to be solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a shielded gate trench device and its manufacturing method, which solves the problem in the prior art where the unevenness of the top of the composite insulating layer causes the gate electrode to have a beveled edge, increasing parasitic capacitance.

[0008] To achieve the above and other related objectives, the present invention provides a method for manufacturing a shielding trench device, comprising the following steps:

[0009] A substrate is provided, and trenches are formed in the substrate;

[0010] A composite dielectric layer and a shielding gate layer are formed. The composite dielectric layer conformally covers the top surface of the substrate and the inner wall of the trench and includes a first dielectric layer and a second dielectric layer stacked sequentially. The shielding gate layer is located in the trench and is separated from the inner wall of the trench by the composite dielectric layer. The dielectric constant of the first dielectric layer is higher than that of the second dielectric layer.

[0011] The composite dielectric layer is etched back using a wet etching process until a portion of the sidewall of the trench is exposed. The top surface of the first dielectric layer after the etch back is higher than the top surface of the second dielectric layer after the etch back.

[0012] An adjustment medium layer is formed in the trench, the adjustment medium layer at least covers the composite medium layer after the etch, and the lowest point of the top surface of the adjustment medium layer is higher than the top surface of the first medium layer;

[0013] The adjusted dielectric layer is re-etched to obtain a dielectric layer with a flush top surface;

[0014] A control gate dielectric layer and a control gate layer are formed in the trench. The control gate layer is located above or on both sides of the shielding gate layer and has a flush bottom surface. The control gate dielectric layer is sandwiched between the outer wall of the control gate layer and the inner wall of the trench.

[0015] Optionally, after the composite dielectric layer is etched back, the top surface of the shielding gate layer and the top of the trench have a preset height difference;

[0016] In the step of forming an adjustment medium layer in the trench, the adjustment medium layer covers the etched composite medium layer and the shielding gate layer;

[0017] In the step of re-etching the adjustment dielectric layer to obtain a dielectric layer with a flush top surface, the re-etched adjustment dielectric layer covers the composite dielectric layer and the shielding grid layer and has a flush top surface. The dielectric layer with a flush top surface is composed of the re-etched adjustment dielectric layer and its top surface is higher than the top surface of the shielding grid layer.

[0018] In the step of forming the control gate dielectric layer and the control gate layer in the trench, the control gate layer is located above the shielding gate layer.

[0019] Optionally, after the composite dielectric layer is etched back, the top surface of the shielding gate layer is higher than the top surface of the first dielectric layer;

[0020] In the step of forming the adjustment medium layer in the trench, the adjustment medium layer is located on both sides of the shielding gate layer and covers the composite medium layer after the etch-back;

[0021] In the step of re-etching the adjustment medium layer to obtain a medium layer with a flush top surface, the re-etched adjustment medium layer covers the composite medium layer and has a flush top surface, and the medium layer with a flush top surface is composed of the re-etched adjustment medium layer.

[0022] In the step of forming the control gate dielectric layer and the control gate layer in the trench, the control gate layer is located on both sides of the shielding gate layer.

[0023] Optionally, after the composite dielectric layer is etched back, the top surface of the shielding gate layer is higher than the top surface of the first dielectric layer;

[0024] In the step of forming the adjustment medium layer in the trench, the adjustment medium layer is located on both sides of the shielding gate layer and covers the composite medium layer after the etch-back;

[0025] In the step of re-etching the adjustment medium layer to obtain a medium layer with a flush top surface, the re-etched adjustment medium layer is inserted between the first medium layer and the shielding gate layer, and the re-etched adjustment medium layer is flush with the top surface of the first medium layer. The medium layer with a flush top surface is composed of the first medium layer and the adjustment medium layer.

[0026] In the step of forming the control gate dielectric layer and the control gate layer in the trench, the control gate layer is located on both sides of the shielding gate layer.

[0027] Optionally, in the step of wet etching back the composite dielectric layer until a portion of the sidewalls of the trench is exposed, and in the step of etching back the adjustment dielectric layer to obtain a dielectric layer with a flush top surface, the same photomask is used to open the etched area.

[0028] Optionally, the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

[0029] Optionally, the material of the adjustment medium layer includes silicon oxide.

[0030] Optionally, the method used to re-etch the adjustment medium layer includes wet etching.

[0031] Optionally, the method further includes the following steps: forming a body region, a source region, and a source metal layer, wherein the body region is located on the upper surface of the substrate on both sides of the trench, the source region is located on the upper surface of the body region, and the source metal layer is located above the trench and electrically connected to the body region and the source region.

[0032] The present invention also provides a shielding trench device, comprising:

[0033] Substrate;

[0034] Trench, located in the substrate;

[0035] A shielding grid layer and a control grid layer are located in the trench and spaced apart, the control grid layer having a flush bottom surface;

[0036] A shielding grid dielectric layer is sandwiched between the outer wall of the shielding grid layer and the inner wall of the trench. The shielding grid dielectric layer is a composite dielectric layer and includes a first dielectric layer and a second dielectric layer stacked in sequence. The dielectric constant of the first dielectric layer is higher than that of the second dielectric layer.

[0037] A control gate dielectric layer is sandwiched between the outer wall of the control gate layer and the inner wall of the trench.

[0038] The shielding trench device is formed using the fabrication method of the shielding trench device described in any of the above schemes.

[0039] As described above, the fabrication method of the shielding trench device of the present invention, after wet etching back the composite dielectric layer, first forms an adjustment dielectric layer. This adjustment dielectric layer at least covers the etched composite dielectric layer, and its lowest point is higher than the top surface of the first dielectric layer. Then, the adjustment dielectric layer is etched back to obtain a dielectric layer with a flush top surface. The subsequently formed control gate layer is located above or to both sides of the shielding trench layer and has a flush bottom surface. The fabrication method of the shielding trench device of the present invention adds a deposition and etch-back step of the adjustment dielectric layer after the composite dielectric layer is etched back and before the control gate layer is fabricated. Because the etching rate of the same material is the same, after etching, the top surface of the resulting dielectric layer is flush, which can avoid the appearance of beveled edges in the subsequent control gate layer, thereby reducing parasitic capacitance. Furthermore, this deposition and etch-back of the adjustment dielectric layer does not require an additional photomask, which helps to reduce production costs and avoid reliability risks. The shielding trench device obtained by the present invention has lower parasitic capacitance and higher reliability. Attached Figure Description

[0040] Figure 1 The diagram shows a cross-sectional view of a shielding trench device.

[0041] Figure 2 The diagram shows a cross-sectional structure of another type of shielded trench device.

[0042] Figure 3 The diagram shows a process flow chart of the method for manufacturing the shielding trench device of the present invention.

[0043] Figure 4 The diagram shown is a schematic diagram of the structure obtained after forming a trench in a substrate in Example 1, which illustrates the fabrication method of the shielding trench device of the present invention.

[0044] Figure 5 The diagram shown is a schematic diagram of the structure obtained after forming a composite dielectric layer and a shielding grid layer in Example 1 of the method for fabricating the shielding grid trench device of the present invention.

[0045] Figure 6 The diagram shown is a schematic diagram of the structure obtained after etching back the composite dielectric layer in Example 1, which is a method for fabricating the shielding trench device of the present invention.

[0046] Figure 7 The diagram shown illustrates the structure obtained after forming the adjustment dielectric layer in Example 1 of the method for fabricating the shielding trench device of the present invention.

[0047] Figure 8 The diagram shown illustrates the structure obtained after re-etching and adjusting the dielectric layer in Example 1 of the fabrication method of the shielding trench device of the present invention.

[0048] Figure 9 The diagram shown is a schematic diagram of the structure obtained after forming the control gate dielectric layer and the control gate layer in Embodiment 1, which is a method for fabricating the shielding gate trench device of the present invention.

[0049] Figure 10 The diagram shown is a schematic diagram of the structure obtained after forming the source metal layer in Example 1 of the method for fabricating the shielding trench device of the present invention.

[0050] Figure 11 The diagram shown is a schematic of the structure obtained after etching back the composite dielectric layer in Example 2 of the method for fabricating the shielding trench device of the present invention.

[0051] Figure 12 The diagram shown is a schematic diagram of the structure obtained after forming the adjustment dielectric layer in Example 2 of the method for manufacturing the shielding trench device of the present invention.

[0052] Figure 13 The diagram shown is a schematic diagram of the structure obtained after re-etching and adjusting the dielectric layer in Example 2 of the method for fabricating the shielding trench device of the present invention.

[0053] Figure 14 The diagram shown is a schematic diagram of the structure obtained after forming the control gate dielectric layer and the control gate layer in Example 2 of the method for fabricating the shielding gate trench device of the present invention.

[0054] Figure 15 The diagram shown is a schematic diagram of the structure obtained after forming the source metal layer in Example 2 of the method for fabricating the shielding trench device of the present invention.

[0055] Figure 16 The diagram shown is a structural schematic of the shielding trench device formed in Example 3 of the method for manufacturing the shielding trench device of the present invention.

[0056] Explanation of reference numerals in the attached figures

[0057] 101、201 Shielding grid 102、202 Control gate layer 103、203 First dielectric layer 104、204 Second dielectric layer S1~S6 step 301 substrate 302 trench 303 First dielectric layer 304 Second dielectric layer 305 Shielding grid 306 Adjusting the medium layer 307 A dielectric layer with a flush top surface 308 Control gate dielectric layer 309 Control gate layer 310 Body area 311 Source region 312 Interlayer dielectric layer 313 Contact hole 314 Source metal layer Detailed Implementation

[0058] Please see Figure 1 The diagram shows a cross-sectional view of a shielded gate trench device, including a shielded gate layer 101 and control gate layers 102 located on both sides of the shielded gate layer 101. The shielded gate dielectric layer includes a first dielectric layer 103 and a second dielectric layer 104. The first dielectric layer 103 is made of a high-k material. Compared to a single-material dielectric layer, the use of a composite material in the shielded gate dielectric layer introduces a high-k material, which is beneficial for improving breakdown voltage and reducing gate leakage current. However, due to the insulating layer being made of a composite material, during wet etching of the composite layer, the different etching rates of the etching solution on each layer of the composite dielectric layer result in an uneven top surface. This leads to a beveled bottom edge on the subsequently deposited control gate layer 102, increasing the gate leakage capacitance of the device and causing performance degradation.

[0059] Please see Figure 2 The diagram shows a cross-sectional view of another type of shielded gate trench device, including a shielded gate layer 201 and control gate layers 202 located on both sides of the shielded gate layer 201. The shielded gate dielectric layer includes a first dielectric layer 203 and a second dielectric layer 204. During the fabrication of this structure, an additional photomask is added to etch the uneven top of the composite dielectric layer, making the top of the composite dielectric layer flat and thus eliminating the beveled edge phenomenon at the bottom of the control gate layer. However, the addition of the photomask increases the cost and also increases the risk to device reliability.

[0060] Through extensive analysis and research, the inventors of this application have improved the manufacturing process of the shielded gate trench device, which can eliminate the slanted edge phenomenon at the bottom of the control gate layer without adding a photomask. This not only reduces the parasitic capacitance of the device, but also reduces production costs and avoids reliability risks.

[0061] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0062] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0063] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0064] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0065] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0066] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0067] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0068] Example 1

[0069] This invention provides a method for manufacturing a shielded trench device. Please refer to [link / reference]. Figure 3 The diagram shows the process flow of this method, which includes the following steps:

[0070] S1: Provide a substrate and form trenches in the substrate;

[0071] S2: Form a composite dielectric layer and a shielding gate layer. The composite dielectric layer conformally covers the top surface of the substrate and the inner wall of the trench and includes a first dielectric layer and a second dielectric layer stacked sequentially. The shielding gate layer is located in the trench and is separated from the inner wall of the trench by the composite dielectric layer. The dielectric constant of the first dielectric layer is higher than that of the second dielectric layer.

[0072] S3: The composite dielectric layer is etched back using a wet etching process until a portion of the sidewall of the trench is exposed. The top surface of the first dielectric layer after the etch back is higher than the top surface of the second dielectric layer after the etch back.

[0073] S4: An adjustment medium layer is formed in the trench, the adjustment medium layer at least covers the composite medium layer after the etch, and the lowest point of the top surface of the adjustment medium layer is higher than the top surface of the first medium layer;

[0074] S5: Re-etch the adjusted dielectric layer to obtain a dielectric layer with a flush top surface;

[0075] S6: A control gate dielectric layer and a control gate layer are formed in the trench. The control gate layer is located above or on both sides of the shielding gate layer and has a flush bottom surface. The control gate dielectric layer is sandwiched between the outer wall of the control gate layer and the inner wall of the trench.

[0076] The following section details the specific implementation methods of each of the above steps, using the structural diagram as an example.

[0077] Please refer to the following first. Figure 4 Perform step S1: Provide a substrate 301 and form a trench 302 in the substrate 301.

[0078] Specifically, the substrate 301 may be a silicon substrate or other suitable semiconductor substrate. In some embodiments, the substrate 301 may include an N-type base layer and an N-type epitaxial layer located on the N-type base layer. The doping concentration of the N-type epitaxial layer is lower than that of the N-type base layer. The trench 302 is formed in the N-type epitaxial layer. The thickness and doping concentration of the N-type epitaxial layer determine the breakdown voltage of the device, and the depth of the trench 302 determines the channel length and breakdown voltage. The specific design can be tailored to actual needs.

[0079] As an example, forming the trench 302 includes the following steps:

[0080] (1) A hard mask layer is formed on the substrate 301, wherein the hard mask layer may be one or a combination of silicon oxide layer and silicon nitride layer;

[0081] (2) The hard mask layer 103 is patterned through steps such as coating, exposure, development and etching to obtain a window pattern corresponding to the trench;

[0082] (3) The substrate 301 is etched based on the patterned hard mask layer to obtain the trench 302. The specific etching method used includes, but is not limited to, deep reactive ion etching (DRIE), which has both high anisotropy and high etching rate, and helps to avoid excessive tilting of the trench sidewalls.

[0083] Please refer to the following. Figure 5 Step S2 is performed: a composite dielectric layer and a shielding gate layer 305 are formed. The composite dielectric layer conformally covers the top surface of the substrate 301 and the inner wall of the trench 302 and includes a first dielectric layer 303 and a second dielectric layer 304 stacked sequentially. The shielding gate layer 305 is located in the trench 302 and is separated from the inner wall of the trench 302 by the composite dielectric layer. The dielectric constant of the first dielectric layer 303 is higher than that of the second dielectric layer 304.

[0084] In some embodiments, the dielectric constant of the first dielectric layer 303 is greater than 3.9, and may include a hafnium oxide layer, a silicon oxynitride layer, an aluminum oxide layer, a doped rare earth oxide layer or other suitable high-k dielectric layer. The second dielectric layer 304 may be a silicon oxide layer or a high-k dielectric layer with a dielectric constant lower than that of the first dielectric layer 303.

[0085] In some embodiments, the thickness of the first dielectric layer 303 is greater than the thickness of the second dielectric layer 304.

[0086] In some embodiments, the thickness of the second dielectric layer 304 does not exceed 6 kiloangs.

[0087] Please see again Figure 6 Then, perform step S3: use wet etching to re-etch the composite dielectric layer until a portion of the sidewall of the trench 302 is exposed, and the top surface of the first dielectric layer 303 after re-etching is higher than the top surface of the second dielectric layer 304 after re-etching.

[0088] As an example, etching back the composite dielectric layer includes the following steps:

[0089] (1) A mask layer is formed above the substrate 301, the mask layer covering the composite dielectric layer and the shielding gate layer 305;

[0090] (2) Provide a photomask, and pattern the mask layer based on the photomask to open the area that needs to be etched back, such as the area where the trench 302 is located;

[0091] (3) Perform wet etching to lower the top surface of the composite dielectric layer to a preset height.

[0092] Specifically, during the wet etching process, because the composite dielectric layer is composed of different materials and the etching rates of different materials are different, the top surface of the composite dielectric layer is uneven after the re-etching, that is, there is a height difference between the top surfaces of the first dielectric layer 303 and the second dielectric layer 304.

[0093] Specifically, during the wet etching process, a portion of the shielding gate layer 305 will also be lost. The degree of loss of the shielding gate layer 305 can be controlled by adjusting the etching time.

[0094] In some embodiments, after the composite dielectric layer is etched back, the top surface of the shielding grid layer 305 and the top end of the trench 302 have a preset height difference, so as to facilitate the subsequent formation of the upper and lower structure of the trench grid, that is, to control the grid layer to be located above the shielding grid layer.

[0095] Please see again Figure 7 Step S4 is performed: an adjustment medium layer 306 is formed in the trench 302, the adjustment medium layer 306 at least covers the composite medium layer after the etch, and the lowest point of the top surface of the adjustment medium layer 306 is higher than the top surface of the first medium layer 303.

[0096] In this embodiment, the adjustment medium layer 306 covers the composite medium layer and the shielding gate layer 305 after the etched back.

[0097] In some embodiments, the material of the adjustment dielectric layer 306 includes silicon oxide.

[0098] In some embodiments, the method for forming the adjusted dielectric layer 306 can be low-pressure chemical vapor deposition (LPCVD), high-density plasma chemical vapor deposition (HDP), or high aspect ratio process (HARP). LPCVD is performed in a vacuum environment below atmospheric pressure, where a gaseous precursor undergoes a chemical reaction on a heated front layer surface to deposit a solid film. The vacuum environment reduces the probability of gas-phase reactions, improving film uniformity and step coverage. HDP utilizes high-density plasma (with an electron density much higher than traditional plasma CVD) to activate the gaseous precursor, simultaneously performing deposition reactions and ion sputtering etching on the front layer surface, achieving a dynamic balance of deposition-etching-redeposition. It combines high step coverage and gap filling capabilities, enabling void-free high aspect ratio structure filling. HARP is an optimized CVD process technology that achieves defect-free filling of ultra-high aspect ratio structures by precisely controlling precursor flow rate, plasma parameters, deposition temperature, etc., avoiding the bottleneck effect and voids that occur in traditional CVD processes.

[0099] Specifically, the adjustment that the lowest point of the top surface of the dielectric layer 306 is higher than the top surface of the first dielectric layer 303 is to fill the height difference between the top surfaces of the first dielectric layer 303 and the second dielectric layer 304, and to provide a basis for subsequent re-etching.

[0100] Please see again Figure 8 Then, perform step S5: re-etch the adjustment dielectric layer 306 to obtain a dielectric layer 307 with a flush top surface.

[0101] In this embodiment, the adjusted dielectric layer 306 after being etched back covers the composite dielectric layer and the shielding gate layer 305 and has a flush top surface. The dielectric layer 307 with a flush top surface is composed of the adjusted dielectric layer 306 after being etched back and has a top surface higher than the top surface of the shielding gate layer 305. The dielectric layer 307 with a flush top surface serves as an inter-gate dielectric layer (IPO) to isolate the shielding gate layer 305 from the subsequently formed control gate layer.

[0102] Specifically, the adjustment medium layer 306 after the re-etching has a flush top surface because the adjustment medium layer 306 is made of a single material. During the re-etching process, the etching rate of the same material is the same. After the etching is completed, the top surface of the resulting medium layer is flush.

[0103] As an example, re-etching the adjustment medium layer 306 includes the following steps:

[0104] (1) A mask layer is formed above the substrate 301, the mask layer covering the adjustment medium layer 306;

[0105] (2) Provide a photomask, and pattern the mask layer based on the photomask to open the area that needs to be etched back, for example, open the area where the trench 302 is located;

[0106] (3) Perform wet etching to lower the top surface of the adjustment dielectric layer 306 to a preset height and obtain a dielectric layer 307 with the top surface flush.

[0107] Specifically, the photomask used for the etch-back of the adjustment dielectric layer in this step is the same as the photomask used for the etch-back of the composite dielectric layer mentioned above. In other words, the deposition and etch-back of the adjustment dielectric layer 306 in this invention does not require the addition of a new photomask, which helps to reduce production costs and avoid reliability risks.

[0108] Please see again Figure 9 Step S6 is performed: a control gate dielectric layer 308 and a control gate layer 309 are formed in the trench 302. The control gate layer 309 is located above the shielding gate layer 305 and has a flush bottom surface. The control gate dielectric layer 308 is sandwiched between the outer wall of the control gate layer 309 and the inner wall of the trench 302.

[0109] As an example, forming the control gate dielectric layer 308 and the control gate layer 309 includes the following steps:

[0110] (1) A sacrificial oxide layer is formed on the inner wall of the trench 302 by thermal oxidation. The oxide layer can wrap the lattice defects and tiny impurities on the inner wall of the trench 302, and temporarily fill the tiny pits on the surface by utilizing the uniformity of thermal oxidation.

[0111] (2) The sacrificial oxide layer is removed by dilute hydrofluoric acid. This process will simultaneously peel off the defects and impurities attached to the sacrificial oxide layer, and at the same time, the inner wall of the trench and the surface of the IPO will be micro-polished to restore the substrate surface to a flat and defect-free single crystal structure, thus solving the surface roughness problem caused by the previous process.

[0112] (3) The control gate dielectric layer 308 is formed by dry oxygen thermal oxidation. The thickness of the control gate dielectric layer 308 can be designed according to the device withstand voltage requirements. In some embodiments, the dielectric layer can be further deposited and etched back. The deposited layer can fill the tiny pores of the gate oxide layer and further thicken the gate dielectric layer, thereby improving the overall insulation capability and structural stability.

[0113] (4) A polysilicon layer is deposited by chemical vapor deposition or other suitable methods, and chemical mechanical polishing is performed to remove the excess polysilicon layer outside the trench 302, so as to obtain the control gate layer 309 filled in the trench 302, the control gate layer 309 being located above the shielding gate layer 305.

[0114] For example, please refer to Figure 10 It also includes the following steps:

[0115] (1) P-type ion implantation is performed on the upper surface layer of the substrate 301 to obtain the body region 310 located on both sides of the trench 302;

[0116] (2) N-type ion implantation is performed on the upper surface layer of the body region 310 to form the source region 311;

[0117] (3) An interlayer dielectric layer 312 is formed on the substrate 301 by chemical vapor deposition or other suitable methods, wherein the interlayer dielectric layer 312 includes, but is not limited to, a silicon oxide layer;

[0118] (4) A contact hole 313 is formed in the interlayer dielectric layer 312 by semiconductor processes such as photolithography and etching. The contact hole 313 also extends into the source region 311 and the body region 310.

[0119] (5) A source metal layer 314 is formed by physical deposition or other suitable semiconductor processes. The source metal layer 314 is located above the trench 302 and is electrically connected to the body region 310 and the source region 311.

[0120] Thus, a shielded gate trench device is fabricated, in which the control gate layer is located above the shielded gate layer and has a flush bottom surface. The fabrication method of the shielded gate trench device in this embodiment adds an adjustment dielectric layer deposition and re-etching step after the composite dielectric layer is etched back and before the control gate layer is fabricated. Because the etching rate of the same material is the same, the top surface of the resulting dielectric layer is flush after etching, which can avoid the subsequent control gate layer from having a slanted edge, thereby reducing parasitic capacitance. Furthermore, this adjustment dielectric layer deposition and re-etching step does not require an additional photomask, which helps to reduce production costs and avoid reliability risks.

[0121] Example 2

[0122] This embodiment provides a method for fabricating a shielding gate trench device. This embodiment uses the same inventive concept as Embodiment 1, but differs in that, in Embodiment 1, after etching back the composite dielectric layer, the top surface of the shielding gate layer 305 and the top of the trench 302 have a predetermined height difference to facilitate the subsequent formation of a top-bottom structure trench gate, i.e., controlling the gate layer to be located above the shielding gate layer; while in this embodiment, by controlling the etching time, the loss of the shielding gate layer 305 during the etching back of the composite dielectric layer is minimized. After the etching back is completed, the top surface of the shielding gate layer 305 is higher than the top surface of the first dielectric layer 303, and the height of the shielding gate layer 305 is not significantly reduced, facilitating the subsequent formation of a left-right structure trench gate, i.e., controlling the gate layer to be located on both sides of the shielding gate layer.

[0123] The following describes in detail the implementation process of the fabrication method of the shielding trench device in this embodiment, with reference to the structural diagram.

[0124] Please refer to the following first. Figure 4 and Figure 5 Perform steps S1 and S2 that are basically the same as in Embodiment 1, namely, form a trench 302 in the substrate 301, and form a composite dielectric layer and a shielding gate layer 305. The composite dielectric layer conformally covers the top surface of the substrate 301 and the inner wall of the trench 302 and includes a first dielectric layer 303 and a second dielectric layer 304 stacked sequentially. The shielding gate layer 305 is located in the trench 302 and is separated from the inner wall of the trench 302 by the composite dielectric layer.

[0125] Please refer to the following. Figure 11 Perform step S3: use wet etching to re-etch the composite dielectric layer until a portion of the sidewall of the trench 302 is exposed. The top surface of the second dielectric layer 304 after re-etching is lower than the top surface of the shielding gate layer 305, and the top surface of the first dielectric layer 303 after re-etching is higher than the top surface of the second dielectric layer 304 after re-etching.

[0126] In this embodiment, by controlling the etching time, after etching back the composite dielectric layer, the top surface of the shielding gate layer 305 is higher than the top surface of the first dielectric layer 303, and the top surface of the shielding gate layer 305 is not significantly lower than the top of the trench 302.

[0127] Please refer to the following. Figure 12 Step S4 is performed: an adjustment medium layer 306 is formed in the trench 302, the adjustment medium layer 306 at least covers the composite medium layer after the etch, and the lowest point of the top surface of the adjustment medium layer 306 is higher than the top surface of the first medium layer 303.

[0128] In this embodiment, the adjustment medium layer 306 is located on both sides of the shielding gate layer 305 and covers the composite medium layer after the etched back.

[0129] Please refer to the following. Figure 13 Then, perform step S5: re-etch the adjustment dielectric layer 306 to obtain a dielectric layer 307 with a flush top surface.

[0130] In this embodiment, the adjusted dielectric layer 306 after being re-etched covers the composite dielectric layer and has a flush top surface. The dielectric layer 307 with a flush top surface is composed of the adjusted dielectric layer 306 after being re-etched.

[0131] As an example, the top surface of the flush dielectric layer 307 is lower than the top surface of the shielding gate layer 305, that is, it does not cover the top surface of the shielding gate layer 305, so as to facilitate the subsequent formation of control gate layers on both sides of the shielding gate layer 305.

[0132] Specifically, the adjustment medium layer 306 after the re-etching has a flush top surface because the adjustment medium layer 306 is made of a single material. During the re-etching process, the etching rate of the same material is the same. After the etching is completed, the top surface of the resulting medium layer is flush.

[0133] Please refer to the following. Figure 14 Step S6 is performed: a control gate dielectric layer 308 and a control gate layer 309 are formed in the trench 302. The control gate layer 309 is located on both sides of the shielding gate layer 305 and has a flush bottom surface. The control gate dielectric layer 308 is sandwiched between the outer wall of the control gate layer 309 and the inner wall of the trench 302.

[0134] As an example, forming the control gate dielectric layer 308 and the control gate layer 309 includes the following steps:

[0135] (1) A sacrificial oxide layer is formed on the inner wall of the trench 302 by thermal oxidation. The oxide layer can wrap the lattice defects and tiny impurities on the inner wall of the trench 302, and temporarily fill the tiny pits on the surface by utilizing the uniformity of thermal oxidation.

[0136] (2) The sacrificial oxide layer is removed by dilute hydrofluoric acid. This process will simultaneously peel off the defects and impurities attached to the sacrificial oxide layer, and at the same time, the inner wall of the trench and the surface of the shielding grid 305 will be micro-polished.

[0137] (3) The control gate dielectric layer 308 is formed by dry oxygen thermal oxidation. The thickness of the control gate dielectric layer 308 can be designed according to the device withstand voltage requirements. In some embodiments, the dielectric layer can be further deposited and etched back. The deposited layer can fill the tiny pores of the gate oxide layer and further thicken the gate dielectric layer, thereby improving the overall insulation capability and structural stability.

[0138] (4) A polysilicon layer is deposited by chemical vapor deposition or other suitable methods, and chemical mechanical polishing is performed to remove the excess polysilicon layer outside the trench 302, so as to obtain the control gate layer 309 filled in the trench 302. The control gate layer 309 is located on both sides of the shielding gate layer 305.

[0139] In some embodiments, the dielectric layer thickness between the sidewall of the control gate layer 309 and the sidewall of the shielding gate layer 305 is greater than the dielectric layer thickness between the sidewall of the control gate layer 309 and the sidewall of the trench 302. For example, the dielectric layer thickness between the sidewall of the control gate layer 309 and the sidewall of the shielding gate layer 305 is 3 to 6 times the dielectric layer thickness between the sidewall of the control gate layer 309 and the sidewall of the trench 302.

[0140] For example, please refer to Figure 15 It also includes the following steps:

[0141] (1) P-type ion implantation is performed on the upper surface layer of the substrate 301 to obtain the body region 310 located on both sides of the trench 302;

[0142] (2) N-type ion implantation is performed on the upper surface layer of the body region 310 to form the source region 311;

[0143] (3) An interlayer dielectric layer 312 is formed on the substrate 301 by chemical vapor deposition or other suitable methods, wherein the interlayer dielectric layer 312 includes, but is not limited to, a silicon oxide layer;

[0144] (4) A contact hole 313 is formed in the interlayer dielectric layer 312 by semiconductor processes such as photolithography and etching, and the bottom of the contact hole 313 exposes the source region 311 and the body region 310;

[0145] (5) A source metal layer 314 is formed by physical deposition or other suitable semiconductor processes. The source metal layer 314 is located above the trench 302 and is electrically connected to the body region 310 and the source region 311.

[0146] Thus, a shielded gate trench device is fabricated, in which the control gate layer is located on both sides of the shielded gate layer and has a flush bottom surface. The fabrication method of the shielded gate trench device in this embodiment adds an adjustment dielectric layer deposition and re-etching step after the composite dielectric layer is etched back and before the control gate layer is fabricated. Because the etching rate of the same material is the same, after etching, the top surface of the resulting dielectric layer is flush, which can avoid the subsequent control gate layer from having a slanted edge, thereby reducing parasitic capacitance. Furthermore, this adjustment dielectric layer deposition and re-etching step does not require an additional photomask, which helps to reduce production costs and avoid reliability risks.

[0147] Example 3

[0148] This embodiment provides a method for fabricating a shielded trench device. For example, please refer to [link to example]. Figure 16 The diagram shows a schematic of the shielding trench device obtained in this embodiment. This embodiment adopts the same technical solution as Embodiment 2, except that in Embodiment 2, the adjusted dielectric layer 306 after etching covers the composite dielectric layer, that is, it covers both the first dielectric layer 303 and the second dielectric layer 304. In this embodiment, the adjusted dielectric layer 306 after etching is inserted between the first dielectric layer 303 and the shielding trench layer 304, covering the second dielectric layer 304 but not the first dielectric layer 303. The adjusted dielectric layer 306 after etching is flush with the top surface of the first dielectric layer 303. The dielectric layer 307 with the flush top surface is composed of the first dielectric layer 303 and the adjusted dielectric layer 306.

[0149] Example 4

[0150] The present invention also provides a shielding trench device, which can be manufactured by the method for manufacturing a shielding trench device described in any one of the embodiments 1 to 3.

[0151] Specifically, the shielding gate trench device includes a substrate, a trench, a shielding gate layer, a control gate layer, a shielding gate dielectric layer, and a control gate dielectric layer. The trench is located in the substrate, the shielding gate layer and the control gate layer are located in the trench and spaced apart. The control gate layer has a flush bottom surface. The shielding gate dielectric layer is sandwiched between the outer wall of the shielding gate layer and the inner wall of the trench. The shielding gate dielectric layer is a composite dielectric layer and includes a first dielectric layer and a second dielectric layer stacked sequentially. The dielectric constant of the first dielectric layer is higher than that of the second dielectric layer. The control gate dielectric layer is sandwiched between the outer wall of the control gate layer and the inner wall of the trench.

[0152] Specifically, because the control gate layer in the shielded trench device of this embodiment has a flush bottom surface, the device has lower parasitic capacitance and higher reliability.

[0153] In summary, the fabrication method of the shielding trench device of the present invention, after wet etching back the composite dielectric layer, first forms an adjustment dielectric layer. This adjustment dielectric layer at least covers the etched composite dielectric layer, and its lowest point is higher than the top surface of the first dielectric layer. Then, the adjustment dielectric layer is etched back to obtain a dielectric layer with a flush top surface. The subsequently formed control gate layer is located above or to both sides of the shielding trench layer and has a flush bottom surface. The fabrication method of the shielding trench device of the present invention adds a deposition and etch-back step of the adjustment dielectric layer after the composite dielectric layer is etched back and before the control gate layer is fabricated. Because the etching rate of the same material is the same, the top surface of the resulting dielectric layer is flush after etching, which can avoid the appearance of beveled edges in the subsequent control gate layer, thereby reducing parasitic capacitance. Furthermore, this deposition and etch-back of the adjustment dielectric layer does not require an additional photomask, which helps to reduce production costs and avoid reliability risks. The shielding trench device obtained by the present invention has lower parasitic capacitance and higher reliability. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0154] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a shielding trench device, characterized in that, Includes the following steps: A substrate is provided, and trenches are formed in the substrate; A composite dielectric layer and a shielding gate layer are formed. The composite dielectric layer conformally covers the top surface of the substrate and the inner wall of the trench and includes a first dielectric layer and a second dielectric layer stacked sequentially. The shielding gate layer is located in the trench and is separated from the inner wall of the trench by the composite dielectric layer. The dielectric constant of the first dielectric layer is higher than that of the second dielectric layer. The composite dielectric layer is etched back using a wet etching process until a portion of the sidewall of the trench is exposed. The top surface of the first dielectric layer after the etch back is higher than the top surface of the second dielectric layer after the etch back. An adjustment medium layer is formed in the trench, the adjustment medium layer at least covers the composite medium layer after the etch, and the lowest point of the top surface of the adjustment medium layer is higher than the top surface of the first medium layer; The adjusted dielectric layer is re-etched to obtain a dielectric layer with a flush top surface; A control gate dielectric layer and a control gate layer are formed in the trench. The control gate layer is located above or on both sides of the shielding gate layer and has a flush bottom surface. The control gate dielectric layer is sandwiched between the outer wall of the control gate layer and the inner wall of the trench.

2. The method for manufacturing the shielding trench device according to claim 1, characterized in that: After the composite dielectric layer is re-etched, the top surface of the shielding grid layer and the top of the trench have a preset height difference; In the step of forming an adjustment medium layer in the trench, the adjustment medium layer covers the etched composite medium layer and the shielding gate layer; In the step of re-etching the adjustment dielectric layer to obtain a dielectric layer with a flush top surface, the re-etched adjustment dielectric layer covers the composite dielectric layer and the shielding grid layer and has a flush top surface. The dielectric layer with a flush top surface is composed of the re-etched adjustment dielectric layer and its top surface is higher than the top surface of the shielding grid layer. In the step of forming the control gate dielectric layer and the control gate layer in the trench, the control gate layer is located above the shielding gate layer.

3. The method for manufacturing the shielding trench device according to claim 1, characterized in that: After the composite dielectric layer is etched back, the top surface of the shielding gate layer is higher than the top surface of the first dielectric layer; In the step of forming the adjustment medium layer in the trench, the adjustment medium layer is located on both sides of the shielding gate layer and covers the composite medium layer after the etch-back; In the step of re-etching the adjustment medium layer to obtain a medium layer with a flush top surface, the re-etched adjustment medium layer covers the composite medium layer and has a flush top surface, and the medium layer with a flush top surface is composed of the re-etched adjustment medium layer. In the step of forming the control gate dielectric layer and the control gate layer in the trench, the control gate layer is located on both sides of the shielding gate layer.

4. The method for manufacturing the shielding trench device according to claim 1, characterized in that: After the composite dielectric layer is etched back, the top surface of the shielding gate layer is higher than the top surface of the first dielectric layer; In the step of forming the adjustment medium layer in the trench, the adjustment medium layer is located on both sides of the shielding gate layer and covers the composite medium layer after the etch-back; In the step of re-etching the adjustment medium layer to obtain a medium layer with a flush top surface, the re-etched adjustment medium layer is inserted between the first medium layer and the shielding gate layer, and the re-etched adjustment medium layer is flush with the top surface of the first medium layer. The medium layer with a flush top surface is composed of the first medium layer and the adjustment medium layer. In the step of forming the control gate dielectric layer and the control gate layer in the trench, the control gate layer is located on both sides of the shielding gate layer.

5. The method for manufacturing the shielding trench device according to any one of claims 1 to 4, characterized in that: In the steps of wet etching back the composite dielectric layer until a portion of the sidewalls of the trench is exposed, and in the step of etching back the adjustment dielectric layer to obtain a dielectric layer with a flush top surface, the same photomask is used to open the etched area.

6. The method for manufacturing the shielding trench device according to any one of claims 1 to 4, characterized in that: The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

7. The method for manufacturing the shielding trench device according to any one of claims 1 to 4, characterized in that: The material of the adjustment medium layer includes silicon oxide.

8. The method for manufacturing the shielding trench device according to any one of claims 1 to 4, characterized in that: The method used to re-etch the adjusted dielectric layer includes wet etching.

9. The method for manufacturing the shielding trench device according to any one of claims 1 to 4, characterized in that, It also includes the following steps: A body region, a source region, and a source metal layer are formed. The body region is located on the upper surface of the substrate on both sides of the trench. The source region is located on the upper surface of the body region. The source metal layer is located above the trench and is electrically connected to the body region and the source region.

10. A shielding trench device, characterized in that, include: Substrate; Trench, located in the substrate; A shielding grid layer and a control grid layer are located in the trench and spaced apart, the control grid layer having a flush bottom surface; A shielding grid dielectric layer is sandwiched between the outer wall of the shielding grid layer and the inner wall of the trench. The shielding grid dielectric layer is a composite dielectric layer and includes a first dielectric layer and a second dielectric layer stacked in sequence. The dielectric constant of the first dielectric layer is higher than that of the second dielectric layer. A control gate dielectric layer is sandwiched between the outer wall of the control gate layer and the inner wall of the trench. The shielding trench device is formed using the manufacturing method of the shielding trench device as described in any one of claims 1 to 9.

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