High-power GaN p-FET device with introduced Mg delta doped buried layer structure and preparation method of high-power GaN p-FET device
By introducing a Mgδ-doped buried layer structure and a recessed gate design into GaN p-FET devices, the problem of obtaining high-concentration p-GaN has been solved, the output current of the devices has been increased and the on-resistance has been reduced, thus promoting the development of GaN CMOS technology.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-03-27
AI Technical Summary
High-concentration p-GaN is difficult to obtain in GaN p-FET devices, resulting in low current density in p-channel field-effect transistors and current mismatch issues, which hinders the development of GaN CMOS technology.
By introducing a Mgδ-doped buried layer structure, a Mgδ-doped buried layer is formed by doping Mgδ in the GaN layer. Combined with a grooved gate design, this increases the 2DHG concentration and carrier mobility at the GaN/AlGaN heterojunction interface, and reduces the channel on-resistance.
It achieves high output current and low specific on-resistance, improving the performance of GaN p-FET devices and making them suitable for high-frequency applications and extreme scenarios.
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Figure CN121751682A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to a high-power GaN p-FET device with an Mg delta-doped buried layer structure and a preparation method thereof, and belongs to the technical field of semiconductor devices. BACKGROUND
[0002] At present, high electron mobility transistors based on AlGaN / GaN heterostructures have been industrialized and applied in mobile phone fast charging and 5G communication fields and play an irreplaceable role. However, the logic control and front-end drive of GaN discrete devices are still mostly Si-based digital circuits at present, which greatly restricts the exertion of the high-frequency application advantages of GaN devices and hinders the application expansion of GaN devices in chip power management and extreme scenarios such as high temperature and irradiation. Complementary metal oxide semiconductor (CMOS) has outstanding static power consumption advantages and is a commonly used technical scheme in logic control chips at present, so the CMOS technology based on GaN materials is a crucial technical support for promoting the development of GaN power integrated circuit industry and will further promote the intelligent miniaturization of GaN power chips. One of the main bottlenecks in the development of GaN-based CMOS technology is the development of high-performance p-channel field effect transistors. Because the activation energy of Mg in GaN is relatively high, the impurity ionization rate is very low, and GaN has nitrogen vacancy defects, high-concentration p-GaN is difficult to obtain, and the p-FET channel resistance is large. The effective mass of holes in GaN is large, and there is strong low-energy phonon scattering, which further reduces the channel conductivity. The above problems result in a low current density of the p-channel field effect transistor and a large current mismatch when the GaN p-FET is integrated. In order to promote the development of GaN CMOS, it is urgent to improve the output current of the GaN p-FET device. SUMMARY
[0003] The application aims to provide a high-power GaN p-FET device with an Mg delta-doped buried layer structure.
[0004] The application achieves the above-mentioned purpose through the following technical scheme. A high-power GaN p-FET device with an Mg delta-doped buried layer structure, characterized in that the bottom layer of the structure is a substrate, and a GaN buffer layer, an Mg delta-doped buried layer, an AlGaN barrier layer, a GaN channel layer, a p-GaN layer and a p+-GaN layer are sequentially grown on the substrate, wherein the Mg delta-doped buried layer is Mg delta-doped in the GaN layer, the thickness of the Mg delta-doped buried layer is 1-2 nm, the Mg doping concentration is 3x10 19 cm -3 - 1x10 20 cm -3, etching the p+-GaN layer, the p-GaN layer to the GaN channel layer in the middle of the device to form a groove as a gate region, and further comprising a source electrode and a drain electrode arranged on the p+-GaN layer at two ends of the device.
[0005] Preferably, the GaN buffer layer has a thickness of 0.1-3 um.
[0006] Preferably, the AlGaN barrier layer has a thickness of 10-40 nm Al x Ga 1-x N barrier layer, wherein x is 0.15-0.4.
[0007] Preferably, the GaN channel layer has a thickness of 10 nm.
[0008] Preferably, the p-GaN layer has a thickness of 70 nm and a doping concentration of 1×10 19 cm -3 .
[0009] Preferably, the p+-GaN layer has a thickness of 20 nm and a doping concentration of 5×10 19 cm -3 .
[0010] Preferably, a dielectric layer is further grown on the GaN channel layer in the gate region, and the gate electrode is arranged on the dielectric layer.
[0011] The application further discloses a preparation method of the high-power GaN p-FET device. A. Device structure growth: selecting a substrate with a smooth surface and epitaxially growing an enhanced p-FET epitaxial wafer structure on the substrate: a GaN layer, a Mg δ-doped layer, an AlGaN barrier layer, a GaN channel layer, a p-GaN layer and a p+-GaN layer; B. Groove gate preparation: etching the p+-GaN layer and the p-GaN layer to the GaN channel layer in the middle of the epitaxial wafer to form a groove, and removing photoresist; C. Source and drain electrode preparation: using photoresist as a mask, and using electron beam evaporation to deposit source and drain electrode metal on the surface of the p+-GaN layer at two ends of the epitaxial wafer, and annealing to form source and drain ohmic contact electrodes; D. Depositing an Al2O3 layer on the surface of the epitaxial wafer as a gate dielectric; E. Gate electrode preparation: using photoresist as a mask, and using electron beam evaporation to deposit gate electrode metal on the dielectric layer in the groove region to form a Schottky contact gate electrode; F. Window opening: etching the Al2O3 in the source and drain regions to expose the source and drain electrodes.
[0012] Preferably, before preparing the recessed gate, a mesa isolation is performed: using dry etching, the two sides of the epitaxial wafer are etched to the substrate layer to form an isolated mesa.
[0013] Commonly doped p-GaN cannot obtain a higher Mg doping concentration (> 3e19), and thus cannot compensate the 2DEG in the channel to achieve the purpose of increasing the output current and reducing the on-resistance. When the doping concentration is too high (> 3e19), the quality of the epitaxial crystal is prone to deterioration. When the thickness of the buried layer is too large, it is also difficult to realize the enhancement type device; and when the Mg concentration is too low, the output current improvement effect is not obvious.
[0014] The Mg δ-doped buried layer structure introduced in the application weakens the scattering of the internal electric field on the carriers, effectively lifts the valence band at the GaN / AlGaN interface to enhance the restriction on holes, and cooperatively improves the mobility and concentration of 2DHG in the channel, realizing high output current and low specific on-resistance. In the p-channel of the traditional GaN p-FET device, the carriers are subjected to strong electric field scattering, and the 2DHG concentration in the channel is low, so that the device channel is large and the device output current is low. After introducing the structure of the Mg δ-doped buried layer, the concentration and carrier mobility of 2DHG in the channel are cooperatively improved, the channel on-resistance is effectively reduced, and the output current of the device is improved. At the same time, the gate region of the device is partially etched, and the 2DHG in the gate region is consumed, realizing a normally-off device. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 The epitaxial wafer structure prepared according to step A of the embodiment is prepared.
[0016] Figure 2 The structure prepared according to step B of the embodiment is prepared.
[0017] Figure 3 The structure prepared according to step C of the embodiment is prepared.
[0018] Figure 4 The structure prepared according to step D of the embodiment is prepared.
[0019] Figure 5 The structure prepared according to step E of the embodiment is prepared.
[0020] Figure 6 The structure prepared according to step F of the embodiment is prepared.
[0021] Figure 7 The structure of the high-power GaN p-FET device of the application introducing the Mg δ-doped buried layer structure is shown in the figure.
[0022] Figure 8Concentration profile at the interface of GaN / AlGaN heterojunction for Mg delta doped buried layer with different concentration range.
[0023] Figure 9 Device transfer characteristic curve graph for Mg delta doped buried layer with different concentration range.
[0024] Figure 10 Output characteristic curve graph for traditional recessed gate p-FET and the present application.
[0025] Figure 11 Structure schematic diagram of traditional recessed gate p-FET device. DETAILED DESCRIPTION
[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present application.
[0027] Embodiment 1 The present application introduces a preparation method of a high-power GaN p-FET device with Mg delta doped buried layer structure, and the steps thereof include: A, device structure growth. Select a substrate with a smooth surface, and use MBE technology to epitaxially grow an enhanced p-FET epitaxial wafer structure on the substrate: keep the N2 flow rate and radio frequency power unchanged, adjust the Ga, Al and Mg source furnace temperature, and epitaxially grow 150 nm GaN, 1-2 nm Mg delta doped layer, wherein the Mg concentration of the Mg delta doped layer is 3×10 19 cm -3 - 1×10 20 cm -3 , 20 nm Al 0.25 Ga 0.75 N barrier layer, 10 nm GaN channel layer, 70 nm p-GaN with a doping concentration of 1×10 19 cm -3 , 20 nm p-GaN with a doping concentration of 5×10 19 cm -3 Figure 1 The epitaxial wafer structure prepared according to step A.
[0028] B, mesa isolation. Dry etching is performed on the epitaxial wafer by using an inductively coupled plasma (ICP) etching device, and the gas condition is BCl3 / Cl2 mixed gas. First, the defined mesa etching area pattern is transferred to the photoresist by photolithography process, and then the photoresist is used as a mask to etch the epitaxial wafer by ICP. Finally, the photoresist is removed by organic ultrasonic cleaning to obtain the corresponding pattern Figure 2 The structure diagram obtained by processing according to step B is shown.
[0029] C, groove gate preparation. The photoresist is spin-coated on the epitaxial wafer, and after exposure and development, a photoresist image is formed. The ICP etching is used to form a groove, and after etching, the photoresist is removed by acetone washing Figure 3 The structure diagram obtained by processing according to step C is shown.
[0030] D, source and drain electrode preparation. The photoresist is used as a mask. The source and drain electrode metal Ni / Au 20nm / 20nm is deposited by electron beam evaporation, and the photoresist is stripped by acetone. The source and drain ohmic contact electrodes are formed by rapid annealing in an oxygen environment Figure 4 The structure diagram obtained by processing according to step D is shown.
[0031] E, depositing an Al2O3 layer as gate dielectric by using ALD Figure 5 The structure diagram obtained by processing according to step E is shown.
[0032] F, gate electrode preparation. The photoresist is used as a mask. The gate electrode metal Ni / Au 50nm / 100nm is deposited by electron beam evaporation, and the photoresist is stripped by acetone to form a Schottky contact gate electrode Figure 6 The structure diagram obtained by processing according to step F is shown.
[0033] G, window opening. Wet and dry methods can be used for window opening. Wet method uses BOE solution, and dry etching uses ICP to etch BCl3 / Cl2 mixed gas to etch Al2O3 at high power. The final device structure is shown in Figure 7 .
[0034] The device is simulated and analyzed, and the results are shown in Figure 8 , Figure 9 From Figure 8 , it can be seen that the 2DHG concentration at the AlGaN / GaN heterojunction interface is greatly improved after introducing the Mg δ-doped buried layer. The results show that when the Mg concentration is 3×10 19 cm -3 - 5×10 19The effect is the best, the large current output of the device can be ensured, and the normally-off device is realized by using the recessed grid structure. It can be seen from the transfer curve that the maximum current of the traditional device is 4.21 mA / mm, the maximum current of the device prepared based on the structure proposed in the application can reach 12 mA / mm, and the current density is greatly improved. The threshold voltage of the traditional device is-1.62 V (linear extrapolation method: -1.62 V@I D =0.1 mA / mm), the threshold voltage of the application does not appear obvious positive drift, the threshold voltage is-1.52 V@I D =0.1 mA / mm, and the enhancement type is still realized. Figure 10 The output curve graphs of the traditional device and the device of the application can be seen, the output current of the device can be improved, and the channel conduction resistance can be reduced.
[0035] The structure of the traditional device is as shown in Figure 11 , that is, the Mg δ doped buried layer is removed on the basis of the structure of the application.
[0036] The above embodiment is a preferred embodiment of the application, but the embodiment of the application is not limited by the above embodiment, any change, modification, substitution, combination, simplification made without departing from the spirit and principle of the application should be an equivalent replacement mode, and all are included in the protection scope of the application.
Claims
1. A high-power GaN p-FET device incorporating a Mg δ-doped buried layer structure, characterized in that, Its structure has a substrate at the bottom, on which GaN buffer layer, Mg δ-doped buried layer, AlGaN barrier layer, GaN channel layer, p-GaN layer, and p+-GaN layer are grown sequentially. The Mg δ-doped buried layer is formed by Mg δ doping in the GaN layer, with a thickness of 1~2 nm and a Mg doping concentration of 3×10⁻⁶. 19 cm -3 - 1×10 20 cm -3 The p+-GaN layer, p-GaN layer and GaN channel layer in the middle of the device are etched away to form a groove as a gate region. It also includes a source, drain and gate, with the source and drain disposed on the p+-GaN layers at both ends of the device.
2. The high-power GaN p-FET device according to claim 1, characterized in that, The thickness of the GaN buffer layer is 0.1-3 μm.
3. The high-power GaN p-FET device according to claim 2, characterized in that: The AlGaN barrier layer is 10-40 nm Al x Ga 1-x N is a barrier layer, where x is 0.15-0.
4.
4. The high-power GaN p-FET device according to claim 3, characterized in that: The thickness of the GaN channel layer is 10 nm.
5. The high-power GaN p-FET device according to claim 4, characterized in that: The p-GaN layer has a thickness of 70 nm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 .
6. The high-power GaN p-FET device according to claim 5, characterized in that: The p+-GaN layer has a thickness of 20 nm and a doping concentration of 5 × 10⁻⁶. 19 cm -3 .
7. The high-power GaN p-FET device according to any one of claims 1-6, characterized in that: A dielectric layer is also grown on the GaN channel layer in the gate region, and the gate is disposed on the dielectric layer.
8. The method for fabricating a high-power GaN p-FET device according to any one of claims 1-7, characterized in that, The steps include: A. Device structure growth: Select a flat substrate and grow an enhancement-type p-FET epitaxial wafer structure on the substrate: GaN layer, Mg δ doped layer, AlGaN barrier layer, GaN channel layer, p-GaN layer, p+-GaN layer; B. Trench gate fabrication: In the middle of the epitaxial wafer, the p+-GaN layer and p-GaN layer are etched to the GaN channel layer to form a trench, and the photoresist is removed; C. Source / drain electrode fabrication: Using photoresist as a mask, source / drain electrode metals are deposited on the p+-GaN layer surfaces at both ends of the epitaxial wafer by electron beam evaporation, followed by annealing to form source / drain ohmic contact electrodes. D. Deposit a layer of Al2O3 on the surface of the epitaxial wafer as a gate dielectric; E. Gate electrode fabrication: Using photoresist as a mask, the gate electrode metal is deposited by electron beam evaporation on the dielectric layer in the groove region to form a Schottky contact gate electrode; F. Opening a window: Etching away the Al2O3 in the source and drain regions to expose the source and drain.
9. The preparation method according to claim 8, characterized in that, Before fabricating the grooved gate, mesa isolation is performed: dry etching is used to etch both sides of the epitaxial wafer down to the substrate layer to form isolation mesa.