Switching element

Abstract

A switching element has, as a lower p layer, at least one of a first lower p layer in contact with a gate insulating film from the lower side and in contact with a drift layer from the upper side, and a second lower p layer in contact with a body layer from the lower side and in contact with the drift layer from the upper side. The lower p layer has: a high-concentration layer having a p-type impurity concentration equal to or greater than half of the maximum value of the p-type impurity concentration in the lower p layer; and a low-concentration layer having a p-type impurity concentration less than half the maximum value. The low-concentration layer has a lower low-concentration layer disposed between the high-concentration layer and the drift layer in the thickness direction of the semiconductor substrate. The thickness (x0) of a portion of the lower low-concentration layer having a p-type impurity concentration higher than the average value (A) of the p-type impurity concentrations of the low-concentration layer is larger than the smaller one of the thicknesses (x1, x2) obtained by a predetermined formula. As a result, leakage current of the switching element can be suppressed.

Description

Technical Field

[0001] The technology disclosed in this specification relates to switching elements. Background Technology

[0002] As described in Patent Document 1, when cosmic rays are incident on the interior of a switching element, electron-hole pairs are generated inside the semiconductor substrate, causing a decrease in the breakdown voltage of the switching element. In the technology of Patent Document 1, the breakdown voltage decrease caused by cosmic rays is suppressed by adjusting the n-type impurity concentration distribution within the drift layer.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2003-338624 Summary of the Invention

[0004] In switching elements having a semiconductor substrate made of silicon carbide, it is known to provide a p-layer (hereinafter referred to as the lower p-layer) within the drift layer. By providing the lower p-layer, the electric field applied to the gate insulating film can be mitigated. However, if the lower p-layer is provided, in the off state of the switching element, the depletion layer extends from the boundary between the drift layer and the lower p-layer into the lower p-layer. Since a large number of crystal defects exist within the lower p-layer, if the depletion layer extends extensively within the lower p-layer, the leakage current of the switching element increases. This specification proposes a technique for suppressing leakage current in switching elements having a lower p-layer.

[0005] The switching element disclosed in this specification comprises: a semiconductor substrate made of silicon carbide; and a gate electrode facing the semiconductor substrate through a gate insulating film. The semiconductor substrate comprises: an n-type source layer in contact with the gate insulating film; a p-type body layer in contact with both the gate insulating film and the source layer; an n-type drift layer in contact with both the gate insulating film and the body layer, and separated from the source layer by the body layer; and at least one of a first lower p-layer and a second lower p-layer, wherein the first lower p-layer is in contact with the gate insulating film from below and with the drift layer from above, and the second lower p-layer is in contact with the body layer from below and with the drift layer from above. The first and second lower p-layers comprise: a high-concentration layer having a p-type impurity concentration of more than half the maximum p-type impurity concentration in the first and second lower p-layers; and a low-concentration layer having a p-type impurity concentration of less than half the maximum value. The low-concentration layer has a lower low-concentration layer disposed between the high-concentration layer and the drift layer in the thickness direction of the semiconductor substrate. The portion of the lower low-concentration layer having a p-type impurity concentration higher than the average p-type impurity concentration A of the low-concentration layer has a thickness x0 that is larger than the smaller of the thicknesses x1 and x2 obtained by the following formulas (1) and (2).

[0006] [Number 1] Here, C represents the average n-type impurity concentration of the drift layer below the first and second lower p-layers, T represents the thickness of the drift layer below the first and second lower p-layers, ε represents the dielectric constant of silicon carbide, q represents the elementary charge, and V represents the dielectric constant of silicon carbide. bi It is the built-in potential at the interface between the low-concentration layer and the drift layer, denoted by V. BV It is the maximum rated voltage that can be applied between the drain and source of the switching element, where k is the Boltzmann constant and n is the source voltage. i It is the intrinsic carrier density of silicon carbide.

[0007] Additionally, in number 2 above, the maximum rated voltage V BV It is a value represented by setting the direction of the drain side to a high potential as positive.

[0008] The aforementioned thickness x1 refers to the magnitude of the depletion layer extending within the low-concentration layer when the drift layer below the lower p-layer is depleted throughout the thickness direction. Additionally, the aforementioned thickness x2 refers to the magnitude of the depletion layer extending within the low-concentration layer when the maximum rated voltage V is applied to the switching element. BV The amplitude of the depletion layer extending within the low-concentration layer. In the case of a punch-through switching element, the drain-source voltage ratio is the maximum rated voltage V. BV When the drift layer is low, the thickness x1 is smaller than the thickness x2. In the case of a non-punch-through switching element, the thickness x2 is smaller than the thickness x1. Therefore, the smaller of the thicknesses x1 and x2 represents the maximum extent of the depletion layer extending within the low-concentration layer during switching element operation. In this switching element, the thickness x0 of the portion of the lower low-concentration layer with a p-type impurity concentration higher than the average p-type impurity concentration A of the low-concentration layer is greater than the maximum extent of the depletion layer extending into the low-concentration layer. Therefore, the depletion layer does not reach the high-concentration layer. Since the depletion layer does not reach the high-density, high-concentration layer where crystal defects exist, leakage current is difficult to generate in this switching element. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view of the switching element in Embodiment 1.

[0010] Figure 2 This is a graph showing the impurity concentration distribution in the lower p-layer of Example 1.

[0011] Figure 3 This is a cross-sectional view of the switching element in the first modified example of Embodiment 1.

[0012] Figure 4This is a graph showing the impurity concentration distribution in the lower p layer of the first modified example of Example 1.

[0013] Figure 5 This is a cross-sectional view of the switching element in the second variation of Embodiment 1.

[0014] Figure 6 This is a cross-sectional view of the switching element in the third variation of Embodiment 1.

[0015] Figure 7 This is a cross-sectional view of the switching element in Embodiment 2.

[0016] Figure 8 This is a cross-sectional view of the switching element in the first modified example of Embodiment 2.

[0017] Figure 9 This is a cross-sectional view of the switching element in the second variation of Embodiment 2. Detailed Implementation

[0018] In one example of the switching element disclosed in this specification, a trench may also be formed on the upper surface of the semiconductor substrate. The gate insulating film and the gate electrode may also be disposed within the trench. A first lower p-layer, in contact with the gate insulating film, may also be present on the bottom surface of the trench.

[0019] In one example of the switching element disclosed in this specification, a second lower p-layer may also be connected to the body layer from below.

[0020] [Example 1] Figure 1 The switching element 10 of Embodiment 1 shown is a trench-gate MOSFET (metal-oxide-semiconductor field-effect transistor). The switching element 10 is designed for use at altitudes of the stratosphere or above (e.g., in outer space) and has a structure capable of suppressing the effects of cosmic rays. The switching element 10 has a semiconductor substrate 12, a gate electrode 22, a gate insulating film 20, a source electrode 26, and a drain electrode 28.

[0021] The semiconductor substrate 12 is made of silicon carbide (SiC). Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 will be referred to as the x-direction, a direction parallel to the upper surface 12a and orthogonal to the x-direction will be referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 will be referred to as the z-direction. A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends linearly along the y-direction on the upper surface 12a. The plurality of trenches 14 are arranged at intervals in the x-direction.

[0022] A gate insulating film 20 covers the inner surface of each trench 14. A gate electrode 22 is disposed within each trench 14. The gate electrode 22 is insulated from the semiconductor substrate 12 by the gate insulating film 20. The upper surface of the gate electrode 22 is covered by an interlayer insulating film 24.

[0023] The source electrode 26 covers the upper surface 12a of the semiconductor substrate 12. The source electrode 26 is insulated from the gate electrode 22 by an interlayer insulating film 24. The drain electrode 28 covers the lower surface 12b of the semiconductor substrate 12.

[0024] The semiconductor substrate 12 has multiple source layers 32, multiple contact layers 34, a body layer 36, a drift layer 38, a buffer layer 40, a drain layer 42, multiple first lower p layers 51, and multiple second lower p layers 52.

[0025] Each source layer 32 is an n-type layer with a high n-type impurity concentration. Each source layer 32 is in ohmic contact with the source electrode 26 on its upper surface 12a. Each source layer 32 is connected to the gate insulating film 20 at the upper end of the side of the corresponding trench 14.

[0026] Each contact layer 34 is a p-type layer with a high p-type impurity concentration. Each contact layer 34 has an ohmic contact with the source electrode 26 on its upper surface 12a.

[0027] Body layer 36 is a p-type layer with a lower p-type impurity concentration than contact layer 34. Body layer 36 is disposed below source layer 32 and contact layer 34. Body layer 36 is connected to source layer 32 and contact layer 34 from below. Body layer 36 is connected to the gate insulating film 20 on the side of trench 14 below source layer 32.

[0028] Drift layer 38 is an n-type layer with a lower n-type impurity concentration than source layer 32. The n-type impurity concentration of drift layer 38 is 9 × 10⁻⁶. 17 cm -3 The drift layer 38 is disposed on the underside of the body layer 36. The drift layer 38 is connected to the body layer 36 from the underside. The drift layer 38 is separated from the source layer 32 through the body layer 36. The drift layer 38 is connected to the gate insulating film 20 on the side of the trench 14 on the underside of the body layer 36. The drift layer 38 is distributed from the position where it is connected to the body layer 36 to a position lower than the lower end of each trench 14.

[0029] Buffer layer 40 is an n-type layer with a higher n-type impurity concentration than drift layer 38. The n-type impurity concentration of buffer layer 40 is higher than 9 × 10⁻⁶. 17 cm -3 The buffer layer 40 is in contact with the drift layer 38 from the bottom.

[0030] The drain layer 42 is an n-type layer with a higher n-type impurity concentration than the buffer layer 40. The drain layer 42 is connected to the buffer layer 40 from the bottom. The drain layer 42 makes ohmic contact with the drain electrode 28 on the lower surface 12b of the semiconductor substrate 12.

[0031] Each first lower p-layer 51 is disposed on the lower side of the corresponding trench 14. Each first lower p-layer 51 is in contact with the gate insulating film 20 on the bottom surface of the corresponding trench 14. That is, each first lower p-layer 51 is in contact with the gate insulating film 20 from the bottom. Each first lower p-layer 51 is in contact with the drift layer 38 from the top. The lower surface and side surface of each first lower p-layer 51 are in contact with the drift layer 38. Each first lower p-layer 51 is connected to the body layer 36 through a p-type layer (not shown). Therefore, the potential of each first lower p-layer 51 is approximately equal to the potential of the body layer 36.

[0032] Each second lower p-layer 52 is disposed on the lower side of the body layer 36. Each second lower p-layer 52 extends relatively long in the y-direction parallel to the trench 14. Each second lower p-layer 52 is in contact with the body layer 36 from the bottom. Each second lower p-layer 52 is in contact with the drift layer 38 from the top. The lower surface and side surface of each second lower p-layer 52 are in contact with the drift layer 38.

[0033] Figure 2 express Figure 1 The distribution of p-type impurity concentration at the location of the II-II line (i.e., the distribution of p-type impurity concentration in the z direction of the lower p layer). Figure 2 The maximum value N shown Amax Value C is the maximum value of the p-type impurity concentration within the first lower p-layer 51, and value C is the average value of the n-type impurity concentration in the drift layer 38 below the first lower p-layer 51. The region with a p-type impurity concentration higher than value C is the first lower p-layer 51. The first lower p-layer 51 has: a high-concentration layer 51a, which has a maximum value N. Amax More than half of the p-type impurity concentration; and a low-concentration layer 51b (i.e., a p-type layer comprising an upper low-concentration layer 51bU and a lower low-concentration layer 51bL), which has a higher than maximum value N Amax The concentration of p-type impurities is half that of smaller p-type impurities. In this embodiment, the maximum value N Amax 5×10 19 cm -3 That's all. (As...) Figure 1 As shown, a high-concentration layer 51a is disposed approximately in the center of the first lower p-layer 51, and a low-concentration layer 51b is disposed around the high-concentration layer 51a. The low-concentration layer 51b has an upper low-concentration layer 51bU and a lower low-concentration layer 51bL. The upper low-concentration layer 51bU is disposed above the high-concentration layer 51a, and the lower low-concentration layer 51bL is disposed below the high-concentration layer 51a. The lower low-concentration layer 51bL is disposed in the z-direction between the high-concentration layer 51a and the drift layer 38. Furthermore, Figure 2 The average value A shown is the average p-type impurity concentration of the low-concentration layer 51b. The lower low-concentration layer 51bL has a region 51c with a p-type impurity concentration higher than the average value A. Region 51c is adjacent to the high-concentration layer 51a from below.

[0034] The thickness x0 of region 51c is greater than the smaller of the thicknesses x1 and x2 obtained by the following formulas (1) and (2).

[0035] [Number 2] Here, as Figure 1 As shown, the symbol T represents the thickness of the drift layer 38 below the first lower p-layer 51. The symbol ε represents the dielectric constant of silicon carbide. The symbol q represents the elementary charge. The symbol V... bi It is the built-in potential at the interface between the low-concentration layer 51b and the drift layer 38. Symbol V BV This is the maximum rated voltage that can be applied between the drain and source of the switching element 10. The symbol k is the Boltzmann constant. The symbol n... i It is the intrinsic carrier density of silicon carbide.

[0036] The concentration of p-type impurities in the second lower p-layer 52 is similar to that in the first lower p-layer 51 (i.e., Figure 2 The p-type impurity concentrations are distributed in a roughly similar manner. The second lower p-layer 52 has a high-concentration layer 52a and a low-concentration layer 52b (i.e., a p-type layer comprising an upper low-concentration layer 52bU and a lower low-concentration layer 52bL). The high-concentration layer 52a has the maximum p-type impurity concentration N of the second lower p-layer 52. Amax More than half of the p-type impurity concentration, the low-concentration layer 52b has a higher than maximum N value. Amax Half the concentration of small p-type impurities. For example... Figure 1 As shown, a high-concentration layer 52a is disposed approximately in the center of the second lower p-layer 52, and a low-concentration layer 52b is disposed around the high-concentration layer 52a. The low-concentration layer 52b has an upper low-concentration layer 52bU and a lower low-concentration layer 52bL. The upper low-concentration layer 52bU is disposed above the high-concentration layer 52a, and the lower low-concentration layer 52bL is disposed below the high-concentration layer 52a. The lower low-concentration layer 52bL has a region 52c, which has a p-type impurity concentration higher than the average p-type impurity concentration A within the low-concentration layer 52b. The region 52c is connected to the high-concentration layer 52a from the bottom. When the above equations (1) and (2) are applied to the drift layer 38 at the bottom of the second lower p-layer 52, the thickness x0 of the region 52c of the second lower p-layer 52 is larger than the smaller of the thicknesses x1 and x2.

[0037] Next, the operation of the switching element 10 will be explained. When using the switching element 10, a higher potential than the source electrode 26 is applied to the drain electrode 28. When a potential above the gate threshold is applied to the gate electrode 22, a channel is formed in the body layer 36 adjacent to the gate insulating film 20. Thus, the source layer 32 and the drift layer 38 are connected through the channel. Therefore, electrons flow from the source layer 32 through the channel, the drift layer 38, and the buffer layer 40 to the drain layer 42. That is, the switching element 10 is turned on. When the potential of the gate electrode 22 is reduced to a potential below the gate threshold, the channel disappears, and the switching element 10 is turned off.

[0038] If the switching element 10 is turned off, a reverse voltage is applied to the interface (i.e., pn junction) between the p-type layer formed by the body layer 36, the first lower p-layer 51, and the second lower p-layer 52 and the drift layer 38. Therefore, the depletion layer extends from the pn junction into the p-type layer and into the drift layer 38.

[0039] When the switching element 10 is a punch-through type, the entire drift layer 38 is depleted when the voltage between the drain and source of the switching element 10 is lower than the maximum rated voltage. Therefore, in the punch-through type, the maximum amplitude of the depletion layer extending within the drift layer 38 is equal to the thickness T of the drift layer 38. In this case, the amplitude of the depletion layer extending from the lower surface (i.e., the pn junction) of the first lower p layer 51 into the first lower p layer 51 becomes the thickness x1 obtained by Equation 1 above. Furthermore, the amplitude of the depletion layer extending from the lower surface (i.e., the pn junction) of the second lower p layer 52 into the second lower p layer 52 also becomes x1 obtained by Equation 1 above.

[0040] When the switching element 10 is a non-punch-through type, when the maximum rated voltage is applied between the drain and source of the switching element 10, a depletion layer with an amplitude corresponding to the maximum rated voltage is formed in the drift layer 38. In this case, the amplitude of the depletion layer extending from the lower surface (i.e., the pn junction) of the first lower p layer 51 into the first lower p layer 51 is the thickness x2 obtained by the above formula 2. In addition, the amplitude of the depletion layer extending from the lower surface (i.e., the pn junction) of the second lower p layer 52 into the second lower p layer 52 is also the thickness x2 obtained by the above formula 2.

[0041] Thus, the smaller of thicknesses x1 and x2 represents the maximum extent of the depletion layer extending within the first lower p-layer 51 and the second lower p-layer 52. In Embodiment 1, the thickness x0 of a portion of the lower low-concentration layer 51bL, i.e., region 51c, located below the high-concentration layer 51a, is greater than the smaller of thicknesses x1 and x2. Furthermore, the thickness x0 of a portion of the lower low-concentration layer 52bL, i.e., region 52c, located below the high-concentration layer 52a, is greater than the smaller of thicknesses x1 and x2. Therefore, when the switching element 10 is turned off, the depletion layer does not reach the high-concentration layers 51a and 52a. Because the high-concentration layers 51a and 52a have high p-type impurity concentrations, crystal defects exist at a high density within them. If the depletion layer reaches the high-concentration layers 51a and 52a with high crystal defect density, a high leakage current is generated. However, in this embodiment, the depletion layer does not reach the high-concentration layers 51a and 52a, thus leakage current is difficult to generate.

[0042] Furthermore, if cosmic rays are incident on the lower p-layer 51 when the switching element 10 is off, electron-hole pairs are generated within the lower p-layer 51. If the holes generated within the lower p-layer 51 are accelerated by the electric field and injected into the gate insulating film 20, the insulation performance of the gate insulating film 20 deteriorates. In Example 1, the maximum value N of the p-type impurity concentration in the lower p-layer 51 is... Amax 5×10 19 cm -3 As described above, the space charge of the lower p-layer 51 is significantly negative. Therefore, even if holes are generated in the lower p-layer 51 due to the incidence of cosmic rays, it is difficult to generate an electric field towards the gate insulating film 20 within the lower p-layer 51, and the injection of holes into the gate insulating film 20 is suppressed. Therefore, the degradation of the gate insulating film 20 is suppressed. Similarly, when cosmic rays are incident into the lower p-layer 52, the injection of holes into the gate insulating film 20 is also suppressed, thus suppressing the degradation of the gate insulating film 20.

[0043] As explained above, in the switching element 10 of Embodiment 1, the injection of holes generated by cosmic rays into the gate insulating film 20 can be suppressed by the first lower p-layer 51 and the second lower p-layer 52, thereby suppressing the degradation of the gate insulating film 20. Furthermore, leakage current caused by the first lower p-layer 51 and the second lower p-layer 52 can be suppressed.

[0044] Furthermore, in Example 1, an upper low-concentration layer 51bU is provided above the high-concentration layer 51a, but it can also be as follows: Figure 3 , Figure 4 As shown, instead of an upper low-concentration layer 51bU, the high-concentration layer 51a is directly connected to the gate insulating film 20. Furthermore, in Embodiment 1, an upper low-concentration layer 52bU is provided above the high-concentration layer 52a, but as... Figure 3, Figure 4 As shown, the upper low-concentration layer 52bL can be omitted, and instead, the high-concentration layer 52a can be directly connected to the body layer 36. In this structure, since the lower low-concentration layers 51bL and 52bL exist below the high-concentration layers 51a and 52a, similar to Example 1, the depletion layer will not reach the high-concentration layers 51a and 52a. Therefore, leakage current can be suppressed. Furthermore, in Figure 4 In the middle, the maximum value N Amax It can also be 5×10 19 cm -3 That's all. Additionally, without setting an upper low-concentration layer of 51bU and 52bU, such as... Figure 5 As shown, low-concentration layers 51b and 52b can also be provided to the sides and below the high-concentration layers 51a and 52a.

[0045] Additionally, in Embodiment 1, the second lower p-layer 52 extends along the y-direction, but as... Figure 6 As shown, the second lower p-layer 52 can also extend along the x-direction (i.e., the direction intersecting with the trench 14). In this configuration, the intersection of the first lower p-layer 51 and the second lower p-layer 52 is interconnected.

[0046] In addition, in embodiment 1, a buffer layer 40 is provided between the drift layer 38 and the drain layer 42, but the buffer layer 40 may not be present, and the drift layer 38 and the drain layer 42 are connected.

[0047] In addition, in Embodiment 1, both a first lower p layer 51 and a second lower p layer 52 are provided on the semiconductor substrate 12, but it is also possible to provide only one of the first lower p layer 51 and the second lower p layer 52.

[0048] [Example 2] Figure 7 The switching element 100 of Embodiment 2 shown is a planar MOSFET. The switching element 100 is designed for use at altitudes above the stratosphere (e.g., outer space) and has a structure capable of suppressing the effects of cosmic rays. In the following description, the same reference numerals as in Embodiment 1 are used to denote the various parts of the switching element 100 of Embodiment 2. The switching element 100 has a semiconductor substrate 12, a gate electrode 22, a gate insulating film 20, a source electrode 26, and a drain electrode 28.

[0049] The semiconductor substrate 12 is made of silicon carbide (SiC). A gate insulating film 20 covers a portion of the upper surface 12a of the semiconductor substrate 12. A gate electrode 22 is disposed on the gate insulating film 20. The gate electrode 22 is insulated from the semiconductor substrate 12 by the gate insulating film 20. The upper surface and side surfaces of the gate electrode 22 are covered by an interlayer insulating film 24. A source electrode 26 covers the upper surface 12a of the semiconductor substrate 12. The source electrode 26 is insulated from the gate electrode 22 by the interlayer insulating film 24. A drain electrode 28 covers the lower surface 12b of the semiconductor substrate 12.

[0050] The semiconductor substrate 12 has multiple source layers 32, multiple contact layers 34, multiple body layers 36, drift layers 38, buffer layers 40, drain layers 42, and multiple lower p layers 52.

[0051] Each source layer 32 is an n-type layer with a high n-type impurity concentration. Each source layer 32 is in ohmic contact with the source electrode 26 on its upper surface 12a. Each source layer 32 is in contact with the gate insulating film 20 on its upper surface 12a.

[0052] Each contact layer 34 is a p-type layer with a high p-type impurity concentration. Each contact layer 34 has an ohmic contact with the source electrode 26 on its upper surface 12a.

[0053] Each body layer 36 is a p-type layer having a lower p-type impurity concentration than the contact layer 34. Multiple body layers 36 are arranged at intervals in the x-direction. Each body layer 36 is disposed around the source layer 32 and the contact layer 34. Each body layer 36 is connected from below to the source layer 32 and the contact layer 34. Each body layer 36 is distributed to the side of the source layer 32 and is connected to the side surface of the source layer 32. Each body layer 36 is connected to the gate insulating film 20 at a position adjacent to the source layer 32.

[0054] Drift layer 38 is an n-type layer with a lower n-type impurity concentration than source layer 32. The n-type impurity concentration of drift layer 38 is 9 × 10⁻⁶. 17 cm -3 The drift layer 38 is disposed on the underside of each body layer 36. The drift layer 38 is distributed on the upper surface 12a between two body layers 36, and is in contact with the side surface of each body layer 36. The drift layer 38 is in contact with the gate insulating film 20 at a position adjacent to the body layer 36. The drift layer 38 is separated from the source layer 32 through the body layer 36.

[0055] Buffer layer 40 is an n-type layer with a higher n-type impurity concentration than drift layer 38. The n-type impurity concentration of buffer layer 40 is higher than 9 × 10⁻⁶. 17 cm -3 The buffer layer 40 is in contact with the drift layer 38 from the bottom.

[0056] The drain layer 42 is an n-type layer with a higher n-type impurity concentration than the buffer layer 40. The drain layer 42 is connected to the buffer layer 40 from the bottom. The drain layer 42 makes ohmic contact with the drain electrode 28 on the lower surface 12b of the semiconductor substrate 12.

[0057] Each lower p-layer 52 is disposed on the underside of the corresponding body layer 36. Each lower p-layer 52 is in contact with the corresponding body layer 36 from the underside. The lower surface and side surface of each lower p-layer 52 are in contact with the drift layer 38.

[0058] The p-type impurity concentration distribution within each lower p-layer 52 is the same as the p-type impurity concentration within the lower p-layer 52 in Example 1 (i.e., Figure 2 The concentrations are equal. That is, each lower p-layer 52 has a high-concentration layer 52a and a low-concentration layer 52b. An upper low-concentration layer 52bU is provided above the high-concentration layer 52a, and a lower low-concentration layer 52bL is provided below the high-concentration layer 52a. The lower low-concentration layer 52bL has a region 52c, which has a p-type impurity concentration higher than the average p-type impurity concentration A of the low-concentration layer 52b. The thickness x0 of region 52c is larger than the smaller of the thicknesses x1 and x2 obtained by the above equations (1) and (2). Therefore, when the switching element 100 of Embodiment 2 is turned off, the depletion layer extending from the lower surface (i.e., pn junction) of each lower p-layer 52 into the interior of each lower p-layer 52 will not reach the high-concentration layer 52a. Therefore, in the switching element of Embodiment 2, leakage current is also suppressed. In addition, in the switching element of Embodiment 2, the injection of holes into the gate insulating film 20 is also suppressed by each lower p layer 52.

[0059] Furthermore, in Example 2, an upper low-concentration layer 52bU is provided above the high-concentration layer 52a, but it can also be as follows: Figure 8 As shown, instead of an upper low-concentration layer 52bU, the high-concentration layer 52a is directly connected to the body layer 36. In this configuration, because a lower low-concentration layer 52bL exists below the high-concentration layer 52a, the depletion layer does not reach the high-concentration layer 52a. Therefore, leakage current can be suppressed. Furthermore, without the upper low-concentration layer 52bU, as... Figure 9 As shown, a low-concentration layer 52b can also be provided on the side and below the high-concentration layer 52a.

[0060] In addition, in Embodiment 2, a buffer layer 40 is provided between the drift layer 38 and the drain layer 42, but the buffer layer 40 may not be present. Furthermore, in the above embodiments, the concentrations of the drift layer 38 and the buffer layer 40 can be adjusted during epitaxial growth or by ion implantation after epitaxial growth.

[0061] The embodiments have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes technologies obtained by various modifications and alterations to the specific examples described above. The technical elements illustrated in this specification or drawings exert their technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of application. Furthermore, the technology illustrated in this specification or drawings achieves multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

Claims

1. A switching element, characterized in that, have: The semiconductor substrate is made of silicon carbide; and The gate electrode is positioned opposite the semiconductor substrate, separated by a gate insulating film. The semiconductor substrate has: The n-type source layer is connected to the gate insulating film; The p-type body layer is connected to the gate insulating film and the source layer; An n-type drift layer is connected to the gate insulating film and the body layer, and is separated from the source layer through the body layer; as well as At least one of a first lower p-layer and a second lower p-layer, wherein the first lower p-layer is connected to the gate insulating film from the bottom and to the drift layer from the top, and the second lower p-layer is connected to the body layer from the bottom and to the drift layer from the top. The first lower p layer and the second lower p layer have: The high-concentration layer has a p-type impurity concentration that is more than half of the maximum p-type impurity concentration in the first lower p-layer and the second lower p-layer; as well as The low-concentration layer has a p-type impurity concentration that is less than half of the maximum value. The low-concentration layer has a lower low-concentration layer disposed between the high-concentration layer and the drift layer in the thickness direction of the semiconductor substrate. The thickness x0 of the portion of the lower low-concentration layer having a p-type impurity concentration higher than the average p-type impurity concentration A of the low-concentration layer is greater than the smaller of the thicknesses x1 and x2 obtained by the following formulas (1) and (2). [Number 1] ， Here, C represents the average n-type impurity concentration of the drift layer below the first lower p-layer and the second lower p-layer, T represents the thickness of the drift layer below the first lower p-layer and the second lower p-layer, ε represents the dielectric constant of silicon carbide, q represents the elementary charge, and V represents the dielectric constant of silicon carbide. bi It is the built-in potential at the interface between the low-concentration layer and the drift layer, denoted by V. BV It is the maximum rated voltage that can be applied between the drain and source of the switching element, where k is the Boltzmann constant and n is the maximum rated voltage that can be applied between the drain and source of the switching element. i It is the intrinsic carrier density of silicon carbide.

2. The switching element according to claim 1, characterized in that, Grooves are formed on the upper surface of the semiconductor substrate. The gate insulating film and the gate electrode are disposed within the trench. The bottom surface of the trench has a first lower p layer that is in contact with the gate insulating film.

3. The switching element according to claim 1, characterized in that, It has a second lower p-layer that is in contact with the body layer from the bottom.

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