Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is provided with a metal gate trench, and the bottom and side walls of the metal gate trench are provided with work function layers; and forming a diffusion barrier layer on the work function layer, namely forming a first diffusion barrier sub-layer on the work function layer at the bottom of the metal gate trench by adopting a physical vapor deposition process and enabling negative bias power to be smaller than preset power. The possibility of sealing in advance can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the development of semiconductor technology, the integration level of semiconductor devices is constantly increasing, and the critical dimension (CD) of semiconductor devices is getting smaller and smaller. This places higher demands on the performance of components such as transistors. Because polysilicon gates have relatively high resistance, existing transistors have begun to use metal materials as gates. By using metal gates (MG) with lower resistance, it is helpful to improve the performance of components.

[0003] However, in the prior art, due to the limitations of critical size and the layer-by-layer stacking of metal gate filling films, the critical size becomes smaller and smaller when the metal material is filled, which in turn makes the metal material filling window smaller and smaller. As a result, the metal material cannot be effectively filled, forming void defects, which affect the electrical performance of the metal gate. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which can reduce the possibility of premature sealing.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate having a metal gate trench, the bottom and sidewalls of the metal gate trench having a work function layer; forming a diffusion barrier layer on the work function layer, comprising: employing a physical vapor deposition process, wherein the negative bias power in the physical vapor deposition process is less than a preset power, so as to form a first diffusion barrier sublayer on the work function layer at the bottom of the metal gate trench.

[0006] Optionally, the preset power is less than or equal to 100W.

[0007] Optionally, the reactant gas forming the first diffusion barrier sublayer includes nitrogen at a first gas flow rate to form a first diffusion barrier sublayer containing a nitride material; the method of forming the diffusion barrier layer further includes: reducing the first gas flow rate to a second gas flow rate to form a second diffusion barrier sublayer containing a nitride material, wherein the first gas flow rate is greater than the second gas flow rate.

[0008] Optionally, before forming the first diffusion barrier sublayer on the work function layer, the method further includes: determining a voltage-nitrogen flow rate relationship curve, the relationship curve comprising a first curve and a second curve, the first curve representing the voltage corresponding to the gradual increase of nitrogen from zero to a preset value, and the second curve representing the voltage corresponding to the gradual decrease of nitrogen from the preset value to zero; determining the voltage inflection point based on the first curve; determining the minimum overlap point among the overlap points of the first curve and the second curve that is greater than the inflection point; the first gas flow rate being greater than the nitrogen flow rate corresponding to the minimum overlap point, and the second gas flow rate being less than the nitrogen flow rate corresponding to the inflection point.

[0009] Optionally, the first gas flow rate is selected from 80 sccm to 120 sccm; and / or, the second gas flow rate is selected from 20 sccm to 40 sccm.

[0010] Optionally, the method for forming the second diffusion barrier layer further includes: using a physical vapor deposition process, with a negative bias power selected from 200W to 600W, such that the second diffusion barrier layer is formed on the work function layer of the sidewall of the metal gate trench and on the first diffusion barrier layer at the bottom of the metal gate trench.

[0011] Optionally, the method further includes: forming a wetting layer on a second diffusion barrier layer on the sidewall of the metal gate trench and on a second diffusion barrier layer at the bottom of the metal gate trench; and filling the trench formed by the wetting layer with a metal material.

[0012] Optionally, the wetting layer includes a titanium layer.

[0013] Optionally, when the first diffusion barrier sublayer is deposited to a preset process time, the first gas flow rate is reduced to the second gas flow rate to form a second diffusion barrier sublayer; wherein, the method for determining the preset process time includes: providing multiple sample substrates, using multiple process times, forming a first diffusion barrier sublayer on each of the multiple sample substrates; measuring the thickness of each formed first diffusion barrier sublayer, and using the process time corresponding to a first diffusion barrier sublayer with a preset thickness as the preset process time.

[0014] Optionally, the preset thickness of the first diffusion barrier sublayer is 0.6 to 0.7 times the total thickness of the diffusion barrier layer.

[0015] Optionally, the preset thickness is 4nm to 7nm.

[0016] Optionally, the sample substrate is an optical sheet; or the sample substrate is an optical sheet and a dielectric layer located on the optical sheet.

[0017] Optionally, the thickness of the first diffusion barrier sublayer formed may be measured using one or more of the following methods: probe profilometer, X-ray fluorescence spectrometer, X-ray photoelectron spectrometer, or section analysis method.

[0018] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate having a metal gate trench, the bottom and sidewalls of the metal gate trench having work function layers; and a diffusion barrier layer including a first diffusion barrier sublayer located on the work function layer at the bottom of the metal gate trench.

[0019] Optionally, the diffusion barrier layer further includes: a second diffusion barrier sublayer located on the work function layer of the sidewall of the metal gate trench, and a first diffusion barrier sublayer located at the bottom of the metal gate trench.

[0020] Optionally, both the first diffusion barrier sublayer and the second diffusion barrier sublayer comprise nitride materials, and the nitrogen content in the first diffusion barrier sublayer is higher than the nitrogen content in the second diffusion barrier sublayer.

[0021] Optionally, the first diffusion barrier sublayer is a titanium nitride layer; and / or, the second diffusion barrier sublayer is a titanium nitride layer.

[0022] Optionally, the semiconductor structure further includes: a wetting layer located on a second diffusion barrier layer on the sidewall of the metal gate trench and on a second diffusion barrier layer located at the bottom of the metal gate trench; and a metal material filling the trench formed by the wetting layer.

[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0024] In this embodiment of the invention, a first diffusion barrier layer is formed using a physical vapor deposition (PVD) process under a negative bias power less than a predetermined power (e.g., less than 100W). Because the negative bias power is relatively low, it is more advantageous to form the first diffusion barrier layer on the work function layer at the bottom of the metal gate trench, thus reducing the amount of deposition on the sidewall surface of the metal gate trench. In practical applications, for example, the negative bias power can be controlled to be less than 100W, so that the first diffusion barrier layer forms only a small amount or almost none on the sidewall surface of the metal gate trench. That is, the first diffusion barrier layer can be controlled to be almost entirely formed on the work function layer at the bottom of the metal gate trench, thereby effectively avoiding the problem of lateral convergence of the first diffusion barrier layer at the top of the metal gate trench and reducing the possibility of premature sealing. Furthermore, since the main function of the diffusion barrier layer is to reduce the diffusion of metal atoms in the metal gate downwards in the vertical direction of the work function layer, forming a first diffusion barrier layer at the bottom of the metal gate trench provides an effective barrier effect while mitigating the lateral convergence problem.

[0025] Furthermore, the first diffusion barrier layer is a TiN layer. When the reaction gas of the first diffusion barrier layer contains N2 at a first gas flow rate, in response to the process time for forming the first diffusion barrier layer reaching a preset process time, the first gas flow rate is reduced to a second gas flow rate to form a second diffusion barrier layer. The first gas flow rate is greater than the second gas flow rate, thereby forming a second diffusion barrier layer on the first diffusion barrier layer. Since the N content in the TiN of the first diffusion barrier layer formed when the N2 gas flow rate is greater (which can be called nitrogen-rich mode) is often greater and the titanium content is relatively smaller, it can have a relatively stronger barrier ability, thus further improving the barrier effect of the first diffusion barrier layer. Since the N content in the TiN of the second diffusion barrier layer formed when the N2 gas flow rate is smaller (which can be called titanium-rich mode) is often smaller and the titanium content is relatively larger, it can have a relatively stronger sidewall adsorption and diffusion ability. Therefore, the second diffusion barrier layer can serve as an effective supplement to the first diffusion barrier layer.

[0026] Furthermore, the second diffusion barrier layer is formed using a PVD process, and the negative bias power is selected from 200W to 600W. This ensures that the second diffusion barrier layer is located on the work function layer on the sidewall of the metal gate trench and on the first diffusion barrier layer at the bottom of the metal gate trench. Since the negative bias power of the second diffusion barrier layer is greater than that of the first diffusion barrier layer, it can be formed not only at the bottom of the metal gate trench but also on the sidewall of the metal gate trench. This isolates the material layer (such as the wetting layer) subsequently formed on the sidewall of the metal gate trench from the work function layer, preventing the wetting layer and the work function layer from reacting and affecting device performance.

[0027] Furthermore, before forming the first diffusion barrier sublayer on the work function layer, multiple sample substrates are provided, and multiple process durations are used to form the first diffusion barrier sublayer on each of the multiple sample substrates. The thickness of the formed first diffusion barrier sublayer is measured, and the process duration corresponding to the first diffusion barrier sublayer with a preset thickness is used as the preset process duration. A more accurate preset process duration can be determined through sample experiments.

[0028] Furthermore, the standard value of the total thickness of the diffusion barrier layer in the standard process of the semiconductor structure is determined, and the preset thickness is determined according to the preset ratio of the preset thickness to the standard value of the total thickness. The preset ratio is selected from 0.6 to 0.7. The accurate thickness of the first diffusion barrier sublayer can be effectively determined by the standard parameter of the total thickness and by the quantifiable and pre-set parameters of the preset thickness and the preset ratio.

[0029] Furthermore, the sample substrate is an optical sheet; or the sample substrate is an optical sheet and a dielectric layer located on the optical sheet, so that materials that are closer to the actual product can be selected according to the actual situation, and sample tests can be conducted to further improve the validity of the obtained data. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a cross-sectional structure of a metal gate device in the prior art;

[0031] Figure 2 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0032] Figures 3 to 6 This is a schematic diagram of the device cross-sectional structure corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention;

[0033] Figure 7 This is a schematic diagram of the voltage-nitrogen flow rate relationship in an embodiment of the present invention.

[0034] Explanation of reference numerals in the attached figures:

[0035] Substrate 100, metal gate trench 101, work function layer 110, diffusion barrier layer 120, wetting layer 130, metal material 140, via 141, substrate 200, metal gate trench 201, sidewall 202, work function layer 210, interface layer 211, gate dielectric layer 212, first work function sublayer 2101, second work function sublayer 2102, third work function sublayer 2103, diffusion barrier layer 220, first diffusion barrier sublayer 2201, second diffusion barrier sublayer 2202, wetting layer 230, metal material 240. Detailed Implementation

[0036] As mentioned earlier, in the prior art, due to the limitations of critical size and the layer-by-layer stacking of metal gate filling films, the critical size becomes smaller and smaller when the metal material is filled, which in turn makes the metal material filling window smaller and smaller, resulting in the metal material being unable to fill effectively and forming void defects.

[0037] Research has revealed that a crucial step in forming a metal gate is the creation of a diffusion barrier layer to reduce the diffusion of metal atoms from the gate into the work function layer. In existing technologies, the diffusion barrier layer tends to overhang at the top of the metal gate trench, which can lead to premature sealing during the filling of the metal material.

[0038] Reference Figure 1 , Figure 1 This is a schematic diagram of a cross-sectional structure of a metal gate device in the prior art. For example... Figure 1 As shown, a substrate 100 is provided, the substrate 100 having a metal gate trench 101, the bottom and sidewalls of the metal gate trench 101 having a work function layer 110, and a diffusion barrier layer 120 formed on the work function layer 110. Further research revealed that because the diffusion barrier layer 120 formed at the apex of the metal gate trench 101 grows rapidly and continuously converges laterally, the opening size D1 at the top of the metal gate trench 101 becomes smaller after the diffusion barrier layer 120 is formed. This further causes subsequent material layers (e.g., wetting layer 130) to further converge laterally, further reducing the opening size at the top of the metal gate trench 101. Based on this, when filling with metal material 140, premature sealing is prone to occur, such as... Figure 1 The metal material 140 shown is prematurely sealed at the top of the metal gate trench 101, resulting in the formation of a hole 141 below, which seriously affects the electrical performance of the metal gate, such as causing high resistance and making it difficult to meet the requirements.

[0039] In this embodiment of the invention, a first diffusion barrier layer is formed using a physical vapor deposition (PVD) process under a negative bias power less than a predetermined power (e.g., less than 100W). Because the negative bias power is relatively low, it is more advantageous to form the first diffusion barrier layer on the work function layer at the bottom of the metal gate trench, thus reducing the amount of deposition on the sidewall surface of the metal gate trench. In practical applications, for example, the negative bias power can be controlled to be less than 100W, so that the first diffusion barrier layer is formed in small amounts or almost none on the sidewall surface of the metal gate trench. That is, the first diffusion barrier layer can be controlled to be almost entirely formed on the work function layer at the bottom of the metal gate trench, thereby effectively avoiding the problem of the first diffusion barrier layer laterally converging at the top of the metal gate trench, reducing the possibility of premature sealing, and effectively improving the electrical performance of the metal gate. Furthermore, since the main function of the diffusion barrier layer is to reduce the diffusion of metal atoms in the metal gate downward in the vertical direction of the work function layer, by forming a first diffusion barrier sub-layer at the bottom of the metal gate trench, an effective blocking effect can be provided while alleviating the lateral convergence problem.

[0040] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Reference Figure 2 , Figure 2 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention. The method for forming the semiconductor structure may include steps S21 to S22:

[0042] Step S21: Provide a substrate having a metal gate trench, the bottom and sidewalls of the metal gate trench having a work function layer;

[0043] Step S22: Forming a diffusion barrier layer on the work function layer includes: using a PVD process and making the negative bias power less than a preset power to form a first diffusion barrier sublayer on the work function layer at the bottom of the metal gate trench.

[0044] The steps described above are explained below.

[0045] Figures 3 to 6 This is a schematic diagram of the device cross-sectional structure corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0046] Reference Figure 3 A substrate 200 is provided, the substrate 200 having a metal gate trench 201, the bottom and sidewalls of the metal gate trench 201 having a work function layer 210.

[0047] The substrate 200 may include a semiconductor substrate, and the metal gate trench 201 may be formed by forming a pseudo gate structure on the semiconductor substrate using polysilicon, forming sidewalls (spacers) 202 on both sides of the pseudo gate structure, and then removing the pseudo gate structure in the sidewalls 202.

[0048] In specific implementations, the semiconductor substrate can be a silicon substrate. In other embodiments, the semiconductor substrate material can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ide. The semiconductor substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The semiconductor substrate can also have other suitable structures. For example, taking a finned field-effect transistor as an example, the semiconductor substrate can also have fins. However, the embodiments of the present invention are not limited to this, and the semiconductor device can also be other semiconductor devices.

[0049] It should be noted that, in specific implementations, other suitable material layers may be formed before the work function layer is formed at the bottom and sidewalls of the metal gate trench. This embodiment of the invention does not limit whether there are other material layers between the substrate 200 and the work function layer 210.

[0050] For example, an interface layer 211 and a gate dielectric layer 212 are formed between the substrate 200 and the work function layer 210. Specifically, the interface layer (IL) 211 can be made of SION, also known as nitrogen-doped silicon oxide. The gate dielectric layer 212 can be made of a high dielectric constant (High K, HK) material layer, such as an HK dielectric layer, and its material can be a combination selected from one or more of the following: hafnium oxide (HfO2), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), and zirconium oxide (ZrO2).

[0051] In some embodiments, the work function layer 210 may be a stacked structure of multiple material layers, which can be used to adjust the electrical properties of the metal gate, thereby affecting the performance of the device, such as electrical parameters like the threshold voltage (Vt) and saturation leakage current (Idsat) of the transistor.

[0052] exist Figure 3 In one specific embodiment shown, the work function layer 210 may include one or more of the following: a first work function sublayer 2101, a second work function sublayer 2102, and a third work function sublayer 2103.

[0053] The material of the first work function sublayer 2101 can be titanium nitride (TiN).

[0054] The material of the second work function sublayer 2102 can be tantalum nitride (TaN).

[0055] The third work function sublayer 2103 can be specifically selected according to the device type. For example, in one specific embodiment, for the metal gate of an N-type metal-oxide-semiconductor (NMOS) device, the material of the third work function sublayer 2103 can be titanium aluminum (TiAl); for the metal gate of a P-type metal-oxide-semiconductor (PMOS) device, the material of the third work function sublayer 2103 can be titanium nitride (TiN).

[0056] The thicknesses of the first work function sublayer 2101, the second work function sublayer 2102, and the third work function sublayer 2103 can all be less than 100 angstroms. In a specific example, they can be formed using atomic layer deposition (ALD) technology.

[0057] Reference Figure 4 A diffusion barrier layer is formed on the work function layer 210. The step of forming the diffusion barrier layer on the work function layer may include: using a PVD process and applying a negative bias power less than a preset power to form a first diffusion barrier sublayer 2201 on the work function layer at the bottom of the metal gate trench.

[0058] In other words, the first diffusion barrier sublayer 2201 is formed using a PVD process, and the negative bias power is less than a preset power. Since a smaller negative bias power results in a more concentrated ion deposition direction, for example, closer to vertical drop, the first diffusion barrier sublayer 2201 can be almost entirely located on the work function layer 210 at the bottom of the metal gate trench 201. For example, the thickness of the first diffusion barrier sublayer formed at the bottom of the metal gate trench can be 4nm to 7nm, while the thickness of the first diffusion barrier sublayer covering the sidewalls of the metal gate trench is only 0 to 0.5nm. The negative bias power can even be further reduced so that the thickness of the first diffusion barrier sublayer covering the sidewalls of the metal gate trench can be close to 0, meaning that almost no material from the first diffusion barrier sublayer is formed on the sidewall surface of the metal gate trench.

[0059] Specifically, Physical Vapor Deposition (PVD) technology involves using physical methods under vacuum conditions to vaporize the surface of a material source (solid or liquid) into gaseous atoms or molecules, or partially ionize them into ions, and then depositing a thin film on the substrate surface through a low-pressure gas (or plasma) process. In one specific embodiment, a target material (such as a Ti target) can be bombarded with an ionized inert gas (such as argon, Ar). The bombarded Ti reacts with the dissociated N2 to form a first diffusion barrier sublayer 2201 containing TiN.

[0060] In this embodiment of the invention, a patterned mask layer (not shown) can be formed on a substrate 200, exposing the area to be deposited. Then, a PVD process is used to ionize the surface portion of the target material, and a thin film of material is deposited through a plasma process. The process parameters may include negative bias power (AC power) and direct current power (DC power).

[0061] In this process, the chamber gas (such as argon, nitrogen, or one or more of these gases) in the PVD process chamber can be dissociated under DC power, and then bombard the target material to obtain ions to be deposited. Under negative bias power, the ions to be deposited react with the chamber gas in the PVD process chamber and are deposited at the bottom of the chamber. It should be noted that the smaller the negative bias power, the more concentrated the direction of the ions to be deposited, for example, more closely resembling a vertical fall. After removing the patterned mask layer, the first diffusion barrier sublayer 2201 formed is almost entirely located on the work function layer 210 at the bottom of the metal gate trench 201. Correspondingly, the larger the negative bias power, the more dispersed the direction of the ions to be deposited. The first diffusion barrier sublayer 2201 formed is not only located on the work function layer 210 at the bottom of the metal gate trench 201, but also on the sidewall surface of the metal gate trench 201.

[0062] In some embodiments, the negative bias power is less than a preset power, which may be less than or equal to 100W. In some embodiments, the preset power may be further less than or equal to 50W. In one specific embodiment, the negative bias power may be 0, thereby theoretically ensuring that the formed first diffusion barrier sublayer 2201 is entirely located on the work function layer 210 at the bottom of the metal gate trench 201.

[0063] Furthermore, the higher the DC power, the more ions dissociate. Conversely, the lower the DC power, the fewer ions dissociate.

[0064] Reference Figure 5 The step of forming the diffusion barrier layer may further include forming a second diffusion barrier sublayer 2202. Specifically, in response to the process time for forming the first diffusion barrier sublayer 2201 reaching a preset process time, the process gas may be adjusted, for example, by reducing the N2 flow rate from a first gas flow rate to a second gas flow rate, to form a second diffusion barrier sublayer 2202 containing a nitride material. It is understood that the diffusion barrier layer 220 in the embodiments of the present invention includes a first diffusion barrier sublayer 2201 and a second diffusion barrier sublayer 2202.

[0065] In some embodiments, the material of the first diffusion barrier sublayer 2201 is TiN, and the reactant gas in the first diffusion barrier sublayer 2201 contains N2 at a first gas flow rate. Therefore, the material of the second diffusion barrier sublayer 2202 may also include TiN. It should be noted that the case with a larger N2 gas flow rate is called the nitrogen-rich mode, in which the N content of TiN in the first diffusion barrier sublayer 2201 formed is often larger, and the titanium content is relatively smaller; the case with a smaller N2 gas flow rate is called the titanium-rich mode, in which the N content of TiN in the second diffusion barrier sublayer 2202 formed is often smaller, and the titanium content is relatively larger.

[0066] In this embodiment of the invention, the first diffusion barrier sublayer 2201 is a TiN layer. When the reaction gas of the first diffusion barrier sublayer contains N2 at a first gas flow rate, in response to the process time for forming the first diffusion barrier sublayer 2201 reaching a preset process time, the first gas flow rate is reduced to a second gas flow rate to form a second diffusion barrier sublayer 2202. The first gas flow rate is greater than the second gas flow rate, thereby forming the second diffusion barrier sublayer 2202 on the first diffusion barrier sublayer 2201. Since the N content of TiN in the first diffusion barrier sublayer 2201 formed in nitrogen-rich mode is often higher and the titanium content is relatively lower, it can have a relatively stronger barrier ability, thus further improving the barrier effect of the first diffusion barrier sublayer 2201. Since the N content of TiN in the second diffusion barrier sublayer 2202 formed in titanium-rich mode is often lower and the titanium content is relatively higher, it can have a relatively stronger sidewall adsorption and diffusion ability. Therefore, the second diffusion barrier sublayer 2202 can serve as an effective supplement to the first diffusion barrier sublayer 2201.

[0067] In one specific embodiment, the subsequent process also includes a Ti deposition process. The use of a titanium-rich mode can also prevent the consumption and diffusion of subsequent Ti deposition, which is equivalent to providing a buffer layer for subsequent Ti in advance, reducing the consumption of subsequent Ti. In this way, enough Ti is effectively retained to provide a wetting layer for subsequent metal (such as Al) filling.

[0068] Furthermore, the method for forming the second diffusion barrier sublayer 2202 may further include: using a PVD process, with a negative bias power selected from 200W to 600W, such that the second diffusion barrier sublayer 2202 is formed on the work function layer 210 on the sidewall of the metal gate trench 201 and on the first diffusion barrier sublayer 2201 at the bottom of the metal gate trench 201. In other words, the formation process of the second diffusion barrier sublayer 2202 may also be a PVD process, with a negative bias power selected from 200W to 600W, such that the second diffusion barrier sublayer 2202 is located on the work function layer 210 on the sidewall of the metal gate trench 201 and on the first diffusion barrier sublayer 2201 at the bottom of the metal gate trench 201.

[0069] It should be noted that the negative bias power in this embodiment of the invention should not be too large. If it is too large, the material (such as TiN) of the bottom first diffusion barrier sublayer 2201 will be sputtered too severely, resulting in a large lateral overhang. The negative bias power in this embodiment of the invention should not be too small. If it is too small, the difference between the formation position of the second diffusion barrier sublayer 2202 and the formation position of the first diffusion barrier sublayer 2201 will be too small, making it difficult to produce adsorption and diffusion effects on the sidewalls.

[0070] In this embodiment of the invention, the second diffusion barrier sublayer 2202 is formed by PVD process, and the negative bias power is selected from 200W to 600W. Since the negative bias power of the second diffusion barrier sublayer 2202 is greater than that of the first diffusion barrier sublayer 2201, it can not only be formed at the bottom of the metal gate trench 201, but also on the sidewall of the metal gate trench 201. Thus, while serving as an effective supplement to the first diffusion barrier sublayer 2201 at the bottom, it can also isolate the material layer (such as the wetting layer) and the work function layer 210 subsequently formed on the sidewall of the metal gate trench, thereby preventing the wetting layer and the work function layer 210 from reacting and affecting the device performance.

[0071] It should be noted that since the first diffusion barrier sublayer 2201 is almost entirely located on the work function layer 210 at the bottom of the metal gate trench 201, the problem of lateral convergence of the first diffusion barrier sublayer 2201 at the top of the metal gate trench 201 has been effectively avoided. Therefore, a good sidewall foundation is provided for the formation of the second diffusion barrier sublayer 2202, effectively mitigating the problem of lateral convergence of the formed second diffusion barrier sublayer 2202. Figure 5 The top of the opening formed by the second diffusion barrier sublayer 2202 shown is less than D2. Figure 1 The top of the opening formed by the diffusion barrier layer 120 shown is at a distance D1.

[0072] Reference Figure 6A wetting layer 230 is formed, which is located on the second diffusion barrier sublayer 2202 on the sidewall of the metal gate trench 201 and on the second diffusion barrier sublayer 2202 at the bottom of the metal gate trench 201; and a metal material 240 is filled into the trench formed by the wetting layer 230.

[0073] The wetting layer 230 can be used to provide a basis for the reflow of the metal material 240, effectively preventing the agglomeration of the metal material 240 and improving the compactness and bonding of the metal material 240.

[0074] In this embodiment of the invention, since the first diffusion barrier sublayer 2201 is almost entirely located at the bottom of the metal gate trench 201, the problem of the work function layer 210 laterally approaching the top of the metal gate trench 201 is effectively avoided. Therefore, it provides a good sidewall foundation for the formation of the wetting layer 230, and correspondingly reduces the problem of the lateral approach of the formed wetting layer 230.

[0075] In some embodiments, the wetting layer 230 includes a Ti layer. It should be noted that since the material of the wetting layer 230 includes Ti, Ti loss is prone to occur in practical applications, leading to insufficient wetting. In this embodiment, the wetting layer 230 is formed on the second diffusion barrier sublayer 2202, and the second diffusion barrier sublayer 2202 is a titanium-rich layer, effectively reducing the consumption of titanium within the wetting layer 230.

[0076] Continue to refer to Figure 2 In some embodiments, when the first diffusion barrier sublayer has been deposited for a preset process time, the first gas flow rate is reduced to the second gas flow rate to form a second diffusion barrier sublayer. The method for determining the preset process time may include: providing multiple sample substrates, using multiple process times, and forming a first diffusion barrier sublayer on each of the multiple sample substrates; measuring the thickness of each formed first diffusion barrier sublayer, and using the process time corresponding to a first diffusion barrier sublayer of a preset thickness as the preset process time. In this way, a more accurate preset process time can be determined through sample testing.

[0077] Furthermore, the preset thickness of the first diffusion barrier sublayer at the bottom of the metal gate trench can be 0.6 to 0.7 times the total thickness of the diffusion barrier layer.

[0078] In some embodiments, before using the process time corresponding to the first diffusion barrier sublayer of a preset thickness as the preset process time, the method may further include: determining a standard value for the total thickness of the diffusion barrier layer in a standard process of the semiconductor structure; and determining the preset thickness according to a preset ratio of the preset thickness to the standard value of the total thickness, wherein the preset ratio is selected from 0.6 to 0.7.

[0079] In one specific embodiment, the preset thickness can be 4nm to 7nm, for example 5nm to 6nm, for example 5.5nm.

[0080] In this embodiment of the invention, the preset thickness of the first diffusion barrier sublayer can be 0.6 to 0.7 times the total thickness of the diffusion barrier layer. This means that in the case of a diffusion barrier layer with a certain thickness, this embodiment divides it into a first diffusion barrier sublayer and a second diffusion barrier sublayer, and makes the total thickness of the first diffusion barrier sublayer and the second diffusion barrier sublayer at the bottom of the metal gate trench reach the expected thickness to meet the requirement of blocking metal atom diffusion in the vertical direction; at the same time, the thickness of the second diffusion barrier sublayer on the sidewall of the metal gate trench is controlled to meet the requirement of blocking metal atom diffusion in the horizontal direction.

[0081] More specifically, by determining the standard value of the total thickness of the diffusion barrier layer in the standard process of the semiconductor structure, the preset thickness is determined according to the preset ratio of the preset thickness to the standard value of the total thickness. The preset ratio is selected from 0.6 to 0.7. The accurate thickness of the first diffusion barrier sublayer can be effectively determined by the standard parameter of the total thickness and by the quantifiable and pre-set parameters of the preset thickness and the preset ratio.

[0082] Furthermore, the sample substrate may be a bare wafer; or the sample substrate may be a bare wafer and a dielectric layer located on the bare wafer.

[0083] Among them, the bare wafer, also known as the monitor wafer, can be regarded as a semiconductor substrate that has not undergone artificial processing.

[0084] The dielectric layer can also be called the insulating layer, and for example, it can be a stack of one or more of the following: oxide layer, nitride layer.

[0085] The oxide layer can be formed by a thermal oxidation process, and its specific material can be determined according to the material of the semiconductor substrate. For example, for a silicon substrate, the first oxide layer formed by the thermal oxidation process is silicon oxide (e.g., SiO2); for a germanium substrate, the first oxide layer formed by the thermal oxidation process is germanium oxide, and so on.

[0086] In this embodiment of the invention, the sample substrate is an optical sheet; or the sample substrate is an optical sheet and a dielectric layer located on the optical sheet, so that materials that are closer to the actual product can be selected according to the actual situation, and sample tests can be conducted to further improve the validity of the obtained data.

[0087] In some embodiments, the thickness of the first diffusion barrier sublayer on the sample substrate may be measured in an appropriate manner.

[0088] Specifically, the thickness of the first diffusion barrier sublayer can be measured using one or more of the following methods: probe profilometer, X-ray fluorescence spectrometer, X-ray photoelectron spectrometer, and slice analysis method.

[0089] Among them, the probe profilometer (also known as the step profiler, or KLA for short) provides high-precision 2D and 3D surface measurement, measuring step height, surface roughness, warpage and stress, as well as excellent stability and reliability.

[0090] An X-ray fluorescence (XRF) spectrometer consists of an excitation source (X-ray tube) and a detection system. The X-ray tube generates incident X-rays (primary X-rays), which excite the sample to produce X-ray fluorescence (secondary X-rays), and the detector detects the X-ray fluorescence.

[0091] X-ray photoelectron spectroscopy (XPS) is a quantitative spectroscopic technique used to measure the empirical chemical formulas, chemical states, and electronic states of various elements in materials. It involves irradiating a material with an X-ray beam while simultaneously measuring the kinetic energy and the number of electrons escaping from the material surface at a distance of 1 to 10 nanometers, thus obtaining the X-ray photoelectron spectrum.

[0092] The slice analysis method can be to slice the sample substrate and the first diffusion barrier sublayer on the sample substrate, and then use scanning electron microscopy (SEM) or other appropriate tools to measure the slices.

[0093] In this embodiment of the invention, by measuring the thickness of the first diffusion barrier sublayer formed in an appropriate manner, the thickness of the first diffusion barrier sublayer formed can be accurately obtained. Then, by using the process time corresponding to the first diffusion barrier sublayer with a preset thickness as the preset process time, an accurate preset process time can be determined, thereby reducing the first gas flow rate to the second gas flow rate at a more precise time point.

[0094] Reference Figure 7 , Figure 7 This is a schematic diagram of the voltage-nitrogen flow rate relationship in an embodiment of the present invention.

[0095] Voltage (also known as target voltage) is used to represent DC voltage associated with DC power. The unit is volt (V).

[0096] Figure 7 The voltage versus nitrogen flow rate curve shown can be obtained beforehand in the process chamber where the first diffusion barrier sublayer is formed.

[0097] Specifically, before forming the first diffusion barrier sublayer on the work function layer, the method may further include: determining a voltage-nitrogen flow rate relationship curve, the relationship curve comprising a first curve and a second curve, the first curve representing the voltage corresponding to the gradual increase of nitrogen from zero to a preset value, and the second curve representing the voltage corresponding to the gradual decrease of nitrogen from the preset value to zero; determining the voltage inflection point based on the first curve; determining the minimum overlap point among the overlap points of the first curve and the second curve that is greater than the inflection point; the first gas flow rate being greater than the nitrogen flow rate corresponding to the minimum overlap point, and the second gas flow rate being less than the nitrogen flow rate corresponding to the inflection point.

[0098] More specifically, N2 is gradually increased from zero to a preset maximum value, and then decreased back to zero to output the curve model.

[0099] Specifically, by setting the first gas flow rate to be greater than the N2 flow rate corresponding to the minimum overlap point, it is possible to use N2 corresponding to the nitrogen-rich saturation region to form the first diffusion barrier sublayer.

[0100] like Figure 7 As shown, the voltage curve exhibits a distinct inflection point as the N2 gas flow rate changes; this can be termed the nitrogen-rich, titanium-rich inflection point. Figure 7 The left side of the inflection point represents the titanium-rich mode, and the right side represents the nitrogen-rich mode. The inflection point indicates a change in voltage from a decreasing trend to an increasing trend; it can be, for example, the lowest voltage point on the curve, or it can be obtained from curve fitting.

[0101] More specifically, in the first curve (also known as the N2 increase curve) where N2 gradually increases from zero to a preset maximum value, the region to the right of the titanium-rich and nitrogen-rich inflection point is collectively referred to as the nitrogen-rich region. This nitrogen-rich region can be divided into a nitrogen-rich saturated region and a nitrogen-rich unsaturated region. The point where the standard voltage values ​​for gradually increasing and decreasing N2 coincide (i.e., the minimum coincidence point, also known as the infinite approximation point) is the starting position of the nitrogen-rich saturated region, and the region to the right of this minimum coincidence point is the nitrogen-rich saturated region.

[0102] Therefore, in one specific embodiment of the present invention, it is only necessary to monitor the standard voltage and confirm the switching between the titanium-rich mode and the nitrogen-rich mode when the nitrogen-rich and titanium-rich inflection point is detected. Thus, reducing the first gas flow rate to the second gas flow rate is more conducive to switching from the nitrogen-rich mode at the first gas flow rate to the titanium-rich mode at the second gas flow rate. Of course, in other optional examples, it is also possible to switch from a film layer with a higher nitrogen content formed at the first gas flow rate to a film layer with a lower nitrogen content formed at the second gas flow rate.

[0103] It should be noted that, in the embodiments of the present invention, other appropriate methods can also be used to distinguish between the nitrogen-rich saturated region and the nitrogen-rich unsaturated region. For example, a bias test (also known as a batch test) can be designed, and XPS technology can be used to measure the Ti / N ratio of the first diffusion barrier sublayer formed under different N2 conditions. When N2 reaches a certain gas flow rate, it will be found that the Ti / N ratio no longer changes, which means that N is saturated. The corresponding N2 gas flow rate in this case is the starting position of the nitrogen-rich saturated region.

[0104] In one specific embodiment, the first gas flow rate may be selected from 80 sccm to 120 sccm, for example from 90 sccm to 110 sccm, for example 100 sccm.

[0105] The second gas flow rate can be selected from 20 sccm to 40 sccm, for example, from 25 sccm to 35 sccm, for example, 30 sccm.

[0106] In this embodiment of the invention, by employing appropriate first and second gas flow rates, the blocking effect of the first diffusion barrier sublayer 2201 can be improved, while the second diffusion barrier sublayer 2202 can achieve relatively stronger sidewall adsorption and diffusion capabilities. In this embodiment of the invention, a semiconductor structure is also disclosed, referring to… Figure 6 It may include: a substrate 200 having a metal gate trench 201 having a work function layer 210 at the bottom and sidewalls of the metal gate trench 201; and a diffusion barrier layer including a first diffusion barrier sublayer 2201 located on the work function layer 210 at the bottom of the metal gate trench 201.

[0107] Furthermore, the diffusion barrier layer may further include: a second diffusion barrier sublayer 2202 located on the work function layer 210 on the sidewall of the metal gate trench 201, and a first diffusion barrier sublayer 2201 located at the bottom of the metal gate trench 201.

[0108] Furthermore, both the first diffusion barrier sublayer 2201 and the second diffusion barrier sublayer 2202 may include nitride materials, and the nitrogen content in the first diffusion barrier sublayer 2201 is higher than the nitrogen content in the second diffusion barrier sublayer 2202.

[0109] Furthermore, the first diffusion barrier sublayer 2201 is a TiN layer; and / or, the second diffusion barrier sublayer 2202 is a TiN layer.

[0110] Furthermore, the semiconductor structure may further include: a wetting layer 230, the wetting layer 230 being located on a second diffusion barrier sublayer 2201 on the sidewall of the metal gate trench 201, and on a second diffusion barrier sublayer 2202 located at the bottom of the metal gate trench 201; and a metal material 240, filling the trench formed by the wetting layer 230.

[0111] In this embodiment of the invention, by forming a first diffusion barrier sublayer 2201 on the work function layer that is almost entirely located at the bottom of the metal gate trench 201, the problem of lateral convergence of the first diffusion barrier sublayer 2201 at the top of the metal gate trench 201 is effectively avoided, thereby reducing the possibility of premature sealing and effectively improving the electrical performance of the metal gate. Furthermore, since the main function of the first diffusion barrier sublayer 2201 is to reduce the diffusion of metal atoms in the vertical direction downwards into the work function layer 210 within the metal gate, forming the first diffusion barrier sublayer 2201 at the bottom of the metal gate trench 201 provides an effective barrier effect while mitigating the lateral convergence problem.

[0112] It should be understood that the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this document indicates that the preceding and following related objects are in an "or" relationship. As used herein, unless explicitly stated otherwise, the term "or" covers all possible combinations unless impractical. For example, if a component is declared to include A or B, then unless explicitly stated otherwise or impractical, the component can include A, or B, or A and B. As a second example, if a component is declared to include A, B, or C, then unless explicitly stated otherwise or impractical, the component can include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0113] In the embodiments of this application, "multiple" refers to two or more.

[0114] Relational terms appearing in the embodiments of this application, such as "first," "second," etc., are used only to distinguish an entity or operation from another entity or operation, without requiring or implying any actual relationship or order between these entities or operations. Furthermore, the words "comprising," "having," and "including," as well as other similar forms, are intended to be equivalent in meaning and are open-ended; one or more items following any of these words do not imply an exhaustive list of such items or that they are limited to only the listed items.

[0115] It should be noted that the sequence number of each step in this embodiment does not represent a limitation on the execution order of each step.

[0116] In the foregoing specification, numerous specific details have been described with reference to embodiments, which may vary depending on the implementation. Certain modifications and alterations may be made to the described embodiments. Other embodiments will be apparent to those skilled in the art in light of the specification and practice disclosed herein. The specification and examples are intended to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims. The sequence of steps shown in the accompanying drawings is also intended for illustrative purposes only and is not intended to limit one to any particular sequence of steps. Therefore, those skilled in the art will understand that these steps may be performed in different orders while achieving the same method.

[0117] Exemplary embodiments have been disclosed in the accompanying drawings and description. However, many variations and modifications can be made to these embodiments. Therefore, although specific terminology has been used, it is used in a general and descriptive sense only and not for limiting purposes.

[0118] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a metal gate trench, the bottom and sidewalls of which have a work function layer; Forming a diffusion barrier layer on the work function layer includes: employing a physical vapor deposition process, wherein the negative bias power in the physical vapor deposition process is less than a preset power, to form a first diffusion barrier sublayer on the work function layer at the bottom of the metal gate trench.

2. The method according to claim 1, characterized in that, The preset power is less than or equal to 100W.

3. The method according to claim 1, characterized in that, The reactive gas forming the first diffusion barrier sublayer contains nitrogen at a first gas flow rate to form a first diffusion barrier sublayer comprising a nitride material; The method for forming the diffusion barrier layer further includes: reducing the first gas flow rate to a second gas flow rate to form a second diffusion barrier sublayer containing a nitride material, wherein the first gas flow rate is greater than the second gas flow rate.

4. The method according to claim 3, characterized in that, The method of forming the second diffusion barrier layer further includes: using a physical vapor deposition process, wherein the negative bias power is selected from 200W to 600W, such that the second diffusion barrier layer is formed on the work function layer on the sidewall of the metal gate trench and on the first diffusion barrier layer at the bottom of the metal gate trench.

5. The method according to claim 3, characterized in that, Before forming the first diffusion barrier sublayer on the work function layer, the method further includes: Determine the voltage-nitrogen flow rate curve, which includes a first curve and a second curve. The first curve represents the voltage corresponding to the process of nitrogen gradually increasing from zero to a preset value, and the second curve represents the voltage corresponding to the process of nitrogen gradually decreasing from the preset value to zero. Based on the first curve, determine the inflection point of the voltage; Determine the smallest coincidence point among the coincidence points of the first curve and the second curve that is greater than the inflection point; and, The first gas flow rate is greater than the nitrogen flow rate corresponding to the minimum coincidence point, and the second gas flow rate is less than the nitrogen flow rate corresponding to the inflection point.

6. The method according to claim 3 or 5, characterized in that, The first gas flow rate is selected from 80 sccm to 120 sccm; And / or, The second gas flow rate is selected from 20 sccm to 40 sccm.

7. The method according to claim 3, characterized in that, When the first diffusion barrier sublayer is deposited for a preset process time, the first gas flow rate is reduced to the second gas flow rate to form the second diffusion barrier sublayer; The method for determining the preset process duration includes: Multiple sample substrates are provided, and multiple process durations are used to form a first diffusion barrier sublayer on each of the multiple sample substrates; The thickness of the first diffusion barrier sublayer formed is measured respectively, and the process time corresponding to the first diffusion barrier sublayer with a preset thickness is used as the preset process time.

8. The method according to claim 4, characterized in that, The method further includes: A wetting layer is formed on a second diffusion barrier sublayer located on the sidewall of the metal gate trench and on a second diffusion barrier sublayer located at the bottom of the metal gate trench; Metal material is filled into the grooves formed by the wetting layer.

9. The method according to claim 8, characterized in that, The wetting layer includes a titanium layer.

10. The method according to claim 1, characterized in that, The thickness of the first diffusion barrier sublayer covering the sidewalls of the metal gate trench is 0 to 0.5 nm; and / or, the thickness of the first diffusion barrier sublayer covering the bottom of the metal gate trench is 4 nm to 7 nm.

11. The method according to claim 1, characterized in that, The thickness of the first diffusion barrier sublayer at the bottom of the metal gate trench is 0.6 to 0.7 times the total thickness of the diffusion barrier layer.

12. A semiconductor structure, characterized in that, include: A substrate having a metal gate trench, the bottom and sidewalls of which have a work function layer; A diffusion barrier layer, including a first diffusion barrier sublayer, the first diffusion barrier sublayer being located on the work function layer at the bottom of the metal gate trench.

13. The semiconductor structure according to claim 12, characterized in that, The diffusion barrier layer further includes: a second diffusion barrier sublayer located on the work function layer of the sidewall of the metal gate trench, and a first diffusion barrier sublayer located at the bottom of the metal gate trench.

14. The semiconductor structure according to claim 13, characterized in that, Both the first diffusion barrier sublayer and the second diffusion barrier sublayer comprise nitride materials, and the nitrogen content in the first diffusion barrier sublayer is higher than the nitrogen content in the second diffusion barrier sublayer.

15. The semiconductor structure according to claim 14, characterized in that, The first diffusion barrier sublayer is a titanium nitride layer; And / or, the second diffusion barrier sublayer is a titanium nitride layer.

16. The semiconductor structure according to claim 13, characterized in that, Also includes: A wetting layer, the wetting layer being located on a second diffusion barrier sublayer on the sidewall of the metal gate trench and on a second diffusion barrier sublayer located at the bottom of the metal gate trench; Metallic material is filled into the grooves formed by the wetting layer.

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