MOSFET collinear packaging control method and system

Abstract

The invention relates to the technical field of semiconductor packaging, and discloses an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) collinear packaging control method and system, comprising a multi-chip collinear integration unit which is responsible for realizing a low parasitic path of power current and high-density arrangement of devices; the state sensing unit is used for synchronously collecting key parameters of each MOSFET in real time in the module operation process; the thermal-electric coordinated regulation and control unit is used for dynamically regulating the gate-source voltage of each chip through an independent programmable gate drive circuit; and the embedded control processing unit is used for receiving the real-time data from the state sensing unit, operating a lightweight closed-loop control algorithm and generating a thermal-electric coordinated regulation and control instruction. According to the scheme, the sensing, regulation and control and autonomous decision-making functions are integrated in the package, the current balance and heat distribution consistency of a multi-chip parallel system are improved, the local overload risk under the dynamic working condition can be relieved, and the operation reliability and availability of the module are enhanced through a localized heat buffering and fault grading response mechanism.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a MOSFET collinear packaging control method and system. Background Technology

[0002] MOSFET collinear packaging has been proposed as a structural form for highly integrated modules. This packaging method arranges multiple MOSFET chips with the same or complementary functions linearly along the main current path. By shortening the power commutation circuit and reducing parasitic inductance, it aims to improve electrical performance and electromagnetic compatibility at high frequencies. Typical application scenarios include the integration of upper and lower bridge arms in half-bridge or full-bridge topologies, where multiple MOSFETs need to coordinate to complete switching actions within microseconds.

[0003] In a MOSFET collinear package structure, multiple chips are closely arranged along the same main current path to reduce parasitic inductance in the power circuit and improve high-frequency switching performance. However, due to unavoidable process deviations such as solder thickness fluctuations, bond wire length differences, and chip mounting position offsets, the on-resistance RDS(on) and thermal resistance of each parallel MOSFET exhibit small but not negligible dispersion. Under dynamic operating conditions, especially high-frequency hard switching or high-current transient conditions, the chip with lower RDS(on) will turn on first and bear a larger proportion of the transient current, leading to local Joule heat concentration. Although silicon-based MOSFETs... RDS(on) has a positive temperature coefficient and can theoretically achieve thermal self-balancing. However, the time constant of this thermal feedback mechanism (usually in the millisecond range) is much slower than the switching transient process (in the microsecond range). It cannot effectively suppress current grabbing during the turn-on and turn-off phases. Under long-term operation, this dynamic uneven current will cause the local junction temperature to rise continuously, accelerating gate oxide degradation and solder joint fatigue. In severe cases, it can induce heat runaway, causing single chip overload failure, while other chips do not reach the rated load, reducing the overall reliability and power utilization of the module. Existing packaging technologies generally lack the ability to perceive and actively control the chip-level operating status in real time, making it difficult to solve this dynamic imbalance problem at the system level. Summary of the Invention

[0004] The purpose of this invention is to propose a MOSFET collinear package control method and system. It integrates an adjustable thermal management unit inside the package and combines it with an independent gate drive control mechanism to build a collaborative control system covering the thermal and electrical domains. This solution does not rely on external cooling equipment, and all control functions are inherent in the package body, making it suitable for space-constrained applications.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A MOSFET collinear package control method and system, comprising:

[0007] Multi-chip collinear integration unit: responsible for realizing low parasitic path of power current and high-density arrangement of devices, arranging several MOSFET chips linearly along the main current direction, and integrating a micro phase change thermal buffer cavity and a high thermal conductivity graphene thermal diffusion enhancement layer under each chip;

[0008] Status awareness unit: During module operation, key parameters of each MOSFET are collected in real time and synchronously, and the parameters are used as the basis for subsequent decision-making;

[0009] Thermal-electric coordinated control unit: Receives control commands and, based on real-time data provided by the state sensing unit, dynamically adjusts the gate-source voltage of each chip through an independent programmable gate drive circuit to compensate for on-resistance dispersion and suppress current snatching.

[0010] Embedded control processing unit: Receives real-time data from the state sensing unit, runs a lightweight closed-loop control algorithm, generates thermo-electric coordinated regulation commands, performs fault classification diagnosis, health log recording and parameter self-calibration, and drives the thermo-electric coordinated regulation unit through a dedicated channel.

[0011] As a preferred embodiment of the present invention, the multi-chip collinear integration unit includes the following modules: a collinear MOSFET chip array: all MOSFET chips are arranged in a straight line along the same main power circuit; a micro phase-change thermal buffer cavity: a cavity is formed in the copper layer on the DBC substrate directly below the source pad of each MOSFET chip by laser etching or photolithography, and the cavity is filled with a phase-change material; a reinforcement layer with thermal diffusion function: a graphene film with a thickness of about 500 nm is grown in situ on the copper layer surface of the DBC where the micro phase-change thermal buffer cavity has been completed; and an independent source lead-out module: the source of each chip is connected to a dedicated pad inside the package through an independent copper trace, the trace width is ≥200 μm, and the length difference is controlled within ±10 μm.

[0012] As a preferred embodiment of the present invention, the dimensions of the micro phase change thermal buffer cavity are 0.6mm × 0.6mm × 30μm.

[0013] As a preferred embodiment of the present invention, the multi-chip collinear integration unit is further provided with a differentiated configuration strategy for non-uniform melting points, which fills different micro phase change heat buffer cavities with phase change materials of different melting points according to the position of the chip in the array.

[0014] As a preferred embodiment of the present invention, the state sensing unit includes: an on-chip integrated temperature sensor: a miniature platinum resistance temperature sensor is integrated at the edge of the active region in the back-end metal interconnect process of MOSFET chip manufacturing to achieve temperature measurement; a high-bandwidth current sampling module: including a precision sampling resistor, a high common-mode rejection ratio differential amplifier, an input RC low-pass filter network, and a shielded differential trace structure, used to measure the drain current; a drain-source voltage detection module: a high-voltage thin-film resistor voltage divider network is integrated between the drain and source of each MOSFET chip to achieve isolated sampling of drain-source voltage inside the package; and a synchronous signal acquisition and interface module: the voltage, current, and temperature signals of all chips are uniformly acquired by a multi-channel synchronous sampling analog-to-digital converter.

[0015] As a preferred embodiment of the present invention, the independent programmable gate drive circuit in the thermo-electric coordinated control unit includes a high-speed operational amplifier, a 10-bit digital-to-analog converter, a programmable delay unit, and a hardware clamping protection circuit.

[0016] As a preferred embodiment of the present invention, the embedded control processing unit includes a local real-time control kernel, a non-volatile parameter storage area, a minimized external interface pin group, and an internal task scheduling and security monitoring logic module.

[0017] As a preferred embodiment of the present invention, the embedded control processing unit further includes a three-level response mechanism, which includes: a first level of dynamic derating, a second level of fault channel shutdown, and a third level of pulling down the fault status output pin to report the fault to the external system.

[0018] Based on the aforementioned MOSFET collinear packaging system, this invention also proposes a MOSFET collinear packaging control method, comprising the following steps: Step 1, Multi-physical quantity synchronous sensing: At the beginning of each control cycle, the temperature, current, and voltage of all parallel MOSFET chips are synchronously sampled at the hardware level using a state sensing unit; Step 2, Steady-state condition judgment: Based on the synchronous sensing data, the embedded control processing unit verifies the effectiveness of the sensors and calculates the key electrical parameters of each chip for the effective channels; Step 3, Thermal-electric coordinated regulation instruction generation: Based on the steady-state condition identification results, the embedded control processing unit generates active electronic control instructions, the thermal-electric coordinated regulation unit executes the instructions, and forms cross-scale coordination with the passive heat dissipation of the phase change material in the micro phase change thermal buffer cavity; Step 4, Three-level fault response and health management: According to the severity of the anomaly, derating, partial shutdown, or global reporting is performed in stages, and health logs are recorded to support predictive maintenance; Step 5, Parameter self-calibration and aging compensation: Control parameters are periodically updated to compensate for performance drift caused by device aging or environmental changes, and lightweight self-calibration is performed every 100ms.

[0019] As a preferred technical solution of the present invention, in step 5, parameter self-calibration and aging compensation, self-calibration is performed under light load and stable temperature conditions. The self-calibration includes: recalibrating the reference value of the on-resistance of each chip; fine-tuning the sensitivity of the gate-source voltage to the on-resistance based on the cumulative number of switching times and temperature rise history to compensate for the drift of the drive sensitivity caused by gate oxide degradation; and dynamically adjusting the phase change material differentiation configuration strategy based on the cumulative thermal stress.

[0020] The present invention has the following beneficial effects:

[0021] This solution, based on a MOSFET collinear package structure, enhances the operational consistency and long-term reliability of multi-chip parallel systems by embedding sensing, regulation, and autonomous decision-making capabilities. Compared to traditional collinear package modules that lack chip-level status feedback and active adjustment mechanisms, this solution helps improve the uniformity of current distribution under dynamic operating conditions, mitigating the risk of localized overload caused by manufacturing discreteness or uneven thermal coupling. The integrated micro phase-change thermal buffer structure provides localized buffering against transient thermal shocks without increasing the external cooling burden. Combined with electronic control compensation strategies, this makes thermal management more targeted. Simultaneously, the fault grading response and health status recording functions implemented within the package provide basic predictive maintenance support for the system and maintain controllable operation of other channels when some channels malfunction, improving overall availability. Furthermore, this solution maintains an external interface similar to conventional power modules, facilitating deployment in existing drive and heat dissipation architectures and enabling higher levels of integrated reliability and operational stability in high-density power electronics applications. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the MOSFET collinear packaging control method and system proposed in this invention;

[0023] Figure 2 This is a schematic diagram of a micro phase change thermal buffer cavity.

[0024] Figure 3 Flowchart of the fabrication process for a micro phase change thermal buffer cavity;

[0025] Figure 4 This is a flowchart of the fabrication process for the reinforcement layer;

[0026] Figure 5 This is a flowchart of a MOSFET collinear packaging control method. Detailed Implementation

[0027] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0028] Please refer to the appendix. Figure 1 A MOSFET collinear package control method and system, comprising the following units:

[0029] Multi-chip collinear integration unit: The multi-chip collinear integration unit is the physical foundation of the system, responsible for achieving low parasitic paths for power current and high-density device arrangement. It enables a high-density, low parasitic inductance power path layout and provides structural support for subsequent chip-level thermal-electrical synergistic regulation. This unit linearly arranges N (N≥2) MOSFET chips along the main current direction, integrating a miniature phase-change thermal buffer cavity and a high thermal conductivity graphene thermal diffusion enhancement layer beneath each chip. This allows the device to combine optimized electrical performance with localized thermal management capabilities. This structure embeds passive thermal buffering functionality into the packaging substrate, achieving chip-level thermal equalization without external cooling equipment and improving the problem of uneven dynamic current distribution. Specifically, it includes the following modules:

[0030] Collinear MOSFET chip array: All MOSFET chips are arranged in a straight line along the same main power circuit, with the chip center spacing controlled within the range of 0.8-1.5mm. The drains are connected to the high-voltage terminals in parallel through a shared metal clip or thick copper layer, and the sources are led out to independent pads. This layout can shorten the commutation path, effectively suppress voltage overshoot and electromagnetic interference during the switching process, and improve the stability of high-frequency operation.

[0031] Miniature phase change thermal buffer cavity: Please refer to the appendix Figure 2 In the upper copper layer of the standard direct bonding copper substrate (DBC substrate) directly below the source pad of each MOSFET chip, a closed microcavity is formed by laser etching or photolithography. The microcavity has a size of 0.6mm×0.6mm×30μm. The inner wall of the cavity is electrically and chemically insulated with AlN or Al2O3 ceramic material, which serves as the space for the subsequent phase change material (PCM) and constitutes the physical basis for passive thermal regulation. The phase change material is a customized organic PCM such as lauric acid with a melting point of 43℃, or a low melting point alloy such as Ga-In-Sn with a melting point of 10℃.

[0032] Traditional power modules rely solely on overall heat dissipation, such as bottom heat sinks, which cannot handle localized hot spots caused by manufacturing discreteness between chips. This solution integrates an independent microcavity in the substrate directly beneath each MOSFET chip and fills it with phase change material. This eliminates the need for thermoelectric coolers or fans, improving system reliability and providing a longer decision window for the electronic control algorithm to prevent instantaneous overload. The localized design of the microcavity ensures that the thermal buffering effect is only applied to the corresponding chip. Heat absorption is only activated when the temperature of a chip exceeds the melting point of the PCM, resulting in energy saving and precision while avoiding thermal crosstalk. Furthermore, its depth is controlled within 30μm, which does not affect the chip mounting coplanarity and solder wettability. The overall structure forms a passive, localized, and passive thermal buffering mechanism that can smooth temperature fluctuations on a millisecond to second timescale, avoiding positive feedback of thermal imbalance.

[0033] More specifically, please refer to the appendix. Figure 3 The fabrication steps of the micro phase change thermal buffer cavity are as follows:

[0034] Step 1: Prepare the substrate: Use a standard DBC substrate with a structure of Cu (300μm), Al2O3 (380μm), Cu (300μm); perform ultrasonic cleaning with acetone, rinse with deionized water, and dry with nitrogen; perform Ar and O2 mixed plasma activation to increase surface energy, thereby improving the adhesion of subsequent photoresist and the uniformity of thin film deposition.

[0035] Step 2, Microcavity Pattern Definition: Laser or photolithography is used. Laser direct writing is suitable for small-batch or rapid prototyping, while photolithography is more suitable for mass production. Specifically, when using photolithography, spin-coat photoresist to a thickness ≥40μm; soft bake at 95℃ for 30min; then expose a 0.6mm × 0.6mm square pattern pre-set directly below each MOSFET source pad using an i-line 365nm wavelength stepper lithography machine at a dose of 300mJ / cm². 2 Then develop with a special developer for 3-5 minutes, and bake at 95℃ for 10 minutes to stabilize the film. The pattern alignment accuracy is <±5μm, ensuring that the cavity is located below the heat flow center of the chip.

[0036] When using laser etching, a UV picosecond laser is used with a wavelength of 355nm, a pulse width of <10ps, a scanning speed of 500mm / s, a repetition frequency of 200kHz, and a single pulse energy of 0.5μJ. This method does not require a mask and is suitable for small batches of various products.

[0037] Step 3, Copper layer microcavity etching: For a depth of 30 μm, wet etching is used. Specifically, a mixed solution of ammonium persulfate (200 g / L) and sulfuric acid (50 mL / L) is used to wet etch the copper layer at 45 °C. The etching rate is controlled at about 1.2 μm / min for 25 minutes to form a microcavity with a depth of 30 μm. During the etching process, magnetic stirring is used to ensure uniformity and samples are taken at regular intervals to verify the depth.

[0038] Step 4: Deposit cavity isolation layer: After etching, N-methylpyrrolidone is used to remove residual photoresist, followed by ultrasonic cleaning with deionized water and nitrogen drying. Then, in a vacuum atomic layer deposition system, using trimethylaluminum and deionized water as precursors, an Al2O3 film of approximately 110 nm thickness is deposited at 200 °C. This film covers the bottom and sidewalls of the microcavity, effectively blocking direct contact between the PCM and the copper substrate, providing electrical insulation and preventing chemical reactions between the phase change material and copper, thus preventing electrochemical corrosion or metal miscibility.

[0039] Step 5, Phase Change Material Filling: The substrate is then placed in a vacuum chamber and the pressure is evacuated to below 10 Pa. The phase change material is heated to a molten state, for example, lauric acid is heated to 50°C to completely melt it. The injection volume is controlled by precision dispensing or vacuum capillary impregnation to fill the microcavity with liquid phase change material to a depth of about 25-27 μm. The vacuum is maintained for 10 minutes to remove air bubbles, and then the material is slowly cooled to solidify.

[0040] Step 6, Cavity Sealing: Finally, a 20nm thick Ti layer and a 50nm thick Cu seed layer are sequentially sputtered onto the substrate surface. Ti enhances the adhesion to the underlying oxide or organic surface, while Cu provides a continuous conductive path, laying the foundation for subsequent electroplating. Then, a pattern covering only the microcavity opening area is defined using photolithography, followed by sulfate electroplating at a current density of 2A / dm². 2 Under certain conditions, copper is electroplated to a thickness of approximately 10 μm in the patterned area to completely seal the cavity; finally, the remaining photoresist and the seed layer above it are removed using a stripping process or plasma stripping, and the surface is restored to a smooth state by chemical mechanical polishing, thus completing the integration of the micro phase change thermal buffer cavity.

[0041] In addition, the unit also features a differentiated configuration strategy with non-uniform melting points. Depending on the chip's position in the array, such as faster heat dissipation at the edges and slower heat dissipation at the center, different cavities are filled with PCMs of different melting points. For example, edge chips use PCMs with a melting point of 35°C for earlier activation to compensate for the heat dissipation advantage, while center chips use PCMs with a melting point of 45°C for delayed activation to avoid premature saturation. This achieves spatial adaptive thermal balance without the need for external energy or control signals, resulting in a simple and reliable structure. Furthermore, it only applies to the corresponding chip, avoiding thermal crosstalk and extending the electronic control response window.

[0042] An enhancement layer that combines interfacial thermal conductivity and lateral thermal diffusion: On the copper layer surface of the completed micro phase change thermal buffer cavity DBC, a graphene film with a thickness of about 500 nm and a lateral thermal conductivity of over 1000 W / m·K is grown in situ to construct an efficient lateral thermal diffusion channel, accelerate the transfer of local heat from the chip to the entire phase change material region, and improve the thermal buffer response speed and uniformity. It should be noted that the graphene growth process must be completed before the MOSFET chip is mounted to avoid the high temperature process affecting the reliability of subsequent solders.

[0043] Specifically, please refer to the appendix. Figure 4 The preparation steps of the high thermal conductivity interface and the thermal diffusion enhancement layer are as follows:

[0044] Substrate pretreatment: The DBC substrate, which has been sealed in a micro phase change heat buffer cavity and polished, is subjected to high-temperature hydrogen annealing. It is kept at 400°C and H2 flow rate of 500 sccm for 30 minutes to allow the surface of the upper copper layer to recrystallize and preferentially expose the (111) crystal plane, providing a highly oriented substrate for subsequent graphene epitaxial growth. It is explained here that the (111) crystal plane is one of the densest packed crystal planes in copper crystals, and its surface energy is the lowest, which means that it is the most stable and has the best adhesion to graphene. Therefore, in the process of graphene chemical vapor deposition growth, preferential exposure of the (111) crystal plane can promote the epitaxial growth of high-quality single crystal graphene.

[0045] CVD growth of graphene: The substrate is transferred to an atmospheric pressure CVD system. After evacuation, high-purity H2 is introduced at a flow rate of 10 to raise the temperature to 600°C and stabilize for 10 minutes to completely reduce the oxide on the copper surface. Then, methane (CH4) gas at a flow rate of 10 sccm is introduced and reacts with H2 for 20 minutes, causing carbon atoms to catalytically decompose on the copper surface and self-assemble to form a continuous graphene film. The low CH4 concentration and high growth temperature synergistically suppress nucleation density and promote the formation of large-size domains. After growth, the CH4 is immediately turned off, the H2 atmosphere is maintained, and the substrate is slowly cooled to room temperature at a rate of less than 5°C / min to minimize wrinkles and cracks caused by thermal stress. The entire process does not require a subsequent transfer step, and the graphene is directly retained on the surface of the DBC copper layer, avoiding the organic residue pollution problem caused by polymethyl methacrylate as a support layer commonly used in traditional transfer processes.

[0046] Independent source lead-out module: The source of each chip is connected to a dedicated pad inside the package via an independent copper trace. The trace width is ≥200μm and the length difference is controlled within ±10μm. This part provides a physical channel for current sampling and independent gate driving, avoiding common impedance coupling introduced by the shared source, and ensuring the independence and accuracy of the control signal.

[0047] State sensing unit: During module operation, it collects the parameters of each MOSFET in real time, synchronously and with high precision. These parameters are the basis for subsequent thermal-electric coordinated control algorithm to make decisions. Compared with the traditional power module that only relies on external current sensors or coarse temperature estimation, this unit integrates the sensing element directly into the chip or on the packaging substrate to achieve chip-level granularity and provide a reliable data foundation for closed-loop control. Through a low parasitic, high bandwidth, and coplanar integrated sensing architecture, it can accurately capture high-frequency dynamic conditions without introducing additional switching oscillations or power losses.

[0048] The state awareness unit consists of four modules: an on-chip integrated temperature sensor, a high-bandwidth current sampling module, a drain-source voltage detection module, and a synchronous signal acquisition and interface module. Each module works collaboratively to ensure high consistency of data in time, space, and accuracy. Specifically:

[0049] On-chip integrated temperature sensor: In the back-end metal interconnect process of MOSFET chip manufacturing, a miniature platinum resistance temperature sensor is integrated at the edge of the active region, i.e., near the power cell but without affecting electrical performance. This sensor utilizes the physical property that the resistance of platinum metal changes approximately linearly with temperature to achieve temperature measurement. This temperature coefficient is approximately 0.00385 / ℃. When the chip junction temperature changes, the resistance of the platinum resistance changes accordingly. An external constant current source, typically 1mA, is injected into this resistor to generate a voltage signal proportional to the temperature, i.e.:

[0050] V T =I bias ×R Pt (T);

[0051] Among them, V T I represents the sensing voltage output across the platinum resistance thermometer. bias This represents the constant bias current applied to the platinum resistance thermometer, typically 1 mA, R Pt (T) represents the resistance of the platinum resistance at the current junction temperature T. This voltage is acquired by the analog-to-digital converter of the embedded controller, and the current junction temperature is calculated by looking up a table or using a linear formula.

[0052] The sensor is connected to a dedicated sensing pad near the chip source via two aluminum interconnect leads. After packaging, it can still be accessed through internal traces without the need for additional wiring or external probes. The measurement range is −40℃ to 150℃. This module can directly reflect the junction temperature, rather than the temperature of the casing or heat sink, avoiding hysteresis and distortion. It has no external leads, does not increase parasitic inductance, and does not affect high-frequency switching performance. In addition, it supports independent temperature measurement of multiple chips, providing basic data for thermal balance control.

[0053] High-bandwidth current sampling module: Includes precision sampling resistors, low-resistance, non-inductive resistors fabricated using thin-film technology, with a resistance range of 5-10mΩ, a temperature coefficient below 25ppm / ℃, and a rated power of not less than 1W. Physically, they are connected in series in the independent source copper trace of each MOSFET chip, located between the chip's source solder joint and the common source plane of the DBC substrate; High common-mode rejection ratio differential amplifier, using commercially available integrated analog front-end chips, such as TI's INA180 series and ADI's AD8421, with a common-mode rejection ratio of ≥80dB and a small-signal impedance analysis (SMI) of ≥10MHz. The bandwidth is such that its input is directly connected to both ends of the sampling resistor; the input RC low-pass filter network consists of a small thin-film resistor (typically 10-100Ω) and a chip ceramic capacitor (typically 10-100pF), integrated near the input pin of the differential amplifier, forming a first-order low-pass filter with a cutoff frequency of approximately 1 to 5 MHz; the shielded differential trace structure uses symmetrical, equal-length, parallel wiring between the sampling resistor and the differential amplifier, and is completely surrounded by a continuous grounded copper layer to suppress dv / dt coupling noise and magnetic field interference from the main power circuit to the greatest extent.

[0054] When the MOSFET is turned on, the drain current flows through the sampling resistor, generating a microvolt-level differential voltage signal proportional to the current across its terminals. This signal is superimposed on a common-mode potential of up to several hundred volts and is accompanied by high-frequency switching transient noise. The differential amplifier utilizes its high common-mode rejection capability to extract and amplify only the differential component at both ends, while suppressing common-mode interference. The input RC low-pass filter network further attenuates high-frequency oscillation components above megahertz to prevent aliasing and overshoot. The conditioned output signal is a single-ended analog voltage in the range of 0-3.3V, whose amplitude accurately reflects the instantaneous current magnitude, and whose rise and fall edge fidelity is sufficient to capture the switching dynamic process at the level of hundreds of nanoseconds. This signal is then sent to the synchronous analog-to-digital converter of the embedded control processing unit as the core input of the current sharing algorithm. The entire link achieves high-fidelity, high-synchronization, and high-bandwidth monitoring of the current of each chip while ensuring low insertion loss, providing a reliable data foundation for dynamic current sharing control.

[0055] Drain-Source Voltage Detection Module: A high-voltage thin-film resistor divider network is integrated between the drain and source of each MOSFET chip. This network consists of two high-precision, high-voltage-resistance thin-film resistors with a typical voltage division ratio of 100:1, for example, an upper resistor of 990 kΩ and a lower resistor of 10 kΩ. The voltage divider output is connected to the ADC input after passing through an RC low-pass filter to suppress high-frequency switching noise while retaining DC voltage information in the on-state. This achieves chip-level drain-source voltage isolation sampling within the package, avoiding parasitic capacitance and safety risks introduced by external high-voltage probes.

[0056] During MOSFET operation, its drain-source voltage VDS In the off state, the DC bus voltage is achievable and cannot be directly acquired by the low-voltage controller. This module uses an on-chip integrated high-precision thin-film resistor voltage divider network to attenuate the high voltage by a fixed ratio, generating a voltage equivalent to V. DS The low-voltage signal exhibits a strictly linear relationship; after filtering, the signal is sent to the analog-to-digital converter of the embedded control processing unit via a dedicated sensing path, where it is digitized under synchronous triggering of current sampling; combined with the synchronously acquired drain current value, the system can calculate the drain-source on-resistance of each chip in real time.

[0057] R DS (on)=V DS / I D ,

[0058] Among them, V DS This represents the DC voltage drop during steady-state conduction, I. D This represents the drain current flowing through the MOSFET, which is synchronously measured by the high-bandwidth current sampling module;

[0059] This parameter directly reflects the manufacturing discreteness, temperature drift, and aging state of the device. It is the core basis for achieving adaptive current sharing in the thermo-electric synergistic control algorithm. The entire detection link does not require external high-voltage isolation devices and is completely embedded in the chip and package, combining high safety, high precision, and high integration.

[0060] Synchronous Signal Acquisition and Interface Module: The voltage, current, and temperature signals of all N chips are uniformly acquired by a multi-channel synchronous sampling analog-to-digital converter (ADC). This ADC has hardware synchronous triggering function, and all channels share the same sampling clock, completing data latching at the same time (time error <10 nanoseconds). The embedded controller starts the sampling cycle at a frequency of 1 kHz to ensure data time alignment. This part solves the problem of false current deviation caused by asynchronous sampling by introducing a hardware-level synchronous sampling architecture in the multi-chip parallel system, avoiding misjudgment of a chip's current being too high or resistance being too low due to sampling time misalignment; improving the reliability and repeatability of on-resistance identification; and providing a high-fidelity, low-noise state vector for subsequent closed-loop control.

[0061] Thermo-electric Co-regulation Unit: Based on real-time data provided by the state sensing unit, and utilizing an integrated micro-phase change thermal buffer cavity, it absorbs local heat energy through latent heat of phase change during transient overload, providing the electronic control algorithm with a millisecond-level response window. This unit overcomes the limitations of traditional regulation that relies solely on a single method, such as adjusting only the gate voltage or simply enhancing heat dissipation, and constructs a co-regulation system that spans time scales and involves multi-physics coupling. Specifically:

[0062] Active electronic control method: Dynamically adjust the gate-source voltage V of each chip through an independent programmable gate drive circuit. GSCompensation for on-resistance R caused by manufacturing variations or temperature drift DS (on) difference, to achieve precise current equalization, this independently programmable gate drive circuit includes:

[0063] High-speed operational amplifier: slew rate >50 V / µs, ensuring rapid gate voltage build-up;

[0064] 10-bit digital-to-analog converter (DAC): update rate ≥100 kHz, used to generate fine-compensation voltage;

[0065] Programmable delay unit: delay step 1 nanosecond, range 0-20 nanoseconds, used to optimize turn-on and turn-off synchronization;

[0066] Hardware clamping protection circuit: ensures that the final drive voltage is always within a safe range, such as 10-15V, and the instantaneous peak value does not exceed 18V, to prevent gate oxide breakdown.

[0067] The active electronic control method and the passive thermal buffer cavity complement each other in terms of time and function. The electronic control quickly suppresses current grabbing, while the thermal buffer delays the accumulation of temperature rise. It can simultaneously deal with the problems of electrical dispersion and uneven thermal coupling, eliminate current distribution imbalance, and has the ability to adapt to non-ideal factors such as incoming material fluctuations, solder voids, and aging degradation. Users do not need to add complex current sharing inductors or additional heat dissipation measures to obtain high reliability parallel performance. Only the control circuit needs to be integrated inside the package, and the external interface is kept consistent with standard power modules such as TO-247-4L and HPDIP-24, which means it is compatible with the existing drive and heat dissipation ecosystem.

[0068] Embedded Control Processing Unit: Receives multi-dimensional real-time data from the state sensing unit, runs a lightweight closed-loop control algorithm, generates thermo-electric coordinated regulation commands, and drives the actuator through a dedicated channel. This unit is fully integrated within the package, independent of external processors or host computers, achieving localized, low-latency, and highly reliable autonomous decision-making capabilities. This unit focuses on chip-level fine-grained management, completing the identification, deviation calculation, and compensation output of the conduction state of each MOSFET within millisecond cycles, forming a complete "sensing-decision-execution" closed loop. It achieves maximum regulation efficiency with limited computing power, specifically including:

[0069] Local real-time control kernel: a 32-bit microcontroller based on the ARM Cortex-M4 architecture, with a main frequency of 100MHz, and a built-in single-precision floating-point unit (FPU) and hardware divider, dedicated to executing the encapsulated internal closed-loop control algorithm;

[0070] Non-volatile parameter storage area: integrates 64kB flash memory and 8kBEEPROM, used to store the proportional gain coefficient K, chip calibration offset, melting point configuration mapping table and cumulative operating status log;

[0071] Minimize the external interface pin group: It includes 4 low-speed signal pins for power supply, basic gate drive input, and fault status output, which are compatible with the pin definitions of standard power module packages;

[0072] Internal task scheduling and safety monitoring logic: A finite state machine implemented by firmware, responsible for periodic triggering, exception detection, derating strategy execution, and watchdog protection.

[0073] The gate-source voltage V applied to the i-th chip GS,i is determined by the following formula:

[0074] V GS,i = V GS,base + ΔV GS,i

[0075] where, V GS,base is the basic PWM drive signal issued by the main controller; ΔV GS,i is the adaptive compensation voltage generated for the i-th chip, used to correct the deviation of its conduction characteristics, where:

[0076] ΔV GS,i = K ⋅ (Ravg − R DS(on),i )

[0077] K is a pre-calibrated proportional gain coefficient, reflecting the regulation sensitivity of the gate-source voltage to the on-resistance. Its value is determined by off-line experiments or device model fitting, with a typical value of 0.8 - 1.5 V / Ω. R DS(on),i is the drain-source on-resistance of the i-th MOSFET chip in the on state, and Ravg represents the arithmetic average of the on-resistances of all N parallel MOSFET chips in the current control cycle;

[0078] If the on-resistance of a certain chip is lower than the average value, i.e., R DS(on),i < Ravg, it means that its conduction ability is too strong and it is easy to snatch current, then ΔV GS, i < 0, reducing its drive strength;

[0079] If the on-resistance of a certain chip is higher than the average value, R DS(on),i > Ravg, it means that its conduction ability is weak, and ΔV GS,i > 0, enhancing its drive strength;

[0080] This solution achieves N-way decoupled gate drive within a single package, replacing the traditional one-drive-multiple-transistor mode. This improves dynamic current sharing accuracy and suppresses the "current snatching" phenomenon during switching transients. Furthermore, the programmable delay unit in the independent programmable gate drive circuit allows for precise calibration of the turn-on and turn-off times of each chip, optimizing EMI and switching losses. Peak-shifting turn-on reduces di / dt peak values, and synchronous turn-off reduces reverse recovery current stress. The closed-loop adaptive compensation design provides a compensation amount ΔV. GS,i It updates in real time as the chip ages and temperature drifts, automatically compensating for R-values ​​caused by aging. DS(on) Increase the current to maintain current balance and prevent individual chips from failing prematurely due to long-term overcurrent.

[0081] Furthermore, this unit, as an autonomous intelligent module within the package, autonomously completes the "sensing-computation-output-diagnosis" closed loop at a fixed period of 1kHz without external intervention. Throughout the operation, the unit continuously records key health indicators such as maximum temperature difference, current imbalance, and number of switching operations. In addition, the unit is equipped with a three-level response mechanism.

[0082] Level 1 is dynamic derating. The triggering condition can be set to a slight over-limit of current imbalance, such as within 10%-15%, or the temperature of a single chip is close to the alarm threshold, such as between 130℃ and 140℃.

[0083] Level 2 is fault channel shutdown, triggered by sensor failure, single chip overheating (e.g., exceeding 140°C), severe current imbalance (e.g., >15%), or sudden change in single channel on-resistance.

[0084] Level 3 is for pulling down the fault state output pin to report the fault to the external system. This includes simultaneous faults in multiple channels, such as ≥2 chips overheating or failing, abnormally sudden increase in total output current, continuous deterioration of key parameters and invalidation of Level 1 and Level 2, and cumulative number of faults exceeding the safety threshold.

[0085] It automatically activates when abnormal conditions such as over-temperature, current imbalance exceeding limits, or sensor failure are detected. The data threshold in the response mechanism can be customized, and the default value is set based on the device reliability boundary. All operating logic is implemented by local firmware. Only basic drive signals and power are required from the outside. It does not rely on the host computer to participate in real-time control, thus achieving package-level intelligent self-adjustment while maintaining external interface compatibility.

[0086] Based on the above MOSFET collinear package system, please refer to the appendix. Figure 5 The present invention also proposes a MOSFET collinear package control method, which includes the following steps:

[0087] Step 1, Multi-physical Quantity Synchronous Sensing: At the beginning of each control cycle, the temperature, current, and voltage of all parallel MOSFET chips are synchronously sampled at the hardware level using the state sensing unit to construct a high-fidelity state vector. Specifically:

[0088] The junction temperature T of each MOSFET chip is obtained using an on-chip platinum resistance temperature sensor. i (i=1,2,...,N);

[0089] The drain current I of each chip is collected using a high-bandwidth current sampling module when the MOSFET is in a steady-state conduction state. D,i ;

[0090] The drain-source voltage drop V of each chip is synchronously collected within the same conduction steady-state window using a drain-source voltage detection module. DS,i ;

[0091] All signals are latched by a multi-channel synchronous ADC on the same clock edge, with a time alignment error of <10ns, ensuring state vector consistency.

[0092] It is important to note that V is only enabled when the main control PWM signal indicates that the MOSFET is in the on state and the current change rate |di / dt| < the threshold (e.g., 5A / μs). DS,i with I D,i Sampling is performed to eliminate transient interference from switching.

[0093] Step 2, Steady-state condition judgment: Based on synchronous sensing data, the embedded control processing unit verifies the validity of the sensors and calculates the key electrical parameters of each chip for valid channels, specifically including:

[0094] Determining sensor effectiveness: If any platinum resistance value R Pt,i If it does not belong to [10 Ω, 200 Ω], mark the corresponding channel sensor as faulty.

[0095] Calculate the on-resistance of the i-th chip:

[0096] ;

[0097] Among them, R DS(on),i V represents the drain-source on-resistance of the i-th MOSFET chip in its current on-state; DS,i I represents the drain-source DC voltage drop of the i-th chip when it is in steady-state conduction; D,i This represents the drain current flowing through the i-th chip, which is synchronously measured by the high-bandwidth current sampling module; i is the chip index, with a value range of 1≤i≤N, and N is the total number of parallel MOSFET chips (N≥2).

[0098] Calculate the arithmetic mean of the on-resistances of N chips:

[0099] ;

[0100] Where Ravg represents the arithmetic mean of the on-resistance of all parallel MOSFET chips in the current control cycle; j is the summation index, which iterates through all valid chip channels. If a channel is turned off or fails, it is excluded from the summation.

[0101] Calculate the current imbalance:

[0102] ;

[0103] η I This represents the normalized current imbalance, usually evaluated as a percentage; max(I D,i ) represents the maximum drain current among all valid chips; min(I D,i The mean(I) represents the minimum drain current among all valid chips. D,i ) represents the arithmetic mean of the drain currents of all valid chips.

[0104] Step 3: Generation of Thermo-Electrical Co-regulation Commands: Based on the health status identification results, the embedded control processing unit generates active electronic control commands such as gate voltage compensation and switching timing fine-tuning. The thermo-electric co-regulation unit executes these commands, forming cross-scale coordination with the passive thermal buffer mechanism. Specifically, this includes:

[0105] Active electronic control compensation: Generates an adaptive gate voltage compensation amount ΔV for each chip. GS,i The gate-source driving voltage V was calculated. GS,i And it is limited to a safe range of 10V≤V through hardware clamping circuit. GS,i ≤15V, instantaneous allowable ≤18V;

[0106] Switching timing fine-tuning: Based on chip location and historical switching losses, programmable delay units are dynamically configured: for edge chips, areas with fast heat dissipation and easy overcurrent, the turn-on delay is increased, for example, +2~5ns, to suppress current preemption; for central chips, i.e. areas with slow heat dissipation, the turn-off is advanced, for example, the advance time is −1~3ns, to reduce reverse recovery stress; all adjustment steps are 1ns, with a range of 0-20ns.

[0107] Passive thermal buffer status assessment: Record the temperature rise rate dT of each chip. i / dt and whether the corresponding PCM melting point has been exceeded are used for fault warning and log recording.

[0108] Step 4, Level 3 Fault Response and Health Management: Based on the severity of the anomaly, implement tiered measures such as de-rating, partial shutdown, or global reporting, and record health logs to support predictive maintenance. Specifically:

[0109] Real-time monitoring determines whether abnormal conditions such as excessively high temperature, current imbalance, or sudden changes in resistance occur, and activates the response mechanism according to the severity:

[0110] Level 1 response: Dynamic devaluation, for example, reducing all V... GS,i Reduce the total output power by 5%, and monitor continuously.

[0111] Level 2 response: Shut down the faulty channel and force the abnormal chip to V. GS,i =0, the remaining chips continue to run, and Ravg is updated to the average of the remaining valid chips;

[0112] Level 3 response: Pull the fault status output pin low to report the fault to the external main controller, and enter the safe shutdown mode at the same time.

[0113] All events such as maximum temperature difference, η I The number of times the device is switched on and off, the type of fault, etc. are written to the EEPROM log, which supports lifespan prediction and maintenance.

[0114] Step 5, Parameter Self-calibration and Aging Compensation: Periodically update control parameters to compensate for performance drift caused by device aging or environmental changes. Perform a lightweight self-calibration every 100 control cycles (100ms) under light load (<20% of rated current) and stable temperature conditions:

[0115] Recalibrate the R of each chip DS(on),i Benchmark value;

[0116] Based on the cumulative number of switching cycles and temperature rise history, the gain coefficient K (±2%) is finely adjusted to compensate for the drive sensitivity drift caused by gate oxide degradation.

[0117] Based on the accumulated thermal stress, the PCM melting point mapping strategy is dynamically adjusted. For example, after long-term high-temperature operation, the central chip PCM may partially decompose, and a higher melting point strategy can be switched.

[0118] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A MOSFET collinear packaging system, characterized in that, include: Multi-chip collinear integration unit: responsible for realizing low parasitic path of power current and high-density arrangement of devices, arranging several MOSFET chips linearly along the main current direction, and integrating a micro phase change thermal buffer cavity and a high thermal conductivity graphene thermal diffusion enhancement layer under each chip; Status awareness unit: During module operation, key parameters of each MOSFET are collected in real time and synchronously, and the parameters are used as the basis for subsequent decision-making; Thermal-electric coordinated control unit: Receives control commands and, based on real-time data provided by the state sensing unit, dynamically adjusts the gate-source voltage of each chip through an independent programmable gate drive circuit to compensate for on-resistance dispersion and suppress current snatching. Embedded control processing unit: Receives real-time data from the state sensing unit, runs a lightweight closed-loop control algorithm, generates thermo-electric coordinated regulation commands, performs fault classification diagnosis, health log recording and parameter self-calibration, and drives the thermo-electric coordinated regulation unit through a dedicated channel.

2. The MOSFET collinear packaging system according to claim 1, characterized in that, The multi-chip collinear integration unit includes the following modules: Collinear MOSFET chip array: All MOSFET chips are arranged in a straight line along the same main power loop; Miniature phase change thermal buffer cavity: A cavity is formed in the copper layer of the DBC substrate directly below the source pad of each MOSFET chip by laser etching or photolithography, and the cavity is filled with phase change material. A reinforcing layer with thermal diffusion function: A graphene film with a thickness of about 500 nm is grown in situ on the copper layer surface of the completed micro phase change thermal buffer cavity DBC. Independent source lead-out module: The source of each chip is connected to a dedicated pad inside the package via an independent copper trace. The trace width is ≥200μm and the length difference is controlled within ±10μm.

3. A MOSFET collinear packaging system according to claim 2, characterized in that, The dimensions of the micro phase change thermal buffer cavity are 0.6mm × 0.6mm × 30μm.

4. A MOSFET collinear packaging system according to claim 3, characterized in that, The multi-chip collinear integration unit also has a differentiated configuration strategy for non-uniform melting points, which fills different micro phase change heat buffer cavities with phase change materials of different melting points according to the position of the chip in the array.

5. A MOSFET collinear packaging system according to claim 1, characterized in that, The state sensing unit includes: On-chip integrated temperature sensor: In the back-end metal interconnect process of MOSFET chip manufacturing, a miniature platinum resistance temperature sensor is integrated at the edge of the active region to achieve temperature measurement. High-bandwidth current sampling module: includes a precision sampling resistor, a high common-mode rejection ratio differential amplifier, an input RC low-pass filter network, and a shielded differential trace structure, used to measure drain current; Drain-source voltage detection module: A high-voltage thin-film resistor voltage divider network is integrated between the drain and source of each MOSFET chip to achieve isolated sampling of drain-source voltage inside the package; Synchronous signal acquisition and interface module: The voltage, current and temperature signals of all chips are acquired by a multi-channel synchronous sampling analog-to-digital converter.

6. A MOSFET collinear packaging system according to claim 1, characterized in that, The independent programmable gate drive circuit in the thermo-electric co-regulation unit includes a high-speed operational amplifier, a 10-bit digital-to-analog converter, a programmable delay unit, and a hardware clamping protection circuit.

7. A MOSFET collinear packaging system according to claim 1, characterized in that, The embedded control processing unit includes a local real-time control kernel, a non-volatile parameter storage area, a minimized external interface pin group, and an internal task scheduling and security monitoring logic module.

8. A MOSFET collinear packaging system according to claim 7, characterized in that, The embedded control processing unit also includes a three-level response mechanism, which includes: level 1 dynamic derating, level 2 fault channel shutdown, and level 3 pulling the fault status output pin low to report the fault to the external system.

9. A MOSFET collinear packaging control method, based on the MOSFET collinear packaging system according to any one of claims 1-9, characterized in that, Includes the following steps: Step 1, Synchronous Sensing of Multiple Physical Quantities: At the beginning of each control cycle, the temperature, current and voltage of all parallel MOSFET chips are synchronously sampled at the hardware level using the state sensing unit. Step 2, Steady-state condition judgment: Based on synchronous sensing data, the embedded control processing unit is used to verify the effectiveness of the sensor and calculate the key electrical parameters of each chip for the effective channel; Step 3: Generation of thermo-electric synergistic control instructions: Based on the steady-state operating condition identification results, the embedded control processing unit generates active electronic control instructions, the thermo-electric synergistic control unit executes the instructions, and forms a cross-scale synergy with the passive heat dissipation of the phase change material in the micro phase change thermal buffer cavity. Step 4, Level 3 Fault Response and Health Management: Based on the severity of the anomaly, implement tiered measures such as de-rated response, partial shutdown, or global reporting, and record health logs to support predictive maintenance; Step 5, Parameter self-calibration and aging compensation: Periodically update control parameters to compensate for performance drift caused by device aging or environmental changes, and perform a lightweight self-calibration every 100ms.

10. A MOSFET collinear package control method and system according to claim 9, characterized in that, In step 5, parameter self-calibration and aging compensation, the self-calibration is performed under light load and stable temperature conditions, and the self-calibration includes: Recalibrate the on-resistance reference value of each chip; Based on the cumulative number of switching cycles and temperature rise history, the sensitivity of the gate-source voltage to the on-resistance is finely adjusted to compensate for the drift in drive sensitivity caused by gate oxide degradation. Based on the cumulative thermal stress, the differentiated configuration strategy of phase change materials is dynamically adjusted.

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