Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a forming method thereof. The method includes forming a first multi-layer stack in a first device region, forming a first gate stack over the first multi-layer stack, forming a second multi-layer stack in a second device region, forming a second gate stack over the second multi-layer stack, etching the first multi-layer stack to form a first source / drain recess, and forming a second source / drain recess over the second multi-layer stack. And etching the second multilayer stack to form a second source / drain recess. The method further includes forming a hard mask in the second source / drain recess and forming a lower source / drain region in the first source / drain recess. After the lower source / drain region is formed, the hard mask is removed from the second source / drain recess. A first upper source / drain region and a second upper source / drain region are formed in the first source / drain recess and the second source / drain recess, respectively.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic products, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and then using photolithography to pattern these material layers to form circuit elements.

[0003] The semiconductor industry increases the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest component, allowing more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of the present application, a method for forming a semiconductor structure is provided, comprising: forming a first multilayer stack in a first device region; forming a first gate stack on the first multilayer stack; forming a second multilayer stack in a second device region; forming a second gate stack on the second multilayer stack; etching the first multilayer stack to form a first source / drain trench; etching the second multilayer stack to form a second source / drain trench; forming a hard mask in the second source / drain trench; forming a lower source / drain region in the first source / drain trench; removing the hard mask from the second source / drain trench after forming the lower source / drain region; and forming a first upper source / drain region in the first source / drain trench and a second upper source / drain region in the second source / drain trench, respectively.

[0005] According to another aspect of the embodiments of this application, a method for forming a semiconductor structure is provided, comprising: forming a first source / drain trench in a first device region, wherein the first source / drain trench is located between two adjacent first multilayer stacks, and wherein a first top surface of the first semiconductor region is located below and exposed to the first source / drain trench; forming a second source / drain trench in a second device region, wherein the second source / drain trench is located between two adjacent second multilayer stacks, and wherein a second top surface of the second semiconductor region is located below and exposed to the second source / drain trench; forming a hard mask in the second source / drain trench and on the surfaces of the two adjacent second multilayer stacks; forming a lower source / drain region in the first source / drain trench; removing the hard mask; and forming a first contact etch stop layer, comprising: a first portion located in the first source / drain trench, wherein the first portion contacts a third top surface of the lower source / drain region; and a second portion located in the second source / drain trench, wherein the second portion contacts a second top surface of the second semiconductor region.

[0006] According to another aspect of the embodiments of this application, a semiconductor structure is provided, comprising: a first device, including: a first plurality of semiconductor nanostructures, including a first semiconductor nanostructure and a second semiconductor nanostructure overlapping the first semiconductor nanostructure; a lower source / drain region laterally adjacent to the first semiconductor nanostructure; and a first upper source / drain region overlapping the lower source / drain region, wherein the first upper source / drain region contacts the second semiconductor nanostructure; a first dielectric region located between the lower source / drain region and the first upper source / drain region; and a second device, including: a second plurality of semiconductor nanostructures, including a third semiconductor nanostructure and a fourth semiconductor nanostructure overlapping the third semiconductor nanostructure; and a second upper source / drain region laterally adjacent to the fourth semiconductor nanostructure; and a second dielectric region located below the second upper source / drain region, wherein the second dielectric region laterally adjacent to the third semiconductor nanostructure. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A perspective view of an exemplary complementary field-effect transistor (CFET) according to some embodiments is shown.

[0009] Figures 2 to 4 , Figures 5A to 5B, Figures 6A to 6B , Figures 7A to 7B , Figures 8A to 8C , Figures 9A to 9B , Figures 10A to 10B , Figures 11A to 11B , Figures 12A to 12B 13A and Figure 13B A view of an intermediate stage in the formation of a CFET according to some embodiments is shown.

[0010] Figure 14A and Figure 14B A CFET structure is shown that, according to some embodiments, can be used to form a portion of a static random access memory (SRAM) cell.

[0011] Figure 15 A circuit schematic of an SRAM cell according to some embodiments is shown.

[0012] Figure 16 A flowchart illustrating the formation of a CFET and a pseudo-CFET according to some embodiments is shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0015] A complementary field-effect transistor (CFET), a pseudo-CFET, and a method for forming the same are provided. The pseudo-CFET has a structure similar to a CFET but lacks one of the FETs, such as a lower FET. In some embodiments, the CFET and the pseudo-CFET form a static random access memory (SRAM) cell (e.g., as shown in the image). Figure 15 The portion shown is part of the SRAM cell 100.

[0016] It is understood that although the PFET is the lower FET in the CFET in the example embodiment, in some alternative embodiments, the PFET may also be formed as the upper FET. Furthermore, in the example illustrated embodiment, the pseudo-CFET lacks the lower FET and has the upper FET. This process concept can also be applied to forming a pseudo-CFET lacking the upper FET and having the lower FET. Although CFETs and pseudo-CFETs are discussed for forming SRAM cells in some example embodiments, they can also be used in any other circuit where there are more PFETs than NFETs, or more NFETs than PFETs. Throughout this specification, the terms "FET" and "transistor" are used interchangeably.

[0017] Figure 15 Circuit diagrams of SRAM cell 100 in some embodiments are shown. SRAM cell 100 includes pull-up transistors PU-1 and PU-2, which are PFETs. SRAM cell 100 also includes pull-down transistors PD-1 and PD-2 and transmission gate transistors PG-1 and PG-2, which are NFETs. The gates of transmission gate transistors PG-1 and PG-2 are connected to and controlled by word line WL to determine whether SRAM cell 100 is selected.

[0018] A latch formed by pull-up transistors PU-1 and PU-2 and pull-down transistors PD-1 and PD-2 can store one bit of data, wherein the complementary value of the bit data is stored in storage nodes SN-1 and SN-2. The stored bit data can be written to or read from SRAM cell 100 via complementary bit lines containing bit lines (BL) and bit line inversion (BLB).

[0019] According to some embodiments, the PFET and NFET in SRAM cell 100 can be implemented using CFET, and their structure can be as follows: Figure 1 As shown. SRAM cell 100 can be accessed via... Figures 2 to 13A and Figure 13B The process flow shown is implemented as follows. It should be noted that the CFET can have pairs of PFETs and NFETs. However, the number of PFETs in the SRAM cell 100 can differ from the number of NFETs, for example... Figure 15 The diagram shows four PFETs and two NFETs, and therefore the PFETs and NFETs are not paired. Embodiments of this disclosure provide methods and structures for implementing such unpaired PFETs and NFETs.

[0020] Figure 1An example of a CFET 10 (including FET (transistor) 10U and 10L) according to some embodiments is shown, which has a structure that can be used to implement unpaired PFETs and NFETs (e.g., SRAM cell 100). Figure 1 This is a 3D view, in which some features of the CFET are omitted for clarity.

[0021] A CFET comprises multiple vertically stacked FETs. For example, a CFET may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type), the second device type being the opposite of the first device type. The nanostructure FETs 10U and 10L include semiconductor nanostructures 26' (including a lower semiconductor nanostructure 26'L and an upper semiconductor nanostructure 26'U), wherein the semiconductor nanostructure 26' serves as the channel region of the nanostructure FET. The lower semiconductor nanostructure 26'L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26'U is used for the upper nanostructure FET 10U.

[0022] A gate dielectric layer 78 surrounds each semiconductor nanostructure 26'. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are disposed above the gate dielectric layer 78. Source / drain regions 62 (including a lower source / drain region 62L and an upper source / drain region 62U) are respectively disposed on opposite sides of the gate dielectric layer 78 and the corresponding gate electrode 80. A source / drain region may refer to a single source or drain, or both, depending on the context. An isolation structure (not shown) may be formed to separate the desired source / drain regions 62 and / or the desired gate electrode 80.

[0023] Figure 1 The reference sections to be used in subsequent figures are further illustrated. Section A-A' is a vertical section parallel to the longitudinal axis of the CFET semiconductor nanostructure 26', oriented, for example, in the direction of the current flow path between the CFET source / drain regions 62. Section B-B' is a vertical section perpendicular to section A-A' and along the longitudinal axis of the CFET gate electrode 80. For clarity, subsequent figures will be labeled with reference to these reference sections.

[0024] Figures 2 to 13A and Figure 13B The following are examples illustrating the formation of CFETs (e.g., according to some embodiments). Figure 1 A schematic cross-sectional view of an intermediate stage is shown. The corresponding process is called the monolithic CFET (mCFET) fabrication process. This process is also schematically reflected in... Figure 16 The process flow shown is as follows.

[0025] like Figure 2 As shown, a wafer 2 comprising a substrate 20 is provided. The substrate 20 may be a semiconductor substrate (e.g., a bulk semiconductor, a silicon-on-insulator (SOI) substrate, etc.), which may be doped (e.g., p-type or n-type dopant) or undoped. The SOI substrate may include a semiconductor material layer formed over an insulating layer. This insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate such as a silicon or glass substrate. Other substrates (e.g., multilayer or gradient substrates) may also be used. In some embodiments, the semiconductor material of the substrate 20 may comprise silicon, germanium, carbon-doped silicon, III-V compound semiconductors, and combinations thereof.

[0026] Multilayer stack 22 is formed on substrate 20. The corresponding process is as follows: Figure 16 The process flow 200 is shown as process 202. The multilayer stack 22 includes alternating dummy semiconductor layers 24 (including dummy semiconductor layers 24A and 24B) and semiconductor layers 26 (including a lower semiconductor layer 26L and an upper semiconductor layer 26U). The lower semiconductor layer 26L and the upper semiconductor layer 26U are used to form the lower FET and the upper FET, respectively.

[0027] Suitable wells (not shown separately) can be formed in the lower semiconductor layer 26L and the upper semiconductor layer 26U. For example, semiconductor layers 26L and 26U can be in-situ doped (during epitaxial growth) and / or implanted to obtain the desired conductivity type.

[0028] In the example shown, the multilayer stack 22 includes six dummy semiconductor layers 24 and six semiconductor layers 26. It should be understood that the multilayer stack 22 may include any number of dummy semiconductor layers 24 and semiconductor layers 26. Each layer of the multilayer stack 22 may be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), etc.

[0029] The dummy semiconductor layer 24A is formed of a first semiconductor material, and the dummy semiconductor layer 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have a high etch selectivity relative to each other. Therefore, the dummy semiconductor layer 24B is removed at a faster rate in subsequent processes than the dummy semiconductor layer 24A.

[0030] Semiconductor layer 26 (including lower semiconductor layer 26L and upper semiconductor layer 26U) is formed of one or more semiconductor materials. The semiconductor material may be selected from candidate semiconductor materials of the substrate 20. The lower semiconductor layer 26L and the upper semiconductor layer 26U may be formed of the same semiconductor material or may be formed of different semiconductor materials.

[0031] In some embodiments, the dummy semiconductor layer 24A is made of or contains silicon germanium, the semiconductor layer 26 is made of silicon, and the dummy semiconductor layer 24B may be made of germanium or silicon germanium having a higher percentage of germanium atoms than in the semiconductor layer 24A.

[0032] exist Figure 3 In this process, the multilayer stack 22 and the substrate 20 are patterned to form semiconductor strips 28. The corresponding process is as follows: Figure 16 The process flow 200 shown is referred to as process 204. Each semiconductor strip 28 includes a semiconductor strip 20' (a portion of the original substrate 20) and a multilayer stack 22', which is the remaining portion of the multilayer stack 22. The remaining portion 22' of the multilayer stack 22 is hereinafter referred to as a nanostructure, using the corresponding reference number followed by an apostrophe. Thus, the multilayer stack 22' includes dummy nanostructures 24'A, dummy nanostructures 24'B, a lower semiconductor nanostructure 26'L, an intermediate semiconductor nanostructure 26'M, and a upper semiconductor nanostructure 26'U. Etching can be performed by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. Etching can be anisotropic. Dummy nanostructures 24'A and dummy nanostructures 24'B can be further referred to individually and collectively as dummy nanostructure 24'. The lower semiconductor nanostructure 26'L and the upper semiconductor nanostructure 26'U can be further collectively referred to as semiconductor nanostructure 26'.

[0033] The lower semiconductor nanostructure 26'L will serve as the channel region of the lower nanostructure FET of the CFET. The upper semiconductor nanostructure 26'U will serve as the channel region of the upper nanostructure FET of the CFET. The intermediate semiconductor nanostructure 26'M is a semiconductor nanostructure 26' immediately above / below (e.g., in contact with) the dummy nanostructure 24'B. The intermediate semiconductor nanostructure 26'M can be used for isolation and may or may not be used as the channel region of the CFET. The dummy nanostructure 24'B will then be replaced by the isolation structure. The isolation structure and the intermediate semiconductor nanostructure 26'M define the boundary between the lower nanostructure FET and the upper nanostructure FET.

[0034] exist Figure 4In this process, isolation region 32 is formed on substrate 20 and between adjacent semiconductor strips 28. The corresponding process is shown as process 205 in process flow 200, as follows: Figure 16 As shown. The isolation region 32 may include a dielectric pad and a dielectric material on top of the dielectric pad. Subsequently, the isolation region 32 is recessed. Some upper portions of the semiconductor strip 28 (including the multilayer stack 22') protrude above the remaining isolation region 32 to form raised fins 34.

[0035] A dummy dielectric layer 36 is then formed on the raised fin 34. This corresponding process is shown in... Figure 16 Process 206 in the process flow 200 shown. The dummy dielectric layer 36 may be formed or comprise, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be formed by deposition or thermal growth according to acceptable techniques.

[0036] A dummy gate layer 38 is formed above the dummy dielectric layer 36. The corresponding process is shown in... Figure 16 Process 208 in the illustrated process flow 200. The dummy gate layer 38 can be deposited by, for example, physical vapor deposition (PVD), CVD, or other techniques, and then planarized by, for example, a chemical mechanical polishing (CMP) process. The material of the dummy gate layer 38 can be conductive or non-conductive and can be selected from the group including amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, or the like. A mask layer 40 is formed over the planarized dummy gate layer 38 and may include, for example, silicon nitride, silicon oxynitride, or the like.

[0037] Next, the mask layer 40 can be patterned using photolithography and etching processes to form a mask. Subsequently, the mask is used to etch and pattern the dummy gate layer 38, and possibly the dummy dielectric layer 36. The resulting structure is as follows: Figure 5A and Figure 5B As shown. The mask layer 40, the dummy gate layer 38, and the remaining portion of the dummy dielectric layer 36 together constitute the dummy gate stack 42. The corresponding process is as follows: Figure 16 The process flow shown in 200 is labeled as process 210.

[0038] In the following description, unless otherwise stated, numbers with the letter "A" correspond to the accompanying drawings (such as...). Figure 5A () all indicate along similar Figure 1 Vertical section view of the reference section A-A'; the numbers with the letter "B" correspond to the attached figures (e.g.) Figure 5B () all indicate along similar Figure 1 A cross-sectional view of the vertical reference section B-B'.

[0039] Figure 5A and Figure 5BAn initial structure for forming a portion of an SRAM cell according to some embodiments is shown. The illustrated structure includes a portion within a CFET region 100C and a portion within a pseudo-CFET region 100PSC. A CFET comprising an NFET and a PFET will be formed in the CFET region 100C. This CFET may form a pull-up transistor PU-1 or PU-2 and a pull-down transistor PD-1 or PD-2. Figure 15 In the 100PSC pseudo-CFET region, an NFET will be formed as a component of the pseudo-CFET. The pseudo-CFET can be formed as a transmission gate transistor PG-1 or PG-2. Figure 15 ). Figure 5A and Figure 5B They are shown respectively Figure 1 The structure of the vertical sections A-A' and B-B'. Figure 5A and Figure 5B The structures shown in the CFET region 100C and the pseudo-CFET region 100PSC can be used to... Figures 2 to 4 The common process shown is formed.

[0040] It needs to be understood that, although Figure 5B For ease of viewing, the CFET region 100C and the pseudo-CFET region 100PSC are displayed on the same plane, but if... Figure 5B The structures in the CFET region 100C and the pseudo-CFET region 100PSC shown may actually be located on different planes.

[0041] exist Figure 5A In this configuration, gate spacers 44 are formed above the multilayer stack 22' and on the exposed sidewalls of the dummy gate stack 42. The corresponding process is described in... Figure 16 The process flow 200 shown is labeled as process 212. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as CVD, ALD, etc. Figure 5B Fin spacer 45 is shown, which is formed from the same dielectric layer used to form gate spacer 44.

[0042] Source / drain trenches 46 are formed in the semiconductor strips 28 of both the CFET region 100C and the pseudo-CFET region 100PSC. The corresponding process is described in... Figure 16 The process flow 200 shown is labeled as process 214. The source / drain recess 46 is formed by etching the semiconductor strip 28, extending through the multilayer stack 22' and into the semiconductor strip 20'. The bottom surface of the source / drain recess 46 may be located in the isolation region 32. Figure 5BAbove, below, or flush with the top surface. During the etching process, the gate spacer 44 and the dummy gate stack 42 shield certain portions of the semiconductor strip 28. The source / drain recess 46 can be formed simultaneously in the CFET region 100C and the dummy CFET region 100PSC in a common process.

[0043] Then, the dummy nanostructure 24'A is laterally recessed, and dielectric material is filled into the corresponding recesses to form internal spacers 54, which are dielectric spacers. A dielectric isolation layer 56 is also formed to replace the dummy nanostructure 24'B.

[0044] See Figure 6A and Figure 6B This forms protective gaskets 48C and 48PSC. The corresponding process is as follows: Figure 16 The process flow 200 shown is designated as process 216. Protective pads 48C and 48PSC can be formed in a common process or a separate process. Protective pads 48C and 48PSC can be formed from or include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, or combinations thereof. The materials of protective pads 48C and 48PSC also differ from the materials of exposed features such as gate spacer 44, mask layer 40, and internal spacer 54, ensuring that the exposed features are not damaged during subsequent removal of protective pads 48C and 48PSC.

[0045] According to some embodiments, forming the protective pads 48C and 48PSC may include: depositing a sacrificial layer (not shown) filling the source / drain trench 46, planarizing the sacrificial layer, and etching back the sacrificial layer. The top surface of the remaining sacrificial layer will be at the same level as the bottom ends of the subsequently formed protective pads 48C and 48PSC. The sacrificial layer may contain photoresist or other polymers, which may or may not be photosensitive.

[0046] A conformal deposition of a protective blanket layer is then performed, followed by an anisotropic etching process to remove the horizontal portion of the protective blanket layer, leaving the protective pads 48C and 48PSC shown. The remaining sacrificial layer portion is then removed. According to some embodiments, the bottom ends of the protective pads 48C and 48PSC are below the dielectric isolation layer 56 and above the bottom surface of the lower semiconductor nanostructure 26'L immediately below the intermediate semiconductor nanostructure 26'M.

[0047] In subsequent processes, such as Figure 6A and Figure 6B As shown, a hard mask 49 is formed in the CFET region 100C and the pseudo-CFET region 100PSC. The corresponding process is shown as follows. Figure 16 Process 218 in the process flow 200 shown. The formation process may include depositing a conformal dielectric layer in the CFET region 100C and the pseudo-CFET region 100PSC. Figure 6A As shown, the hard mask 49 masks the exposed sidewalls of the semiconductor nanostructure 26'L and the surface of the semiconductor strip 20'.

[0048] The formation process of the hard mask 49 may include conformal deposition processes such as ALD, CVD, etc. According to some embodiments, the hard mask 49 is formed of a different material than that of the protective pads 48C and 48PSC. The material of the hard mask 49 may (or may not) be selected from the same group of candidate materials used to form the protective pads 48C and 48PSC. For example, the material of the hard mask 49 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, etc., or combinations thereof.

[0049] refer to Figure 7A and Figure 7B The etching mask 50 is formed and patterned. The corresponding process is shown as follows. Figure 16 Process 220 is shown in process flow 200. According to some embodiments, the etching mask 50 may include patterned photoresist and may have a single-layer, double-layer, or triple-layer structure. The etching mask 50 is removed from the CFET region 100C and has a remaining portion in the pseudo-CFET region 100PSC. The etching mask 50 may further fill the source / drain recesses 46 in the pseudo-CFET region 100PSC.

[0050] According to some embodiments, the hard mask 49 and the etch mask 50 may be portions of a mask used to mask certain protected circuit regions (such as test keys (not shown) in scribe lines), so that subsequent epitaxial processes do not result in undesirable growth of semiconductor material in the protected circuit regions. Therefore, the hard mask 49 and the etch mask 50 can be formed using existing processes and existing hard and etch masks, without resulting in additional processes. When the etch mask 50 is removed from the CFET region 100C (while remaining in the pseudo-CFET region 100PSC), the etch mask will remain in the protected circuit region.

[0051] In subsequent processes, the hard mask 49 is patterned in an etching process, during which the exposed portions of the hard mask 49 are removed. The resulting structure is... Figure 8A and Figure 8B The corresponding process is shown in the diagram. Figure 16 Process 222 in the process flow 200 shown. The removal process can be performed by an isotropic etching process that uses a wet etch solution or etch gas to attack the hard mask 49 but not the protective layers 48C and 48PSC, the internal spacers 54 and the semiconductor strip 20'.

[0052] Figure 8C It shows Figure 8A and Figure 8B A perspective view of the structure shown. The portion shown reflects a portion of the pseudo-CFET region 100PSC. The etch mask 50 is schematically shown. The openings in the etch mask 50 schematically illustrate the CFET region 100C.

[0053] After the hard mask 49 is patterned, the remainder of the etched mask 50 is removed, exposing the underlying hard mask 49, which is located in the pseudo CFET region 100PSC but not in the CFET region 100C.

[0054] Next, as Figure 9A and Figure 9B As shown, a lower source / drain region 62L-C is formed in the lower portion of the source / drain recess 46 in the CFET region 100C. The corresponding process is shown as process 224 in the process flow diagram 200, as follows. Figure 16 As shown. The lower source / drain region 62L-C is in contact with the lower semiconductor nanostructure 26'L, but not with the upper semiconductor nanostructure 26'U. The internal spacer 54 physically and electrically insulates the lower source / drain region 62L-C from the dummy nanostructure 24'A, which will be replaced with a replacement gate in a subsequent process.

[0055] During the formation of the lower source / drain region 62L-C via selective epitaxy, the semiconductor material does not grow in the source / drain trench 46 in the pseudo-CFET region 100PSC due to the masking of the hard mask 49.

[0056] The lower source / drain region 62L-C has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. In the following discussion, it is assumed that the lower nanostructure FET is a PFET and the upper nanostructure FET is an NFET. According to an alternative embodiment, the lower nanostructure FET can be an NFET and the upper nanostructure FET can be a PFET.

[0057] When the lower source / drain region 62L-C is a p-type source / drain region, the corresponding material may include silicon or silicon-germanium, which is doped with p-type dopants such as boron or indium. The lower source / drain region 62L-C may be in-situ doped and may or may not be implanted with corresponding p-type or n-type dopants.

[0058] In subsequent processes, the remaining portion of the hard mask 49 is removed, and the resulting structure is shown in... Figure 10A and Figure 10B The corresponding process is shown as follows. Figure 16Process 226 in the process flow 200 shown. The removal process can be implemented by an isotropic etching process using a wet etch solution or etch gas that attacks the hard mask 49 but does not attack the protective pads 48C and 48PSC. Figure 9A and Figure 9B ), internal spacer 54, lower source / drain region 62L-C and semiconductor strip 20'.

[0059] Next, remove the protective pads 48C and 48PSC ( Figure 9A and Figure 9B The corresponding process is shown as follows. Figure 16 Process 228 in the process flow 200 shown. Removal can be performed by an isotropic etching process, in which either a wet etching process or a dry etching process can be used. The etching chemical is selected to not etch the internal spacer 54, the lower source / drain region 62L-C, and other exposed materials such as the gate spacer 44 and the hard mask 40. The resulting structure is also shown in Figure 10A and Figure 10B middle.

[0060] refer to Figure 11A and Figure 11B This process forms a first contact etch stop layer (CESL) 66 and a first interlayer dielectric layer (ILD) 68. The process is carried out in... Figure 16 The process flow 200 shown is represented as process 230. The first CESL 66 and the first ILD 68 can be formed simultaneously in the CFET region 100C and the pseudo-CFET region 100PSC. The first CESL 66 can be formed from a dielectric material with high selectivity for etching the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed from a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or flow chemical vapor deposition (FCVD). Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0061] The formation process may include: depositing a conformal CESL layer, depositing material for ILD 68, followed by a planarization process to form a flat top surface of the deposited material. An etch-back process is then performed to etch back the deposited material. In some embodiments, the first ILD 68 is etched first, leaving the first CESL 66 unetched. An anisotropic etching process is then performed to remove the portion of the first CESL 66 above the recessed first ILD 68. After the etch-back, the sidewalls of the upper semiconductor nanostructure 26'U are exposed.

[0062] Due to the planarization and etch-back processes, the top surfaces of the first ILD 68 and the first CESL 66 in the CFET region 100C and the pseudo-CFET region 100PSC can be at the same level or slightly different levels. Whether at the same level or different levels, the top surfaces of the first ILD 68 and the first CESL 66 in the CFET region 100C and the pseudo-CFET region 100PSC are higher than the bottom surface of the internal spacer 54 immediately below the dielectric isolation layer 56 and lower than the top surface of the internal spacer 54 immediately above the dielectric isolation layer 56.

[0063] The bottom surface of the first CESL 66 in the CFET region 100C is in contact with the top surface of the lower source / drain region 62L-C. The bottom surface of the first CESL 66 in the pseudo-CFET region 100PSC is lower than the bottom surface of the first CESL 66 in the CFET region 100C. Furthermore, the first CESL 66 in the pseudo-CFET region 100PSC is in contact with the top surface of the semiconductor strip 20' in the pseudo-CFET region 100PSC, and also in contact with the sidewall of the semiconductor nanostructure 26'L.

[0064] Next, refer to Figure 12A and Figure 12B The upper epitaxial source / drain regions 62U-C and 62U-PSC are formed in the upper portion of the source / drain recess 46, and are respectively formed in the CFET region 100C and the pseudo-CFET region 100PSC. The corresponding process is as follows: Figure 16 The process flow 200 shown is referred to as process 232. The epitaxial source / drain regions 62U-C and 62U-PSC can be formed simultaneously or in separate processes. Therefore, the upper epitaxial source / drain region 62U-C can have the same structure and composition as the upper epitaxial source / drain region 62U-PSC.

[0065] The upper epitaxial source / drain regions 62U-C and 62U-PSC can be in-situ doped with n-type or p-type dopants and / or implanted with n-type or p-type dopants, depending on the expected conductivity type. For example, when the upper epitaxial source / drain regions 62U-C and 62U-PSC are n-type semiconductor regions, SiP, SiCP, etc., can be used.

[0066] Next, the second CESL70 and the second ILD72 are formed. The second CESL70 and the second ILD72 can be formed simultaneously in the CFET region 100C and the pseudo-CFET region 100PSC. The corresponding process is shown as process 234 in process flow diagram 200, as follows: Figure 16 As shown.

[0067] The materials and formation methods of the second CESL70 and the second ILD72 can be similar to those of the first CESL66 and the first ILD68, respectively, and will not be discussed in detail here. The formation process may include depositing layers for CESL70 and ILD72, and performing a planarization process to remove excess portions of the respective layers. After the planarization process, the top surfaces of the second ILD72, the gate spacer 44, and the dummy gate stack 42 are coplanar (within process variations). The planarization process may remove the mask layer 40, or it may not remove the mask layer 40.

[0068] Next, the dummy gate stack 42 is removed in one or more etching processes to form trenches. Each trench exposes and / or lies on a portion of the multilayer stack 22'. The dummy nanostructure 24'A is then removed by etching. Figure 12A The remaining portion of the groove extends between the upper semiconductor nanostructures 26'U.

[0069] Then, replacement gate stacks 90 (each including gate stacks 90L and 90U) are formed in their respective recesses, and can be formed simultaneously in the CFET region 100C and the pseudo-CFET region 100PSC. The corresponding process is described in... Figure 16 The process flow 200 is shown as process 236. Gate stack 90L includes gate dielectric 78 and gate electrode 80L. Gate stack 90U includes gate dielectric 78 and gate electrode 80U. Each gate dielectric 78 may include an interface layer (such as a silicon oxide layer) and a high-k dielectric layer on that interface layer. Gate dielectric 78 is formed on the exposed semiconductor nanostructure 26' and includes a portion on the gate spacer 44. Gate dielectric 78 encloses all (e.g., four) sides of the semiconductor nanostructure 26'.

[0070] A dielectric hard mask 92 is formed over the gate stack 90U. Gate electrodes 80L and 80U comprise conductive material that can provide a suitable work function for the resulting lower FET (lower transistor) 10L and upper FET (upper transistor) 10U. Gate electrodes 80L and 80U can be a common gate formed in the same fabrication process, or they can be electrically isolated from each other.

[0071] Figure 14A A structure comprising two CFET regions and one pseudo-CFET region according to some embodiments is shown. Figure 13A and Figure 13B The CFET region 100C and the pseudo-CFET region 100PSC shown can be obtained from Figure 14A Obtained. According to some embodiments, Figure 14A The structure shown implements a pull-up transistor PU, a pull-down transistor PD, and a transmission gate transistor PG, which are also shown in Figure 15 In the middle. Therefore, as Figure 15 The SRAM cell 100 shown can be used as follows Figure 14A The structure shown is used for implementation.

[0072] Figure 14A Further illustration shows the formation of a top source / drain contact plug 81T connected to upper source / drain regions 62U-C and 62U-PSC, and a bottom source / drain contact plug 81B connected to lower source / drain region 62L-C, according to some embodiments. It should be understood that the illustrated connection scheme is merely an example, and different connection schemes may be employed. A source / drain silicide layer 83 is also formed. Electrical connections to the lower source / drain region 62L-C can be achieved via vertical interconnects, wherein the source / drain contact plug 81T (in illustrated device region 100C) electrically interconnects the upper source / drain region 62U-C and the lower source / drain region 62L-C.

[0073] It should be understood that by employing embodiments of this disclosure, it is not necessary to form a dummy lower source / drain region and then perform a patterning process to remove the dummy lower source / drain region used for the dummy CFET. If formation and patterning are performed to remove the dummy lower source / drain region, the corresponding photolithography process may suffer from overlay misalignment issues, which have a small process window due to the small spacing between adjacent CFETs. The uniformity of the device wafer may be compromised. Furthermore, removing the dummy lower source / drain region may damage the gate spacers and internal spacers.

[0074] The embodiments of this disclosure have several advantageous features. By employing the process of this disclosure, it is unnecessary to form and then etch dummy lower source / drain regions, and problems caused by etching dummy lower source / drain regions are avoided. The process according to embodiments of this disclosure can use existing masks, thus eliminating the need for additional masks and photolithography processes.

[0075] According to some embodiments of this disclosure, a method of forming a semiconductor structure includes: forming a first multilayer stack in a first device region; forming a first gate stack on the first multilayer stack; forming a second multilayer stack in a second device region; forming a second gate stack on the second multilayer stack; etching the first multilayer stack to form a first source / drain trench; etching the second multilayer stack to form a second source / drain trench; forming a hard mask in the second source / drain trench; forming a lower source / drain region in the first source / drain trench; removing the hard mask from the second source / drain trench after forming the lower source / drain region; and forming a first upper source / drain region in the first source / drain trench and a second upper source / drain region in the second source / drain trench, respectively.

[0076] In one embodiment, the lower source / drain region is a first conductivity type, and the first upper source / drain region and the second upper source / drain region are second conductivity types opposite to the first conductivity type. In one embodiment, the first conductivity type is p-type, and the second conductivity type is n-type. In one embodiment, the first upper source / drain region, the lower source / drain region, and the second upper source / drain region are respectively formed as portions of the pull-up transistor, pull-down transistor, and transmission gate transistor of a static random access memory cell.

[0077] In one embodiment, the method further includes: after removing the hard mask from the second source / drain trench, forming a contact etch stop layer and an interlayer dielectric layer above the contact etch stop layer, wherein portions of the contact etch stop layer and the interlayer dielectric layer are located in the second source / drain trench and are at the same level as the lower source / drain region. In one embodiment, the contact etch stop layer contacts a second multilayer stacked semiconductor nanostructure. In another embodiment, a portion of the contact etch stop layer extends to the bottom of the second source / drain trench.

[0078] In an embodiment, forming a hard mask includes: depositing a blanket-covered hard mask layer in a first device region and a second device region; and removing the blanket-covered hard mask layer from the first device region. In an embodiment, the method further includes: before depositing the blanket-covered hard mask layer, forming a first protective pad and a second protective pad, respectively, on the upper portions of the first source / drain trench and the second source / drain trench. In an embodiment, a first gate stack is replaced with a first replacement gate stack; and a second gate stack is replaced with a second replacement gate stack. In an embodiment, the first replacement gate stack and the second replacement gate stack are formed using a common process.

[0079] According to some embodiments of this disclosure, a method of forming a semiconductor structure includes: forming a first source / drain trench in a first device region, wherein the first source / drain trench is located between two adjacent first multilayer stacks, and wherein a first top surface of the first semiconductor region is located below and exposed to the first source / drain trench; forming a second source / drain trench in a second device region, wherein the second source / drain trench is located between two adjacent second multilayer stacks, and wherein a second top surface of the second semiconductor region is located below and exposed to the second source / drain trench; forming a hard mask in the second source / drain trench and on the surfaces of the two adjacent second multilayer stacks; forming a lower source / drain region in the first source / drain trench; removing the hard mask; and forming a first contact etch stop layer, including: a first portion located in the first source / drain trench, wherein the first portion contacts a third top surface of the lower source / drain region; and a second portion located in the second source / drain trench, wherein the second portion contacts a second top surface of the second semiconductor region.

[0080] In one embodiment, the method further includes forming a first interlayer dielectric layer over the first contact etch stop layer, wherein the first interlayer dielectric layer includes portions of the first source / drain trench and the second source / drain trench, respectively. In another embodiment, the method further includes forming a first upper source / drain region in the first source / drain trench and forming a second upper source / drain region in the second source / drain trench. In yet another embodiment, the first source / drain trench and the second source / drain trench are formed in a common process.

[0081] In one embodiment, the method further includes forming a second contact etch stop layer, the second contact etch stop layer being a portion of the first source / drain recess and the second source / drain recess. In another embodiment, the first upper source / drain region, the lower source / drain region, and the second upper source / drain region are formed as portions of a static random access memory cell.

[0082] According to some embodiments of this disclosure, a semiconductor structure includes: a first device, comprising: a first plurality of semiconductor nanostructures, including a first semiconductor nanostructure and a second semiconductor nanostructure overlapping the first semiconductor nanostructure; a lower source / drain region laterally adjacent to the first semiconductor nanostructure; and a first upper source / drain region overlapping the lower source / drain region, wherein the first upper source / drain region contacts the second semiconductor nanostructure; and a first dielectric region located between the lower source / drain region and the first upper source / drain region; and a second device, comprising: a second plurality of semiconductor nanostructures, including a third semiconductor nanostructure and a fourth semiconductor nanostructure overlapping the third semiconductor nanostructure; and a second upper source / drain region laterally adjacent to the fourth semiconductor nanostructure; and a second dielectric region located below the second upper source / drain region, wherein the second dielectric region laterally adjacent to the third semiconductor nanostructure.

[0083] In one embodiment, the second dielectric region includes a contact etch stop layer and an interlayer dielectric layer located above the contact etch stop layer. In another embodiment, the semiconductor structure further includes a semiconductor strip, wherein the second dielectric region contacts the top surface of the semiconductor strip.

[0084] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A method for forming a semiconductor structure, comprising: A first multilayer stack is formed in the first device region; A first gate stack is formed on the first multilayer stack; A second multilayer stack is formed in the second device region; A second gate stack is formed on the second multilayer stack; Etch the first multilayer stack to form the first source / drain trench; The second multilayer stack is etched to form a second source / drain trench; A hard mask is formed in the second source / drain groove; A lower source / drain region is formed in the first source / drain groove; After forming the lower source / drain region, the hard mask is removed from the second source / drain recess; as well as A first upper source / drain region is formed in the first source / drain groove and a second upper source / drain region is formed in the second source / drain groove.

2. The method according to claim 1, wherein, The lower source / drain region is a first conductivity type, and the first upper source / drain region and the second upper source / drain region are a second conductivity type opposite to the first conductivity type.

3. The method according to claim 1, wherein, The first upper source / drain region, the lower source / drain region, and the second upper source / drain region are respectively formed as portions of the pull-up transistor, pull-down transistor, and transmission gate transistor of a static random access memory cell.

4. The method according to claim 1, further comprising: After the hard mask is removed from the second source / drain recess, a contact etch stop layer and an interlayer dielectric layer are formed above the contact etch stop layer, wherein portions of the contact etch stop layer and the interlayer dielectric layer are located in the second source / drain recess and are at the same level as the lower source / drain region.

5. The method according to claim 1, wherein, Forming the hard mask includes: Deposit blanket-covered hard mask layers in the first device region and the second device region; and Remove the blanket-covered hard mask layer from the first device region.

6. The method of claim 5, further comprising forming a first protective pad and a second protective pad on the upper portions of the first source / drain groove and the second source / drain groove, respectively, before depositing the blanket-covered hard mask layer.

7. A method for forming a semiconductor structure, comprising: A first source / drain recess is formed in a first device region, wherein the first source / drain recess is located between two adjacent first multilayer stacks, and wherein a first top surface of a first semiconductor region is located below and exposed to the first source / drain recess. A second source / drain recess is formed in the second device region, wherein the second source / drain recess is located between two adjacent second multilayer stacks, and wherein the second top surface of the second semiconductor region is located below the second source / drain recess and exposed to the second source / drain recess; A hard mask is formed in the second source / drain recess and on the surfaces of the two adjacent second multilayer stacks; A lower source / drain region is formed in the first source / drain groove; Remove the hard mask; and Forming a first contact etch stop layer includes: A first portion located in the first source / drain recess, wherein the first portion contacts the third top surface of the lower source / drain region; and The second portion is located in the second source / drain groove, wherein the second portion contacts the second top surface of the second semiconductor region.

8. The method of claim 7, further comprising forming a first interlayer dielectric layer over the first contact etch stop layer, wherein the first interlayer dielectric layer comprises portions of the first source / drain trench and the second source / drain trench, respectively.

9. The method according to claim 7, wherein, The first source / drain groove and the second source / drain groove are formed in a common process.

10. A semiconductor structure comprising: The first device includes: The first plurality of semiconductor nanostructures includes a first semiconductor nanostructure and a second semiconductor nanostructure overlapping the first semiconductor nanostructure; The lower source / drain region is laterally adjacent to the first semiconductor nanostructure; and A first upper source / drain region overlaps with the lower source / drain region, wherein the first upper source / drain region contacts the second semiconductor nanostructure; The first dielectric region is located between the lower source / drain region and the first upper source / drain region; The second device includes: The second plurality of semiconductor nanostructures includes a third semiconductor nanostructure and a fourth semiconductor nanostructure overlapping the third semiconductor nanostructure; and The second upper source / drain region is laterally adjacent to the fourth semiconductor nanostructure; and The second dielectric region is located below the second upper source / drain region, wherein the second dielectric region is laterally adjacent to the third semiconductor nanostructure.

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