Passive device and integrated passive device

Abstract

The invention provides a passive device and an integrated passive device. The passive device comprises a substrate and an inductor located on one side of the substrate. The inductor comprises a first conductive layer and a second conductive layer, and the first conductive layer is arranged on one side of the substrate. The second conductive layer is arranged on the side, away from the substrate, of the first conductive layer, and the first conductive layer and the second conductive layer are different in thickness; the first insulating layer is arranged between the first conductive layer and the second conductive layer; and the at least one first connecting part penetrates through the first insulating layer and is electrically connected with the first conductive layer and the second conductive layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular to a passive device and an integrated passive device. BACKGROUND

[0002] With the development of communication technology, the integration and performance requirements of integrated passive devices prepared by semiconductor processes are increasingly high. Integrated passive devices include capacitors, inductors, resistors, etc. During operation, excessive loss will affect the operation effect of the integrated passive device. Therefore, improving the performance of the device is a current problem to be solved. SUMMARY

[0003] The present disclosure provides a passive device, comprising:

[0004] a substrate and an inductor located on one side of the substrate, the inductor comprising:

[0005] a first conductive layer disposed on one side of the substrate;

[0006] a second conductive layer disposed on the side of the first conductive layer away from the substrate, the thickness of the first conductive layer and the second conductive layer being different;

[0007] a first insulating layer disposed between the first conductive layer and the second conductive layer;

[0008] at least one first connecting portion penetrating the first insulating layer and electrically connected to the first conductive layer and the second conductive layer.

[0009] According to an embodiment of the present disclosure, the first insulating layer is provided with at least one first via hole corresponding to the at least one first connecting portion one by one, at least a part of the first connecting portion is disposed in the first via hole;

[0010] In the direction away from the substrate, the aperture of the first via hole gradually increases.

[0011] According to an embodiment of the present disclosure, the first conductive layer is provided with at least one first blind hole corresponding to the at least one first connecting portion on the side away from the substrate, the first blind hole is in the orthographic projection of the first via hole on the substrate, a part of the first connecting portion is disposed in the first via hole, and another part of the first connecting portion is disposed in the first blind hole.

[0012] According to an embodiment of the present disclosure, in the direction away from the substrate, the aperture change rate of the first via hole is less than the aperture change rate of the first blind hole.

[0013] According to an embodiment of the present disclosure, the first conductive layer and the second conductive layer are arranged in a strip structure, and a hole diameter of the first via is positively correlated with a thickness or a strip width of the second conductive layer.

[0014] According to an embodiment of the present disclosure, the passive device further comprises a second transition layer,

[0015] The second transition layer is arranged on a sidewall of the first via, a bottom and a sidewall of the first blind hole, and a side of the first insulating layer away from the substrate.

[0016] The second conductive layer covers the second transition layer.

[0017] According to an embodiment of the present disclosure, the first conductive layer and the second conductive layer are arranged in a strip structure, and a thickness of the second transition layer is positively correlated with a thickness or a strip width of the second conductive layer.

[0018] According to an embodiment of the present disclosure, the second transition layer comprises a second adhesion layer and a second seed layer, and the second seed layer is arranged on a side of the second adhesion layer away from the substrate.

[0019] According to an embodiment of the present disclosure, a projection of the first conductive layer on the substrate is a first annular pattern with a first opening, and a projection of the second conductive layer on the substrate is a second annular pattern with a second opening.

[0020] According to an embodiment of the present disclosure, a proportion of the first opening in the first annular pattern and a proportion of the second opening in the second annular pattern are both greater than one half.

[0021] According to an embodiment of the present disclosure, the first opening and the second opening are directed to different directions.

[0022] According to an embodiment of the present disclosure, the first annular pattern and the second annular pattern are symmetrical patterns.

[0023] According to an embodiment of the present disclosure, the symmetrical pattern is a circle or a polygon.

[0024] According to an embodiment of the present disclosure, an internal angle of the polygon is greater than 90°.

[0025] According to an embodiment of the present disclosure, the first annular pattern and the second annular pattern have the same pattern and different sizes.

[0026] According to an embodiment of the present disclosure, a width of the second annular pattern is greater than a width of the first annular pattern, and the width is a distance between an inner ring and an outer ring of the annular pattern.

[0027] According to an embodiment of the present disclosure, at least one of the first conductive layer and the second conductive layer has a protrusion in a direction parallel to the substrate, and the protrusion is connected to the first connecting portion.

[0028] According to embodiments of this disclosure, the passive device further includes:

[0029] A third conductive layer is disposed on the side of the second conductive layer away from the substrate.

[0030] A second insulating layer is disposed between the second conductive layer and the third conductive layer;

[0031] At least one second connection portion penetrates the second insulating layer and is electrically connected to the second conductive layer and the third conductive layer;

[0032] The thickness of one of the first conductive layer, the second conductive layer, and the third conductive layer is different from the thickness of the other two.

[0033] According to an embodiment of this disclosure, the orthogonal projection of the third conductive layer onto the substrate is a third annular pattern having a third opening, the width of which is greater than the width of the second annular pattern.

[0034] According to embodiments of this disclosure, the thickness of the second conductive layer is greater than the thickness of the first conductive layer and the third conductive layer; or

[0035] The thickness of the first conductive layer is greater than the thickness of the second conductive layer, and the thickness of the second conductive layer is greater than the thickness of the third conductive layer.

[0036] According to an embodiment of this disclosure, the second insulating layer is provided with at least one second through hole corresponding to the second connecting portion, and at least a portion of the second connecting portion is disposed in the second through hole;

[0037] The first connecting portion and the second connecting portion do not overlap in their orthographic projections onto the substrate.

[0038] This disclosure also provides an integrated passive device, including:

[0039] The passive devices described above and

[0040] A capacitor, which is electrically connected to the first conductive layer of the inductor.

[0041] According to an embodiment of the present disclosure, the capacitor includes a first electrode disposed on one side of a substrate, a second electrode disposed on the side of the first electrode away from the substrate, and a first dielectric layer disposed between the first electrode and the second electrode;

[0042] The first electrode, the first dielectric layer, and the second electrode at least partially overlap in their orthogonal projections onto the substrate.

[0043] The inductor and the capacitor are disposed on the same side of the substrate, and the first conductive layer of the inductor and the first electrode of the capacitor are disposed on the same layer and electrically connected.

[0044] According to embodiments of this disclosure, the thickness of the first electrode is the same as the thickness of the first conductive layer, and the thickness of the first electrode is greater than the thickness of the second electrode.

[0045] The beneficial effects of this disclosure are to reduce the parasitic resistance of the inductor, improve the quality factor of the inductor, and at the same time minimize the phenomenon that the outermost conductive layer is prone to peeling. Attached Figure Description

[0046] The accompanying drawings are used to further illustrate various embodiments and explain all the various principles and advantages of this disclosure. Similar reference numerals throughout the drawings refer to the same or functionally similar elements. The drawings are not necessarily drawn to scale. The drawings, together with the detailed description below, are incorporated into and form part of this specification.

[0047] Figure 1 A partial structural schematic diagram of an integrated passive integrated circuit is shown.

[0048] Figure 2 A cross-sectional view of a passive device according to an embodiment of the present disclosure is shown.

[0049] Figure 3 A cross-sectional view of a passive device according to another embodiment of the present disclosure is shown.

[0050] Figure 4 A cross-sectional view of a passive device according to another embodiment of the present disclosure is shown.

[0051] Figure 5 A perspective view of a passive device according to an embodiment of the present disclosure is shown.

[0052] Figure 6 A perspective view of a passive device according to another embodiment of the present disclosure is shown.

[0053] Figure 7 A cross-sectional view of a passive device according to an embodiment of the present disclosure is shown.

[0054] Figure 8 A partial cross-sectional view of a passive device according to an embodiment of the present disclosure is shown.

[0055] Figure 9 A partial cross-sectional view of a passive device according to another embodiment of the present disclosure is shown.

[0056] Figure 10 A partial cross-sectional view of a passive device according to another embodiment of the present disclosure is shown.

[0057] Figure 11 A cross-sectional view of a passive device according to another embodiment of the present disclosure is shown. Figure 1 Figure 2 shows a schematic cross-sectional view of a passive device according to another embodiment of the present disclosure.

[0058] Figure 13 A perspective view of a passive device according to another embodiment of the present disclosure is shown.

[0059] Figure 14 A perspective view of a passive device according to another embodiment of the present disclosure is shown.

[0060] Figure 15 A perspective view of a passive device according to another embodiment of the present disclosure is shown.

[0061] Figure 16 A perspective view of a passive device according to another embodiment of the present disclosure is shown.

[0062] Figure 17 A perspective view of a passive device according to another embodiment of the present disclosure is shown.

[0063] Figure 18 A perspective view of a passive device according to another embodiment of the present disclosure is shown.

[0064] Figure 19 A perspective view of a passive device according to another embodiment of the present disclosure is shown.

[0065] Figure 20 A cross-sectional view of an integrated passive device according to an embodiment of the present disclosure is shown.

[0066] Figure 21 A cross-sectional view of an integrated passive device according to another embodiment of the present disclosure is shown.

[0067] Figure 22 A cross-sectional view of an integrated passive device according to another embodiment of the present disclosure is shown.

[0068] Figure 23 A cross-sectional view of an integrated passive device according to another embodiment of the present disclosure is shown.

[0069] The components in the attached diagram are labeled as follows:

[0070] 1. Substrate; 2. Capacitor; 21. First electrode; 22. First dielectric; 23. Second electrode; 3. Inductor; 31. First conductive layer; 32. Second conductive layer; 33. Third conductive layer; 34. Fourth conductive layer; First trace 302; Second trace 303; 4. Insulating layer; 5. Connector; 51. First connector; 52. Second connector; 53. Third connector; 54. Fourth connector; 511. First via; 521. Second via; 501. First aperture; 502. Second aperture; 512. First blind via; 522. Second blind via; 540. First transition layer; 550. Second transition layer; 560. Second transition layer; 541. First adhesive layer; 542. First seed layer; 551. Second adhesive layer; 552. Second seed layer; 561. Third adhesive layer; 562. Third seed layer; 530. Protrusion; 531. First protrusion; 532. Second protrusion; 6. Bump; 7. Solder ball; 100. Integrated passive circuit Detailed Implementation

[0071] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0072] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0073] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0074] Throughout the description, the terms “vertical,” “perpendicularly,” and “first direction” refer to a direction perpendicular to a plane parallel to the conventional plane or surface of the substrate, i.e., the Z-direction or the first direction.

[0075] Throughout the description, "outermost layer" refers to the layer furthest from the substrate along the first direction, where the Z direction refers to the first direction. The "outermost conductive layer" in the figure refers to the conductive layer furthest from the substrate among the multiple conductive layers.

[0076] Integrated passive devices (IPDs) are a technology that integrates passive components (such as resistors, capacitors, and inductors) from a circuit onto a small chip. Compared to traditional discrete components, IPDs offer numerous advantages, including small size, high performance consistency, good stability, low cost, and high efficiency. Because integrated passive devices can provide excellent high-frequency characteristics and bandwidth, they are widely used in mobile communications, wireless networks, satellite communications, radar systems, and other fields, where they are typically used for filtering, matching networks, power distribution, and signal coupling.

[0077] Integrated passive devices typically include a variety of passive components, such as resistors, capacitors, and inductors, and high-density, high-performance passive component integration is usually achieved on a substrate 10 using semiconductor processes. Figure 1 A partial structural schematic diagram of an integrated passive integrated circuit is shown. The passive integrated circuit includes a capacitor structure 20 and an inductor 30 on one side of a substrate 10, which are connected by conductive material filled in the via structure of a multilayer insulating layer 40.

[0078] During the operation of passive integrated devices, the conductive layer in inductor 30 generates parasitic resistance, affecting its quality factor (Q value) and efficiency, resulting in operating losses. A higher Q value indicates lower losses; conversely, a lower Q value indicates greater losses, which has a greater impact on the operating performance of inductor 30 and the entire passive integrated device. Currently, with the increasing integration density of passive integrated devices, the area of ​​inductor 30 is becoming smaller and smaller. How to reduce the losses caused by parasitic resistance and improve the Q value of inductors under high integration density is a major problem facing the development of passive integrated devices.

[0079] This disclosure provides a passive device and integrated passive circuit that can improve the quality factor of an inductor.

[0080] like Figure 2As shown, the passive device includes a substrate 1 and an inductor 3 located on one side of the substrate 1. The inductor 3 includes a first conductive layer 31, a second conductive layer 32, a first insulating layer P1, and at least one first connection portion 51. The first conductive layer 31 is disposed on one side of the substrate 1, and the second conductive layer 32 is disposed on the side of the first conductive layer 31 away from the substrate 1. The first conductive layer 31 and the second conductive layer 32 have different thicknesses. The first insulating layer P1 is disposed between the first conductive layer 31 and the second conductive layer 32. At least one first connection portion 51 penetrates the first insulating layer P1 and is electrically connected to the first conductive layer 31 and the second conductive layer 32.

[0081] In some embodiments, at least one first via 511 corresponding to at least one first connection portion 51 is provided in the first insulating layer P1. At least a portion of the first connection portion 51 is disposed within the first via 511. The diameter of the first via 511 gradually increases in the direction away from the substrate 1.

[0082] The above description uses a two-layer conductive layer as an example. The inductor 3 includes a first conductive layer 31 and a second conductive layer 32 spaced apart on one side of the substrate 1. A first insulating layer P1 is disposed between the first conductive layer 31 and the second conductive layer 32. The first insulating layer P1 has at least a first via 511. A first connecting portion 51 connects the first conductive layer 31 and the second conductive layer 32 within the first via 510, thereby realizing the electrical connection between the first conductive layer 31 and the second conductive layer 32 of the inductor. However, the embodiments of this disclosure are not limited to this. In some embodiments, the inductor 3 may also include three or more conductive layers.

[0083] like Figure 2 As shown, the inductor may further include a third conductive layer 33, a second insulating layer P2, and at least one second connection portion 52. The third conductive layer 33 is disposed on the side of the second conductive layer 32 away from the substrate 1. The second insulating layer P2 is disposed between the second conductive layer 32 and the third conductive layer 33. At least one second connection portion 52 penetrates the second insulating layer P2 and is electrically connected to the second conductive layer 32 and the third conductive layer 33.

[0084] The thickness of one of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 may differ from the thicknesses of the other two. In some embodiments, the thickness of the third conductive layer 33 is less than the thickness of the first conductive layer 31 and the second conductive layer 32. In the fabrication process of sequentially stacked multi-layer films, the thicker the conductive layer in subsequent processes, the more likely it is to induce film peeling or separation. The embodiments of this disclosure design the thickness of the third conductive layer 33 to be less than the thickness of the first conductive layer 31 and the second conductive layer 32, so that the conductive layer furthest from the substrate is the thinnest, preventing film peeling during the fabrication of multi-layer films and improving the reliability of inductors and integrated passive devices.

[0085] The thicknesses of the second conductive layer 32 and the first conductive layer 31 may be the same or different.

[0086] For example, the thickness of the second conductive layer 32 can be greater than the thickness of the first conductive layer 31 and the third conductive layer 33, such as... Figure 2 As shown. This method achieves a multi-layer conductive structure that is thicker in the middle and thinner at the edges, reducing the parasitic resistance of the inductor 3 during operation and increasing the Q value of the inductor without changing its area, thus improving the operating performance of the inductor and integrated passive devices. Furthermore, making the outermost conductive layer thinner prevents peeling during the fabrication of the integrated passive device, thereby improving the manufacturing yield of the integrated passive device. In some embodiments, the thickness of the second conductive layer 32 is 1.5 to 2 times the thickness of the third conductive layer 33, such as... Figure 2 As shown. When the thickness of the second conductive layer 32 is less than 1.5 times the thickness of the third conductive layer 33, its effect on improving the parasitic resistance generated in the intermediate layer of the inductor is not significant; when the thickness of the second conductive layer 32 is more than twice the thickness of the third conductive layer 33, due to the large difference between the film layers, the multi-film inductor is prone to film peeling during the fabrication process, reducing the reliability between the film layers of the inductor.

[0087] For example, the thickness of the first conductive layer 31 can be greater than the thickness of the second conductive layer 32, and the thickness of the second conductive layer 32 can be greater than the thickness of the third conductive layer 33, such as... Figure 3 As shown, this method achieves a multilayer conductive structure that gradually thins from bottom to top, with the first conductive layer 31 at the bottom having the greatest thickness. This reduces the parasitic resistance of the inductor 3 and the risk of film peeling, thereby improving the performance of the inductor 3. In some embodiments, the thickness of the first conductive layer 31 is 1.5 to 2 times the thickness of the second conductive layer 32. This can further improve the quality factor of the inductor without causing film peeling.

[0088] For example, such as Figure 4 As shown, taking a four-layer inductor 3 as an example, the inductor 3 has an alternating stacked structure comprising four conductive layers and insulating layers. A first conductive layer 31, a second conductive layer 32, a third conductive layer 33, and a fourth conductive layer 34 are sequentially and spaced apart on one side of the substrate 1. Each conductive layer is covered by insulating layers P1, P2, P3, and P4, respectively. During the fabrication of the inductor 3, the conductive layers are fabricated in the following order: first conductive layer 31, second conductive layer 32, third conductive layer 33, and fourth conductive layer 34.

[0089] In some embodiments, the thickness of the fourth conductive layer 34 is less than the thickness of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33. While ensuring an increased inductance value, the Q value of the inductor 3 is improved by increasing the thickness of the conductive layers in the inductor 3; in addition, making the outermost conductive layer of the inductor thinner avoids the phenomenon of outer film peeling that is easily caused by multi-layer structures.

[0090] In other embodiments, the thickness of the fourth conductive layer 34 is less than the thickness of the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33, and the thickness of the third conductive layer 33 is less than the thickness of the first conductive layer 31 and the second conductive layer 32.

[0091] In some other embodiments, the thicknesses of the first conductive layer 31, the second conductive layer 32, the third conductive layer 33, and the fourth conductive layer 34 decrease sequentially. Specifically, the thickness of the fourth conductive layer 34 is less than the thicknesses of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33; the thickness of the third conductive layer 33 is less than the thicknesses of the first conductive layer 31 and the second conductive layer 32; and the thickness of the second conductive layer 32 is less than the thickness of the first conductive layer 31. To achieve a high inductance value for the multilayer inductor 3, the inductance Q value is improved by adjusting the thickness of the conductive layers.

[0092] In practical applications, the required inductance value of inductor 3 varies. To obtain a larger inductance value, the number of inductor coils can be increased. Ensuring a high Q-value while maintaining multiple conductive layers is one of the main challenges in passive device fabrication. This application achieves a higher Q-value inductor 3 by increasing the thickness of the conductive layer in inductor 3.

[0093] In this embodiment of the disclosure, the conductive layer in the inductor 3 has a strip structure, and the strip width of the conductive layer can be different.

[0094] For example, taking a two-layer inductor as an example, the inductor includes a first conductive layer 31 disposed on one side of a substrate 1; a second conductive layer 32 disposed on the side of the first conductive layer 31 away from the substrate 1, the first conductive layer 31 and the second conductive layer 32 having different thicknesses; a first insulating layer P1 disposed between the first conductive layer 31 and the second conductive layer 32; and at least one first connecting portion 51 penetrating the first insulating layer P1 and electrically connecting to the first conductive layer 31 and the second conductive layer 32. The width of the second conductive layer 32 is greater than the width of the first conductive layer 31. By increasing the cross-section of the second conductive layer 32, the parasitic resistance is reduced, further improving the quality factor of the inductor.

[0095] Figure 5 A perspective view of a passive device according to an embodiment of the present disclosure is shown. For clarity, only the conductive structure of the passive device, namely the conductive layer and the connection portion, is shown in the figure.

[0096] like Figure 5 As shown, the inductor includes a first conductive layer 31, a second conductive layer 32, and a third conductive layer 33, as well as a first connecting portion 51 and a second connecting portion 52 located between the conductive layers. The first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 are all configured as strip structures, with the width of the strip being the width perpendicular to the strip's extension direction within the plane of the conductive layer. Figure 5 As shown, the width of the third conductive layer 33 is greater than the width of the first conductive layer 31 and the second conductive layer 32. With this arrangement, the cross-sectional area of ​​the conductive layer can be increased without increasing the thickness of the film inductance, thereby reducing parasitic resistance and improving inductance quality. In addition, the contact area between the outermost conductive layer (the third conductive layer 33 in this embodiment) and the lower insulating layer can be increased, preventing film peeling in multilayer inductor structures.

[0097] In some embodiments, the width of the third conductive layer 33 is 1.5 to 2 times the width of the second conductive layer 32. When the width of the third conductive layer 33 is less than 1.5 times the width of the second conductive layer 32, the performance improvement of the inductor is not significant; when the width of the third conductive layer 33 is more than twice the width of the second conductive layer 32, the increased projected area of ​​the conductive layer on the insulating layer 4 affects the horizontal uniformity of the conductive layer, thereby affecting the performance of the inductor. The embodiments of this disclosure achieve a good balance between the above two aspects by setting the width of the third conductive layer 33 to 1.5 to 2 times the width of the second conductive layer 32, thereby improving the performance of the inductor.

[0098] In other embodiments, such as Figure 6 As shown, the width of the third conductive layer 33 can be greater than the width of the first conductive layer 31 and the second conductive layer 32, and the width of the second conductive layer 32 can be greater than the width of the first conductive layer 31. By increasing the cross-sectional area of ​​the second conductive layer 32, the Q value of the inductor structure can be improved. For example, the width of the third conductive layer 33 and the width of the second conductive layer 32 are 1.5 to 2 times the width of the first conductive layer 31. When the width of the third conductive layer 33 and the width of the second conductive layer 32 are less than 1.5 times the width of the first conductive layer 31, the performance improvement of the inductor is not significant; when the width of the third conductive layer 33 and the width of the second conductive layer 32 are more than twice the width of the first conductive layer 31, the increased projected area of ​​the conductive layer on the insulating layer 4 affects the horizontal uniformity of the conductive layer, thereby affecting the performance of the inductor. The embodiments of this disclosure achieve a good balance between the above two aspects by setting the width of the third conductive layer 33 and the width of the second conductive layer 32 to 1.5 to 2 times the width of the first conductive layer 31, thus improving the performance of the inductor.

[0099] According to embodiments of this disclosure, the thickness of the insulating layer can be set as needed. In some embodiments, the thickness of the first insulating layer P1 is 1 to 2.5 times the thickness of the first conductive layer 31 to prevent the distance between the first conductive layer 31 and the second conductive layer 32 from being too small, which would generate parasitic resistance and reduce inductance quality. In other embodiments, the thickness of the second insulating layer P2 is 1 to 2.5 times the thickness of the second conductive layer 32 to prevent the distance between the second conductive layer 32 and the third conductive layer 33 from being too small, which would generate parasitic resistance and reduce inductance quality.

[0100] Figure 7 A cross-sectional view of a passive device according to an embodiment of the present disclosure is shown.

[0101] like Figure 7 As shown, the inductor is configured as a three-layer conductive structure, including a first conductive layer 31, a second conductive layer 32 and a third conductive layer 33, as well as first to third insulating layers P1, P2, P3 and first to third connecting portions 51, 52, 53 located between them.

[0102] The first conductive layer 31 has at least one first blind via 512 on the side away from the substrate 11, corresponding one-to-one with at least one first connection portion 51. The orthographic projection of the first blind via 512 onto the substrate 1 is within the orthographic projection of the first via 511 onto the substrate 1. A portion of the first connection portion 51 is disposed within the first via 511, and the other portion of the first connection portion 51 is disposed within the first blind via 512. In this way, the portion of the first connection portion 51 located in the first blind via 512 is surrounded by the material of the first conductive layer 31, which allows for better contact between the first connection portion 51 and the first conductive layer 31, improves the electrical connection reliability of the inductor structure, and thus improves the quality factor of the inductor.

[0103] After the first blind hole 512 is prepared, the first connection portion 51 can be further prepared by photolithography, thereby removing the material or metal oxide formed on the surface of the lower conductive layer connected to the first connection portion 51, improving the electrical connection performance between the first connection portion 51 and the lower connected conductive layer, reducing the contact resistance of the via structure 5 between conductive layers, and improving the performance of the inductor.

[0104] In some embodiments, the depth of the first blind via 512 is less than 15% of the thickness of the first conductive layer 31. This avoids reducing the thickness of the first conductive layer 31 at the blind via due to excessive depth, thereby preventing a decrease in the inductance quality factor.

[0105] For example, the depth of the first blind via 512 can be greater than 50 nm, and the oxide thickness on the surface of the first conductive layer 31 is relatively thin. This can effectively improve the electrical connection between the first conductive layer 31 and the second conductive layer 32, thereby improving the inductor quality.

[0106] For example, the depth of the first blind via 512 can be less than 400 nm. This can effectively improve the electrical connection between the first conductive layer 31 and the second conductive layer 32, improve inductance quality, and save process time.

[0107] For example, the depth of the first blind via 512 can be less than 100 nm. In the fabrication process of the inductor structure, the oxide thickness generated on the surface of the first conductive layer 31 is relatively thin, and the depth of the first blind via 512 is less than 100 nm, which can improve the electrical connection performance between the conductive layer and the first connection portion 51.

[0108] For example, the depth of the first blind via 512 ranges from 100 to 200 nm. During the fabrication process of the inductor structure, efforts are made to remove as much oxide as possible from the surface of the first conductive layer 31, thereby improving the inductor quality by improving electrical connections.

[0109] For example, the depth of the first blind via 512 ranges from 200 to 400 nm. During the fabrication process of the inductor structure, the oxide thickness generated on the surface of the first conductive layer 31 is completely removed, thereby improving the inductor quality by improving electrical connections.

[0110] In this embodiment of the disclosure, Figure 7 As shown, the inductor 3 also includes a first transition layer 540, which is disposed on the side of the first conductive layer 31 near the substrate 1, and the first conductive layer 31 covers the first transition layer 540. The first transition layer 540 includes a first adhesive layer 541 and a first seed layer 542, with the first seed layer 542 disposed on the side of the first adhesive layer 541 away from the substrate 1.

[0111] In this embodiment of the disclosure, Figure 7 As shown, the inductor 3 further includes a second transition layer 550, which is disposed on the sidewall of the first via 511, the bottom and sidewall of the first blind via 512, and the side of the first insulating layer P1 away from the substrate. The second conductive layer 32 covers the second transition layer 550. The second transition layer 550 connects the second conductive layer 32 away from the substrate 1 and the first connecting portion 51, improving the stability of the second conductive layer 32, preventing the second conductive layer 32 from peeling off, and ensuring the compactness of the prepared second conductive layer 32.

[0112] The second transition layer 550 may include a second adhesive layer 551 and a second seed layer 552, with the second seed layer 552 disposed on the side of the second adhesive layer 551 away from the substrate 1. The second adhesive layer 551 prevents the first connection portion 51 and the second conductive layer 32 from easily peeling off during the fabrication process. The second seed layer 552 being disposed on the side of the second adhesive layer 551 away from the substrate 1 results in a denser second conductive layer 32, and the first connection portion 51 fills the first via 511 and the first blind via 512.

[0113] In the embodiments disclosed herein, such as Figure 7 As shown, along the direction away from the substrate 1, the aperture change rate of the first via 511 is less than that of the first blind via 512. For example, along the direction away from the substrate 1, the apertures of the first via 511 and the first blind via 512 can gradually increase. This is because in photolithography processes, such as laser etching, the energy is not uniform along the extension direction of the laser beam. By making the aperture change rate of the first via 511 less than that of the first blind via 512, the electrical connection between the first connection portion 51 and the first conductive layer 31 is further improved, thereby increasing the quality factor of the inductor.

[0114] like Figure 7 The second insulating layer P2 has at least one second via 521 corresponding to the second connection portion 52, and at least a portion of the second connection portion 52 is disposed within the second via 521; the first connection portion 51 and the second connection portion 52 do not overlap in their orthogonal projections onto the substrate. A portion of the second connection portion 52 is disposed within the second via 521, and another portion of the second connection portion 52 is disposed within the second blind via 522. The second blind via 522 allows for better contact between the second connection portion 52 and the second conductive layer 32, further improving the electrical connection reliability of the inductor structure, thereby improving the quality factor of the inductor.

[0115] In this embodiment of the disclosure, Figure 7 As shown, the inductor also includes a third transition layer 560, which is disposed on the sidewall of the second via 521, the bottom and sidewall of the second blind via 522, and the side of the second insulating layer P2 away from the substrate. A third conductive layer 33 covers the third transition layer 560. The third transition layer 560 includes a third adhesive layer 561 and a third seed layer 562, with the third seed layer 562 disposed on the side of the third adhesive layer 561 away from the substrate. The third transition layer 560 connects the third conductive layer 33 away from the substrate and the second connecting portion 52, improving the stability of the third conductive layer 33, preventing peeling of the third conductive layer 33, and ensuring the compactness of the prepared third conductive layer 33.

[0116] In some embodiments, the orthographic projection of the first connection portion 51 between the first conductive layer 31 and the second conductive layer 32 onto the substrate 1 and the orthographic projection of the second connection portion 52 located between the second conductive layer 32 and the third conductive layer 33 onto the substrate 1 do not overlap. Maintaining a certain distance between the orthographic projections of the first connection portion 51 and the second connection portion 52 onto the substrate 1 can prevent the problem of poor uniformity of the conductive layer surface caused by the via structure, thereby improving the quality and performance of the inductor structure.

[0117] For example, the distance between the first connecting portion 51 and the second connecting portion 52 is greater than 15–50 μm. Here, the distance between the connecting portions can be the distance between their geometric centers. For example, the first connecting portion 51 and the second connecting portion 52 can be configured as a columnar structure, and the distance between the first connecting portion 51 and the second connecting portion 52 can be defined as the distance between the central axes of the columnar structure. In some embodiments, such as… Figures 2 to 7 As shown, the central axes of the first connecting portion 51 located between the first conductive layer 31 and the second conductive layer 32 and the second connecting portion 52 located between the second conductive layer 32 and the third conductive layer 33 are parallel but do not intersect, and the distance between the first connecting portion 51 and the second connecting portion 52 is greater than 15 to 50 μm.

[0118] like Figure 8 As shown, the first via 511 has a slope angle α, and the first blind via 512 has a slope angle β. Here, the slope angle refers to the angle between the sidewall of the via and a direction parallel to the substrate (horizontal direction in the figure). The slope angle α of the first via 511 can be greater than the slope angle β of the first blind via 512. For example, the slope angle (α) of the first via 511 ranges from 20° to 90°. The slope angle β of the first blind via 512 can range from 30° to 60°. This allows for the removal of as much of the surface insulating layer 4 material or metal oxide as possible from the first conductive layer 31 connected to the first connection portion 51.

[0119] In some embodiments, the slope angle α of the first via 511 ranges from 70±5°. The first via 511 can be implemented by photolithography, such as laser drilling. When the slope angle of the first via 511 is less than 20°, it is easy to cause film peeling. The embodiments of this disclosure set the slope angle α of the first via 511 to a range of 70±5°, so that the sidewall of the via is as vertical as possible under process constraints, thereby minimizing the risk of film peeling.

[0120] exist Figure 8 In the first blind hole 512, the surface of the second transition layer 550 on the side away from the substrate 1 (the upper surface in the figure) is recessed relative to the surface of the first conductive layer 31 on the side away from the substrate 1 (the upper surface in the figure). However, the embodiments of this disclosure are not limited to this, and the former may be flush with the latter or protrude relative to the latter.

[0121] like Figure 9 As shown, the distance between the upper surface of the second transition layer 550 and the first surface S1 of the substrate 1 is equal to the thickness of the first conductive layer 31. This removes oxides from the surface of the first conductive layer 31 as much as possible, thereby improving the electrical connection between the first conductive layer 31 and the first connection portion 51.

[0122] like Figure 10As shown, the distance between the upper surface of the second transition layer 550 and the first surface S1 of the substrate 1 is greater than the thickness of the first conductive layer 31. While removing the oxide on the surface of the first conductive layer 31, the uniformity of the overall thickness of the first conductive layer 21 is improved, ensuring the inductor quality.

[0123] In this embodiment, the aperture of the first via 511 is positively correlated with the thickness of the second conductive layer 32. Compared to a situation where the second conductive layer 32 and the first conductive layer 31 have the same thickness, when the thickness of the second conductive layer 32 is greater than the thickness of the first conductive layer 31, the size of the first via 511 increases accordingly, and the size of the corresponding first connection portion 51 increases, preventing the second conductive layer 32 from easily peeling off. In some embodiments, the aperture of the first via 511 may be related to other dimensions of the second conductive layer 32, such as length, width, etc. In some embodiments, the first conductive layer 31 and the second conductive layer 32 are configured as a strip structure, for example... Figure 5 and Figure 6 The strip structure is shown. In this case, the aperture of the first via 511 can be positively correlated with the strip width of the second conductive layer 32. Here, the strip width refers to the width perpendicular to the strip extension direction.

[0124] In some embodiments, the size of the first aperture 501 of the first via 511 is 3 to 6 times the thickness of the second conductive layer 32. When the size of the first aperture 501 of the first via 511 is greater than or equal to 3 times the thickness of the second conductive layer 32, the mechanical reliability of the second conductive layer 32 is significantly improved; when the size of the first aperture 501 of the first via 511 is less than or equal to 6 times the thickness of the second conductive layer 32, the thickness uniformity of the second conductive layer 32 is ensured, and the inductance quality factor is reduced.

[0125] For example, such as Figure 11 As shown, taking a three-layer inductor as an example, when the thickness of the second conductive layer 32 is greater than the thickness of the first conductive layer 31 and the third conductive layer 33, the size of the first via 511 is greater than the size of the second via 521. The difference between the first aperture 501 of the first via 511 and the second aperture 532 of the second via 521 is 15-30 μm. When the difference between the first aperture 501 and the second aperture 532 of the second via 521 is greater than 15 μm, the effect of preventing the second conductive layer 32 from peeling off is significant. When the difference between the first aperture 501 and the second aperture 532 of the second via 521 is less than 30 μm, there is sufficient space to set the conductive layer, ensuring the uniformity of the thickness of the second conductive layer 32 and improving the quality factor of the inductor 3.

[0126] For example, when the width of the second conductive layer 32 is the same as that of the first conductive layer 31, the size of the first via 511 increases as the width of the second conductive layer 32 is greater than that of the first conductive layer 31, and the size of the corresponding first connection portion 51 increases to prevent the second conductive layer 32 from easily peeling off.

[0127] For example, the size of the first aperture 501 of the first via 511 is 3 to 6 times the width of the second conductive layer 32. When the size of the first aperture 501 of the first via 511 is greater than or equal to 3 times the width of the second conductive layer 32, the mechanical reliability of the second conductive layer 32 is significantly improved. When the size of the first aperture 501 of the first via 511 is less than or equal to 6 times the width of the second conductive layer 32, the width uniformity of the second conductive layer 32 is ensured and the inductance quality factor is improved.

[0128] For example, taking a three-layer inductor, when the width of the second conductive layer 32 is greater than the widths of the first conductive layer 31 and the third conductive layer 33, the size of the first via 511 is greater than the size of the second via 521, and the difference between the first aperture 501 of the first via 511 and the second aperture 532 of the second via 521 is 15-30 μm. When the difference between the first aperture 501 and the second aperture 532 of the second via 521 is greater than or equal to 15 μm, the effect of preventing the second conductive layer 32 from peeling off is significant; when the difference between the first aperture 501 and the second aperture 532 of the second via 521 is less than or equal to 30 μm, the uniformity of the width of the second conductive layer 32 is ensured, and the quality factor of the inductor 3 is improved.

[0129] For example, such as Figure 12 As shown, when the width of the third conductive layer 33 is greater than the widths of the second conductive layer 32 and the first conductive layer 31, the size of the second via 521 is greater than the size of the first via 511 to prevent the film layer of the third conductive layer 33 from peeling off.

[0130] In other embodiments, the first conductive layer 31 and the second conductive layer 32 are configured as strip structures, and the thickness of the first transition layer 540 is positively correlated with the width of the second conductive layer 32. When the width of the second conductive layer 32 is greater than the width of the first conductive layer 31, the thickness of the second transition layer 550 is greater than the thickness of the first transition layer 540. This prevents film peeling due to the increased width of the second conductive layer 32. When the third conductive layer 33 is greater than the thickness of the second conductive layer 32 and / or the first conductive layer 31, the thickness of the third transition layer 560 is greater than the thickness of the first transition layer 540 and / or the second transition layer 550. This prevents film peeling of the third conductive layer 33 during preparation and use.

[0131] For example, such as Figure 12As shown, the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 are configured as a strip structure, and the thickness of the first transition layer 540 is positively correlated with the thickness of the second conductive layer 32. When the thickness of the second conductive layer 32 is greater than the thickness of the first conductive layer 31 and / or the third conductive layer 33, the thickness of the second transition layer 550 is greater than the thickness of the first transition layer 540 and / or the third transition layer 560, thereby preventing the second conductive layer 32 from easily peeling off as its thickness increases.

[0132] For example, the thickness of the second transition layer 550 is 1.25 to 2 × 10⁻⁶ times the thickness of the second conductive layer 32. -2 The thickness of the three transition layers 560 is 1.25 to 2 × 10⁻⁶ times that of the thickness of the third conductive layer 33. -2 When the conductivity of the transition layer is less than that of the conductive layer, controlling the conductive layer within a suitable range ensures stable electrical connection performance between the conductive layers and improves inductance performance.

[0133] The following is for reference. Figures 13 to 19 Several examples of inductors in passive devices that are embodiments of the present disclosure are described below.

[0134] like Figure 1 3 to Figure 19 As shown in this embodiment, the orthographic projection of the first conductive layer 31 onto the substrate 1 is a first annular pattern with a first opening, and the orthographic projection of the second conductive layer 32 onto the substrate 1 is a second annular pattern with a second opening. The proportion of the first opening in the first annular pattern and the proportion of the second opening in the second annular pattern are both greater than one-half.

[0135] In this embodiment, the aforementioned annular pattern is a symmetrical pattern, and the conductive layer of the inductor is a strip structure. The projection of the pattern onto the substrate is part of a symmetrical pattern, which is beneficial for the inductor to have a more uniform inductance distribution during operation, thereby further improving the inductor quality.

[0136] As an example, the centrally symmetrical pattern can be a circle or a polygon. When the symmetrical pattern is a polygon, the interior angles of the sides are greater than or equal to 90°. When the included angle is less than 90°, the outer edge of the conductive layer at the included angle is far from the central axis of the conductive layer, which can easily lead to poor conductivity consistency and thus affect the performance of the inductor. The embodiments of this disclosure avoid this problem by setting the interior angle of the polygon to be greater than 90°.

[0137] exist Figure 13In this design, the orthographic projection of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 onto the substrate 1 is a symmetrical quadrilateral with an opening, such as a rectangle or a square, with the opening occupying two adjacent sides of the quadrilateral. The included angle of the traces of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 is 90°; in some embodiments, the quadrilateral can be set as a rounded quadrilateral. The first conductive layer 31 and the second conductive layer 32 are connected by a first connecting portion 51, and the second conductive layer 32 and the third conductive layer 33 are connected by a second connecting portion 52; the orthographic projections of the first conductive layer 31 and the second conductive layer 32 onto the substrate 1 overlap, and the orthographic projections of the second conductive layer 32 and the third conductive layer 33 onto a plane perpendicular to the thickness direction of the conductive layer overlap; the orthographic projections of the first connecting portion 51 and the second connecting portion 52 onto the substrate 1 do not overlap.

[0138] For example, such as Figure 14 As shown, taking a three-layer inductor structure as an example, the orthographic projection of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 onto the substrate 1 is a symmetrical quadrilateral with an opening, such as a rectangle or a square, with the opening occupying one side of the quadrilateral. The included angle of the traces of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 is 90°; in some embodiments, the quadrilateral can be set as a rounded quadrilateral. The first conductive layer 31 and the second conductive layer 32 are connected by a first connecting portion 51, and the second conductive layer 32 and the third conductive layer 33 are connected by a second connecting portion 52; the first conductive layer 31 and the second conductive layer 32 overlap in the orthographic projection portion onto the substrate 1, and the second conductive layer 32 and the third conductive layer 33 overlap in the orthographic projection portion onto the substrate 1; the orthographic projections of the first connecting portion 51 and the second connecting portion 52 onto the substrate 1 do not overlap.

[0139] For example, such as Figure 15 As shown, taking a three-layer inductor structure as an example, the orthographic projection of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 on the substrate 1 is a symmetrical octagonal structure of seven-eighths. The included angle of the traces of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 is 135°. The first conductive layer 31 and the second conductive layer 32 are connected by the first connecting portion 51, and the second conductive layer 32 and the third conductive layer 33 are connected by the second connecting portion 52. The first conductive layer 31 and the second conductive layer 32 overlap in the orthographic projection portion on the substrate 1, and the second conductive layer 32 and the third conductive layer 33 overlap in the orthographic projection portion on the substrate 1. The orthographic projections of the first connecting portion 51 and the second connecting portion 52 on the substrate 1 do not overlap.

[0140] In this embodiment, the orthographic projection of the first conductive layer 31 onto the substrate 1 is an annular pattern with a first opening, and the orthographic projection of the second conductive layer 32 onto the substrate 1 is an annular pattern with a second opening. The first and second openings face different directions. Reducing the overlap area of ​​the orthographic projections of the first conductive layer 31 and the second conductive layer 32 onto the substrate 1 lowers the parasitic resistance of the first conductive layer 31 and the second conductive layer 32 during operation, thereby improving inductance quality.

[0141] For example, taking a three-layer inductor 3 as an example, the orthographic projection of the first conductive layer 31 onto the substrate 1 is a first annular pattern with a first opening; the orthographic projection of the second conductive layer 32 onto the substrate 1 is a second annular pattern with a second opening; and the orthographic projection of the third conductive layer 33 onto the substrate 1 is a third annular pattern with a third opening. The first, second, and third openings face different directions. Further reducing the overlap area of ​​the orthographic projections of the first conductive layer 31, second conductive layer 32, and third conductive layer 33 onto the substrate 1 reduces the parasitic resistance of the first conductive layer 31, second conductive layer 32, and third conductive layer 33 during operation, thereby improving inductor quality.

[0142] In this embodiment, the first annular pattern and the second annular pattern have the same shape but different sizes. Parasitic resistance is easily generated between adjacent conductive layers during operation, leading to a decrease in the inductance and Q-value of the inductor, thus affecting the overall reliability of the integrated passive device. For example, during the operation of a filter, the parasitic resistance generated by adjacent conductive layers can cause changes in the filtering frequency band, resulting in poor filtering performance. By adjusting the orthographic projection relationship of the conductive layers of inductor 3 onto the substrate 1, the parasitic resistance between conductive layers can be reduced, improving the inductor quality.

[0143] For example, the width of the second annular pattern is greater than the width of the first annular pattern, and the width is the distance between the inner and outer rings of the annular pattern. As described above, by increasing the width of the second conductive layer 32 of the strip structure, the parasitic resistance during operation can be reduced, thereby improving the inductance quality.

[0144] For example, the width of the first annular pattern is greater than the width of the second annular pattern, which can also reduce the parasitic resistance of the inductor.

[0145] Furthermore, taking a three-layer inductor as an example, the width of the third ring pattern is greater than the width of the second ring pattern, which can improve the quality factor of the multilayer inductor.

[0146] For example, the first, second, and third annular patterns have the same shape but different sizes, such as... Figure 6As shown. This can minimize the overlap area of ​​the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33 projected onto the substrate 1, and further improve the quality factor of the three-layer inductor 3.

[0147] For example, such as Figure 17 As shown, taking a three-layer inductor 3 as an example, at least one of the first conductive layer 31 and the second conductive layer 32 has a partial circular projection pattern on the substrate 1. The first conductive layer 31 has a first annular pattern in its projection on the substrate 1, the second conductive layer 32 and the third conductive layer 33 have a second annular pattern in their projections on the substrate 1, and the third conductive layer 33 has a third annular pattern in their projections on the substrate 1. The size of the second annular pattern is smaller than the sizes of the first and third annular patterns; here, the size refers to the diameter of the annulus. However, the embodiments of this disclosure are not limited to this; the size can also be the width of the annulus (the distance between the inner and outer diameters) or the area of ​​the annulus, etc. In this way, the problem of inductor quality degradation caused by parasitic resistance between adjacent conductive layers can be avoided.

[0148] For example, such as Figure 18 As shown, taking a three-layer inductor 3 as an example, at least one of the first conductive layer 31 and the second conductive layer 32 has a circular projection pattern on the substrate 1. The first conductive layer 31 has a first annular pattern in its projection on the substrate 1, the second conductive layer 32 and the third conductive layer 33 have a second annular pattern in their projections on the substrate 1, and the third conductive layer 33 has a third annular pattern in its projections on the substrate 1. The size of the second annular pattern is larger than the sizes of the first and third annular patterns, which also avoids the problem of inductor quality degradation caused by parasitic resistance between adjacent conductive layers.

[0149] For example, such as Figure 19 As shown, taking a three-layer inductor 3 as an example, at least one of the first conductive layer 31 and the second conductive layer 32 has a circular projection pattern on the substrate 1. The first conductive layer 31 has a first annular pattern in its projection on the substrate 1, the second conductive layer 32 and the third conductive layer 33 have a second annular pattern in their projections on the substrate 1, and the third conductive layer 33 has a third annular pattern in its projections on the substrate 1. The size of the second annular pattern is larger than the size of the first annular pattern, and the size of the third annular pattern is larger than the size of the second annular pattern. This also avoids the problem of inductor quality degradation caused by parasitic resistance between adjacent conductive layers.

[0150] Furthermore, the geometric centers (e.g., the center of a circle) of the first, second, and third annular patterns may overlap or not overlap, depending on the actual situation.

[0151] In this embodiment, at least one of the first conductive layer 31 and the second conductive layer 32 has a protrusion 530 in a direction parallel to the substrate 1, and the protrusion 530 is connected to the first connecting portion 51. The protrusion 530 and the conductive layer are fabricated in the same layer, reducing the process and realizing the connection of conductive layers of different sizes.

[0152] like Figures 17 to 19 As shown, taking a three-layer inductor as an example, one or more of the first to third conductive layers may have protrusions. Taking the second conductive layer 32 as an example, it has protrusions in a direction parallel to the substrate 1. These protrusions include a first protrusion 501 and a second protrusion 502. The first protrusion 501 connects to the first connecting portion 51, and the second protrusion 502 connects to the second connecting portion 52. Depending on the actual situation, the position of the protrusions relative to the same conductive layer can be adjusted. For example, in… Figure 17 and Figure 19 In the middle, the protrusion of the second conductive layer 32 is projected onto the substrate 1 outside the annulus of the projected second conductive layer 32 onto the substrate 1; in Figure 18 In the middle, the protrusion of the second conductive layer 32 is projected onto the substrate 1 in the annulus of the projection of the second conductive layer 32 onto the substrate 1.

[0153] This disclosure provides an integrated passive device. For example... Figures 20 to 23 As shown, the integrated passive device includes the aforementioned passive device and capacitor 2. Capacitor 2 is electrically connected to the first conductive layer 31 of inductor 3. The connection between capacitor 2 and inductor 3 enables them to be connected in series, forming the circuit of the integrated passive device, which can be used in integrated passive devices such as filters and duplexers.

[0154] The capacitor 2 may include a first electrode 21 disposed on one side of the substrate 1, a second electrode 23 disposed on the side of the first electrode 21 away from the substrate 1, and a first dielectric layer 22 disposed between the first electrode 21 and the second electrode 23. The orthographic projections of the first electrode 21, the first dielectric layer 22, and the second electrode 23 onto the substrate 1 at least partially overlap. The overlapping projection area of ​​the first electrode 21, the first dielectric layer 22, and the second electrode 23 onto the substrate 1 determines the capacitance value of the capacitor 2.

[0155] For example, such as Figure 20 As shown, capacitor 2 has a first trace 302 and a second trace 303 on the side away from the substrate 1. The first trace 302 and the second conductive layer 32 are on the same layer, and the second trace 303 and the third conductive layer 33 are on the same layer. The third connection portion 53 penetrates the insulating layer P2 to connect the second electrode 23 and the first trace 302. The fourth connection portion 54 penetrates the insulating layer P3 to connect the first trace 302 and the second trace 303. The orthographic projections of the third connection portion 53 and the fourth connection portion 54 on the substrate 1 do not overlap.

[0156] For example, such as Figure 20 As shown, the integrated passive device 100 also includes a fifth connection portion 55 and a sixth connection portion 56. The fifth connection portion 55 and the sixth connection portion 56 penetrate the third insulating layer P3 and connect to different bumps 6. The bumps 6 connect to different solder balls 7, which are used to connect to external circuits.

[0157] The connection between the first trace 302 and the second trace 303 can be used as a signal connection, or it can be used to form an inductor 3, which is connected to the second electrode 23 of the capacitor 2.

[0158] For example, such as Figure 20 As shown, inductor 3 and capacitor 2 are disposed on the same side of substrate 1. The first conductive layer 31 of inductor 3 and the first electrode 21 of capacitor 2 are disposed in the same layer and electrically connected. This structure has a simpler fabrication process and saves on manufacturing steps. The first conductive layer 31 and the first electrode 21 are fabricated in the same layer on the surface of substrate 1, making the first conductive layer 31 and the first electrode 21 flatter and the electrical connection performance more stable, which is beneficial to improving the reliability of integrated passive device circuits. At the same time, it reduces the overall thickness of integrated passive device 100 and prevents the problem of film peeling that is easily caused by multi-film integrated passive device 100.

[0159] In some embodiments, the thickness of the first electrode 21 is the same as the thickness of the first conductive layer 31, and the thickness of the first electrode 21 is greater than the thickness of the second electrode 22. As the thickness of the first conductive layer 31 increases, the high-temperature structural stability of the first electrode 21 is higher, which can prevent the problem of reduced capacitance 2 consistency caused by deformation of the first electrode 21 during high-temperature processes.

[0160] For example, such as Figure 21 As shown, inductor 3 and capacitor 2 are disposed on the same side of substrate 1. First electrode 21 and first conductive layer 31 are disposed in the same layer, with the thickness of first electrode 21 being the same as the thickness of first conductive layer 31, but the thickness of first electrode 21 being greater than the thickness of second electrode 22. On the side of capacitor 2 away from substrate 1, first trace 302 and second trace 303 are disposed. First trace 302 and second conductive layer 32 are in the same layer, and second trace 303 and third conductive layer 33 are in the same layer and electrically connected. The connection between capacitor 2 and inductor 3 can be achieved through the third conductive layer 33. The signal connection bumps 6 and solder balls 7 are configured according to actual conditions.

[0161] For example, such as Figure 22 As shown, the thickness of the second conductive layer 32 is greater than the thickness of the first conductive layer 31 and the second conductive layer 32. By increasing the thickness of the second conductive layer 32, the quality factor of the inductor is improved.

[0162] For example, such as Figure 23As shown, the thickness of the first conductive layer 31 is greater than the thickness of the second conductive layer 32, and the thickness of the second conductive layer 32 is greater than the thickness of the third conductive layer 33, further improving the quality factor of the inductor.

[0163] For example, taking a two-layer inductor 3 as an example, the inductor 3 includes a first conductive layer 31 and a second conductive layer 32. The first conductive layer 31 and the first electrode 21 are fabricated in the same layer, and the thickness of the first electrode 21 is greater than the thickness of the second electrode 23. The first electrode 21 and the first conductive layer 31 can be electrically connected to realize the series connection of the capacitor 2 and the inductor 3; or the second conductive layer 32 and the first trace 302 can be disposed in the same layer and electrically connected to realize the series connection of the capacitor 2 and the inductor 3.

[0164] Furthermore, the fifth connecting portion 55 and the sixth connecting portion 56 penetrate the second insulating layer P2, and different bumps 6 are connected to the side of the second insulating layer P2 away from the substrate. The bumps 6 are connected to solder balls 7 for connecting external circuits. The number and position of the bumps 6 and solder balls 7 are designed according to the actual situation.

[0165] This disclosure provides a method for fabricating an integrated passive device. This method is applicable to fabricating integrated passive devices according to any of the above embodiments. Referring below to the above... Figures 20 to 23 To describe each step of the preparation method.

[0166] Step 1601: A first electrode 21 and a first conductive layer 31 are formed on one side of the substrate 1.

[0167] For example, the first electrode 21 and the first conductive layer 31 are formed by an additive method: a full-surface photoresist is coated on one side of the first surface S1 of the substrate 1, and then the photoresist is exposed and developed using a mask to form a photoresist pattern corresponding to the area and thickness of the first electrode 21 and the first conductive layer 31. Then, an electroplating process is performed to form the first conductive layer 31 pattern on the side of the insulating layer 4 away from the substrate 1.

[0168] For example, the first electrode 21 and the first conductive layer 31 are patterned using a subtractive method: the first conductive layer 31 is formed on the substrate 1 by physical vapor deposition (PVD). A layer of photoresist is coated on the surface of the first conductive layer 31 away from the substrate 1, with the photoresist thickness ensuring complete coverage of the surface of the first conductive pattern material. Then, using a mask, the photoresist is exposed and developed, retaining the photoresist above the pattern of the first electrode 21 and the first conductive layer 31, while removing all other areas. The structure outside the pattern of the first electrode 21 and the first conductive layer 31 is etched, and then the photoresist above the pattern of the first electrode 21 and the first conductive layer 31 is removed, thus forming the pattern of the first electrode 21 and the first conductive layer 31. Compared to the previous semi-additive process, due to the isotropic nature of wet metal etching, the subtractive process has lower precision, resulting in a rougher metal surface. This roughness is also affected by the skin effect to some extent, increasing resistance and thus increasing losses. Therefore, the previous semi-additive process is more commonly used.

[0169] Furthermore, a first adhesive layer 541 and a first seed layer 542 are sequentially formed on one side of the substrate 1. The first adhesive layer 541 and the first seed layer 542 are formed on one side of the substrate 1 by means of electroplating, chemical plating or sputtering, and the pattern of the first adhesive layer 541 and the first seed layer 542 is formed by photolithography.

[0170] Step 1602: A first dielectric 22 is formed on the side of the first electrode 21 away from the substrate 1, and a second electrode 23 is formed on the side of the first dielectric 22 away from the substrate 1.

[0171] For example, a first dielectric 22 is formed on the side of the first electrode 21 away from the substrate 1. The first dielectric 22 layer is deposited on the entire surface of the first electrode 21 away from the substrate 1 by physical vapor deposition (PVD), and a pattern of the first dielectric 22 is formed by processes such as photoresist coating, exposure, development and etching.

[0172] For example, a second electrode 23 is formed on the first dielectric 22. A second electrode layer 23 is formed on the side of the first dielectric 22 away from the substrate 1 by physical vapor deposition (PVD). A photoresist layer is coated on the surface of the second electrode layer 23 away from the substrate 1, with a thickness sufficient to completely cover the surface of the first conductive pattern material. Then, using a mask, the photoresist is exposed and developed. The photoresist above the pattern of the second electrode 23 is retained, while all other areas are removed. The second electrode layer 23 outside the pattern of the second electrode 23 is etched to remove the photoresist above the pattern of the second electrode 23, thus forming the pattern of the second electrode 23.

[0173] Step 1603: A first insulating layer P1 pattern is formed on the side of the second electrode 23 and the first conductive layer 31 away from the substrate 1; a second conductive layer 32 and a first trace 302 are formed on the side of the first insulating layer P1 away from the substrate 1, a first connection portion 51 connecting the second conductive layer 32 and the first conductive layer 31, and a third connection portion 53 connecting the first trace 302 and the second electrode 23 are formed.

[0174] For example, an insulating layer P1 is formed on the side of the second electrode 23 and the first conductive layer 31 away from the substrate 1. After spin-coating the insulating layer P0 to cover the entire layer, a pattern of the insulating layer P0 is formed by processes such as photoresist coating, exposure, development, and etching. The second conductive layer 32, the first trace 302, and the first connection portion 51 connecting the second conductive layer 32 and the first conductive layer 31 and the third connection portion 53 connecting the first trace 302 and the second electrode 23 can be prepared by additive or subtractive methods.

[0175] Furthermore, before fabricating the second conductive layer 32, the first trace 302, and the first connection portion 51 connecting the second conductive layer 32 and the first conductive layer 31, and the third connection portion 53 connecting the first trace 302 and the second electrode 23, a second adhesive layer 551 and a second seed layer 552 can be formed on the side of the first insulating layer P1 away from the substrate 1 by electroplating, chemical plating, or sputtering, and the pattern of the second adhesive layer 551 and the second seed layer 552 can be formed by photolithography.

[0176] In step 1604, a second insulating layer P2 pattern is formed on one side of the second conductive layer 32 and the first trace 302; a third conductive layer 33 and a second trace 303 are formed on the side of the second insulating layer P2 away from the substrate 1; a second electrolytic portion 52 connects the third conductive layer 33 and the second conductive layer 32; and a fourth connection portion 54 connects the second trace 303 and the first trace 302.

[0177] For example, the second insulating layer P2 can be fabricated by semiconductor photolithography, in the same way as the second insulating layer P1; the third conductive layer 33, the second trace 303, the second electrolytic portion 52 connecting the third conductive layer 33 and the second conductive layer 32, and the fourth connecting portion 54 connecting the second trace 303 and the first trace 302 can be fabricated by semi-forming or additive methods.

[0178] Furthermore, before the third conductive layer 33, the second trace 303, the second electrolytic portion 52 connecting the third conductive layer 33 and the second conductive layer 32, and the fourth connection portion 54 connecting the second trace 303 and the first trace 302 are prepared, a third adhesive layer 561 and a third seed layer 562 are formed on the side of the first insulating layer P1 away from the substrate 1, and the pattern of the third adhesive layer 561 and the third seed layer 562 is formed by photolithography.

[0179] Step 1604: A third insulating layer P3 pattern is formed on the side of the third conductive layer 33 and the second trace 303 away from the substrate 1; bumps 6 and solder balls 7 are formed on the side of the third insulating layer P3 away from the substrate 1.

[0180] For example, the third insulating layer P3 can be fabricated using a semiconductor photolithography process, the same as the method used to fabricate the second insulating layer P2; the fifth connecting portion 55 and the sixth connecting portion 56, as well as the bump 6 connecting the two, can be fabricated using a semi-forming method or an additive method.

[0181] The integrated passive device disclosed in this application can be used in filters, baluns, duplexers, etc., and is suitable for mobile communication RF front-end modules, Bluetooth, and mobile hotspot applications.

[0182] The first electrode 21 and the second electrode 23 can be made of one or more metallic materials (Au, Al, Ag, Cu, W, etc.) or other materials with good conductivity, and the thickness is generally between 0.2 and 2 μm.

[0183] The first dielectric 22 can be made of insulating materials such as silicon nitride (SiNx), and its thickness can be designed and determined according to the requirements of the capacitance value. Typically, the thickness can be set between 80 and 200 nm.

[0184] It should be noted that the substrate 1 can be made of materials such as glass, ceramic, silicon or other polymers, and the thickness of the substrate 1 can be about 200 μm, depending on the design requirements.

[0185] It should be noted that the thickness of insulating layer 4 ranges from 5 to 8 μm. The material of insulating layer 4 can be a photosensitive insulating material, such as polyimide (PI); a common photosensitive photoresist can be used, either positive or negative, with the thickness determined by design requirements. If the thickness of insulating layer 4 is too small, parasitic resistance can easily be generated in the conductive layers on both sides of insulating layer 4 during device operation, affecting the device's performance. If the thickness of insulating layer 4 is too large, the phenomenon of film glass formation can easily occur during the fabrication of multi-layer integrated passive devices, reducing the device fabrication yield.

[0186] It should be noted that the thickness of the conductive layer ranges from 3 to 9 μm. If the thickness of the conductive layer is too small, parasitic resistance is easily generated due to the small area of ​​the conductive cross-section, which affects the performance of the device; if the thickness of the conductive layer is too large, the conductive layer is prone to peeling during the fabrication process, which affects the reliability of the device.

[0187] It should be noted that the conductive layer and the conductive material filling the first connecting portion 51 can be metals such as Au, Al, Ag, Cu, W, or other conductive materials, and are not limited here. This is used to achieve electrical connection between different conductive layers.

[0188] It should be noted that the first adhesive layer 541, the second adhesive layer 551, and the third adhesive layer 561 in this application can be Ti, Ti, Ta, TiN, or TaN, etc., and the thickness of the adhesive layer 541 is in the range of 100–200 nm, which is not limited here. If the thickness of the adhesive layer is too small, the adhesion of the grown conductive layer to the underlying film layer is weak, and film peeling is likely to occur; if the thickness of the adhesive layer is too thick, the conductivity of the adhesive layer will be weak, which will affect the electrical connection between the conductive layers.

[0189] It should be noted that the first seed layer 542, the second seed layer 552, and the third seed layer 562 in the via structure, including the first one mentioned above, can be made of materials such as Ti or Cu, and the thickness of the seed layer ranges from 5 to 300 nm, without limitation here. They are used for the growth of the conductive material to be filled during the electroplating process.

[0190] It should be noted that the accompanying drawings in this disclosure are schematic diagrams. In passive devices and passive integrated devices, the position of passive devices can be set according to the actual situation.

[0191] In the actual product structure, due to the thinness of the adhesive layer and seed layer, it is difficult to accurately distinguish the boundary position between the two in microscopic characterization, such as scanning electron microscope images and transmission electron microscope images.

[0192] The above description is merely an embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural or procedural transformations made using the content of this disclosure and its drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this disclosure.

Claims

1. A passive device, comprising a substrate and an inductor located on one side of the substrate, the inductor comprising: A first conductive layer is disposed on one side of the substrate; The second conductive layer is disposed on the side of the first conductive layer away from the substrate, and the first conductive layer and the second conductive layer have different thicknesses. A first insulating layer is disposed between the first conductive layer and the second conductive layer; At least one first connection portion extends through the first insulating layer and is electrically connected to the first conductive layer and the second conductive layer.

2. The passive device according to claim 1, wherein, The first insulating layer is provided with at least one first through hole corresponding to the at least one first connecting portion, and at least a portion of the first connecting portion is disposed in the first through hole; Along the direction away from the substrate, the diameter of the first via gradually increases.

3. The passive device according to claim 2, wherein, The first conductive layer has at least one first blind hole on the side away from the substrate, which corresponds to at least one first connection portion. The orthographic projection of the first blind hole on the substrate is within the orthographic projection of the first via on the substrate. A portion of the first connection portion is disposed in the first via, and another portion of the first connection portion is disposed in the first blind hole.

4. The passive device according to claim 2, wherein, Along the direction away from the substrate, the aperture change rate of the first via is less than the aperture change rate of the first blind via.

5. The passive device according to claim 2, wherein, The first conductive layer and the second conductive layer are configured as strip structures, and the aperture of the first via is positively correlated with the thickness of the second conductive layer or the width of the strip.

6. The passive device according to claim 2, wherein, It also includes a second transition layer, which is disposed on the sidewall of the first via, the bottom and sidewall of the first blind via, and the side of the first insulating layer away from the substrate. The second conductive layer covers the second transition layer.

7. The passive device according to claim 6, wherein, The first conductive layer and the second conductive layer are configured as strip structures, and the thickness of the second transition layer is positively correlated with the thickness of the second conductive layer or the strip width.

8. The passive device according to claim 6, wherein, The second transition layer includes a second adhesive layer and a second seed layer, wherein the second seed layer is disposed on the side of the second adhesive layer away from the substrate.

9. The passive device according to claim 1, wherein, The first conductive layer, when projected onto the substrate, is a first annular pattern with a first opening, and the second conductive layer, when projected onto the substrate, is a second annular pattern with a second opening.

10. The passive device according to claim 9, wherein, The proportion of the first opening in the first annular pattern and the proportion of the second opening in the second annular pattern are both greater than one-half.

11. The passive device according to claim 9, wherein, The first opening and the second opening face different directions.

12. The passive device according to claim 9, wherein, The first annular pattern and the second annular pattern are symmetrical patterns.

13. The passive device according to claim 12, wherein, The symmetrical pattern is a circle or a polygon.

14. The passive device according to claim 13, wherein, The interior angles of the polygon are greater than 90°.

15. The passive device according to claim 9, wherein, The first annular pattern and the second annular pattern have the same shape but different sizes.

16. The passive device according to claim 15, wherein, The width of the second annular pattern is greater than the width of the first annular pattern, and the width is the distance between the inner and outer rings of the annular pattern.

17. The passive device according to claim 1, wherein, At least one of the first conductive layer and the second conductive layer has a protrusion in a direction parallel to the substrate, and the protrusion is connected to the first connecting portion.

18. The passive device according to any one of claims 1-17, wherein, Also includes: A third conductive layer is disposed on the side of the second conductive layer away from the substrate. A second insulating layer is disposed between the second conductive layer and the third conductive layer; At least one second connection portion penetrates the second insulating layer and is electrically connected to the second conductive layer and the third conductive layer; The thickness of one of the first conductive layer, the second conductive layer, and the third conductive layer is different from the thickness of the other two.

19. The passive device according to claim 18, wherein, The orthographic projection of the third conductive layer onto the substrate is a third annular pattern with a third opening, the width of which is greater than the width of the second annular pattern.

20. The passive device according to claim 18, wherein, The thickness of the second conductive layer is greater than the thickness of the first conductive layer and the third conductive layer; or The thickness of the first conductive layer is greater than the thickness of the second conductive layer, and the thickness of the second conductive layer is greater than the thickness of the third conductive layer.

21. The passive device according to claim 18, wherein, The second insulating layer is provided with at least one second through hole corresponding to the second connecting portion, and at least a portion of the second connecting portion is disposed in the second through hole; The first connecting portion and the second connecting portion do not overlap in their orthographic projections onto the substrate.

22. An integrated passive device, comprising: At least one passive device as described in any one of claims 1-21; as well as A capacitor, which is electrically connected to the first conductive layer of the inductor.

23. The integrated passive device according to claim 22, wherein, The capacitor includes a first electrode disposed on one side of the substrate, a second electrode disposed on the side of the first electrode away from the substrate, and a first dielectric layer disposed between the first electrode and the second electrode; The first electrode, the first dielectric layer, and the second electrode at least partially overlap in their orthogonal projections onto the substrate. The inductor and the capacitor are disposed on the same side of the substrate, and the first conductive layer of the inductor and the first electrode of the capacitor are disposed on the same layer and electrically connected.

24. The integrated passive device according to claim 23, wherein, The thickness of the first electrode is the same as the thickness of the first conductive layer, and the thickness of the first electrode is greater than the thickness of the second electrode.

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