Semiconductor device and method of manufacturing the same
By forming a protective structure of a sacrificial layer and a photoresist layer on the oxide layer, and combining high-energy medium-current and low-energy high-current ion implantation processes, the oxide layer damage problem caused by the trap proximity effect is solved, thereby improving the performance and stability of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-02-26
- Publication Date
- 2026-06-23
AI Technical Summary
During the fabrication of the well region in semiconductor devices, the well proximity effect caused by the high-current ion implantation process results in oxide layer damage and defects, affecting device performance and stability.
A protective structure is adopted by forming a sacrificial layer and a photoresist layer on the oxide layer. The damage to the oxide layer by ion reflection is reduced by a first high-energy medium-current ion implantation process and a second low-energy high-current ion implantation process. The specific steps include forming the sacrificial layer and photoresist layer, patterning, two ion implantations and subsequent removal steps.
It effectively reduces oxide layer damage caused by ion reflection, thereby improving the performance and stability of semiconductor devices.
Smart Images
Figure CN121752041B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] In typical well region fabrication processes, the implantation dose of ion implantation (IMP) can usually reach the order of E12-E13. However, for advanced 28nm processes, the ion implantation dose of the well region requires high beam current, typically reaching the order of E15. At this point, the energy requirement for high beam current ion implantation is relatively low.
[0003] However, during ion implantation in the well region, there is a well-proximity effect. If the photoresist layer (PR) in the well region is thick, the probability of collision between ions and the photoresist layer increases. This leads to an increase in the dose of implanted ions reflected to the interface between the photoresist layer and the underlying oxide layer. The interface becomes a weak point, which is prone to defects. After the oxide layer is removed by wet etching (WET), active region damage (AA damage) is easily caused. Summary of the Invention
[0004] Therefore, it is necessary to provide a semiconductor device and its manufacturing method to reduce oxide layer damage caused by ion reflection during the formation of the well region.
[0005] This application provides a method for manufacturing a semiconductor device, comprising:
[0006] A substrate is provided on which an oxide layer is formed;
[0007] A sacrificial layer and a patterned photoresist layer are formed on the oxide layer, and the sacrificial layer is patterned to expose a portion of the oxide layer;
[0008] A first ion implantation process is performed to implant ions into the substrate beneath the exposed oxide layer;
[0009] Remove the photoresist layer;
[0010] A second ion implantation process is performed to form a trap region within the substrate beneath the exposed oxide layer;
[0011] Remove the sacrificial layer;
[0012] The beam current intensity of the second ion implantation process is greater than that of the first ion implantation process, and the implantation energy of the second ion implantation process is less than that of the first ion implantation process.
[0013] In one embodiment, prior to forming a sacrificial layer on the oxide layer, the method of manufacturing the semiconductor device further includes:
[0014] The oxide layer is subjected to decoupled plasma oxidation treatment.
[0015] In one embodiment, the beam current intensity range of the first ion implantation process includes 1×10⁻⁶. 13 mA~1×10 14 mA, with implantation energy ranging from 50 KeV to 3000 KeV, and implanted ions including either phosphorus ions or arsenic ions;
[0016] The beam current intensity range of the second ion implantation process includes 1×10⁻⁶. 15 mA~1×10 16 mA, with implantation energies ranging from 2 KeV to 10 KeV, and implanted ions including germanium ions.
[0017] In one embodiment, the thickness of the sacrificial layer is positively correlated with at least one of the parameters of the beam intensity, implantation energy, and implantation time of the second ion implantation process.
[0018] In one embodiment, the thickness of the sacrificial layer ranges from 2kÅ to 3kÅ.
[0019] In one embodiment, the thickness of the photoresist layer ranges from 8 kÅ to 50 kÅ.
[0020] In one embodiment, the material of the photoresist layer is different from the material of the sacrificial layer.
[0021] In one embodiment, both the photoresist layer removal method and the sacrificial layer removal method include a wet etching process, and during the removal of the photoresist layer, the etching rate of the photoresist layer is greater than the etching rate of the sacrificial layer.
[0022] In one embodiment, after removing the sacrificial layer, the method of manufacturing the semiconductor device further includes:
[0023] Perform the annealing process;
[0024] Remove the oxide layer.
[0025] Accordingly, this application also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above.
[0026] The unexpected effect of this application is that a sacrificial layer and a photoresist layer are formed on the oxide layer to protect the oxide layer during subsequent ion implantation. The first ion implantation process is based on the photoresist layer and the second ion implantation process is based on the sacrificial layer. The beam current intensity of the second ion implantation process is greater than that of the first ion implantation process, and the implantation energy of the second ion implantation process is less than that of the first ion implantation process. This reduces ion reflection during the two ion implantation processes while forming the well region, thereby reducing oxide layer damage caused by ion reflection and effectively improving the performance and stability of the semiconductor device. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a schematic diagram of the structure corresponding to the step of forming a doped region in a semiconductor device manufacturing method in a related technology.
[0029] Figure 2 This is a schematic diagram of the structure corresponding to the step of removing the photoresist layer in the manufacturing method of a semiconductor device in a related technology.
[0030] Figure 3 This is a schematic diagram of the structure corresponding to the annealing process in a semiconductor device manufacturing method in a related technology.
[0031] Figure 4 This is a schematic diagram of the structure corresponding to the step of removing the silicon oxide layer in a semiconductor device manufacturing method in a related technology.
[0032] Figure 5 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application.
[0033] Figure 6 This is a schematic diagram of the structure corresponding to the step of providing a substrate and forming an oxide layer on the substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.
[0034] Figure 7 This is a schematic diagram of the structure corresponding to the step of forming a sacrificial layer on an oxide layer in a method for manufacturing a semiconductor device according to one embodiment of this application.
[0035] Figure 8This is a schematic diagram of the structure corresponding to the step of forming a patterned photoresist layer on a sacrificial layer in a method for manufacturing a semiconductor device according to one embodiment of this application.
[0036] Figure 9 This is a schematic diagram of the structure corresponding to the step of patterning the sacrificial layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.
[0037] Figure 10 This is a schematic diagram of the structure corresponding to the first ion implantation process in the manufacturing method of a semiconductor device provided in one embodiment of this application.
[0038] Figure 11 This is a schematic diagram of the structure corresponding to the step of removing the photoresist layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.
[0039] Figure 12 This is a schematic diagram of the structure corresponding to the second ion implantation process in the manufacturing method of a semiconductor device provided in one embodiment of this application.
[0040] Figure 13 This is a schematic diagram of the structure corresponding to the step of removing the sacrificial layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.
[0041] The reference numerals in the figures include: 100-substrate; 101-doped region; 110-silicon oxide layer; 120-photoresist layer; 200-substrate; 201-well region; 210-oxide layer; 220-sacrificial layer; 230-photoresist layer. Detailed Implementation
[0042] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0044] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0045] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0046] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0047] Figures 1 to 4 This is a schematic diagram of some steps in the manufacturing method of a semiconductor device in a related technology. The following is combined with... Figures 1 to 4 This section explains the general methods for forming doped regions.
[0048] First, refer to Figure 1 A substrate 100 is provided, on which a silicon oxide layer 110 and a patterned photoresist layer 120 are formed; an ion implantation (IMP) process is performed to form a doped region 101 in the substrate 100 below the silicon oxide layer 110 exposed by the photoresist layer 120. Optionally, the doped region 101 can be a well region.
[0049] It should be noted that because the photoresist layer is relatively thick (e.g., 8 kÅ), during the ion implantation process to form the doped region, a large number of ions will be reflected to the interface between the silicon oxide layer and the photoresist layer, causing the interface to become a weak point. Figure 1 The area circled in the middle is prone to defects.
[0050] Next, refer to Figure 2 The photoresist layer 120 is removed. Optionally, a wet etching process is used to remove the photoresist layer 120. It should be noted that during the removal of the photoresist layer 120, the silicon oxide layer 110 will also be etched and damaged, resulting in a deterioration in the quality of the silicon oxide layer and further increasing the risk of defects in the silicon oxide layer 110.
[0051] Then refer to Figure 3 and Figure 4 The substrate 100 and the silicon oxide layer 110 are annealed; then, the silicon oxide layer 110 is removed to prepare for subsequent processing steps. Optionally, a wet etching process is used to remove the silicon oxide layer 110.
[0052] It should be noted that, due to the presence of weak points in the silicon oxide layer and the damage to the silicon oxide layer during the removal of the photoresist layer, the area near the weak points in the silicon oxide layer is removed faster than the remaining part of the silicon oxide layer. This causes the substrate below the weak points to be exposed and etched first, which can even lead to active area damage (AA Damage) in semiconductor devices, seriously affecting the yield and stability of semiconductor devices.
[0053] Therefore, it is necessary to provide a semiconductor device and its manufacturing method to reduce oxide layer damage caused by ion reflection during the formation of the well region.
[0054] Figure 5A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application. See also... Figure 5 One embodiment of this application provides a method for manufacturing a semiconductor device, which includes the following steps S01 to S06.
[0055] Step S01: Provide a substrate on which an oxide layer is formed.
[0056] Step S02: A sacrificial layer and a patterned photoresist layer are stacked on the oxide layer, and the sacrificial layer is patterned to expose a portion of the oxide layer.
[0057] Step S03: Perform the first ion implantation process to implant ions into the substrate beneath the exposed oxide layer.
[0058] It should be noted that, since a sacrificial layer is formed on the oxide layer, during the first ion implantation process, the reflected ions will preferentially enter the sacrificial layer, thereby reducing or even avoiding the probability of reflected ions entering the oxide layer, thus reducing ion damage to the oxide layer.
[0059] Step S04: Remove the photoresist layer.
[0060] Step S05: Perform a second ion implantation process to form a trap region in the substrate below the exposed oxide layer; wherein the beam current intensity of the second ion implantation process is greater than the beam current intensity of the first ion implantation process, and the implantation energy of the second ion implantation process is less than the implantation energy of the first ion implantation process.
[0061] It should be noted that the beam current intensity of the second ion implantation process is greater than that of the first ion implantation process, while the implantation energy of the second process is less than that of the first. That is, the first ion implantation process is a high-energy, medium-current ion implantation process, while the second is a low-energy, high-current ion implantation process. Based on common knowledge in the field, ion reflection is relatively rare in high-energy, medium-current ion implantation processes. Therefore, using a high-energy, medium-current first ion implantation process can further reduce the probability of ion damage to the oxide layer. In contrast, in the low-energy, high-current second ion implantation process, the reflected ions generated during the process preferentially penetrate the sacrificial layer due to the barrier effect of the sacrificial layer, thereby minimizing the probability of ions reflecting into the oxide layer and effectively reducing the risk of oxide layer damage.
[0062] Step S06: Remove the sacrificial layer.
[0063] The semiconductor device manufacturing method described above involves forming a sacrificial layer and a photoresist layer on an oxide layer to protect the oxide layer during subsequent ion implantation. A first ion implantation process based on the photoresist layer and a second ion implantation process based on the sacrificial layer are performed, with the beam current intensity of the second ion implantation process being greater than that of the first ion implantation process, and the implantation energy of the second ion implantation process being less than that of the first ion implantation process. This reduces ion reflection during both ion implantation processes while forming a trap region, thereby reducing oxide layer damage caused by ion reflection and effectively improving the performance and stability of the semiconductor device.
[0064] Figures 6 to 13 This is a schematic diagram of the structure corresponding to some steps in the manufacturing method of a semiconductor device provided in one embodiment of this application. The following is in conjunction with... Figures 6 to 13 This application provides a detailed description of a method for manufacturing a semiconductor device according to one embodiment.
[0065] First, refer to Figure 6 A substrate 200 is provided, on which an oxide layer 210 is formed. In one embodiment, prior to forming a sacrificial layer on the oxide layer 210, the method for manufacturing the semiconductor device further includes: performing decoupled plasma oxidation (DPO) on the oxide layer to repair damage to the oxide layer 210 in previous processes, improve the surface smoothness and density of the oxide layer 210, thereby reducing ion reflection during subsequent ion implantation. Optionally, the material of the oxide layer 210 includes silicon dioxide (SiO2).
[0066] Next, refer to Figures 7 to 9 A sacrificial layer 220 and a patterned photoresist layer 230 are formed on the oxide layer 210, and the sacrificial layer 220 is patterned to expose a portion of the oxide layer 210. In one embodiment, the photoresist layer 230 is made of a different material than the sacrificial layer 220 so that the photoresist layer 230 and the sacrificial layer 220 can be removed separately in subsequent processes. Optionally, the material of the sacrificial layer 220 includes silicon nitride (SiN).
[0067] In one embodiment, the thickness of the sacrificial layer ranges from 2 kÅ to 3 kÅ; the thickness of the photoresist layer ranges from 8 kÅ to 50 kÅ. It should be noted that in other embodiments of this application, the specific thickness ranges of the oxide layer, sacrificial layer, and photoresist layer can be adjusted according to the process parameters of the subsequent ion implantation process, or the corresponding thickness ranges can be set according to actual needs. The only requirement is that the stacked structure formed by the oxide layer and sacrificial layer has sufficient thickness to protect the substrate and prevent damage from ion implantation. This application does not impose any limitations on this.
[0068] In one embodiment, the specific formation process of the sacrificial layer and the photoresist layer includes: (See below) Figure 7 A sacrificial layer 220 is deposited on the oxide layer 210; then, refer to Figure 8 A photoresist layer 230 is formed on the sacrificial layer 220, and the photoresist layer 230 is exposed and etched to form a patterned photoresist layer 230; subsequently, refer to Figure 9 The sacrificial layer 220 is etched using the photoresist layer 230 as a mask to pattern the sacrificial layer 220 and expose part of the oxide layer 210 for subsequent ion implantation of the trap region.
[0069] Next, refer to Figure 10 A first ion implantation process is performed to implant ions into the substrate beneath the exposed oxide layer 210. In one embodiment, the beam current intensity range of the first ion implantation process includes 1 × 10⁻⁶. 13 mA~1×10 14 mA, with implantation energies ranging from 50 KeV to 3000 KeV, and implanted ions including either phosphorus (P) or arsenic (As).
[0070] It is important to emphasize that, since the first ion implantation process is a high-energy, medium-current ion implantation process, there is relatively little ion reflection during this ion implantation process. Therefore, using a high-energy, medium-current first ion implantation process can reduce the probability of ion damage to the oxide layer.
[0071] Then refer to Figure 10 and Figure 11 The photoresist layer 230 is removed. In one embodiment, an ashing process and a wet etching process can be used to remove the photoresist layer 230, and during the removal of the photoresist layer 230, the etching rate of the photoresist layer 230 is greater than the etching rate of the sacrificial layer 220, so as to avoid the sacrificial layer 220 being removed along with the photoresist layer 230.
[0072] Next, refer to Figure 12 A second ion implantation process is performed to form a well region 201 within the substrate 200 beneath the exposed oxide layer 210. The beam current intensity of the second ion implantation process is greater than that of the first ion implantation process, and the implantation energy of the second ion implantation process is less than that of the first ion implantation process. In one embodiment, the beam current intensity range of the second ion implantation process includes 1 × 10⁻⁶. 15 mA~1×10 16 mA, with implantation energies ranging from 2 KeV to 10 KeV, and implanted ions including germanium ions (Ge).
[0073] In other embodiments of this application, the implanted ions in the first ion implantation process and the second ion implantation process can also be selected from other ions that meet the process requirements according to actual needs, as long as the limiting condition that "the types of implanted ions corresponding to the first ion implantation process and the second ion implantation process are different" is met. This application does not impose any restrictions on this.
[0074] It should be noted that in the low-energy, high-current second ion implantation process, the reflected ions generated during the process will preferentially enter the sacrificial layer due to the barrier effect of the sacrificial layer, thereby minimizing the probability of ions being reflected into the oxide layer and effectively reducing the risk of oxide layer damage. Simultaneously, the sacrificial layer suffers significant ion damage during the second ion implantation process, which can even lead to thinning of the sacrificial layer in severe cases. Therefore, the thickness of the sacrificial layer needs to be adjusted in conjunction with the process parameters of the second ion implantation process to ensure that the sacrificial layer consistently protects the oxide layer throughout the process. In one embodiment, the thickness of the sacrificial layer is positively correlated with at least one of the parameters of the second ion implantation process: beam current intensity, implantation energy, and implantation time.
[0075] Then refer to Figure 13 The sacrificial layer 220 is removed. In one embodiment, a wet etching process is used to remove the sacrificial layer 220. In other embodiments of this application, other methods may be used to remove the sacrificial layer 220, and this application does not limit this method.
[0076] In one embodiment, after removing the sacrificial layer, the method for manufacturing the semiconductor device further includes: performing an annealing process to repair ion implantation damage within the semiconductor device; and removing the oxide layer to allow for subsequent process steps.
[0077] Accordingly, please continue to refer to Figure 13 One embodiment of this application also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above. In other embodiments of this application, the semiconductor device manufacturing method described above can also be used to manufacture doped regions, ion implantation regions, or other similar semiconductor structures to reduce or even avoid oxide layer damage or active region damage caused by ion reflection, thereby helping to improve the performance and stability of the semiconductor device.
[0078] The unexpected effect of this application is that a sacrificial layer and a photoresist layer are formed on the oxide layer to protect the oxide layer during subsequent ion implantation. The first ion implantation process is based on the photoresist layer and the second ion implantation process is based on the sacrificial layer. The beam current intensity of the second ion implantation process is greater than that of the first ion implantation process, and the implantation energy of the second ion implantation process is less than that of the first ion implantation process. This reduces ion reflection during the two ion implantation processes while forming the well region, thereby reducing oxide layer damage caused by ion reflection and effectively improving the performance and stability of the semiconductor device.
[0079] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0081] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided on which an oxide layer is formed; A sacrificial layer and a patterned photoresist layer are stacked on the oxide layer. The material of the photoresist layer is different from that of the sacrificial layer. The sacrificial layer is patterned based on the patterned photoresist layer to expose part of the oxide layer. A first ion implantation process is performed to implant ions into the substrate beneath the exposed oxide layer; Remove the photoresist layer; A second ion implantation process is performed to form a trap region within the substrate beneath the exposed oxide layer; Remove the sacrificial layer; Wherein, the beam current intensity of the second ion implantation process is greater than that of the first ion implantation process, and the implantation energy of the second ion implantation process is less than that of the first ion implantation process. Before forming a sacrificial layer on the oxide layer, the method for manufacturing the semiconductor device further includes: The oxide layer is subjected to decoupled plasma oxidation treatment.
2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The beam current intensity range of the first ion implantation process includes 1×10⁻⁶. 13 mA~1×10 14 mA, with implantation energy ranging from 50 KeV to 3000 KeV, and implanted ions including either phosphorus ions or arsenic ions; The beam current intensity range of the second ion implantation process includes 1×10⁻⁶. 15 mA~1×10 16 mA, with implantation energies ranging from 2 KeV to 10 KeV, and implanted ions including germanium ions.
3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The thickness of the sacrificial layer is positively correlated with at least one of the parameters of the second ion implantation process: beam intensity, implantation energy, and implantation time.
4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The thickness of the sacrificial layer ranges from 2kÅ to 3kÅ.
5. The method for manufacturing a semiconductor device according to claim 1 or 4, characterized in that, The thickness of the photoresist layer ranges from 8 kÅ to 50 kÅ.
6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Both the photoresist layer removal method and the sacrificial layer removal method include a wet etching process, and during the removal of the photoresist layer, the etching rate of the photoresist layer is greater than the etching rate of the sacrificial layer.
7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After removing the sacrificial layer, the method for manufacturing the semiconductor device further includes: Perform the annealing process; Remove the oxide layer.
8. A semiconductor device, characterized in that, It is manufactured using the manufacturing method of any one of claims 1 to 7.