Semiconductor device preparation method and semiconductor device
By selective exposure and material modification, the problem of film depression caused by clearance area was solved, ensuring the performance and yield of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-23
- Publication Date
- 2026-03-27
AI Technical Summary
In the fabrication of three-dimensional integrated circuits, the clearance area leads to film layer depressions and material residues, which affect the performance and yield of semiconductor devices.
By selective exposure and material modification, the removal rate of the film layer above the clearance zone is reduced, making it consistent with other areas and eliminating the depression.
This achieves a near-uniform film height, optimizing the performance and yield of semiconductor devices.
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Figure CN121752047A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device preparation method and a semiconductor device. BACKGROUND
[0002] At present, in the preparation process of three-dimensional integrated circuits, in order to improve the integration capability of the longitudinal dimension of the chip, a large number of advanced packaging chip designs will use high-density TSV (Through-Silicon Via) technology. When using the TSV technology, a larger non-pattern open area needs to be reserved as a reserved area for opening the TSV, that is, a keep out zone (KOZ).
[0003] Since no pattern is formed above the keep out zone, when performing photolithography, etching or chemical mechanical polishing (CMP) on the same film layer, the etching rate or polishing rate of the keep out zone and the non-keep out zone is different, resulting in a height difference between the keep out zone and the non-keep out zone of the same film layer. When the keep out zone is large, the film layer in the keep out zone is prone to recess due to the existence of the height difference, and then other materials deposited in the subsequent process are prone to remain in the recess of the film layer, thereby causing defects in the finally prepared semiconductor device, affecting the performance and yield of the product. SUMMARY
[0004] The semiconductor device preparation method and the semiconductor device provided by the present application can optimize the film layer recess and material residue caused by the keep out zone reservation, and ensure the performance and yield of the prepared semiconductor device.
[0005] In a first aspect, the present application provides a semiconductor device preparation method, which comprises: forming a first structure on a wafer; depositing a first film layer on the first structure, wherein the first film layer is formed with a recess above the keep out zone; depositing a photoresist on the first film layer; selectively exposing the photoresist located above the keep out zone or the rest of the photoresist by using a customized photomask; removing the exposed photoresist; performing material modification on the part of the first film layer located above the keep out zone or the rest of the first film layer, and the removal rate of the part of the modified first film layer located above the keep out zone is lower than that of the rest of the first film layer under the same removal process; removing the remaining photoresist on the first film layer; performing the removal process on the first film layer to expose the first structure.
[0006] Optionally, the selective exposure of the photoresist above the clearance area or the rest of the photoresist comprises exposing the photoresist above the clearance area. The material modification of the first film layer above the clearance area or the rest of the first film layer comprises modifying the material of the first film layer above the clearance area, and the modified portion has a removal rate lower than that of the unmodified portion in the same removal process.
[0007] Optionally, the selective exposure of the photoresist above the clearance area or the rest of the photoresist comprises exposing the photoresist above the clearance area. The material modification of the first film layer above the clearance area or the rest of the first film layer comprises modifying the material of the first film layer above the clearance area, and the modified portion has a removal rate lower than that of the unmodified portion in the same removal process.
[0008] Optionally, the material modification of the first film layer above the clearance area or the rest of the first film layer comprises ion implantation to the first film layer, and the implanted ions can modify the material of the first film layer without modifying the photoresist.
[0009] Optionally, the ion implantation to the first film layer comprises vertically downward ion implantation to the first film layer above the first film layer.
[0010] Optionally, the ion implantation to the first film layer comprises: Controlling at least one of the energy, dose, depth and concentration of the ion implantation so that after the chemical physical polishing of the first film layer and the exposure of the first structure, the modified portion of the remaining first film layer is as little as possible.
[0011] Optionally, the opening shape of the customized mask matches the shape of the clearance area, and the opening size of the customized mask is the same as or slightly larger than the size of the clearance area.
[0012] Optionally, the opening shape of the customized mask matches the shape of the area other than the clearance area, and the opening size of the customized mask is the same as or slightly larger than the size of the area other than the clearance area.
[0013] Optionally, the clearance area comprises a through silicon via clearance area and / or other 3D clearance area.
[0014] In a second aspect, the present application provides a semiconductor device prepared by the above semiconductor device preparation method.
[0015] The semiconductor device preparation method and the semiconductor device provided by the embodiment of the present application can modify the material of the recessed part or the remaining part of the first film layer, so that the removal rate of the modified first film layer located above the clearance area is lower than that of the remaining part under the same removal process, thereby realizing that the height of the entire first film layer tends to be flush after the removal process is performed on the first film layer, and the recessed part is eliminated, so that the film layer recess and material residue caused by the clearance area reservation can be optimized, and the performance and yield of the prepared semiconductor device can be ensured. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 The flowchart of the semiconductor device preparation method of an embodiment of the present application is shown in the figure. Figures 2-9 The structure diagram corresponding to each step of the semiconductor device preparation method of another embodiment of the present application is shown in the figure. Figure 10 The schematic diagram of the customized photomask used in the semiconductor device preparation method of another embodiment of the present application is shown in the figure. DETAILED DESCRIPTION
[0017] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be described clearly and completely below in combination with the drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.
[0018] The semiconductor device preparation method provided by the embodiment of the present application comprises the following steps. Figure 1 As shown in the figure, the method comprises the following steps. S11, forming a first structure on a wafer; S12, depositing a first film layer on the first structure, wherein the first film layer is recessed at a position above a clearance area; S13, depositing a photoresist on the first film layer.
[0019] S14, selectively exposing the photoresist located above the clearance area or the photoresist of the remaining part through a customized photomask.
[0020] Optionally, the photoresist located above the clearance area can be exposed, or the photoresist of the remaining part can be exposed; If the photoresist above the clearance area is selected to be exposed, the opening shape of the customized photomask matches the shape of the clearance area, and the opening size of the customized photomask is the same as or slightly larger than the size of the clearance area. If the photoresist of the remaining part is selected to be exposed, the opening shape of the customized photomask matches the shape of the area other than the clearance area, and the opening size of the customized photomask is the same as or slightly larger than the size of the area other than the clearance area.
[0021] S15, the exposed photoresist is removed.
[0022] S16, the first film layer above the clearance area or the remaining part is subjected to material modification, and the removal rate of the modified first film layer above the clearance area is lower than that of the remaining part in the same removal process.
[0023] Corresponding to step S14, if the photoresist above the clearance area is selected to be exposed, in this step, the first film layer above the clearance area is selected to be subjected to material modification, and the removal rate of the modified part is lower than that of the unmodified part in the same removal process. If the photoresist of the remaining part is selected to be exposed, in this step, the remaining part of the first film layer is selected to be subjected to material modification, and the removal rate of the modified part is higher than that of the unmodified part in the same removal process.
[0024] S17, the photoresist remaining on the first film layer is removed.
[0025] S18, the first film layer is subjected to the removal process, and the first structure is exposed.
[0026] The semiconductor device preparation method provided by the embodiment of the present application is used for the first film layer with a recess formed above the clearance area, the recess part or the remaining part is subjected to material modification, so that the removal rate of the modified first film layer above the clearance area is lower than that of the remaining part in the same removal process, thereby realizing that the height of the entire first film layer tends to be flat after the removal process of the first film layer, and the recess part is eliminated, so that the film layer recess and material residue caused by the clearance area reservation can be optimized, and the performance and yield of the prepared semiconductor device are ensured.
[0027] The semiconductor device preparation method of the present application will be described in detail below in combination with specific embodiments.
[0028] This embodiment uses the fabrication of FINFET as an example for illustration. In the process of forming the fin, the recess formed above the clearance area after the oxide dielectric layer is deposited is modified with material so that the removal rate of the modified oxide dielectric layer above the clearance area is lower than that of the rest of the part under the same removal process.
[0029] The semiconductor device fabrication method provided in this embodiment of the invention includes the following steps: S21. Fins 11 are formed on wafer 10 to obtain the following: Figure 2 The structure shown.
[0030] S22. Deposit an oxide dielectric layer 12 on wafer 10 to obtain the following: Figure 3 The structure shown.
[0031] The height of the formed medium layer 12 is higher than the height of the fin 11.
[0032] In addition, since a blank area without patterns needs to be reserved as a reserved area for opening TSV or other 3D through-holes, i.e., the clearance area, more space needs to be filled when forming the dielectric layer in this area than in other areas. This results in a depression of the dielectric layer in the clearance area. In other words, the height of the dielectric layer above the clearance area is lower than the height of the dielectric layer in other areas, and there is a height difference between the two.
[0033] S23. Deposit photoresist 13 on dielectric layer 12 to obtain as shown in the figure. Figure 4 The structure shown.
[0034] S24, such as Figure 5 As shown, a custom photomask is used to selectively expose the photoresist above the clearance area.
[0035] The customized photomask is selectively configured based on the required clearance area location. Specifically, the opening shape of the customized photomask matches the shape of the clearance area, and the opening size of the customized photomask is the same as or slightly larger than the clearance area. The clearance area includes through-silicon via clearance areas and / or other 3D clearance areas.
[0036] For example, such as Figure 10 As shown, the TSV clearance area is a centrally cleared area enclosed by an octagonal protective ring. Therefore, the pattern opened on the custom photomask can be defined as an octagon with the same size as or slightly larger than the inner size of the octagonal protective ring. If there are other 3D clearance area designs, such as a square clearance area design similar to the bonding mark of 80um*80um, then the pattern opened on the custom photomask can be designed as an 80um*80um or slightly larger square shape.
[0037] likeFigure 5 As shown, the custom mask is only opened at the corresponding position above the clearance area, thus, when the selective exposure is performed, only the photoresist above the clearance area is exposed, while the photoresist in other areas is covered and not exposed.
[0038] S25, the exposed photoresist is removed, and the structure as shown is obtained. Figure 6
[0039] As shown, the photoresist above the clearance area has been exposed and can be removed after cleaning, while the photoresist in other areas is retained after this step because it has not been exposed. Figure 6
[0040] S26, selective ion implantation is performed to partially modify the material of the dielectric layer in the clearance area, and the modified portion 14 has a lower removal rate than the unmodified dielectric layer in the remaining portion under the same removal process.
[0041] As shown, the photoresist above the clearance area has been removed, exposing the dielectric layer in the clearance area, while the photoresist in other areas blocks the ion implantation. The ion implantation can modify the material of the dielectric layer without modifying the photoresist. After ion implantation, the material of the dielectric layer in the clearance area is partially modified, while the dielectric layer in other areas is not modified due to the blocking of the photoresist. Thus, the modified portion 14 has a lower removal rate than the unmodified dielectric layer in other areas under the same removal process, so that the recessed portion is eliminated after the subsequent removal process, and the height of the entire dielectric layer tends to be flat. Figure 7 Optionally, the oxide dielectric layer can be doped with carbon (C+), nitrogen (N+), silicon (Si+), etc. to modify the dielectric layer.
[0042] Preferably, the ion implantation can be performed vertically downward on the oxide dielectric layer above the dielectric layer.
[0043] Further, at least one parameter of the ion implantation, such as energy, dose, depth, and concentration, can be controlled to ensure that the modified portion of the remaining dielectric layer is as small as possible after the chemical and physical polishing of the dielectric layer and the exposure of the fins.
[0044] S27, the remaining photoresist is removed, and the structure as shown is obtained.
[0045] Figure 8
[0046] Specifically, the photoresist remaining outside the clearance area is removed to expose the dielectric layer. At this point, the entire dielectric layer is fully exposed. There is still a depression in the dielectric layer above the reserved clearance area. However, the upper part of the dielectric layer above the reserved clearance area has been modified.
[0047] S28. Perform chemical and physical polishing on the dielectric layer to expose the fins, resulting in the following: Figure 9 The structure shown.
[0048] Since the upper part of the medium layer above the clearance zone has been modified, the removal rate is reduced. However, the material of the medium layer outside the clearance zone is not modified, and the medium layer removal rate is fast. Therefore, during the chemical and physical polishing of the medium layer, the height difference between the medium layer above the clearance zone and the medium layer in other areas gradually decreases, the depression is gradually reduced, and finally, after the fin is exposed, the depression in the clearance zone is eliminated, the height of the entire medium layer reaches the same level, and the modified part of the remaining medium layer is basically removed.
[0049] The semiconductor device fabrication method provided in this invention addresses the issue of a recessed oxide dielectric layer formed above a clearance area. It employs selective ion implantation to modify the material in the recessed portion, resulting in a lower removal rate for the modified portion under the same removal process compared to the unmodified portion. This ensures that after the oxide dielectric layer is removed, the overall height of the oxide dielectric layer becomes flush, eliminating the recess. This optimizes the film layer recesses and material residues caused by clearance area reservations, guaranteeing the performance and yield of the fabricated semiconductor device.
[0050] Similarly, in the subsequent formation of dummy gates, metal gates, and other structures, a process similar to that used for fin formation can be employed. Depending on the material of the deposited film on different structures, different ions can be implanted to modify the material of the deposited film. This allows the height difference between the film above the clearance zone and other areas to gradually decrease during subsequent removal processes, eliminating the depression in the clearance zone. The process steps employed in this procedure are highly compatible and have minimal impact on subsequent processes.
[0051] For example, in the process of forming a dummy gate, for the depression formed above the reserved clearance area in the deposited polysilicon layer, boron can be doped into the polysilicon layer in that area. + Light ions are implanted at low doses to modify the polycrystalline silicon layer material in this region. The modified part is removed at a lower rate during subsequent chemical and physical polishing than the rest.
[0052] In the process of forming the metal gate, for the recess formed above the reserved clearance area of the deposited gate metal layer, nitrogen (N) can be doped into the gate metal layer in that area. + ), carbon (C) + ), titanium (Ti + ) or tantalum (Ta + Light ions, such as those present in the image, modify the gate metal layer in this region. The modified portion is removed at a lower rate during subsequent chemical and physical polishing than the remaining portion.
[0053] Optionally, in the above embodiments, when exposing the photoresist, the opening shape of the customized photomask can be matched with the shape of the area outside the clearance area, and the opening size is the same as or slightly larger than the size of the area outside the clearance area. This allows the photoresist outside the clearance area to be exposed and removed, while the photoresist above the clearance area is not exposed and is retained. Subsequently, the material of the dielectric layer outside the clearance area is modified. The removal rate of the modified part under the same removal process is higher than that of the unmodified part. In subsequent removal processes, the height difference between the dielectric layer above the clearance area and the dielectric layer in other areas can be gradually reduced, eliminating the depression in the clearance area.
[0054] This invention also provides a semiconductor device, which is fabricated using the semiconductor device fabrication method described above.
[0055] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The method includes: The first structure is formed on the wafer; A first film layer is deposited on the first structure, wherein the first film layer has a depression formed above the clearance area; Photoresist is deposited on the first film layer; By using a custom photomask, selective exposure can be performed on the photoresist located above the clearance area or on the rest of the photoresist. Remove the exposed photoresist; The material of the portion or the rest of the first membrane layer located above the clearance area is modified. The removal rate of the modified portion of the first membrane layer located above the clearance area is lower than the removal rate of the rest of the portion under the same removal process. Remove the residual photoresist on the first film layer; The first membrane layer is subjected to the removal process described above to expose the first structure.
2. The method according to claim 1, characterized in that, The selective exposure of the photoresist located above the clearance area or the remaining portion of the photoresist includes: exposing the photoresist located above the clearance area; The material modification of the portion or remaining portion of the first membrane layer located above the clearance area includes: modifying the material of the portion of the first membrane layer located above the clearance area, wherein the removal rate of the modified portion under the same removal process is lower than the removal rate of the unmodified portion.
3. The method according to claim 1, characterized in that, The selective exposure of the photoresist located above the clearance area or the remaining portion of the photoresist includes: exposing the remaining portion of the photoresist; The modification of the material of the portion or the remainder of the first membrane layer located above the clearance zone includes: modifying the material of the remaining portion of the first membrane layer, wherein the removal rate of the modified portion under the same removal process is higher than that of the unmodified portion.
4. The method according to claim 2 or 3, characterized in that, The modification of the material of the portion or the remainder of the first film layer located above the clearance area includes: ion implantation into the first film layer, wherein the implanted ions can modify the material of the first film layer without modifying the photoresist.
5. The method according to claim 4, characterized in that, The ion implantation into the first membrane layer includes: implanting ions vertically downwards into the first membrane layer above it.
6. The method according to claim 2 or 3, characterized in that, The ion implantation into the first membrane layer includes: At least one of the parameters of ion implantation energy, dose, depth and concentration is controlled such that after the first film layer is chemically and physically polished and the first structure is exposed, the remaining modified portion of the first film layer is minimized.
7. The method according to claim 2, characterized in that, The opening shape of the custom photomask matches the shape of the clearance area, and the opening size of the custom photomask is the same as or slightly larger than the size of the clearance area.
8. The method according to claim 3, characterized in that, The opening shape of the custom photomask matches the shape of the area outside the clearance zone, and the opening size of the custom photomask is the same as or slightly larger than the size of the area outside the clearance zone.
9. The method according to claim 1, characterized in that, The clearance area includes through-silicon via clearance area and / or other 3D clearance areas.
10. A semiconductor device, characterized in that, The semiconductor device is prepared by the method described in any one of claims 1 to 9.