Bonding method and bonding structure

Abstract

The invention relates to the technical field of bonding, in particular to a bonding method and a bonding structure.The bonding method comprises the steps that a to-be-scribed wafer is scribed to obtain a chip, and the chip is provided with a first to-be-bonded face; removing partial thickness of the chip in the edge area of the first to-be-bonded surface to form a boss and an annular gap surrounding the boss; the target wafer is provided with a second to-be-bonded surface, and after the boss is formed, the first to-be-bonded surface of the chip and the second to-be-bonded surface of the target wafer are bonded. According to the bonding structure and the three-dimensional packaging structure with the bonding structure, the first to-be-bonded surface of the chip is subjected to graphical processing after scribing, so that edge defects of the chip are removed, adverse effects of the edge defects of the chip on the bonding strength are avoided, the bonding strength of the chip and the target wafer is improved, and the long-term reliability of the bonding structure and the three-dimensional packaging structure with the bonding structure is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of bonding, in particular to a bonding method and a bonding structure. BACKGROUND

[0002] With the development of integrated circuit industry into the post-moore era, the key pitch and size of chips are continuously shrinking, and some new integrated packaging methods emerge, such as hybrid bonding technology. Hybrid bonding technology combines dielectric bonding and metal interconnection bonding technology, and establishes permanent electrical connection through forming dielectric bonding metal bond, without the need for solder bumps, so hybrid bonding can further reduce the interconnection pitch of bonding, realize high-density integration, and plays an irreplaceable role in 3D packaging. Hybrid bonding technology includes wafer to wafer (W2W) bonding technology and die to wafer (D2W) bonding technology, wherein the D2W hybrid bonding technology is more adaptable, especially suitable for high-performance computing scenarios that need to integrate multiple chips with different functions, and is a key technology for realizing chip three-dimensional stacking, and plays an important role in Chiplet, HBM, CIS and other technologies.

[0003] D2W hybrid bonding technology needs to cut the chip from the wafer to be scribed through scribing. However, the current scribing method is easy to cause chip edge defects, thereby generating microcracks and debris at the edge of the chip, and attaching pollutants such as particles in the environment, and after bonding with the target wafer, the bonding surface is easy to produce more voids, and the voids constitute an un-bonded area, which has an adverse effect on the bonding strength. SUMMARY

[0004] Therefore, the present application provides a bonding method and a bonding structure to improve the bonding strength.

[0005] In a first aspect, the present application provides a bonding method, comprising: scribing a wafer to be scribed to obtain a chip, the chip having a first bonding surface to be bonded; removing a portion of the thickness of the chip located at the edge region of the first bonding surface to be bonded to form a boss and an annular notch surrounding the boss; a target wafer has a second bonding surface to be bonded, after forming the boss, the first bonding surface to be bonded of the chip and the second bonding surface to be bonded of the target wafer are bonded.

[0006] By patterning the first bonding surface to be bonded of the chip after scribing to remove the chip edge defects, the adverse effect of the chip edge defects on the bonding strength is avoided, the bonding strength of the chip and the target wafer is improved, and the long-term reliability of the bonding structure and the three-dimensional packaging structure containing the bonding structure is improved.

[0007] In some optional embodiments, the removing the partial thickness of the chip at the edge region of the first bonding surface comprises: forming a first mask on the surface of the chip, the first mask exposing the edge region of the first bonding surface; performing a first etching on the first bonding surface based on the first mask; and removing the first mask.

[0008] In some optional embodiments, the first etching on the first bonding surface based on the first mask obtains a first protrusion; and the removing the partial thickness of the chip at the edge region of the first bonding surface further comprises: forming an nth mask on the surface of the chip, the nth mask exposing the edge region of the first bonding surface at an (n-1)th protrusion; performing an nth etching on the first bonding surface based on the nth mask, removing the partial thickness of the edge region of the (n-1)th protrusion to obtain an nth protrusion, n being an integer greater than or equal to 2; removing the nth mask; and obtaining an Nth protrusion after the Nth etching, N being an integer greater than or equal to 2, and n being less than or equal to N, the residual structures of the first protrusion to the (N-1)th protrusion and the Nth protrusion constituting the protrusion with multiple sub-protrusions.

[0009] In some optional embodiments, the chip comprises: a first semiconductor substrate having a first device structure therein; a first redistribution layer on a side surface of the first semiconductor substrate, the first redistribution layer having a first metal wiring region; and a first bonding structure on a side surface of the first redistribution layer away from the first semiconductor substrate, the first bonding structure being composed of a first dielectric layer and a first pad penetrating through the first dielectric layer, a side surface of the first bonding structure constituting the first bonding surface. The removing the partial thickness of the chip at the edge region of the first bonding surface corresponds to removing at least part of the thickness of the first dielectric layer at the edge region of the first bonding surface. Alternatively, the removing the partial thickness of the chip at the edge region of the first bonding surface corresponds to removing the entire thickness of the first dielectric layer and at least part of the thickness of the first redistribution layer at the edge region of the first bonding surface, and the removal region being located outside the first metal wiring region. Alternatively, the removing the partial thickness of the chip at the edge region of the first bonding surface corresponds to removing the entire thickness of the first dielectric layer and the first redistribution layer at the edge region of the first bonding surface, and part of the thickness of the first semiconductor substrate, and the removal region being located outside the first metal wiring region and the first device structure.

[0010] In some alternative embodiments, the process of removing a portion of the thickness of the chip at the edge region of the first bonding surface comprises one of plasma etching and wet etching.

[0011] In a second aspect, the present application provides a bonded structure comprising a chip and a target wafer bonded together, the chip having a boss and an annular notch surrounding the boss on a side facing the target wafer.

[0012] In some alternative embodiments, the sidewall of the boss smoothly transitions in a direction from the target wafer to the chip.

[0013] In some alternative embodiments, adjacent sidewalls of the boss smoothly transition.

[0014] In some alternative embodiments, the boss gradually increases in size in a direction perpendicular to the thickness of the chip in a direction from the target wafer to the chip.

[0015] In some alternative embodiments, the annular notch has a depth of 0.5-1 μm; and / or, the annular notch has a ring width of 1-5 μm.

[0016] In some alternative embodiments, the boss is composed of multiple levels of sub-bosses connected in sequence in a direction from the target wafer to the chip, and a front level of sub-bosses has a footprint on the target wafer within a footprint of a rear level of sub-bosses on the target wafer. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the description of the embodiments or the prior art. Obviously, the drawings described below are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0018] Figure 1 is a process flow chart of the bonding method of the embodiment of the present application.

[0019] Figure 2 is a structure schematic diagram of the temporary bonding of the wafer to be scribed and the carrier wafer of the embodiment of the present application.

[0020] Figure 3 is a schematic diagram of scribing the wafer to be scribed of the embodiment of the present application.

[0021] Figure 4 is a schematic diagram of removing a portion of the thickness of the chip at the edge region of the embodiment of the present application.

[0022] Figure 5 is a schematic diagram of the embodiment of the present application for debonding a chip from a carrier wafer.

[0023] Figure 6 is a schematic diagram of the embodiment of the present application for bonding a chip to a target wafer.

[0024] Figure 7 is a schematic diagram of the structure of a chip of the embodiment of the present application.

[0025] Figure 8 is a top view of a chip of the embodiment of the present application.

[0026] Figure 9 is a top view of another chip of the embodiment of the present application.

[0027] Figure 10 is a schematic diagram of the structure of another chip of the embodiment of the present application.

[0028] BRIEF DESCRIPTION OF DRAWINGS 1 - wafer to be diced; 11 - chip; 111 - boss; 112 - annular notch; 113 - sub-boss; 2 - target wafer; 3 - carrier wafer. DETAILED DESCRIPTION

[0029] The technical solutions of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0031] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used in this specification, specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0032] Embodiments of the application are described herein with reference to the drawings, which are idealized representations of the illustrative embodiments (and intermediate structures) of the application, as can be expected to vary, e.g., due to manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result from, e.g., manufacturing. The regions illustrated in the figures are schematic and many of the regions are not drawn to scale. The same reference numerals in different figures are intended to represent the same, similar or equivalent components.

[0033] As background, the current dicing method is prone to cause chip edge defects, such as sawtooth structure or rounded corner structure. The semiconductor material and dielectric material in the wafer to be diced are both high-brittle materials, which are prone to brittle fracture to form debris during the cutting process. The sawtooth structure is also prone to brittle fracture to form debris when the chip obtained by cutting receives mechanical stress or thermal stress. The larger specific surface area of the sawtooth structure or the rounded corner structure is prone to adhere to debris and other contaminants from the environment, and the jagged irregular edge is also prone to retain the above contaminants, so that it is difficult to completely remove the contaminants on the surface of the chip even after cleaning. That is, the above chip edge defects introduce contaminants on the surface of the chip, and the presence of the above contaminants hinders the close adhesion of the bonding interface, generates more voids on the bonding surface, and adversely affects the bonding strength.

[0034] The sawtooth structure of the chip edge can scratch the surface of the first dielectric layer of the target wafer during the bonding process, causing microcracks or scratches on the first dielectric layer, thereby generating voids on the bonding surface after the bonding is completed, affecting the bonding strength. The thermal stress generated by the bonding structure formed by bonding or the mechanical stress received by the bonding structure will first act on the sawtooth structure of the chip edge, thereby initiating microcracks, and under the long-term action of thermal stress or mechanical stress, the bonding surface has the risk of cracking.

[0035] Based on this, referring to Figure 1 , in a first aspect, the application provides a bonding method, comprising: Step S1, referring to Figure 3 , a chip 11 is obtained by dicing the wafer to be diced 1, and the chip 11 has a first bonding surface; Step S2, referring to Figure 4 , a portion of the thickness of the chip 11 located in the edge region of the first bonding surface is removed to form a boss 111 and an annular gap 112 surrounding the boss 111; Step S3, referring to Figure 6 , the target wafer 2 has a second bonding surface, and after the boss 111 is formed, the first bonding surface of the chip 11 is bonded to the second bonding surface of the target wafer 2.

[0036] The first bonding surface of the chip 11 is patterned after dicing to remove the edge defects of the chip 11, avoid the adverse effects of the edge defects of the chip 11 on the bonding strength, improve the bonding strength between the chip 11 and the target wafer 2, and thus improve the long-term reliability of the bonding structure and the three-dimensional packaging structure containing the bonding structure.

[0037] The bonding method of the chip 11 and the target wafer 2 can be hybrid bonding.

[0038] The bonding method provided by the application is described in detail below.

[0039] Step S10, providing a wafer 1 to be diced and a target wafer 2.

[0040] The wafer 1 to be diced can be divided into a plurality of chips 11, and the chip 11 includes a first semiconductor substrate, a first redistribution layer and a first bonding structure arranged in sequence. The first semiconductor substrate has a first device structure therein; the first redistribution layer is located on one side surface of the first semiconductor substrate, and the first redistribution layer has a first metal wiring area. The first redistribution layer is composed of a third dielectric layer and a first metal wiring located in the third dielectric layer. The first metal wiring is located in the first metal wiring area, and there is a certain distance between the first metal wiring area and the sidewall of the chip 11. The first metal wiring area and the sidewall of the chip 11 are filled with dielectric material. The first bonding structure is located on the side surface of the first redistribution layer away from the first semiconductor substrate. The first bonding structure is composed of a first dielectric layer and a first pad penetrating through the first dielectric layer. One side surface of the first bonding structure constitutes a first bonding surface. The first bonding surface includes a first metal bonding area and a first dielectric bonding area adjacent to the first metal bonding area. The first metal wiring and the first pad are electrically connected. The first metal wiring can also be electrically connected to the first device structure.

[0041] The first semiconductor substrate can also contain a first through silicon via (TSV) as a vertical conductive channel. The first through silicon via can be electrically connected to the first device structure and can also be electrically connected to the first metal wiring.

[0042] The material of the first dielectric layer includes but is not limited to silicon dioxide, and the material of the first pad is metal, such as one or more of copper, aluminum, gold, etc. The first device structure can be a storage device, a logic operation device, a power device, a photoelectric sensor device, etc.

[0043] The target wafer 2 comprises a second semiconductor substrate, a second redistribution layer and a second structure to be bonded which are sequentially stacked. The second redistribution layer is located on one side surface of the second semiconductor substrate, and the second redistribution layer is composed of a fourth dielectric layer and a second metal wiring in the fourth dielectric layer. The second structure to be bonded is located on the side surface of the second redistribution layer away from the second semiconductor substrate, and the second structure to be bonded is composed of a second dielectric layer and a second pad penetrating through the second dielectric layer. One side surface of the second structure to be bonded forms a second bonding surface, and the second bonding surface comprises a second metal bonding area and a second dielectric bonding area adjacent to the second metal bonding area. The second metal wiring and the second pad are electrically connected.

[0044] The second semiconductor substrate can have a second device structure therein, and the second device structure can be electrically connected with the second metal wiring. The second semiconductor substrate can also contain a second through-silicon via (TSV) which is a vertical conductive channel, and the second TSV can be electrically connected with the second device structure and the second metal wiring.

[0045] The material of the second dielectric layer includes but is not limited to silicon dioxide, and the material of the second pad is metal such as one or more of copper, aluminum, gold, etc. The second device structure can be a storage device, a logic operation device, a power device, a photoelectric sensor device, etc.

[0046] In step S20, the first bonding surface of the wafer to be scribed 1 and the second bonding surface of the target wafer 2 are polished.

[0047] For example, the chemical mechanical polishing (CMP) process can be used to polish the bonding surface, so that the surface roughness of the dielectric layer is less than 0.5 nm, and the surface roughness of the pad is less than 1 nm. Preferably, the pad is slightly recessed relative to the dielectric layer, and the maximum depth of the recess is less than 15 nm. After the chemical mechanical polishing is completed, the bonding surface is cleaned alternately with organic acid and deionized water to remove polishing residues and impurities, and then dried.

[0048] In step S30, referring to Figure 2 The wafer to be scribed 1 has a temporary bonding surface opposite to the first bonding surface, and the temporary bonding surface of the wafer to be scribed 1 is temporarily bonded to the carrier 3.

[0049] The carrier 3 includes but is not limited to glass, silicon wafer or ceramic wafer, and preferably glass.

[0050] In some optional embodiments, the wafer to be scribed 1 and the carrier 3 can be bonded together by using a temporary bonding glue. The temporary bonding glue includes a thermal stripping type bonding glue, a light stripping type bonding glue, a chemical stripping type bonding glue, etc.

[0051] In other alternative embodiments, temporary bonding between the diced wafer 1 and the carrier 3 can be achieved using physical forces (such as van der Waals forces or electrostatic forces). This bonding method is suitable for temporary bonding surfaces with low roughness. For example, the temporary bonding surfaces of the diced wafer 1 and the carrier 3 can be plasma-treated to improve surface hydrophilicity, and then the temporary bonding surfaces of the diced wafer 1 and the carrier 3 can be bonded together, with temporary bonding achieved by van der Waals forces.

[0052] Step S40, see Figure 3 The wafer 1 to be diced is diced to obtain chip 11.

[0053] A blade or laser can be used to dicing the wafer 1 to be diced into multiple chips 11.

[0054] Step S50, see Figure 4 A portion of the thickness of the chip 11 located in the edge region of the first bonding surface is removed to form a boss 111 and an annular notch 112 surrounding the boss 111.

[0055] In some optional implementations, removing a portion of the thickness of the chip 11 located in the edge region of the first bonding surface may include: Step S51: A first mask is formed on the surface of the chip 11. The first mask exposes the edge region of the first bonding surface and covers the middle region of the first bonding surface and the side of the chip 11. The material of the first mask can be photoresist, silicon dioxide or silicon nitride. Step S52: Perform a first etching on the first bonding surface based on the first mask; Step S53: Remove the first mask.

[0056] In some alternative embodiments, steps S51-S53 are repeated to obtain the protrusion 111. Specifically, the first protrusion is obtained by first etching the first bonding surface based on the first mask; removing part of the thickness of the chip 11 located in the edge region of the first bonding surface further includes: forming an nth mask on the surface of the chip 11, the nth mask exposing the edge region of the first bonding surface located in the (n-1)th protrusion, the nth mask covering the central region of the first bonding surface and the side of the chip 11, the side of the (n-1)th protrusion belonging to the side of the chip 11; and performing an nth etching on the first bonding surface based on the nth mask. Etching removes part of the thickness of the edge region of the (n-1)th protrusion to obtain the nth protrusion, where n is an integer greater than or equal to 2; removing the nth mask; after the Nth etching, the Nth protrusion is obtained, where N is an integer greater than or equal to 2 and n is less than or equal to N. The residual structures of the first protrusion to the (N-1)th protrusion and the Nth protrusion constitute the protrusion 111 having multiple levels of sub-protrusions 113. The multiple levels of sub-protrusions 113 are connected sequentially along the thickness direction of the chip 11, and the annular notch 112 is formed by the sequential connection of the annular sub-notches surrounding each level of sub-protrusion.

[0057] The width of the removal area at the edge of the chip 11 is related to the type of functional layer to be removed. The smaller the width of the removal area, the higher the precision requirement for etching. Therefore, before etching, it is necessary to determine the type of functional layer to be removed and the width of the area to be removed based on the specific chip 11 structure, and select the etching process and specific etching steps.

[0058] Case 1: The partial thickness of the chip 11 removed from the edge region of the first bonding surface corresponds to at least a portion of the thickness of the first dielectric layer removed from the edge region of the first bonding surface. That is, when the functional layer removed is only a partial or full thickness of the first dielectric layer, the width of the removal area can be slightly larger, and the width requirement of the removal area is low. As long as the removal area is located outside the first pad to avoid the first pad being exposed after etching is completed.

[0059] Case 2: The removal of a portion of the thickness of the chip 11 located in the edge region of the first bonding surface corresponds to the removal of the entire thickness of the first dielectric layer and at least a portion of the thickness of the first redistribution layer in the edge region of the first bonding surface. The removal area is located outside the first metal wiring area. That is, when the removed functional layer is the first dielectric layer and the first redistribution layer with a partial or full thickness, the width of the removal area needs to be reduced. The width requirement of the removal area is slightly higher. The removal area needs to be located not only outside the first pad but also outside the first metal wiring area to avoid the first pad and the first metal wiring being exposed after etching.

[0060] Case 3: The removal of a portion of the chip 11 thickness located in the edge region of the first bonding surface corresponds to: removing the entire thickness of the first dielectric layer and the first redistribution layer in the edge region of the first bonding surface, as well as a portion of the thickness of the first semiconductor substrate. The removal area is located outside the first metal wiring area and the first device structure. That is, when the removed functional layers are the first dielectric layer, the first redistribution layer, and a portion of the thickness of the first semiconductor substrate, the width of the removal area needs to be further reduced, and the width requirement needs to be slightly increased. The removal area not only needs to be located outside the first pad and the first metal wiring area, but also outside the first device structure, to avoid exposing the first pad, the first metal wiring, and the first device structure after etching. When the first semiconductor substrate also contains a first through-silicon via (TSV), the removal area also needs to be located outside the TSV to avoid exposing the metal material in the TSV after etching.

[0061] One or more of the metal materials in the first pad, the first metal wiring, the first device structure, and the first through-silicon via are exposed, which not only makes them prone to oxidation and affects their conductivity, but may also cause wear or detachment, which is detrimental to the structural stability of the chip 11.

[0062] In some optional embodiments, the depth d of the annular notch 112 can be 0.5μm-1μm, such as 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1μm, or any range of the above values; the annular width w of the annular notch 112 can be 1μm-5μm, such as 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, or any range of the above values. The annular width refers to the maximum size of the annular notch 112 in the direction perpendicular to the thickness of the chip 11.

[0063] If the depth and / or width of the annular notch 112 are too small, edge defects of the chip 11 may not be effectively removed. If the depth and / or width of the annular notch 112 are too large, not only will the area of ​​the first bonding surface of the chip 11 after etching be small, resulting in a smaller bonding surface area between the chip 11 and the target wafer, thus reducing the bonding strength, but it may also expose one or more of the metal materials in the first device structure, the first pad, the first metal wiring, and the first through-silicon via. Although increasing the size of the chip 11 can avoid the adverse effects of an excessively large depth and / or width of the annular notch 112, this approach is not conducive to the miniaturization of the bonding structure and the three-dimensional packaging structure containing the bonding structure. By limiting the width and depth of the annular notch 112 to the above range, not only can edge defects of the chip 11 be effectively removed, effectively avoiding the adverse effects of edge defects of the chip 11 on the bonding strength, but the first bonding surface of the chip 11 can also have a larger area, thereby effectively improving the bonding strength between the chip 11 and the target wafer, and the process is easy to implement.

[0064] In some alternative implementations, the process of removing a portion of the thickness of the chip 11 located in the edge region of the first bonding surface includes, but is not limited to, one of plasma etching and wet etching.

[0065] In some alternative implementations, after etching is completed, the morphology of the chip 11 edge can be inspected using SEM (scanning electron microscope) to ensure that edge defects of the chip 11 are completely removed, while the integrity of the first pad is inspected, and the etching process is controlled accordingly.

[0066] Step S60, see Figure 5 The chip 11 is debonded to the carrier 3 to obtain multiple independent chips 11.

[0067] The debonding method is determined by the temporary bonding method between the diced wafer 1 and the carrier 3. If the diced wafer 1 and the carrier 3 are bonded using thermally release adhesive, debonding is achieved by heating to reduce the adhesive's stickiness. If the diced wafer 1 and the carrier 3 are bonded using light-release adhesive, debonding is achieved by irradiating the adhesive to destroy its molecular structure. If the diced wafer 1 and the carrier 3 are bonded using chemically release adhesive, debonding is achieved using a specific solvent that dissolves the adhesive. If the diced wafer 1 and the carrier 3 are temporarily bonded using van der Waals forces, debonding is achieved using mechanical force. When temporary bonding is used, after separating the chip 11 from the carrier 3, the chip 11 needs to be thoroughly cleaned to prevent residual temporary bonding adhesive from contaminating the first bonding surface.

[0068] After debonding, qualified chips can be sorted out to prevent defective chips from participating in subsequent bonding steps.

[0069] Step S70: Perform surface activation treatment on the first bonding surface of chip 11 and the second bonding surface of target wafer 2.

[0070] Surface activation is achieved by plasma activation of the first bonding surface of chip 11 and the second bonding surface of target wafer 2, with nitrogen or oxygen atmosphere used for plasma activation. After surface activation, chip 11 and target wafer 2 need to be cleaned to remove byproducts and residual contaminants generated during activation, so as to avoid affecting the bonding strength between chip 11 and target wafer 2.

[0071] Step S80: Align the chip 11 with the target wafer 2.

[0072] The first bonding surface of chip 11 and the second bonding surface of target wafer 2 are set opposite to each other, and the first dielectric layer of chip 11 and the second dielectric layer of target wafer 2, as well as the first pad of chip 11 and the pad of target wafer 2, are precisely aligned by an optical alignment system, with the alignment error controlled at the nanometer level.

[0073] Step S90, see Figure 6 The chip 11 is pre-bonded to the target wafer 2.

[0074] At room temperature (25℃±5℃), a pressure of 1N-10N is applied to the aligned chip 11 and the target wafer 2, so that the first dielectric layer and the second dielectric layer form an initial bond through intermolecular forces, and the relative positions of the chip 11 and the target wafer 2 are initially fixed.

[0075] Step S100: Perform heat treatment on the pre-bonded bonding structure.

[0076] The pre-bonded bonding structure undergoes high-temperature annealing at 250℃-350℃ for 2-4 hours. Since the thermal expansion coefficient of the pads is greater than that of the dielectric layer, during annealing, both the first pad in chip 11 and the second pad in target wafer 2 undergo volume expansion, resulting in close contact and atomic interdiffusion, forming strong metallic bonds. The first and second dielectric layers further react during annealing to form stable covalent bonds, significantly enhancing the bonding strength. After bonding, target wafer 2 and chip 11 form a bonded structure, with the first and second pads directly interconnected to enable power and signal transmission between chip 11 and target wafer 2.

[0077] Secondly, refer to Figure 7This invention provides a bonding structure comprising a chip 11 and a target wafer 2 bonded together. The chip 11 has a boss 111 on the side facing the target wafer 2 and an annular notch 112 surrounding the boss 111. This bonding structure can be prepared by the bonding method provided in the first aspect. Therefore, the technical features in the first aspect (such as structure, material, size, etc.) are all applicable to the bonding structure of the second aspect, and will not be repeated here.

[0078] In some alternative implementations, the sidewalls of the boss 111 may have a smooth transition in the direction from the target wafer 2 to the chip 11.

[0079] Figures 8-9 This is a top view of the chip. (Reference) Figures 8-9 In some optional embodiments, in the direction from the target wafer 2 to the chip 11, the size of the boss 111 in the direction perpendicular to the thickness of the chip 11 can gradually increase, that is, the lateral size of the boss 111 gradually increases. This structure makes it less likely for debris and other contaminants to be hidden on the sidewall of the boss 111, and the contaminants can be easily removed by cleaning.

[0080] refer to Figure 10 In some optional embodiments, in the direction from the target wafer 2 to the chip 11, the protrusion 111 is composed of a series of sub-protrusions 113 connected in sequence, and the orthographic projection of the previous sub-protrusion 113 on the target wafer 2 is located within the orthographic projection of the subsequent sub-protrusion 113 on the target wafer 2, that is, the lateral dimension of the previous sub-protrusion 113 is smaller than the lateral dimension of the subsequent sub-protrusion 113.

[0081] refer to Figure 9 In some alternative embodiments, the adjacent sidewalls of the boss 111 can be smoothly transitioned, which can reduce the risk of stress concentration on the sidewalls of the boss 111 and improve the structural stability of the chip 11 and even the bonding structure.

[0082] Unless otherwise specified herein, there is no strict order in which these steps are performed; they may be performed in any other order. Moreover, these steps or stages are not necessarily to be completed at the same time, but may be performed at different times, and the order of execution of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of steps or stages within other steps.

[0083] In the description of this specification, references to terms such as "some embodiments," "optional implementations," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0084] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A bonding method, characterized in that, include: A chip is obtained by dicing a wafer to be diced, and the chip has a first bonding surface; Remove a portion of the chip thickness located in the edge region of the first bonding surface to form a boss and an annular notch surrounding the boss; The target wafer has a second bonding surface. After the protrusion is formed, the first bonding surface of the chip is bonded to the second bonding surface of the target wafer.

2. The bonding method according to claim 1, characterized in that, Removing a portion of the chip thickness from the edge region of the first bonding surface includes: A first mask is formed on the chip surface, the first mask exposing the edge region of the first surface to be bonded; The first bonding surface is etched based on the first mask; Remove the first mask.

3. The bonding method according to claim 2, characterized in that, The first protrusion is obtained by first etching the first bonding surface based on the first mask; The process of removing a portion of the chip thickness located in the edge region of the first bonding surface further includes: An nth mask is formed on the chip surface, and the nth mask exposes the edge region of the first bonding surface located at the (n-1)th protrusion; Based on the nth mask, the first bonding surface is etched n times to remove part of the thickness of the edge region of the (n-1)th protrusion to obtain the nth protrusion, where n is an integer greater than or equal to 2; Remove the nth mask; After the Nth etching, the Nth boss is obtained, where N is an integer greater than or equal to 2 and n is less than or equal to N. The residual structures of the first boss to the (N-1)th boss and the Nth boss constitute the boss with multiple levels of sub-bodies.

4. The bonding method according to any one of claims 1 to 3, characterized in that, The chip includes: A first semiconductor substrate, wherein the first semiconductor substrate has a first device structure; A first redistribution layer is located on one side surface of the first semiconductor substrate, and the first redistribution layer has a first metal wiring region; A first bonding structure located on the side surface of the first redistribution layer opposite to the first semiconductor substrate, the first bonding structure being composed of a first dielectric layer and a first pad penetrating the first dielectric layer, and one side surface of the first bonding structure constituting the first bonding surface; The removal of a portion of the chip thickness located in the edge region of the first bonding surface corresponds to: removing at least a portion of the thickness of the first dielectric layer in the edge region of the first bonding surface; Alternatively, the removal of a portion of the chip thickness located in the edge region of the first bonding surface corresponds to: the removal of the entire thickness of the first dielectric layer and at least a portion of the thickness of the first redistribution layer in the edge region of the first bonding surface, and the removal area is located outside the first metal wiring area; Alternatively, the removal of a portion of the chip thickness located in the edge region of the first bonding surface corresponds to: the removal of the entire thickness of the first dielectric layer and the first redistribution layer in the edge region of the first bonding surface, and a portion of the thickness of the first semiconductor substrate, and the removal area is located outside the first metal wiring area and the first device structure.

5. The bonding method according to any one of claims 1 to 3, characterized in that, The process for removing a portion of the chip thickness located in the edge region of the first bonding surface includes one of plasma etching and wet etching.

6. A bonding structure, characterized in that, It includes a chip and a target wafer bonded together, wherein the chip has a boss on the side facing the target wafer and an annular notch surrounding the boss.

7. The bonding structure according to claim 6, characterized in that, In the direction from the target wafer to the chip, the sidewalls of the boss have a smooth transition; and / or, The adjacent sidewalls of the boss transition smoothly.

8. The bonding structure according to claim 7, characterized in that, In the direction from the target wafer to the chip, the size of the boss gradually increases in the direction perpendicular to the thickness of the chip.

9. The bonding structure according to any one of claims 6 to 8, characterized in that, The depth of the annular notch is 0.5μm-1μm; and / or the width of the annular notch is 1μm-5μm.

10. The bonding structure according to any one of claims 6 to 8, characterized in that, In the direction from the target wafer to the chip, the protrusion is composed of a series of connected sub-protrusions, and the orthographic projection of the previous sub-protrusion on the target wafer is located within the orthographic projection of the subsequent sub-protrusion on the target wafer.

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