POWER MONITORING AND LIMITING OF PROCESSING UNITS (PU) IN A PROCESSOR-BASED SYSTEM TO LIMIT Overall POWER CONSUMPTION OF A PROCESSOR

Abstract

Processing units in a processor-based system are power monitored and limited to limit overall power consumption of the processor-based system. In an exemplary aspect, to limit overall power consumption of a processor-based system while attempting to achieve optimal performance for all processing units, an overall power limit budget ("processing unit power limit budget") is allocated for processing units. The processor-based system is configured to dynamically determine a total processing unit power limit budget available to the processing units based on remaining available overall power not consumed by other power consuming circuitry. A processor-based system is configured to allocate a total processing unit power limit budget for processing units, which is then allocated to different processing units based on differences in workloads of the different processing units to attempt to achieve optimal performance of the processing units, and meanwhile, the processor-based system is kept within the overall power consumption limit.

Description

[0001] Priority Application

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 463,557, filed September 8, 2023, entitled “POWER MONITORING AND LIMITING OF PROCESSING UNITS (PUs) IN A PROCESSOR-BASED SYSTEM TO LIMIT OVERALL POWER CONSUMPTION OF THE PROCESSOR-BASED SYSTEM,” which is incorporated by reference herein in its entirety. BACKGROUND

[0003] I. TECHNICAL FIELD

[0004] The field of the disclosure relates to a processor-based system including one or more processing units (e.g., central processing units (CPUs), graphics processing units (GPUs), and / or neural processing units (NPUs)), and more specifically to power distribution of the processing units in the processor-based system.

[0005] II. BACKGROUND

[0006] Conventionally, a processor-based system includes a power management system that controls the supply of power to power rails that power circuits for their operation. The processor-based system can also include multiple power rails each having a separately settable voltage level such that different voltage levels can be supplied in the system. Some circuits can require lower voltage levels than others in order to operate. Further, it can be desirable to provide a circuit (e.g., a processor) whose power rail or domain is different from other circuits (e.g., memory circuits) having a minimum voltage level whose power can collapse during idle time. Further, the processor-based system can include a frequency and voltage scaling system configured to dynamically change or scale the frequency of a clock circuit and / or its voltage level in order to operate. The higher the frequency, the faster the speed of operation of the clock circuit. However, higher voltage levels can be required to support higher frequency operation. Further, higher frequency and voltage operation can result in increased power consumption. Other devices in the processor-based system can not need to scale in performance.

[0007] Circuits in a processor-based device generate heat due to energy loss from the power supply operation of the circuits. Processor-based systems can have thermal and temperature limits on operation. The thermal limit can be based on circuit performance criteria (e.g., the circuit will have a thermal limit where performance begins to degrade), to extend battery life and / or to maintain temperature within a "skin limit" range. For example, the processor-based device can be a wearable device, or can be other devices (e.g., a laptop computer) that are intended or designed to be in contact with a user's skin. Ambient temperature also affects the temperature of the processor-based device. SUMMARY

[0008] Aspects disclosed herein include power monitoring and limiting of PUs in a processor-based system to limit the overall power consumption of the processor-based system. Related methods of power monitoring and limiting of PUs in the processor-based system are also disclosed. Workloads performed by the PUs in the processor-based system can vary significantly over time, such that their power consumption will also vary. This causes the overall power consumption of the processor-based system to vary. However, limiting the power of individual PUs can degrade their performance in non-desirable ways, or the PUs can not be able to perform workloads that cause them to consume power up to the power limit. Therefore, in exemplary aspects, to limit the overall power consumption of the processor-based system while attempting to still achieve optimal performance of all PUs in the processor-based system, an overall power limit budget ("PU power limit budget") is allocated for the PUs. In this regard, in exemplary aspects, the processor-based system is configured to dynamically determine a total PU power limit budget available for the PUs that can be kept available from unused power of other power consuming circuits (e.g., non-PU devices) of the processor-based system to be within an overall power consumption limit. The processor-based system is configured to allocate an overall or total PU power limit budget for the PUs in the processor-based system, which is then allocated to different PUs based on workload differences of the different PUs to attempt to achieve optimal performance of the PUs while keeping the processor-based system within its overall power consumption limit.

[0009] The overall power consumption of the processor-based system can be related to the heat generated due to expected energy loss, which can then be related to the thermal limit of the processor-based system. Thus, by monitoring and limiting the overall power consumption of the processor-based system and its PUs, the temperature of the processor-based system can be limited to balance the overall average power consumption of different systems in the processor-based system while remaining within the thermal limit of the processor-based system while achieving optimal performance of the PUs. Limiting the power consumption in the processor-based system can also achieve desired overall workload performance in a sustainable manner, as heat and temperature can reduce workload performance. Limiting the power consumption in the processor-based system can also extend battery life, as temperature can negatively impact battery performance and power supply capabilities. Limiting the power consumption in the processor-based system can also limit the temperature of the processor-based device to avoid hotspots that can otherwise occur due to heat generated from energy loss from causing harm to a user's skin. For example, the processor-based system can be a wearable device, or can be other devices such as a laptop or an extended reality (XR) device that are expected to be in contact with a user's skin.

[0010] In other example aspects, the processor-based system includes multiple PUs that perform workloads and thus consume power. As an example, such multiple PUs can include central PUs (CPUs), graphics PUs (GPUs), and / or neural signal processors (NSPs). In example aspects, to monitor and limit the overall power consumption of the processor-based system, the processor-based system includes a power limiter circuit configured to set a power budget ("power limit budget") for the PUs to operate and perform workloads and provide power consumption limits for the PUs. In one example, the power limit for the PUs ("PU power limit budget") is based on subtracting the power consumption of other circuits and systems in the processor-based system (e.g., power management circuits, network interface circuits, battery charging circuits, etc.) outside of the PUs from the overall power consumption limit of the processor-based system. The power limiter circuit then uses the remaining power limit to determine a total processing power limit budget, which is then allocated as individual power limit budgets for the different PUs to operate. The PU power limit budgets allocated to different PUs can be based on the workloads being performed by the PUs. This allows the total PU power limit budget to be allocated to different PUs based on the relative workload power demands of the different PUs to attempt to achieve optimal performance while keeping the total PU power consumption within the remaining PU power limit budget to maintain the overall power consumption limit of the processor-based system. For example, performance monitoring circuits can be associated with the different PUs to provide workload information to the power limiter circuit. The power limiter circuit can then allocate (e.g., proportionally) the PU power limit budget to the different PUs.

[0011] In other example aspects, while the PUs are operating to execute their workloads in the processor-based system, the power limiter circuit is further configured to determine whether a given PU is consuming less power than its allocated power limit budget. If so, the power limiter circuit can be configured to adjust the PU power limit budget and reallocate it to a different PU for operation. In this way, other PUs can enjoy an increase in their respective power limit budgets if needed so as to enhance performance. Additionally, while the PUs are operating to execute their workloads in the processor-based system, in another example, the power limiter circuit is further configured to determine whether a given PU is consuming more power than its allocated power limit budget. If so, this means that such a PU can be executing a workload that causes the PU to consume more power than the power limit budget allocated to such a PU. In this scenario, in one example, the processor-based system can be configured to cause the performance of the PU to be reduced or regulated (e.g., by causing a clock frequency, throughput, and / or instructions processed per unit of time (e.g., through pipeline stalling) to be reduced) such that the PU reduces its performance and thus reduces power consumption close to or below the power limit budget allocated to such a PU. In one example, the processor-based system can be configured to generate a signal to a separate performance regulation system in the processor-based system that is configured to regulate the performance of the PU (e.g., a dynamic voltage frequency scaling (DVFS) circuit).

[0012] In another example, when the power limiter circuit allocates or reallocates the total PU power limit budget to the PUs, the power limiter circuit can also be configured to request an operating state change (e.g., a change in clock frequency and / or voltage) for the PUs. For example, if the power limit budget allocated to a PU has increased, the operating state for such a PU can also need to be increased (e.g., increase clock frequency and / or voltage) to cause such a PU to operate at an increased performance level to allow power consumption to the increased power limit budget allocated to the PU. As another example, if the power limit budget allocated to a PU has decreased, the operating state for such a PU can need to be decreased (e.g., decrease clock frequency and / or voltage) to cause such a PU to operate more efficiently at a reduced performance level that will reduce its power consumption and / or maintain its power consumption within its allocated power limit budget.

[0013] The power limiter circuit can execute a state machine or other process that continuously monitors and allocates the power limit budget to the PUs in the processor-based system. In this regard, the power limiter circuit can continuously determine a total PU power limit budget based on subtracting power consumption of external circuits from the overall power limit of the processor-based system. The power limiter circuit can continuously allocate a power limit budget to each of the PUs based on the remaining total PU power limit budget from the overall power consumption limit of the processor-based system and workload information of the PUs. The power limiter circuit can then continuously monitor power consumption of the PUs to determine whether any of the PUs is consuming power under its respective allocated power limit budget, and if so, adjust the total PU power limit budget and reallocate the total PU power limit budget to the PUs to prevent additional power needed for performance by other PUs. The power limiter circuit can also continuously monitor power consumption of the PUs to determine whether the PUs are consuming more power than their allocated power limit budget, and if so, adjust and reallocate the total PU power limit budget to possibly be able to allocate additional power to the PUs beyond their power limit budget. In this way, the power limiter circuit is constantly optimizing the allocation of power limit budgets to the PUs to achieve optimization of the overall combined performance of all the PUs in the processor-based system, and based on their individual workload demands, while still limiting the overall power consumption of the processor-based system.

[0014] In this regard, in one example aspect, a power limiter circuit for limiting power consumption of a plurality of PUs in a processor-based system is provided. The power limiter circuit is configured to: (a) determine a total PU power limit budget based on a difference between an overall power limit for the processor-based system and power usage in the processor-based system. The power limiter circuit is further configured to: (b) receive a plurality of workload data indicative of workload activity of each of the plurality of PUs. The power limiter circuit is further configured to: (c) allocate a power limit budget to each of the PUs from the total PU power limit budget based on workload data of the plurality of workload data corresponding to each of the PUs. The power limiter circuit is further configured to: (d) cause power consumption of each of the PUs to be constrained within the allocated power limit budget determined for the PUs. The power limiter circuit is further configured to: (e) determine a difference between actual power consumption of each of the PUs and the power limit budget for each of the PUs. The power limiter circuit is further configured to: (f) reallocate a new power limit budget to each of the PUs from the total PU power limit budget based on the determined difference between the actual power consumption of each of the PUs and the power limit budget for each of the PUs.

[0015] In another example aspect, a method of limiting power consumption of a plurality of PUs in a processor-based system is provided. The method (a) determines a total PU power limit budget based on a difference between an overall power limit for the processor-based system and power usage in the processor-based system. The method also includes (b) receiving a plurality of workload data indicative of workload activity of each PU of the plurality of PUs. The method also includes (c) allocating a power limit budget from the total PU power limit budget for each PU based on workload data of the plurality of workload data corresponding to each PU of the plurality of PUs. The method also includes (d) causing power consumption of each PU of the plurality of PUs to be constrained within the allocated power limit budget determined for the PU. The method also includes (e) determining a difference between actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU. The method also includes (f) reallocating a new power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the determined difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU.

[0016] In another example aspect, a processor-based system is provided. The processor-based system includes a plurality of non-PU power consumption devices. The processor-based system also includes a plurality of PUs. The processor-based system also includes a plurality of PU performance monitoring circuits, each PU performance monitoring circuit configured to: monitor workload activity of a PU of the plurality of PUs; and generate workload data corresponding to the monitored workload activity of the PU of the plurality of PUs. The processor-based system also includes a plurality of power monitoring circuits, each power monitoring circuit configured to monitor actual power consumption of a PU of the plurality of PUs. The processor-based system also includes a plurality of power constraint circuits, each power constraint circuit configured to constrain power consumption of a PU of the plurality of PUs. The processor-based system also includes a power limiter circuit. The power limiter circuit is configured to: (a) determine a total PU power limit budget based on a difference between an overall power limit for the processor-based system and power usage of the plurality of non-PU power consumption devices. The power limiter circuit is also configured to: (b) allocate a power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the workload data corresponding to each PU of the plurality of PUs. The power limiter circuit is also configured to: (c) instruct each power constraint circuit of the plurality of power constraint circuits to constrain the power consumption of a PU of the plurality of PUs within the allocated power limit budget for the PU. The power limiter circuit is also configured to: (d) determine a difference between the actual power consumption of each PU of the plurality of PUs from the plurality of power monitoring circuits and the power limit budget for each PU. The power limiter circuit is also configured to: (e) reallocate a new power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the determined difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a block diagram of an example processor-based system that includes power consumption circuits and processing units (PUs) and also includes a power limit (PL) circuit that is configured to determine a total PU power limit budget available to the PUs based on a remaining power available to maintain the processor-based system within its overall power consumption limit and to allocate a total PU power limit budget to the PUs to control power consumption of the PUs based on workloads being performed by the PUs;

[0018] Figure 2is a block diagram of an example processor-based system and power limiter circuit that illustrates example components associated with determining a total PU power limit budget available to a PU based on a remaining power available to maintain the processor-based system within its overall power consumption limit and allocating and reallocating the determined total PU power limit budget available to the PU based on a workload of the PU being executed by the PU;

[0019] Figure 3 is a flowchart of an example process of a power limiter circuit in Figure 1 and Figure 2 determining a total PU power limit budget available to a PU based on a remaining power available to maintain the processor-based system within its overall power consumption limit and allocate and reallocate the total PU power limit budget to the PU to control power consumption of the PU based on a workload of the PU being executed by the PU;

[0020] Figure 4 is a power consumption graph illustrating an example time-based allocation and reallocation of a determined total PU power limit budget to a PU in a processor-based system in Figure 1 and Figure 2 while maintaining the processor-based system within its overall power consumption limit based on a workload of the PU being executed by the PU;

[0021] Figure 5 is a flowchart of another example process of a power limiter circuit in Figure 1 and Figure 2 determining a total PU power limit budget available to a PU based on a remaining power available to maintain the processor-based system within its overall power consumption limit and allocate and reallocate the total PU power limit budget to the PU to control power consumption of the PU based on a workload of the PU being executed by the PU;

[0022] Figure 6 is an example state machine diagram illustrating a power limiter circuit determining a total PU power limit budget available to a PU based on a remaining power available and allocating the total PU power limit budget to the PU to control power consumption of the PU according to an active state of the processor-based system;

[0023] Figure 7 is a block diagram of an example thermal management system that can be provided in a processor-based system in Figure 1 and Figure 2 to monitor temperatures in the processor-based system and manage devices and PUs in the processor-based system to perform thermal limiting;

[0024] Figure 8is a block diagram of an example processor-based system that includes a power limiter circuit configured to determine a total PU power limit budget available to a PU based on any of the example processes in Figure 3 , Figure 5 and Figure 6 and the processor-based system can include, but is not limited to, the processor-based systems and power limiter circuits in Figure 1 and Figure 2 ; and

[0025] Figure 9 is a block diagram of an example wireless communication device that includes a radio frequency (RF) component that can include a processor-based system that includes a power limiter circuit configured to determine a total PU power limit budget available to a PU based on any of the example processes in Figure 3 , Figure 5 and Figure 6 and the processor-based system can include, but is not limited to, the processor-based systems and power limiter circuits in Figure 1 and Figure 2 . DETAILED DESCRIPTION

[0026] Several example aspects of the disclosure are now described with reference to the drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0027] Aspects disclosed herein include power monitoring and limiting of processing units (PUs) in a processor-based system to limit the overall power consumption of the processor-based system. Related methods of power monitoring and limiting of PUs in the processor-based system are also disclosed. Workloads executed by the PUs in the processor-based system can vary significantly over time, such that their power consumption will also vary. This results in variations in the overall power consumption of the processor-based system. However, limiting the power of individual PUs can reduce their performance in undesirable ways, or the PUs can not be able to execute workloads that result in them consuming power up to the power limit. Thus, in example aspects, to limit the overall power consumption of the processor-based system while attempting to still achieve optimal performance of all PUs in the processor-based system, an overall power limit budget is allocated for the PUs (“PU power limit budget”). In this regard, in example aspects, the processor-based system is configured to dynamically determine a total PU power limit budget available to PUs that can remain available from unused power of other power consuming circuits (e.g., non-PU devices) to keep the processor-based system within an overall power consumption limit. The processor-based system is configured to allocate an overall or total PU power limit budget for PUs in the processor-based system, which is then allocated to different PUs based on workload differences of the different PUs to attempt to achieve optimal performance of the PUs while keeping the processor-based system within its overall power consumption limit.

[0028] The overall power consumption of the processor-based system can be related to heat generated due to expected energy loss, which can then be related to thermal limits of the processor-based system. Thus, by monitoring and limiting the overall power consumption of the processor-based system and its PUs, the temperature of the processor-based system can be limited to balance the overall average power consumption of different systems in the processor-based system while remaining within the thermal limits of the processor-based system while achieving optimal performance of the PUs. Limiting power consumption in the processor-based system can also achieve desired overall workload performance in a sustainable way, as heat and temperature can reduce workload performance. Limiting power consumption in the processor-based system can also extend battery life, as temperature can generate negative effects on battery performance and power supply capabilities. Limiting power consumption in the processor-based system can also limit the temperature of the processor-based device to avoid hotspots that can otherwise occur due to heat generated from energy loss from causing harm to a user’s skin. For example, the processor-based system can be a wearable device, or can be other devices such as a laptop computer or an extended reality (XR) device that are expected to be in contact with a user’s skin.

[0029] In this regard,Figure 1 is a block diagram of an example processor-based system 100 that includes power consumption circuitry and processing units (PUs) where limiting overall power consumption can be desirable. The processor-based system 100 includes an integrated circuit (IC) chip 102 in this example, which is a system on a chip (SoC) 104. The SoC 104 in this example includes multiple PUs 106, which are central PUs (CPUs) 108, graphics PUs (GPUs) 110, and neural PUs (NPUs) 112 in this example, each configured to execute instructions to perform respective tasks. Thus, the PUs 106 consume power to operate. In this example, the SoC 104 includes a shared memory system 114 that is accessible by each of the PUs 106 for storing and retrieving data for executing instructions. As an example, the shared memory system 114 can be a cache memory, such as a last level cache memory. In this example, the shared memory system 114 has a shared memory 116 that is generally accessible by each of the PUs 106. The shared memory system 114 can also have a memory management unit (MMU) configured to manage access to the shared memory 116. The shared memory system 114 can also have statically configured memory regions (i.e., CPU memory region 118, GPU memory region 120, NPU memory region 122, and multimedia region 123) to provide dedicated memory for the respective CPU 108, GPU 110, NPU 112, and multimedia system. In this example, the SoC 104 also includes a system memory 124 that is also accessible by the PUs 106 through the shared memory system 114, which has sufficient memory for the entire memory map of the PUs 106.

[0030] With continued reference to Figure 1 , the processor-based system 100 also includes other devices external to the SoC 104 and its PUs 106 that provide support functions including powering the SoC 104 and its PUs 106 for operation. These other devices are non-PU power consumption devices 125 that are external to the SoC 104 and its PUs 106, and are also electrical devices that themselves consume power. In this example, the processor-based system 100 includes a battery charging circuit 126 that is a circuit configured to charge a battery 128. The battery 128 is provided to power the processor-based system 100 if the processor-based system 100 is not connected to a fixed power source. As such, the processor-based system 100 is configured to operate on battery power as a wireless power device, such as in a mobile device. Also as Figure 1As shown, the processor-based system includes a power management IC (PMIC) 130 configured to manage the supply of power to the SoC 104 and other components of the processor-based system 100, such as a fan 132 for cooling. When the processor-based system 100 is connected to a power source, the PMIC 130 manages the battery charging circuit 126 to charge the battery 128. When the processor-based system 100 is not connected to a power source, the PMIC 130 manages the discharge of the battery 128 to provide power.

[0031] Workloads performed by the PUs 106 in the processor-based system 100 can vary significantly over time, such that their power consumption will also vary. This causes the overall power consumption of the processor-based system 100 to vary. However, limiting the power of an individual PU 106 can reduce its performance in non-desirable ways, or the PUs 106 can not be able to perform workloads that cause them to consume power up to the power limit. The overall power consumption of the processor-based system 100 can be related to the heat generated due to expected energy loss, which can then be related to the thermal limit of the processor-based system 100. Limiting the power consumption in the processor-based system 100 can also limit the temperature of the processor-based system 100 to avoid hotspots that can otherwise occur due to heat generated from energy loss from harming the skin of a user. For example, the processor-based system 100 can be included in a wearable device or other device expected to come into contact with the skin of a user, such as a laptop computer or an extended reality (XR) device.

[0032] Thus, as discussed in greater detail below, to limit the overall power consumption of the processor-based system 100 while attempting to still achieve optimal performance of all of the PUs 106, the processor-based system 100 includes a power limiter circuit 134. The power limiter circuit 134 is configured to limit the power consumption of the PUs 106 in the processor-based system 100 based on a total power limit budget established for the PUs 106. In this example, the power limiter circuit 134 is not a current limiter that limits sudden changes in current rate (e.g., the derivative of current - di / dt) but rather constrains the power consumption of the PUs 106. In this regard, as discussed below, the power limiter circuit 134 is configured to dynamically determine a total processing unit power limit budget available to the PUs 106. The total PU power limit budget is a power budget that is kept available as unused power of other power consuming circuits (e.g., non-PU devices) external to the PUs 106 in the overall power consumption limit of the processor-based system 100. The power limiter circuit 134 is configured to communicate with the battery charging circuit 126 and the PMIC 130 over the communication link 133 to determine their power consumption external to the PUs 106 so that it can determine how much of the overall power consumption limit of the processor-based system 100 is being consumed. The remaining unused power of the overall power consumption limit of the processor-based system 100 can be allocated to the PUs 106 for operation. In this regard, the power limiter circuit 134 can be configured to allocate the total PU power limit budget that is still available to operate the PUs 106 into individual power limit budgets for each of the PUs 106 that will be constrained for operation. The total PU power limit budget is allocated by the power limiter circuit 134 to the different PUs 106 based on workload differences of that PU to attempt to achieve optimal performance of the PUs 106 while keeping the processor-based system 100 within its overall power consumption limit. The power limiter circuit 134 is then configured to monitor the actual power consumption of the PUs 106 and the workload that the PUs are performing and reallocate or adjust the power limit budgets of the PUs 106 for their operation.

[0033] For example, as discussed in more detail below, if the monitored actual power consumption of a PU 106 is below its allocated power limit budget, meaning that the performance of such PU 106 does not require the full power limit budget, the power limiter circuit 134 can be configured to reduce the power limit budget of such PU 106 and increase the power limit budgets of other PUs 106 in the total PU power limit budget. Also as an example, as also discussed in more detail below, if the monitored actual power consumption of a PU 106 exceeds its allocated power limit budget, and / or the performance of such PU 106 is throttled at a level that would exceed the power limit budget of that PU, the power limiter circuit 134 can be configured to reduce the power limit budget of such PU 106 and increase the power limit budgets of other PUs 106 in the total processing unit power limit budget.

[0034] The power limiter circuit 134 can be configured to continuously allocate power limit budgets to the PUs 106 and monitor and limit power consumption based on respective workloads, as well as reallocate power limit budgets to the PUs 106. In this way, the power consumption of the processor-based system 100 can be controlled to remain within its thermal limits while still achieving optimal performance of the PUs 106 based on their varying workload demands and reallocation of unused power budgets. Limiting power consumption in the processor-based system 100 can also achieve the desired overall workload performance of the PUs 106 in a sustainable way, as heat and temperature can degrade workload performance. Limiting power consumption in the processor-based system 100 can also extend the life of the battery 128, as temperature can negatively impact battery 128 performance and power delivery capabilities. Limiting power consumption in the processor-based system 100 can also limit the temperature of a device incorporating the processor-based system 100 to avoid hotspots that can otherwise occur due to heat generated from energy loss from causing harm to a user’s skin. For example, the processor-based system 100 can be a wearable device, or can be other devices such as a laptop computer or an extended reality (XR) device that are intended to be in contact with a user’s skin.

[0035] With continued reference to Figure 1In this example, power limiter circuitry 134 is a processing device configured to execute firmware or software instructions to perform tasks such as allocating a power limit budget to PU 106, monitoring and limiting power consumption, and reallocating the power limit budget to PU 106. In this example, power limiter circuitry 134 includes root memory 136 residing within the power limiter circuitry 134 on SoC 104, and includes a bootloader 138 configured to execute upon startup or power-on of SoC 104 and power limiter circuitry 134. When executed by power limiter circuitry 134, bootloader 138 is configured to communicate via communication link 142 with firmware interface 140 (e.g., Unified Extensible Firmware Interface (UEFI)) to receive application firmware 143 to be executed by power limiter circuitry 134. Thus, the application firmware controlling the operation of power limiter circuitry 134 can be programmable. The application firmware, when executed by power limiter circuitry 134, can access configuration memory from shared memory system 114. This configuration information may include a total power limit for the processor-based system 100, which the power limiter circuit 134 will use to calculate the remaining available power limit budget for the PU 106, as discussed in more detail below. The power limiter circuit 134 may use shared memory 116 for memory storage for faster access, including storing the calculated individual power limit budget for the PU 106.

[0036] For example Figure 1 As illustrated in this example, the processor-based system 100 also includes a High-Level Operating System (HLOS) 127. HLOS 127 is configured to interface with power limiter circuitry 134 via communication link 144 to communicate the overall power limit budget of the processor-based system 100 to the power limiter circuitry 134. The power limiter circuitry 134 can also be configured to communicate power budget messages and other information to HLOS 127 via communication link 144. For example, the power limiter circuitry 134 can receive workload data indicating the workload of PU 106 from HLOS 127 via communication link 144. As discussed above and in more detail below, the power limiter circuitry 134 is configured to allocate a total PU power limit budget to PU 106 relative to the workload in an attempt to provide sufficient power for performance requirements under such workload.

[0037] Figure 2 This is an example Figure 1FIG. 1 illustrates an example processor-based system 100 and a block diagram of more example details of portions of the power limiter circuit 134 to further explain examples of allocating and reallocating a determined total PU power limit budget available to the PUs based on a remaining available power and workload of the PUs 106 to maintain the processor-based system 100 within its overall power consumption limit. As Figure 2 As shown, the power limiter circuit 134 is disposed in the SoC 104. In this example, the power limiter circuit 134 includes a power limit budget determination circuit 200 configured to receive power telemetry data 202 indicative of power usage from non-PU devices 125 in the processor-based system 100. In this example, the power limit budget determination circuit 200 is configured to determine a total PU power limit budget 204 based on a difference between an overall power limit for the processor-based system 100 and power usage of the other non-PU devices 125. In this way, the power limiter circuit 134 is able to determine how much power is available to power the SoC 104 and its PUs 106 such that the power consumption of the processor-based system 100 remains within its overall power limit. In this example, the power limit budget determination circuit 200 receives an overall power limit 206 for the processor-based system 100 through the firmware interface 140. The power limit budget determination circuit 200 subtracts the power usage of the non-PU devices 125 obtained from the power telemetry data 202 from the overall power limit 206 to be provided in the total PU power limit budget 204. In this example, the power limit budget determination circuit 200 is also configured to subtract an average power consumption 208 of a multimedia system 210 and an average power consumption 212 of a shared memory system 114 in the processor-based system 100 from the overall power limit 206 for the processor-based system 100 while also consuming a portion of the overall power limit 206 for the processor-based system 100 to provide in the total PU power limit budget 204. In this way, the remaining total PU power limit budget 204 is the available power that the PUs 106 can consume without causing the processor-based system 100 to exceed its overall power limit 206.

[0038] As an example, as discussed in greater detail below, the power limiter circuit 134 can be configured such that the total PU power limit budget determination circuit 200 periodically calculates the total PU power limit budget 204, such as between one (1) second to sixty (60) seconds. In this way, the total PU power limit budget 204, which is used to constrain the power consumption of the PUs 106, is periodically and continuously updated such that unused power from reduced power consumption by the non-PU devices 125, the multimedia system 210, and / or the shared memory system 114 can be made available to the PUs 106 as part of the total PU power limit budget 204. Likewise, if the non-PU devices 125, the multimedia system 210, and / or the shared memory system 114 consume more power, then the total PU power limit budget 204 can be reduced so as not to exceed the overall power limit 206 for the processor-based system 100.

[0039] With continued reference to Figure 2 The power limiter circuit 134 in this example also includes a power limit budget circuit 214. The power limit budget circuit 214 is configured to execute the application firmware 143 to perform a power limit budget loop 216 for controlling the allocation and reallocation of the power limit budgets 218(1) to 218(3) for the respective CPUs 108, GPUs 110, and NPUs 112 such that the power consumption of such PUs 106 is constrained to their respective power limit budgets. For example, the power limit budget circuit 214 can be configured to periodically perform the power limit budget loop 216 between one (1) millisecond (ms) and ten (10) seconds, depending on the desired frequency of changing the power limit budgets 218(1) to 218(3) for constraining the respective CPU 108, GPU 110, and NPU 112 power consumption. The power limit budgets 218(1) to 218(3) used by the power limiter circuit 134 to constrain the power consumption of the PUs 106 are based on the power consumption in the processor-based system 100, which is then used to generate the total PU power limit budget. The power limit budgets 218(1) to 218(3) are not based on transient current consumption or flow rates as a derivative or rate of change of current (e.g., di / dt). Thus, the power limit budget loop 216 for controlling the allocation and reallocation of the power limit budgets 218(1) to 218(3) for the respective CPUs 108, GPUs 110, and NPUs 112 can not need to be performed as frequently as would be required to detect and change based on current flow rates. However, it is desirable to perform the power limit budget loop 216 frequently enough such that any changes in the workloads of the PUs 106 can be used to reallocate the total PU power limit budget 204 to optimize the performance of the PUs 106 while not exceeding the overall power limit 206 for the processor-based system 100.

[0040] In this regard, the power limit budget circuit 214 is coupled to a power limit budget allocation circuit 220 that is configured to receive workload data 224(1) through 224(3) indicative of the workload of the respective CPU 108, GPU 110, and NPU 112. For example, the processor-based system 100 can include PU performance monitoring circuits 222(1) through 222(3) that are configured to monitor workload activity of the respective CPU 108, GPU 110, and NPU 112 of the PUs 106. The PU performance monitoring circuits 222(1) through 222(3) are further configured to generate respective workload data 224(1) through 224(3) indicative of the workload activity of the respective CPU 108, GPU 110, and NPU 112. As such, the power limit budget allocation circuit 220 can receive the workload data 224(1) through 224(3) to understand the relative workload activity of the CPU 108, GPU 110, and NPU 112. The power limit budget allocation circuit 220 is configured to allow individual power budgets from the total PU power limit budget 204 to the CPU, GPU, and NPU based on the respective workload activity of the CPU 108, GPU 110, and NPU 112 from the respective workload data 224(1) through 224(3). For example, the power limit budget allocation circuit 220 includes a power budget generation circuit 226 that is configured to allocate power budget weights 228(1) through 228(3) corresponding to the respective CPU 108, GPU 110, and NPU 112 based on the workload activity of the CPU 108, GPU 110, and NPU 112. For example, if it is desired to allocate the total PU power limit budget 204 equally to the CPU 108, GPU 110, and NPU 112, the power budget generation circuit 226 can be configured to assign a weight of 33.33% to each of the power budget weights 228(1) through 228(3). This can be an initial setting by the power budget generation circuit 226 at reset or start-up when the workload data 224(1) through 224(3) has not yet been received or has not been received long enough for it to be stable. The power budget generation circuit 226 can be configured to allocate the power limit budgets 218(1) through 218(3) using the power budget weights 228(1) through 228(3) based on the respective workload data 224(1) through 224(3) (e.g., proportionally). For example, the power budget generation circuit 226 can be configured to determine a percentage weight of the total PU power limit budget 204 for each PU 106 as a proportion of the workload activity of that PU from the workload data 224(1) through 224(3) to the total workload activity of the PUs 106.The power budget generation circuit 226 is then configured to communicate or make available to the power limit budget circuit 214 power budget weights 228(1) through 228(3) for allocating the power limit budgets 218(1) through 218(3) to the PUs 106.

[0041] With continued reference to Figure 2 , the power limit budget circuit 214 is configured to allocate the power limit budgets 218(1) through 218(3) to the PUs 106 based on the power budget weights 228(1) through 228(3). For example, the power budget weights 228(1) through 228(3) can be applied to the total PU power limit budget 204 such that the total PU power limit budget 204 is allocated to each of the PUs 106 based on respective workload activities of the PUs. As an example, the power limit budget circuit 214 can include power limit budget registers 230(1) through 230(3) each configured to store a computed power limit budget 218(1) through 218(3) to be applied to the PUs 106. The power limit budget circuit 214 can then access the power limit budget registers 230(1) through 230(3) to perform the power limit budget loop 216 to constrain power consumption of the PUs 106 based on the respective power limit budgets 218(1) through 218(3).

[0042] With continued reference to Figure 2 , the performance of the power limit budget loop 216 by the power limit budget circuit 214 causes power consumption of the PUs 106 to be constrained within the determined power limit budgets 218(1) through 218(3) of the PUs. In this regard, as Figure 2If, as shown, the determined power limit budget 218(1) to 218(3) for a given PU 106 would require a change in its operating point (i.e., clock frequency and / or voltage) to achieve the power limit budget 218(1) to 218(3), the power limit budget circuit 214 is configured to communicate a new operating point 232(1) to 232(3) for the given respective CPU 108, GPU 110, or NPU 112 to a dynamic voltage and frequency scaling (DVFS) circuit 234. The DVFS circuit 234 has a look-up table (LUT) 236(1) to 236(3) corresponding to each of the CPUs 108, GPUs 110, and NPUs 112 to look up the new operating point to operate the CPUs 108, GPUs 110, and NPUs 112 based on the determined power limit budget 218(1) to 218(3) of the power limit budget circuit 214 based on the new operating point 232(1) to 232(3) from the power limit budget circuit 214. The power limit budget circuit 214 can reset the new operating point 232(1) to 232(3) for the given respective CPU 108, GPU 110, or NPU 112 to the DVFS circuit 234 when the power limit budget 218(1) to 218(3) is redistributed by the power limit budget circuit 214.

[0043] At this point, the power limiter circuit 134 and its supporting components have been described in terms of determining and allocating the power limit budgets 218(1) through 218(3) for a given respective CPU 108, GPU 110, or NPU 112 to constrain the respective power consumption of that CPU, GPU, or NPU. Now, the power limiter circuit 134 and components and functionality of the power limiter circuit’s supporting components in the SoC 104 are described in terms of constraining the power consumption of a respective CPU 108, GPU 110, or NPU 112 and adjusting and reallocating the power limit budgets 218(1) through 218(3) for a given respective CPU 108, GPU 110, or NPU 112 based on monitoring of the actual power consumption of that CPU, GPU, or NPU. The power limiter circuit 134 is able to reallocate the power limit budgets 218(1) through 218(3) for a given respective CPU 108, GPU 110, or NPU 112 in the event that the actual power consumption of that CPU, GPU, or NPU exceeds or falls below the power limit budget 218(1) through 218(3) for that CPU, GPU, or NPU to prevent the processor-based system 100 from exceeding its overall power limit 206 while also achieving optimal performance of the PUs 106. It is the feedback of the monitored actual power consumption and the monitoring of the workload data 224(1) through 224(3) from the PUs 106 that allows the power limiter circuit 134 to continuously allocate and reallocate the power limit budgets 218(1) through 218(3) to attempt to optimize the performance of the PUs 106 while also maintaining the overall power consumption of the processor-based system 100 within the overall power limit 206.

[0044] In this regard, as Figure 2As shown, the SoC 104 in this example includes power constraint circuits 238(1) through 238(3) that receive respective power limit budgets 218(1) through 218(3) from the power limit budget circuit 214. The power constraint circuits 238(1) through 238(3) cause the power consumption of the respective CPU 108, GPU 110, or NPU 112 to be constrained according to the respective power limit budgets 218(1) through 218(3). The power constraint circuits 238(1) through 238(3) are configured to generate power tracking indicators 240(1) through 240(3) that indicate the constrained power consumption according to the respective power limit budgets 218(1) through 218(3). The power constraint circuits 238(1) through 238(3) are further configured to provide the power tracking indicators 240(1) through 240(3) to respective power consumption differential circuits 242(1) through 242(3), which are a kind of comparator circuit. The power consumption differential circuits 242(1) through 242(3) further receive actual power consumptions 244(1) through 244(3) of the respective CPU 108, GPU 110, and NPU 112 as measured by respective power monitoring circuits 246(1) through 246(3). The actual power consumptions 244(1) through 244(3) can be the average actual power consumptions of the respective CPU 108, GPU 110, and NPU 112 over a specified time period. The power consumption differential circuits 242(1) through 242(3) are configured to determine the difference between the actual power consumptions 244(1) through 244(3) of the respective CPU 108, GPU 110, or NPU 112 and the respective power limit budgets 218(1) through 218(3) indicated by the power tracking indicators 240(1) through 240(3) that indicate the constrained power consumption according to the respective power limit budgets 218(1) through 218(3). The power consumption differential circuits 242(1) through 242(3) are each configured to generate performance adjustment events 248(1) through 248(3) based on the difference between the actual power consumptions 244(1) through 244(3) of the respective CPU 108, GPU 110, and NPU 112 and the power tracking indicators 240(1) through 240(3) that indicate the power limit budgets 218(1) through 218(3) of the respective CPU 108, GPU 110, and NPU 112. The power consumption differential circuits 242(1) through 242(3) are configured to generate the respective performance adjustment events 248(1) through 248(3) to the respective performance adjustment circuits 250(1) through 250(3) to adjust the performance of the respective CPU 108, GPU 110, and NPU 112 based on the performance adjustment events 248(1) through 248(3).As an example, if the actual power consumption 244(1) through 244(3) exceeds the power limit budget 218(1) through 218(3) indicated by the power tracking indicators 240(1) through 240(3), the performance adjustment circuit 250(1) through 250(3) can be configured to adjust the performance of the PU 106 by adjusting (reducing) the throughput or clock frequency.

[0045] For example, if the actual power consumption 244(1) through 244(3) of the PU 106 exceeds its power limit budget 218(1) through 218(3), the performance adjustment event 248(1) through 248(3) will cause the respective performance adjustment circuit 250(1) through 250(3) for the respective CPU 108, GPU 110, and NPU 112 to reduce its performance level, thereby reducing its power consumption. If the actual power consumption 244(1) through 244(3) of the PU 106 does not exceed its power limit budget 218(1) through 218(3), the performance adjustment event 248(1) through 248(3) will cause the respective performance adjustment circuit 250(1) through 250(3) for the respective CPU 108, GPU 110, and NPU 112 to potentially increase its performance level (e.g., not adjust), thereby allowing its power consumption to increase in accordance with its power limit budget 218(1) through 218(3).

[0046] With continued reference to Figure 2The performance adjustment events 248(1) to 248(3) are also provided to the power limit budget allocation circuit 220. The power limit budget allocation circuit 220 is configured to reallocate the power budget weights 228(1) to 228(3) based on the determined difference between the respective actual power consumption 244(1) to 244(3) and the respective power limit budget 218(1) to 218(3). The power limit budget allocation circuit 220 is configured to reallocate the power budget weights 228(1) to 228(3) based on the performance adjustment events 248(1) to 248(3) such that any PUs 106 that must be adjusted will have their power budget weights 228(1) to 228(3) reallocated (e.g., reduced). This in turn will cause the power limit budget circuit 214 to reallocate new power limit budgets 218(1) to 218(3) accordingly. Thus, for example, if a PU 106’s performance must be adjusted based on the performance adjustment events 248(1) to 248(3), the power limit budget allocation circuit 220 can use this information to learn that the power budget weight 228(1) to 228(3) for such an adjusted PU 106 can be increased because it is known that the PU 106’s power consumption exceeded its previous power limit budget 218(1) to 218(3). As such, the power limit budget 218(1) to 218(3) can be increased to allow the adjusted PU 106 not to be adjusted such that the power consumption difference circuit 242(1) to 242(3) will not determine that the PU 106’s actual power consumption 244(1) to 244(3) exceeds its power tracking indicator 240(1) to 240(3) that indicates its power limit budget 218(1) to 218(3).

[0047] The power limit budget circuit 214 is configured to set new operating points 232(1) to 232(3) for the respective CPU 108, GPU 110, or NPU 112 to the DVFS circuit 234 based on the respective allocated power budget weight 228(1) to 228(3) for the given respective CPU 108, GPU 110, or NPU 112. If the reallocated power budget weight 228(1) to 228(3) determined for the given PU 106 will require a change in operating point (i.e., clock frequency and / or voltage) for the given respective CPU 108, GPU 110, or NPU 112 to achieve the power limit budget 218(1) to 218(3), the power limit budget circuit 214 is configured to reset the new operating point 232(1) to 232(3) for the given respective CPU 108, GPU 110, or NPU 112 to the DVFS circuit 234. As discussed above, the DVFS circuit 234 has LUTs 236(1) to 236(3) corresponding to each of the CPUs 108, GPUs 110, and NPUs 112 to look up new operating points to operate the CPUs 108, GPUs 110, and NPUs 112 based on the power limit budget 218(1) to 218(3) determined by the power limit budget circuit 214 based on the new operating point 232(1) to 232(3) from the power limit budget circuit 214. The power limit budget circuit 214 can reset the new operating point 232(1) to 232(3) for the given respective CPU 108, GPU 110, or NPU 112 to the DVFS circuit 234 when the power limit budget 218(1) to 218(3) is reallocated by the power limit budget circuit 214.

[0048] With continued reference to Figure 2 The performance regulation event 248(1) to 248(3) is also provided to respective power dissipation differential circuit 252(1) to 252(3) in the power limiter circuit 134 in this example. The power dissipation differential circuit 252(1) to 252(3) are each configured to compare the actual power dissipation 244(1) to 244(3) of the respective CPU 108, GPU 110, and NPU 112 determined by the respective power monitoring circuit 246(1) to 246(3) with the power limit budget 218(1) to 218(3) from the power limit budget circuit 214. The power dissipation differential circuit 252(1) to 252(3) are each configured to generate a differential power signal 254(1) to 254(3) to the power limit budget allocation circuit 220 indicating a difference between the actual power dissipation 244(1) to 244(3) of the respective CPU 108, GPU 110, or NPU 112 and its respective power limit budget 218(1) to 218(3).

[0049] If the respective power monitoring circuit 246(1) through 246(3) determines that the difference between the actual power consumption 244(1) through 244(3) of the respective CPU 108, GPU 110, or NPU 112 does not exceed the respective power limit budget 218(1) through 218(3), the power limit budget allocation circuit 220 can use this information to learn that the power budget weight 228(1) through 228(3) for such PU 106 should be reduced. The power limit budget allocation circuit 220 can then reallocate the unused power budget to other PUs 106 in its respective power budget weight 228(1) through 228(3). In this way, another PU 106 can be given the unused power budget to further optimize its performance. If the respective power monitoring circuit 246(1) through 246(3) determines that the difference between the actual power consumption 244(1) through 244(3) of the respective CPU 108, GPU 110, or NPU 112 exceeds the respective power limit budget 218(1) through 218(3), the power limit budget allocation circuit 220 can use this information to learn that the power budget weight 228(1) through 228(3) for such PU 106 should be increased, if possible. The power limit budget allocation circuit 220 can then reallocate the power limit budget 218(1) through 218(3) from another PU 106 in its respective power budget weight 228(1) through 228(3), if available. In this way, the PU 106 whose actual power consumption 244(1) through 244(3) exceeds its power limit budget 218(1) through 218(3) can be given additional power budget to further optimize its performance.

[0050] Figure 3 is an example of a power limiter circuit 134 in Figure 1 and Figure 2 The flowchart of the example process 300 illustrates the power limiter circuit 134, which can be used as the power limit budget loop 216 to determine the total PU power limit budget 204 available to the PUs 106 based on the remaining power available to maintain the processor-based system 100 within its overall power consumption limit and allocate and reallocate the total PU power limit budget 204 to the PUs 106 to control the power consumption of the PUs based on the workloads the PUs are performing.

[0051] In this regard, as shown in Figure 3 the first step of the power limit budget loop 216 is to receive power telemetry data 202 including power usage in the processor-based system 100 (block 302 in Figure 3 The next step in the power limit budget loop 216 can be to determine the total PU power limit budget 204 based on the difference between the overall power limit 206 for the processor-based system 100 and the power usage (block 304 in Figure 3of block 304 in FIG. 2). A next step in the power limit budget loop 216 can be to receive a plurality of workload data 224(1) through 224(3) indicative of workload activity of each of the plurality of PUs 106, 108, 110, 112 (of block 306 in FIG. 2). A next step in the power limit budget loop 216 can be to allocate a power limit budget 218(1) through 218(3) from the total PU power limit budget 204 for each of the plurality of PUs 106, 108, 110, 112 based on the workload data 224(1) through 224(3) of the plurality of workload data 224(1) through 224(3) corresponding to each of the plurality of PUs 106, 108, 110, 112 (of block 308 in FIG. 2). Figure 3 of block 306 in FIG. 2). A next step in the power limit budget loop 216 can be to allocate a power limit budget 218(1) through 218(3) from the total PU power limit budget 204 for each of the plurality of PUs 106, 108, 110, 112 based on the workload data 224(1) through 224(3) of the plurality of workload data 224(1) through 224(3) corresponding to each of the plurality of PUs 106, 108, 110, 112 (of block 308 in FIG. 2). Figure 3 of block 306 in FIG. 2). A next step in the power limit budget loop 216 can be to allocate a power limit budget 218(1) through 218(3) from the total PU power limit budget 204 for each of the plurality of PUs 106, 108, 110, 112 based on the workload data 224(1) through 224(3) of the plurality of workload data 224(1) through 224(3) corresponding to each of the plurality of PUs 106, 108, 110, 112 (of block 308 in FIG. 2). Figure 3 of block 306 in FIG. 2). A next step in the power limit budget loop 216 can be to allocate a power limit budget 218(1) through 218(3) from the total PU power limit budget 204 for each of the plurality of PUs 106, 108, 110, 112 based on the workload data 224(1) through 224(3) of the plurality of workload data 224(1) through 224(3) corresponding to each of the plurality of PUs 106, 108, 110, 112 (of block 308 in FIG. 2). Figure 3 of block 306 in FIG. 2). A next step in the power limit budget loop 216 can be to allocate a power limit budget 218(1) through 218(3) from the total PU power limit budget 204 for each of the plurality of PUs 106, 108, 110, 112 based on the workload data 224(1) through 224(3) of the plurality of workload data 224(1) through 224(3) corresponding to each of the plurality of PUs 106, 108, 110, 112 (of block 308 in FIG. 2). Figure 3 of block 306 in FIG. 2). A next step in the power limit budget loop 216 can be to allocate a power limit budget 218(1) through 218(3) from the total PU power limit budget 204 for each of the plurality of PUs 106, 108, 110, 112 based on the workload data 224(1) through 224(3) of the plurality of workload data 224(1) through 224(3) corresponding to each of the plurality of PUs 106, 108, 110, 112 (of block 308 in FIG. 2).

[0052] Figure 3Process 300 in FIG. 3 can be repeated continuously, periodically (e.g., between every 1 ms and 1 second), to determine the total PU power limit budget 204 available to the PUs 106 based on the remaining power available to maintain the processor-based system 100 within its overall power consumption limit and to allocate and reallocate the total PU power limit budget 204 to the PUs 106 to control the power consumption of the PUs based on the workloads being performed by the PUs. Figure 3 Process 300 in FIG. 3 can be repeated in response to the expiration of a periodic timer set to expire after a constant amount of time and / or after an interrupt drive.

[0053] Figure 4 is an example of maintaining the processor-based system 100 within its total PU power limit budget 204 of 30 Watts (W) while the power limiter circuit 134 allocates and reallocates the total PU power limit budget 204 to the PUs 106 based on the workloads being performed by the PUs in Figure 1 and Figure 2 An example time-based allocation and reallocation of the determined total PU power limit budget 204 to the PUs 106 in the processor-based system 100 in FIG. 3. In this example, the power limiter circuit 134 operates the power limit budget loop 216 to allocate the total PU power limit budget 204 to the PUs 106 based on every ten (10) ms.

[0054] In this regard, as Figure 4 shown in an example of a first iteration 402(1) of the power limit budget loop 216 by the power limit budget circuit 214 in the power limiter circuit 134, the power limit budget allocation circuit 220 initially allocates power budget weights 228(1) through 228(3) to the CPU 108, GPU 110, and NPU 112 based on the balancing mode, where each power budget weight 228(1) through 228(3) is 33.3%. Accordingly, the power limit budget circuit 214 applies the total PU power limit budget 204 of 30 W based on the power budget weights 228(1) through 228(3) to allocate power limit budgets 218(1) through 218(3) of 10 W each to the CPU 108, GPU 110, and NPU 112. In Figure 4In an example of a second iteration 402(2) of the power limit budget loop 216 in the graph 400, the power budget weights 228(1) to 228(3) for the CPU 108, GPU 110, and NPU 112 are adjusted to 66.6%, 16.6%, and 16.6%, respectively, based on the workload data 224(1) to 224(3) indicating that the NPU 112 has 66.6% of the total workload activity indicated by the sum of the workload data 224(1) to 224(3). Prior to the power limit budgets 218(1) to 218(3) being allocated by the power limit budget circuit 214, the power limiter circuit 134 can set new operating points 232(1) to 232(2) in the DVFS circuit 234 so that the PUs 106 can operate at performance levels that are compatible with their allocated power limit budgets 218(1) to 218(3). Setting the new operating points 232(1) to 232(2) in the DVFS circuit 234 prior to reallocating the power limit budgets 218(1) to 218(3) can prevent the PUs 106 from immediately adjusting, which otherwise according to the operating points 232(1) to 232(3) of that PU, the PU can be allocated a power limit budget 218(1) to 218(3) that exceeds its performance capabilities. The power limit budget circuit 214 allocates power limit budgets 218(1) to 218(3) of 5W, 5W, and 20W, respectively, for the CPU 108, GPU 110, and NPU 112 based on the power budget weights 228(1) to 228(3) being applied to the total PU power limit budget 204 of 30W.

[0055] Subsequently, at Figure 4In an example of a third iteration 402(3) of the power limit budget loop 216 in the graph 400, the power budget weights 228(1) through 228(3) for the CPU 108, GPU 110, and NPU 112 are adjusted based on the workload data 224(1) through 224(3) indicating that the NPU 112 has 60% of the total workload activity indicated by the sum of the workload data 224(1) through 224(3) and the GPU 110 has 23.3% of the total workload activity indicated by the sum of the workload data 224(1) through 224(3) to 16.6%, 23.3%, and 60%, respectively. Before the power limit budgets 218(1) through 218(3) are allocated by the power limit budget circuit 214, the power limiter circuit 134 can set new operating points 232(1) through 232(2) in the DVFS circuit 234 so that the PUs 106 can be at performance levels that are compatible with their allocated power limit budgets 218(1) through 218(3) only when needed. Thus, the power limit budget circuit 214 allocates power limit budgets 218(1) through 218(3) of 5W, 7W, and 18W for the CPU 108, GPU 110, and NPU 112, respectively, based on the power budget weights 228(1) through 228(3) applied to the total PU power limit budget 204 of 30W.

[0056] Subsequently, at Figure 4In an example of a fourth iteration 402(4) of the power limit budget loop 216 in the graph 400, the power budget weights 228(1) to 228(3) for the CPU 108, GPU 110, and NPU 112 are adjusted to 53.3%, 26.6%, and 20% respectively based on the workload data 224(1) to 224(3) indicating that the NPU 112 has 53.3% of the total workload activity indicated by the sum of the workload data 224(1) to 224(3) and the GPU 110 has 26.6% of the total workload activity indicated by the sum of the workload data 224(1) to 224(3). Accordingly, the power limit budget circuit 214 allocates power limit budgets 218(1) to 218(3) of 6W, 8W, and 18W respectively for the CPU 108, GPU 110, and NPU 112 based on the power budget weights 228(1) to 228(3) being applied to the total PU power limit budget 204 of 30W. In this example, the power limiter circuit 134 sets new operating points 232(2), 232(3) for the GPU 110 and NPU 112 in the DVFS circuit 234 prior to allocating the new power limit budgets 218(2), 218(3) for the GPU and the NPU that are higher than the previously allocated new power limit budgets in the third iteration 402(3) of the power limit budget loop 216. This allows the immediate adjustment of the GPU 112 and / or NPU 112 to be avoided.

[0057] Subsequently, in Figure 4 In an example of a fifth iteration 402(5) of the power limit budget loop 216 in the graph 400, the power budget weights 228(1) to 228(3) for the CPU 108, GPU 110, and NPU 112 are adjusted to 30%, 40%, and 20% respectively based on the workload data 224(1) to 224(3). The power limiter circuit 134 sets new operating points 232(1) to 232(3) for the PUs 106 in the DVFS circuit 234. In this example, since the SoC 104 does not consume all of the power from the total PU power limit budget 204, there is an excess credit of 2W of the 30W total PU power limit budget 204. The actual power consumptions 244(1) to 244(3) for the CPU 108, GPU 110, and NPU 112 are 9W, 8W, and 16W respectively. Subsequently, in Figure 4In an example of the sixth iteration 402(6) of the power limit budget loop 216 in the diagram 400, the power budget weights 228(1) to 228(3) for the CPU 108, GPU 110, and NPU 112 are each adjusted to balance to 33% based on the workload data 224(1) to 224(3). In this example, the SoC 104 is set to a power save mode, whereby the total PU power limit budget 204 is reduced from 30W to 9W. As a result, the power limit budgets 218(1) to 218(3) for the CPU 108, GPU 110, and NPU 112 are each set to 3W, which is an equal allocation of the 9W available in the new total PU power limit budget 204.

[0058] It should be noted that in an alternative example, the power limit budget circuit 214 can be configured to set the power limit budgets 218(1) to 218(3) for any of the PUs 106 at a fixed set power limit budget for the total PU power limit budget 204 (e.g., 50%). Thus, in this example, the power limit budget circuit 214 would only be able to allocate and reallocate the remaining percentage (e.g., 50%) of the total PU power limit budget 204 to the other PUs 106 that do not have a fixed power limit budget 218(1) to 218(3) setting.

[0059] Figure 5 is an example of Figure 1 and Figure 2 a flowchart of another example process 500 of determining the total PU power limit budget 204 available to the PUs 106 based on the remaining power available to maintain the processor-based system 100 within the overall power limit 206 of the processor-based system and allocate and reallocate the total PU power limit budget 204 to the PUs 106 to control the power consumption of the PUs based on the workloads the PUs are performing by the power limiter circuit 134 in the diagram 400. Figure 5 The process 500 in the diagram 400 can be the power limit budget loop 216 performed by the power limiter circuit 134. Figure 5 The process 500 in the diagram 400 can be performed according to two different threads 502(1), 502(2) in this example. The first thread 502(1) can start when the power limiter circuit 134 is started or reset and be initialized (block 504 in the diagram 400) to wait for the expiration of a timer set to expire after a constant time period (block 506 in the diagram 400), then perform the power limit budget loop 216. Alternatively, the second thread 502(2) can start when the power limiter circuit 134 is started or reset and be initialized (block 508 in the diagram 400) to generate an interrupt (block 510 in the diagram 400), then perform the power limit budget loop 216. Figure 5 Figure 5 Figure 5 Figure 5 ​​​Box 510 in the middle) generates a wake-up signal 512 to trigger the power-limited budget loop 216 when it expires due to the timer ( Figure 5 In addition to the periodic execution controlled by box 506, temporary execution is performed. The power limiting budget circuit 214 waits for the timer to expire or for the wake-up signal 512, and then executes an iteration of the power limiting budget loop 216. Figure 5 (Box 514 in the middle).

[0060] In this respect, such as Figure 5 As shown, the power limiting budget loop 216 in this example involves: reading the existing power limiting budgets 218(1) to 218(3) for PU106 to determine which of the power limiting budgets 218(1) to 218(3) has the most constraints. Figure 5 (See box 516 in the diagram). Subsequently, the power limit budget loop 216 reads the actual power consumption 244(1) to 244(2) from the power monitoring circuits 246(1) to 246(2) in order to determine whether the PU 106 is consuming more or less power than its existing power limit budget 218(1) to 218(3). Figure 5 (Box 518 in the text). Also, for example... Figure 5 As shown, the power limiting budget loop 216 also involves: updating the total PU power limiting budget 204 based on the total PU power limiting budget 204 to establish the total PU power limiting budget 204 ( Figure 5 (in box 520). Subsequently, the power limiting budget loop 216 generates new power budget weights 228(1) to 228(3) based on the workload activity of PU 106 from workload data 224(1) to 224(3) and the actual power consumption of PU 106 244(1) to 244(3). Figure 5 (See box 522 in the text). If the total PU power limit budget 204 is less than the minimum power limit required to operate PU 106, then the power limit budget loop 216 also (if necessary) adjusts the total PU power limit budget. Figure 5 (See box 524 in the image). Subsequently, the power limit budget circuit 214 allocates the new power limit budget 218(1) to 218(3) based on the new power budget weights 228(1) to 228(3). Figure 5 (in box 526), ​​and then used to communicate with power constraint circuits 238(1) to 238(3) to constrain the power usage of the corresponding PU 106 ( Figure 8 (Box 528 in the middle).

[0061] It should be noted that, such as Figure 6As shown, the overall power limit 206 of the processor-based system 100 can be received from a separate thermal management system 530 that includes temperature sensors in the processor-based system 100 and the SoC 104 to measure temperature and adjust the overall power limit 206 of the processor-based system 100 in response. This can change the overall power limit 206 of the processor-based system 100, which is then used by the power limiter circuit 134 to allocate the power limit budget to the PUs 106. The following references Figure 5 An example thermal management system 530 is discussed.

[0062] Figure 6 is an example state machine diagram 600 that illustrates the enabling and disabling of the power limiter circuit 134 to enable and disable the threads 502(1), 502(2) in Figure 1 to enable and disable the power limit budget loop 216. For example, Figure 2 the state 602 in Figure 5 and Figure 5 when the CPU 108 is in an active state. When the CPU 108 transitions from the inactive operating state to the active operating state 602, the CPU 108 can generate a PU enable signal 606 that can be received by the power limiter circuit 134, which then resumes the timer and continues the threads 502(1), 502(2) in Figure 7 to perform the power limit budget loop 216. When the CPU 108 transitions from the active operating state to the inactive operating state 604, the CPU 108 can generate a PU disable signal 608 that can be received by the power limiter circuit 134, which then disables the timer and Figure 5 the threads 502(1), 502(2) in

[0063] Figure 1 is a block diagram of an example thermal management system 530 referenced in Figure 2 and can be provided in the processor-based system 100 in Figure 7 and Figure 7 to monitor temperature in the processor-based system 100 and manage devices and PUs 106 in the processor-based system 100 to perform thermal limits. As Figure 1As shown, the thermal management system 530 includes temperature sensors 702 placed in the processor-based system 100 and / or the SoC 104 to sense temperature. For example, the temperature sensors 702 can be placed in known hot spots of the SoC 104. As discussed above, the temperature of the processor-based system 100 can affect performance. The processor-based system 100 and its SoC 104 can have an operating temperature limit or skin limit. Power consumption affects temperature. The temperature sensors 702 provide temperature data 704 to a temperature controller 706, which can also include temperature sensors 705 that provide temperature data 704, but is also configured to receive temperature data 704 from the remote temperature sensors 702. The temperature controller 706 can be configured to reset the SoC 104 and / or the processor-based system 100 if the temperature according to the temperature data 704 exceeds a maximum temperature programmed for the SoC 104 and / or the processor-based system 100. The thermal management system 700 also includes a temperature sensor driver circuit 708 configured to read the temperature data 704 from the temperature controller 706. Temperature sensors 709 can also be associated with the temperature sensor driver circuit 708 that also provides temperature data 704. The temperature sensor driver circuit 708 is also configured to program the maximum temperature limit for the processor-based system 100 and / or the SoC 104 into the temperature controller 706.

[0064] With continued reference to Figure 7 , the thermal management system 530 also includes a thermal interface circuit 710 configured to receive the temperature data 704 and aggregate temperature thresholds for multiple thermal zones 712(1) through 712(X) in the processor-based system 100 and / or the SoC 104. The thermal management system 530 also includes a thermal system circuit 714 that resides in the HLOS 127 (see Figure 1 ) and interfaces with each of the thermal zones 712(1) through 712(X). There are temperature sensors 702 associated with each of the thermal zones 712(1) through 712(X). When the thermal system circuit 714 determines that a thermal limit has been exceeded for a thermal zone 712(1) through 712(X), the thermal system circuit 714 is configured to perform a thermal mitigation task to reduce temperature. The thermal system circuit 714 is configured to control various devices in the processor-based system 100 that correspond to the thermal zone 712(1) through 712(X) that exceeded its thermal limit through a mitigation interface circuit 716. The mitigation interface circuit 716 can then communicate with devices in the thermal zone 712(1) through 712(X) to reduce power consumption and / or perform another task to reduce power consumption, which in turn will reduce temperature.

[0065] For example, as Figure 2If the thermal zones 712(1) through 712(X) associated with the CPU 108 exceed their thermal limits, the thermal system circuit 714 can cause the scheduler 718 of the CPU 108 to reduce the scheduling frequency of processes to reduce workload activity of the CPU 108 to reduce power consumption. If the thermal zones 712(1) through 712(X) associated with the display driver 720 exceed their thermal limits, the thermal system circuit 714 can cause the display driver 720 to reduce its refresh rate to reduce power consumption. If the thermal zones 712(1) through 712(X) associated with the battery charging circuit 126 or its battery 128 exceed their thermal limits, the thermal system circuit 714 can cause the battery charging circuit 126 to reduce its recharge rate to reduce power consumption. If the thermal zones 712(1) through 712(X) associated with the GPU 110 exceed their thermal limits, the thermal system circuit 714 can cause the clock frequency driver circuit 722 of the GPU 110 to reduce its frequency rate to reduce power consumption in the GPU 110. If the thermal zones 712(1) through 712(X) associated with the CPU 108 exceed their thermal limits, the thermal system circuit 714 can cause the clock frequency driver circuit 724 of the CPU 108 to reduce its frequency rate to reduce power consumption in the CPU 108. If the thermal zones 712(1) through 712(X) exceed their thermal limits, the thermal system circuit 714 can cause the fan 132 to be turned on or increase its fan speed to reduce the temperature in the CPU 108.

[0066] In the case of each of the mitigation efforts to reduce power consumption in the PUs 106, this will be reflected in the actual power consumption 244(1) through 244(3) of such PUs 106, which in turn can cause Figure 3 and Figure 5 the power limiter circuit 134 to reallocate its power limit budgets 218(1) through 218(3) in response. Even before mitigation efforts are taken, if a thermal event is causing or resulting from the actual power consumption 244(1) through 244(3) of the PUs 106 to exceed their power limit budgets 218(1) through 218(3), the power limiter circuit 134 is configured to reallocate the power limit budgets 218(1) through 218(3) as possible, as discussed above.

[0067] A processor-based system including a power limiter circuit configured to allocate a total processing unit power limit budget to processing units to control power consumption of the processing units based on workloads being executed by the processing units and to reallocate the total processing unit power limit budget based on Figure 6 、 Figure 1 and Figure 2any of the example processes 300, 500, 600 in FIGS. 3-5, and the processor-based system can include, but is not limited to Figure 1 and Figure 2 the processor-based system 100 in FIG. 1 and / or Figure 8 and Figure 3 the power limiter circuit 134 in FIG. 1, and in accordance with any of the aspects disclosed herein, the processor-based system can be disposed in or integrated into an IC package disposed in any processor-based device. Non-limiting examples include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computer (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a transportation component, avionics systems, a drone, and a multicopter.

[0068] In this regard, Figure 5 An example of a processor-based system 800 is illustrated. The processor-based system 800 can include a power limiter circuit 802 configured to determine a total processing unit power limit budget available to a processing unit based on a remaining power available to maintain the processor-based system within its overall power consumption limit and allocate the total processing unit power limit budget to the processing unit to control power consumption of the processing unit based on a workload the processing unit is executing and in accordance with any of the example processes 300, 500, 600 in FIGS. 3-5, and the processor-based system can include, but is not limited to Figure 6 , Figure 1 and Figure 2 any of the example processes 300, 500, 600 in FIGS. 3-5, and the processor-based system can include, but is not limited to Figure 1 and Figure 2 the processor-based system 100 in FIG. 1 and / or Figure 8 and Figure 8 the power limiter circuit 134 in FIG. 1, and in accordance with any of the aspects disclosed herein.

[0069] In this example, the processor-based system 800 can be formed as an IC 804 and as a system on a chip (SoC) 806. The processor-based system 800 includes a PU 808 that includes one or more processors 810, which can include CPUs, GPUs, and NPUs, as examples. The PU 808 can have a shared memory 812 (e.g., a shared cache memory) coupled to the PU 808 for fast access to temporarily stored data. The PU 808 is coupled to a system bus 814 and can couple master and slave devices included in the processor-based system 800 to one another. As is well known, the PU 808 communicates with such other devices by exchanging address, control, and data information over the system bus 814. For example, the PU 808 can communicate bus transaction requests to a memory controller 816, which is a slave device, as examples. Although not illustrated in Figure 9 multiple system buses 814 can be provided, with each system bus 814 constituting a different fabric.

[0070] Other master and slave devices can be connected to the system bus 814. As illustrated in Figure 3 FIG. 1, such devices can include a memory system 820 (including the memory controller 816 and a memory array 818), one or more input devices 822, one or more output devices 824, one or more network interface devices 826, and one or more display controllers 828, as examples. The input devices 822 can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output devices 824 can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface devices 826 can be any devices configured to allow exchange of data to and from a network 830. The network 830 can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH® network, and the Internet. The network interface devices 826 can be configured to support any type of communications protocol desired. ™

[0071] ​The PU 808 can also be configured to access the display controller 828 over the system bus 814 to control information sent to one or more displays 832. The display controller 828 sends information to the display(s) 832 to be displayed via one or more video processors 834, which process the information to be displayed into a format suitable for the display(s) 832. As examples, the display controller 828 and video processor(s) 834 can be included in the same or different ICs, or included in the same IC 804 as the PU 808. The display(s) 832 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light-emitting diode (LED) display, etc.

[0072] Figure 5 An example wireless communication device 900 is illustrated that includes a radio frequency (RF) component and includes a power limiter circuit 902, 902(1) through 902(2) configured to determine a total processing unit power limit budget available to a processing unit based on any of the example processes 300, 500, 600 in Figure 6 、 Figure 1 and Figure 2 and the processor-based system can include, but is not limited to, the processor-based system 100 in Figure 1 and Figure 2 and / or the power limiter circuit 134 in Figure 9 and Figure 9 and in accordance with any of the aspects disclosed herein. As an example, the wireless communication device 900 can include or be disposed in any of the devices mentioned above. As shown in Figure 9 the wireless communication device 900 includes a transceiver 904 and a data processor 906, each of which can include its own power limiter circuit 902(1), 902(2). The data processor 906 can include a memory for storing data and program codes. The transceiver 904 includes a transmitter 908 and a receiver 910 that support bi-directional communication. In general, the wireless communication device 900 can include any number of transmitters 908 and / or receivers 910 for any number of communication systems and frequency bands. All or a portion of the transceiver 904 can be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0073] The transmitter 908 or receiver 910 can be implemented with a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, a signal is frequency converted between RF and baseband in multiple stages, e.g., for the receiver 910, in one stage from RF to an intermediate frequency (IF), and then in another stage from IF to baseband. In a direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures can use different circuit blocks and / or have different requirements. In ​ In the wireless communication device 900 of FIG. 1, the transmitter 908 and receiver 910 are implemented with a direct-conversion architecture.

[0074] In the transmit path, the data processor 906 processes data to be transmitted and provides I and Q analog output signals to the transmitter 908. In the exemplary wireless communication device 900, the data processor 906 includes digital-to-analog converters (DACs) 912(1), 912(2) to convert digital signals generated by the data processor 906 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0075] Within the transmitter 908, lowpass filters 914(1), 914(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 916(1), 916(2) amplify the signals from the lowpass filters 914(1), 914(2), respectively, and provide I and Q baseband signals. An upconverter 918 upconverts the I and Q baseband signals with I and Q TX local oscillator (LO) signals from a TX LO signal generator 922 through mixers 920(1), 920(2) to provide an upconverted signal 924. A filter 926 filters the upconverted signal 924 to remove undesired signals caused by the upconversion as well as noise in the receive band. A power amplifier (PA) 928 amplifies the upconverted signal 924 from the filter 926 to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 930 and transmitted via an antenna 932.

[0076] In the receive path, antenna 932 receives signals transmitted by base stations and provides a received RF signal, which is routed through duplexer or switch 930 and provided to low noise amplifier (LNA) 934. Duplexer or switch 930 is designed to operate with a particular receive (RX) to TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by LNA 934 and filtered by filter 936 to obtain a desired RF input signal. Down-conversion mixers 938(1), 938(2) mix the output of filter 936 with I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 940 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 942(1), 942(2) and further filtered by low pass filters 944(1), 944(2) to obtain I and Q analog input signals, which are provided to data processor 906. In this example, data processor 906 includes analog-to-digital converters (ADCs) 946(1), 946(2) to convert the analog input signals to digital signals to be further processed by data processor 906.

[0077] In ​ wireless communication device 900, TX LO signal generator 922 generates I and Q TX LO signals for up-conversion, while RX LO signal generator 940 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal having a particular base frequency. TX phase-locked loop (PLL) circuit 948 receives timing information from data processor 906 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from TX LO signal generator 922. Similarly, RX PLL circuit 950 receives timing information from data processor 906 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from RX LO signal generator 940.

[0078] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device or combination thereof. The memory disclosed herein can be of any type and size and can be configured to store data desired in any data type. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices made by the implementer, and / or design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0079] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0080] The aspects disclosed herein can be embodied in hardware and in instructions stored in hardware, and can reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a remote station. In the alternative, the processor and the storage medium can reside as discrete components in a remote station, a base station, or a server.

[0081] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0082] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0083] Specific implementation examples are described in the following numbered clauses:

[0084] 1. A power limiter circuit for limiting the power consumption of multiple processing units (PUs) in a processor-based system, the power limiter circuit being configured to:

[0085] (a) Determine the total PU power limit budget based on the difference between the overall power limit for the processor-based system and the power usage in the processor-based system;

[0086] (b) Receive multiple workload data indicating the workload activity of each of the plurality of PUs;

[0087] (c) Based on the workload data in the plurality of workload data corresponding to each of the plurality of PUs, allocate a power limit budget from the total PU power limit budget for each PU;

[0088] (d) Constrain the power consumption of each of the plurality of PUs within the allocated power limit budget determined for the PU;

[0089] (e) Determine the difference between the actual power consumption of each of the plurality of PUs and the power constraint budget for each PU; and

[0090] (f) reallocating a new power limit budget for each PU of the plurality of PUs from the total PU power limit budget based on the determined difference between the actual power consumption of each PU and the power limit budget for each PU.

[0091] 2. The power limiter circuit of clause 1, the power limiter circuit being further configured to set an operating point for a PU of the plurality of PUs based on the allocated power limit budget for the PU.

[0092] 3. The power limiter circuit of clause 1 or 2, the power limiter circuit being further configured to reset the operating point for the PU of the plurality of PUs based on the reallocated new power limit budget for the PU.

[0093] 4. The power limiter circuit of any of clauses 1 to 3, the power limiter circuit being configured to:

[0094] determine the difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU by being configured to:

[0095] receive a first actual power consumption of a first PU of the plurality of PUs;

[0096] compare the first actual power consumption to the power limit budget allocated to the first PU; and

[0097] determine a difference between the first actual power consumption and the power limit budget allocated to the first PU; and

[0098] reallocate the new power limit budget by being configured to:

[0099] reallocate the new power limit budget for the first PU from the total PU power limit budget based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and

[0100] reallocate at least one power limit budget from the total PU power limit budget for at least one second PU of the plurality of PUs based on a difference between the total PU power limit budget and the new power limit budget for the first PU.

[0101] 5. The power limiter circuit of clause 4, the power limiter circuit being configured to:

[0102] determining the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine whether the first actual power consumption is less than the power limit budget allocated to the first PU;

[0103] re-allocating the new power limit budget for the first PU from the total PU power limit budget based on increasing the power limit budget for the first PU in accordance with the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and

[0104] re-allocating the at least one power limit budget for the at least one second PU from the total PU power limit budget by being configured to increase the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU.

[0105] 6. The power limiter circuit of clause 4 or 5, the power limiter circuit being configured to:

[0106] determining the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine whether the first actual power consumption is greater than the power limit budget allocated to the first PU;

[0107] re-allocating the new power limit budget for the first PU from the total PU power limit budget based on increasing the power limit budget for the first PU in accordance with the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and

[0108] re-allocating the at least one power limit budget for the at least one second PU from the total PU power limit budget by being configured to decrease the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU.

[0109] 7. The power limiter circuit of any one of clauses 1 to 6, the power limiter circuit being further configured to:

[0110] receiving a performance adjustment event for a first PU of the plurality of PUs; and

[0111] in response to receiving the performance adjustment event for the first PU:

[0112] reallocate, for the first PU, a new power limit budget that is lower than the power limit budget allocated to the first PU; and

[0113] reallocate, for at least one second PU of the plurality of PUs, at least one new power limit budget based on a difference between the total PU power limit budget and the new power limit budget allocated to the first PU.

[0114] 8. The power limiter circuit of any of clauses 1-7, the power limiter circuit being further configured to:

[0115] (e) monitor the actual power consumption including an average power consumption of each PU of the plurality of PUs; and

[0116] (f) reallocate, for each PU of the plurality of PUs, the new power limit budget from the total PU power limit budget based on the monitored average power consumption of each PU of the plurality of PUs.

[0117] 9. The power limiter circuit of any of clauses 1-8, the power limiter circuit further comprising a power budget weight distribution circuit configured to:

[0118] (b) receive the plurality of workload data indicative of the workload activity of each PU of the plurality of PUs; and

[0119] (c) allocate, for each PU of the plurality of PUs, the power limit budget by being configured to:

[0120] determine a percentage weight of the total PU power limit budget of each PU of the plurality of PUs proportional to the workload activity of each PU of the plurality of PUs of a total workload activity of the plurality of workload data of the plurality of PUs; and

[0121] allocate, for each PU of the plurality of PUs, the power limit budget from the total PU power limit budget based on the percentage weight of each PU of the plurality of PUs.

[0122] 10. The power limiter circuit of any of clauses 1-9, the power limiter circuit further comprising a memory comprising a plurality of power limit budget registers, each power limit budget register configured to store the power limit budget for a PU of the plurality of PUs,

[0123] wherein:

[0124] the power limiter circuit is further configured to:

[0125] storing the allocated power limit budget for each PU of the plurality of PUs in a power limit budget register of the plurality of power limit budget registers assigned to the PU; and

[0126] accessing the stored power limit budget for each PU of the plurality of PUs in the plurality of power limit budget registers; and

[0127] the power limiter circuit is configured to cause the power consumption of each PU of the plurality of PUs to be constrained within the accessed stored power limit budget determined for each PU.

[0128] 11. The power limiter circuit of any one of clauses 1-10, the power limiter circuit configured to continuously repeat (a)-(f).

[0129] 12. The power limiter circuit of clause 11, the power limiter circuit configured to continuously repeat (a)-(f) in response to expiration of a timer reset to a constant time.

[0130] 13. The power limiter circuit of clause 11 or 12, the power limiter circuit configured to continuously repeat (a)-(f) in response to a power limit budget interrupt.

[0131] 14. The power limiter circuit of any one of clauses 11-13, the power limiter circuit further configured to disable the continuous repeating of (a)-(f) in response to a PU disable signal indicating an inactive operating state of the plurality of PUs.

[0132] 15. The power limiter circuit of any one of clauses 11-14, the power limiter circuit further configured to enable the continuous repeating of (a)-(f) in response to a PU enable signal indicating an active operating state of the plurality of PUs.

[0133] 16. The power limiter circuit of any one of clauses 1-15, the power limiter circuit further configured to receive power telemetry data comprising the power usage in the processor-based system.

[0134] 17. The power limiter circuit of clause 16, wherein the power telemetry data comprises power usage of a plurality of non-PU power consuming devices in the processor-based system.

[0135] 18. The power limiter circuit of any one of clauses 1-17, the power limiter circuit further comprising:

[0136] a power limit budget determining circuit configured to:

[0137] (a) determine the total PU power limit budget based on the difference between the overall power limit for the processor-based system and the power usage;

[0138] a power limit budget allocating circuit configured to:

[0139] (b) receive the plurality of workload data indicative of the workload activity of each PU of the plurality of PUs;

[0140] a power limit budget circuit configured to:

[0141] (c) allocate the power limit budget for each PU from the total PU power limit budget based on the workload data of the plurality of workload data corresponding to each PU of the plurality of PUs; and

[0142] (d) cause the power consumption of each PU of the plurality of PUs to be constrained within the allocated power limit budget determined for each PU;

[0143] a power consumption difference circuit configured to:

[0144] (e) determine the difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU; and

[0145] the power limit budget allocating circuit, the power limit budget allocating circuit being further configured to:

[0146] (f) reallocate the new power limit budget for each PU of the plurality of PUs from the total PU power limit budget based on the determined difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU.

[0147] 19. The power limiter circuit of any one of clauses 1-18, integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a transportation component; avionics; a drone; and a multicopter.

[0148] 20. A method of limiting power consumption of a plurality of processing units (PUs) in a processor-based system, the method comprising:

[0149] (a) determining a total PU power limit budget based on a difference between an overall power limit for the processor-based system and power usage in the processor-based system;

[0150] (b) receiving a plurality of workload data indicative of workload activity of each PU of the plurality of PUs;

[0151] (e) allocating a power limit budget from the total PU power limit budget for each PU based on workload data of the plurality of workload data corresponding to each PU of the plurality of PUs;

[0152] (d) causing power consumption of each PU of the plurality of PUs to be constrained within the allocated power limit budget determined for the PU;

[0153] (e) determining a difference between actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU; and

[0154] (f) reallocating a new power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the determined difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU.

[0155] 21. The method of clause 20, wherein causing the power consumption of each PU of the plurality of PUs to be constrained within the power limit budget determined for each PU comprises:

[0156] setting an operating point for a PU of the plurality of PUs based on the allocated power limit budget for the PU.

[0157] 22. The method of clause 20 or 21, the method further comprising resetting the operating point for the PU based on a newly allocated new power limit budget for the PU of the plurality of PUs.

[0158] 23. The method of any of clauses 20-22, wherein:

[0159] determining the difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU comprises:

[0160] receiving a first actual power consumption of a first PU of the plurality of PUs;

[0161] comparing the first actual power consumption to the power limit budget allocated to the first PU; and

[0162] determining a difference between the first actual power consumption and the power limit budget allocated to the first PU; and

[0163] re-allocating the new power limit budget comprises:

[0164] re-allocating the new power limit budget from the total PU power limit budget for the first PU based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and

[0165] re-allocating at least one power limit budget from the total PU power limit budget for at least one second PU of the plurality of PUs based on a difference between the total PU power limit budget and the new power limit budget for the first PU.

[0166] 24. The method of clause 23, the method comprising:

[0167] determining the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine whether the first actual power consumption is less than the power limit budget allocated to the first PU;

[0168] re-allocating the new power limit budget from the total PU power limit budget for the first PU based on reducing the power limit budget for the first PU according to the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and

[0169] reallocate the at least one power limit budget for the at least one second PU by being configured to increase the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU.

[0170] 25. The method of clause 23 or 24, the method comprising:

[0171] determine the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine whether the first actual power consumption is greater than the power limit budget allocated to the first PU;

[0172] reallocate the new power limit budget for the first PU from the total PU power limit budget based on increasing the power limit budget for the first PU according to the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and

[0173] reallocate the at least one power limit budget for the at least one second PU by being configured to decrease the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU.

[0174] 26. The method of any one of clauses 20 to 25, the method further comprising:

[0175] receiving a performance adjustment event for a first PU of the plurality of PUs; and

[0176] in response to receiving the performance adjustment event for the first PU:

[0177] reallocate for the first PU a new power limit budget that is lower than the power limit budget allocated to the first PU; and

[0178] reallocate to at least one second PU of the plurality of PUs at least one new power limit budget based on a difference between the total PU power limit budget and the new power limit budget allocated to the first PU.

[0179] 27. The method of any one of clauses 20 to 26, the method further comprising:

[0180] (e) monitor the actual power consumption including an average power consumption of each PU of the plurality of PUs; and

[0181] (f) reallocating, for each PU of the plurality of PUs, the new power limit budget from the total PU power limit budget based on the monitored average power consumption of each PU of the plurality of PUs.

[0182] 28. The method of any of clauses 20-27, further comprising: continuously repeating (a)-(f).

[0183] 29. The power limiter circuit of any of clauses 20-28, further configured to: receive power telemetry data comprising the power usage in the processor-based system.

[0184] 30. The method of clause 29, wherein the power telemetry data comprises power usage of a plurality of non-PU power consumption devices in the processor-based system.

[0185] 31. A processor-based system, comprising:

[0186] a plurality of non-processing unit (PU) power consumption devices;

[0187] a plurality of processing units (PUs);

[0188] a plurality of PU performance monitoring circuits, each PU performance monitoring circuit configured to:

[0189] monitor workload activity of a PU of the plurality of PUs;

[0190] generate workload data corresponding to the monitored workload activity of the PU of the plurality of PUs;

[0191] a plurality of power monitoring circuits, each power monitoring circuit configured to monitor actual power consumption of a PU of the plurality of PUs;

[0192] a plurality of power constraint circuits, each power constraint circuit configured to constrain power consumption of a PU of the plurality of PUs; and

[0193] a power limiter circuit configured to:

[0194] (a) determine a total PU power limit budget based on a difference between an overall power limit for the processor-based system and power usage of the plurality of non-PU power consumption devices;

[0195] (b) allocate, for each PU of the plurality of PUs, a power limit budget from the total PU power limit budget based on the workload data corresponding to each PU;

[0196] (c) instructing each power constrained circuit of the plurality of power constrained circuits to constrain the power consumption of a PU of the plurality of PUs within an allocated power limit budget for the PU;

[0197] (d) determining a difference between the actual power consumption of each PU of the plurality of PUs from the plurality of power monitoring circuits and the power limit budget for each PU; and

[0198] (e) reallocating a new power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the determined difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU.

[0199] 32. The processor-based system of clause 31, the processor-based system comprising:

[0200] a dynamic voltage and frequency scaling (DVFS) circuit configured to set an operating frequency and voltage for operation of a PU of the plurality of PUs;

[0201] the power limiter circuit, the power limiter circuit further configured to:

[0202] set an operating point for the PU of the plurality of PUs in the DVFS circuit based on the allocated power limit budget for the PU of the plurality of PUs.

[0203] 33. The processor-based system of clause 31 or 32, wherein the power limiter circuit is further configured to reset the operating point for the DVFS circuit of a plurality of DVFS circuits for a PU of the plurality of PUs based on the reallocated new power limit budget for the PU.

[0204] 34. The processor-based system of any of clauses 31 to 33, wherein the power limiter circuit is configured to:

[0205] determine the difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU by being configured to:

[0206] receive a first actual power consumption of a first PU of the plurality of PUs from a power monitoring circuit of the plurality of power monitoring circuits, the power monitoring circuit configured to monitor the actual power consumption of the first PU;

[0207] compare the first actual power consumption to the power limit budget allocated to the first PU; and

[0208] determining a difference between the first actual power consumption and the power limit budget allocated to the first PU; and

[0209] re-allocating the new power limit budget from the total PU power limit budget by being configured to:

[0210] re-allocating the new power limit budget for the first PU from the total PU power limit budget based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and

[0211] re-allocating at least one power limit budget for at least one second PU from the total PU power limit budget based on a difference between the total PU power limit budget and the new power limit budget for the first PU.

[0212] 35. The processor-based system of clause 34, wherein the power limiter circuit is configured to:

[0213] determining the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine whether the first actual power consumption is less than the power limit budget allocated to the first PU;

[0214] re-allocating the new power limit budget for the first PU from the total PU power limit budget based on reducing the power limit budget for the first PU based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and

[0215] re-allocating the at least one power limit budget for the at least one second PU from the total PU power limit budget by being configured to increase the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU.

[0216] 36. The processor-based system of clause 34 or 35, wherein the power limiter circuit is configured to:

[0217] determining the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine whether the first actual power consumption is greater than the power limit budget allocated to the first PU;

[0218] reallocate the new power limit budget for the first PU from the total PU power limit budget based on increasing the power limit budget for the first PU according to the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and

[0219] reallocate the at least one power limit budget for the at least one second PU from the total PU power limit budget by being configured to reduce the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU.

[0220] 37. The processor-based system of any one of clauses 31-36, the processor-based system further comprising:

[0221] a plurality of power consumption comparator circuits, each power consumption comparator circuit configured to:

[0222] generate a power difference signal between the power limit budget for a PU of the plurality of PUs and the actual power consumption for the PU of the plurality of PUs; and

[0223] a plurality of performance adjustment circuits, each performance adjustment circuit configured to:

[0224] generate a performance adjustment event for a PU of the plurality of PUs to have performance adjusted based on the power difference signal indicating that the actual power consumption for the PU exceeds the power limit budget for the PU;

[0225] the power limiter circuit, the power limiter circuit further configured to:

[0226] receive the performance adjustment event for a first PU of the plurality of PUs; and

[0227] in response to receiving the performance adjustment event for the first PU:

[0228] reallocate a new power limit budget for the first PU that is lower than the power limit budget allocated to the first PU; and

[0229] reallocate at least one new power limit budget for at least one second PU of the plurality of PUs based on a difference between the total PU power limit budget and the new power limit budget allocated to the first PU.

[0230] 38. The processor-based system of any one of clauses 31-37, wherein:

[0231] each of the plurality of power monitoring circuits is configured to monitor an average power consumption of a PU of the plurality of PUs; and

[0232] the power limiter circuit is configured to reallocate the new power limit budget from the total PU power limit budget for each of the plurality of PUs based on the monitored average power consumption of each of the plurality of PUs.

[0233] 39. The processor-based system of any one of Clauses 31-38, wherein the power limiter circuit is configured to continuously repeat (a)-(e).

[0234] 40. The processor-based system of any one of Clauses 31-39, integrated into a device selected from a group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a transportation component; avionics; a drone; and a multicopter.

Claims

1. A power limiter circuit for limiting power consumption of a plurality of processing units (PUs) in a processor-based system, the power limiter circuit configured to: (a) determine a total PU power limit budget based on a difference between an overall power limit for the processor-based system and power usage in the processor-based system; (b) receive a plurality of workload data indicative of workload activity of each PU of the plurality of PUs; (c) allocate a power limit budget from the total PU power limit budget for each PU based on workload data of the plurality of workload data corresponding to each PU of the plurality of PUs; (d) cause power consumption of each PU of the plurality of PUs to be constrained within the allocated power limit budget determined for the PU; (e) determine a difference between actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU; and (f) reallocate a new power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the determined difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU.

2. The power limiter circuit of claim 1, the power limiter circuit further configured to set an operating point for a PU of the plurality of PUs based on the allocated power limit budget for the PU.

3. The power limiter circuit of claim 2, the power limiter circuit further configured to reset the operating point for the PU based on the reallocated new power limit budget for the PU of the plurality of PUs.

4. The power limiter circuit of claim 1, the power limiter circuit configured to: determine the difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU by being configured to: receive a first actual power consumption of a first PU of the plurality of PUs; compare the first actual power consumption to the power limit budget allocated to the first PU; and determine a difference between the first actual power consumption and the power limit budget allocated to the first PU; and reallocate the new power limit budget by being configured to: reallocate the new power limit budget from the total PU power limit budget for the first PU based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and reallocate at least one power limit budget from the total PU power limit budget for at least one second PU of the plurality of PUs based on a difference between the total PU power limit budget and the new power limit budget for the first PU.

5. The power limiter circuit of claim 4, the power limiter circuit configured to: determining the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine whether the first actual power consumption is less than the power limit budget allocated to the first PU; re-allocating the new power limit budget for the first PU from the total PU power limit budget based on increasing the power limit budget for the first PU in accordance with the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and re-allocating the at least one power limit budget for the at least one second PU from the total PU power limit budget by being configured to increase the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU.

6. The power limiter circuit of claim 4, the power limiter circuit configured to: determining the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine whether the first actual power consumption is greater than the power limit budget allocated to the first PU; re-allocating the new power limit budget for the first PU from the total PU power limit budget based on increasing the power limit budget for the first PU in accordance with the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and re-allocating the at least one power limit budget for the at least one second PU from the total PU power limit budget by being configured to decrease the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU.

7. The power limiter circuit of claim 1, the power limiter circuit further configured to: receive a performance adjustment event for a first PU of the plurality of PUs; and in response to receiving the performance adjustment event for the first PU: re-allocate a new power limit budget for the first PU that is lower than the power limit budget allocated to the first PU; and re-allocate at least one new power limit budget for at least one second PU of the plurality of PUs based on a difference between the total PU power limit budget and the new power limit budget allocated to the first PU.

8. The power limiter circuit of claim 1, the power limiter circuit further configured to: (e) monitor the actual power consumption including an average power consumption of each PU of the plurality of PUs; and (f) re-allocate the new power limit budget for each PU of the plurality of PUs from the total PU power limit budget based on the monitored average power consumption of each PU of the plurality of PUs.

9. The power limiter circuit of claim 1, the power limiter circuit further comprising a power budget weight distribution circuit configured to: (b) receive the plurality of workload data indicative of the workload activity of each of the plurality of PUs; and (c) allocate the power limit budget for each of the plurality of PUs by being configured to: determine a percentage weight of the total PU power limit budget of each of the plurality of PUs to a total workload activity of the plurality of workload data of the plurality of PUs proportional to the workload activity of each PU; and allocate the power limit budget from the total PU power limit budget for each of the plurality of PUs based on the percentage weight of each of the plurality of PUs.

10. The power limiter circuit of claim 1, the power limiter circuit further comprising a memory comprising a plurality of power limit budget registers, each power limit budget register configured to store the power limit budget for a PU of the plurality of PUs, wherein: the power limiter circuit is further configured to: store the allocated power limit budget for each of the plurality of PUs in a power limit budget register of the plurality of power limit budget registers assigned to the PU; and access the stored power limit budget for each of the plurality of PUs in the plurality of power limit budget registers; and the power limiter circuit is configured to cause the power consumption of each of the plurality of PUs to be constrained within the accessed stored power limit budget determined for each PU.

11. The power limiter circuit of claim 1, the power limiter circuit configured to continuously repeat (a) through (f).

12. The power limiter circuit of claim 11, the power limiter circuit configured to continuously repeat (a) through (f) in response to a timer reset to a constant time expiring.

13. The power limiter circuit of claim 11, the power limiter circuit configured to continuously repeat (a) through (f) in response to a power limit budget interrupt.

14. The power limiter circuit of claim 11, the power limiter circuit further configured to disable the continuous repeating of (a) through (f) in response to a PU disable signal indicative of an inactive operating state of the plurality of PUs.

15. The power limiter circuit of claim 11, the power limiter circuit further configured to enable the continuous repeating of (a) through (f) in response to a PU enable signal indicative of an active operating state of the plurality of PUs.

16. The power limiter circuit of claim 1, the power limiter circuit further configured to receive power telemetry data comprising the power usage in the processor-based system.

17. The power limiter circuit of claim 16, wherein the power telemetry data comprises power usage of a plurality of non-PU power consuming devices in the processor-based system.

18. The power limiter circuit of claim 1, the power limiter circuit further comprising: a power limit budget determination circuit configured to: (a) determine a total PU power limit budget based on the difference between the overall power limit for the processor-based system and the power usage; a power limit budget allocation circuit configured to: (b) receive the plurality of workload data indicative of the workload activity of each of the plurality of PUs; a power limit budget circuit configured to: (c) allocate the power limit budget for each of the plurality of PUs from the total PU power limit budget based on the workload data of the plurality of workload data corresponding to each of the plurality of PUs; and (d) cause the power consumption of each of the plurality of PUs to be constrained within the allocated power limit budget determined for each of the plurality of PUs; a power consumption difference circuit configured to: (e) determine the difference between the actual power consumption of each of the plurality of PUs and the power limit budget for each of the plurality of PUs; and the power limit budget allocation circuit, the power limit budget allocation circuit further configured to: (f) reallocate the new power limit budget for each of the plurality of PUs from the total PU power limit budget based on the determined difference between the actual power consumption of each of the plurality of PUs and the power limit budget for each of the plurality of PUs.

19. The power limiter circuit of claim 1 integrated into a device selected from a group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a transportation component; avionics systems; a drone; and a multicopter.

20. A method of limiting power consumption of a plurality of processing units (PUs) in a processor-based system, the method comprising: (a) determining a total PU power limit budget based on a difference between an overall power limit for the processor-based system and power usage in the processor-based system; (b) receiving a plurality of workload data indicative of workload activity of each of the plurality of PUs; (c) allocating a power limit budget from the total PU power limit budget for each of the plurality of PUs based on workload data of the plurality of workload data corresponding to each of the plurality of PUs; (d) causing the power consumption of each of the plurality of PUs to be constrained within the allocated power limit budget determined for the PU; (e) determining a difference between the actual power consumption of each of the plurality of PUs and the power limit budget for each of the plurality of PUs; and (f) reallocating a new power limit budget from the total PU power limit budget for each of the plurality of PUs based on the determined difference between the actual power consumption of each of the plurality of PUs and the power limit budget for each of the plurality of PUs.

21. The method of claim 20, wherein causing the power consumption of each of the plurality of PUs to be constrained within the power limit budget determined for each of the plurality of PUs comprises: setting an operating point for a PU of the plurality of PUs based on the allocated power limit budget for the PU; resetting the operating point for the PU based on the reallocated new power limit budget for the PU of the plurality of PUs.

22. The method of claim 21, further comprising:

23. The method of claim 20, wherein: determining the difference between the actual power consumption of each of the plurality of PUs and the power limit budget for each of the plurality of PUs comprises: receiving a first actual power consumption of a first PU of the plurality of PUs; comparing the first actual power consumption to the power limit budget allocated to the first PU; and determining a difference between the first actual power consumption and the power limit budget allocated to the first PU; and reallocating the new power limit budget comprises: reallocating the new power limit budget from the total PU power limit budget for the first PU based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and reallocating at least one power limit budget from the total PU power limit budget for at least one second PU of the plurality of PUs based on a difference between the total PU power limit budget and the new power limit budget for the first PU.

24. The method of claim 23, the method comprising: determining the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine whether the first actual power consumption is less than the power limit budget allocated to the first PU; reallocating the new power limit budget from the total PU power limit budget for the first PU based on reducing the power limit budget for the first PU based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and ​ reallocate the at least one power limit budget for the at least one second PU by being configured to increase the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU.

25. The method of claim 23, the method comprising: determining the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine whether the first actual power consumption is greater than the power limit budget allocated to the first PU; reallocate the new power limit budget for the first PU from the total PU power limit budget based on increasing the power limit budget for the first PU according to the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and reallocate the at least one power limit budget for the at least one second PU by being configured to decrease the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU.

26. The method of claim 20, the method further comprising: receiving a performance adjustment event for a first PU of the plurality of PUs; and in response to receiving the performance adjustment event for the first PU: reallocate a new power limit budget for the first PU that is lower than the power limit budget allocated to the first PU; and reallocate at least one new power limit budget for at least one second PU of the plurality of PUs based on a difference between the total PU power limit budget and the new power limit budget allocated to the first PU.

27. The method of claim 20, the method further comprising: (e) monitoring the actual power consumption including an average power consumption of each PU of the plurality of PUs; and (f) reallocating the new power limit budget for each PU of the plurality of PUs from the total PU power limit budget based on the monitored average power consumption of each PU of the plurality of PUs.

28. The method of claim 20, further comprising: continuously repeating (a) through (f).

29. The power limiter circuit of claim 20, the power limiter circuit further configured to receive power telemetry data including the power usage in the processor-based system.

30. The method of claim 29, wherein the power telemetry data includes power usage of a plurality of non-PU power consumption devices in the processor-based system.

31. A processor-based system, the processor-based system comprising: a plurality of non-processing unit (PU) power consumption devices; a plurality of processing units (PUs); a plurality of PU performance monitoring circuits, each PU performance monitoring circuit configured to: monitor workload activity of a PU of the plurality of PUs; generating workload data corresponding to monitored workload activity of the PUs in the plurality of PUs; a plurality of power monitoring circuits, each power monitoring circuit configured to monitor actual power consumption of a PU in the plurality of PUs; a plurality of power constraint circuits, each power constraint circuit configured to constrain power consumption of a PU in the plurality of PUs; and a power limiter circuit configured to: (a) determine a total PU power limit budget based on a difference between an overall power limit for the processor-based system and power usage of the plurality of non-PU power consuming devices; (b) allocate a power limit budget from the total PU power limit budget for each PU in the plurality of PUs based on the workload data corresponding to each PU; (c) instruct each power constraint circuit in the plurality of power constraint circuits to constrain the power consumption of a PU in the plurality of PUs within the allocated power limit budget for the PU; (d) determine a difference between the actual power consumption of each PU in the plurality of PUs from the plurality of power monitoring circuits and the power limit budget for each PU; and (e) reallocate a new power limit budget from the total PU power limit budget for each PU in the plurality of PUs based on the determined difference between the actual power consumption of each PU in the plurality of PUs and the power limit budget for each PU.

32. The processor-based system of claim 31, the processor-based system comprising: a dynamic voltage frequency scaling (DVFS) circuit configured to set an operating frequency and voltage for operation of a PU in the plurality of PUs; the power limiter circuit further configured to: set an operating point for the PU in the plurality of PUs in the DVFS circuit based on the allocated power limit budget for the PU in the plurality of PUs.

33. The processor-based system of claim 32, wherein the power limiter circuit is further configured to reset the operating point for the DVFS circuit for a PU in the plurality of PUs based on the reallocated new power limit budget for the PU.

34. The processor-based system of claim 31, wherein the power limiter circuit is configured to: determine the difference between the actual power consumption of each PU in the plurality of PUs and the power limit budget for each PU by being configured to: receive a first actual power consumption of a first PU in the plurality of PUs from a power monitoring circuit of the plurality of power monitoring circuits, the power monitoring circuit configured to monitor the actual power consumption of the first PU; compare the first actual power consumption to the power limit budget allocated to the first PU; and determine a difference between the first actual power consumption and the power limit budget allocated to the first PU; and ​ reallocate the new power limit budget from the total PU power limit budget for the first PU based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and reallocate at least one power limit budget from the total PU power limit budget for at least one second PU of the plurality of PUs based on a difference between the total PU power limit budget and the new power limit budget for the first PU.

35. The processor-based system of claim 34, wherein the power limiter circuit is configured to: determine the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine whether the first actual power consumption is less than the power limit budget allocated to the first PU; reallocate the new power limit budget from the total PU power limit budget for the first PU based on reducing the power limit budget for the first PU based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and reallocate the at least one power limit budget for the at least one second PU from the total PU power limit budget based on increasing the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU.

36. The processor-based system of claim 34, wherein the power limiter circuit is configured to: determine the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine whether the first actual power consumption is greater than the power limit budget allocated to the first PU; reallocate the new power limit budget from the total PU power limit budget for the first PU based on increasing the power limit budget for the first PU based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU; and reallocate the at least one power limit budget for the at least one second PU from the total PU power limit budget based on decreasing the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU.

37. The processor-based system of claim 31, the processor-based system further comprising: a plurality of power consumption comparator circuits, each power consumption comparator circuit configured to: generate a power difference signal between the power limit budget for a PU of the plurality of PUs and the actual power consumption for the PU of the plurality of PUs; and a plurality of performance adjustment circuits, each performance adjustment circuit configured to: ​ generate a performance adjustment event to cause performance of a PU of the plurality of PUs to be adjusted based on the power difference signal indicating that the actual power consumption of the PU exceeds the power limit budget for the PU; the power limiter circuit, the power limiter circuit being further configured to: receive the performance adjustment event for a first PU of the plurality of PUs; and in response to receiving the performance adjustment event for the first PU: reallocate a new power limit budget for the first PU that is lower than the power limit budget allocated to the first PU; and reallocate at least one new power limit budget for at least one second PU of the plurality of PUs based on a difference between the total PU power limit budget and the new power limit budget allocated to the first PU.

38. The processor-based system of claim 31, wherein: each power monitor circuit of the plurality of power monitor circuits is configured to monitor average power consumption of a PU of the plurality of PUs; and the power limiter circuit is configured to reallocate the new power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the monitored average power consumption of each PU of the plurality of PUs.

39. The processor-based system of claim 31, wherein the power limiter circuit is configured to continuously repeat (a) through (e).

40. The processor-based system of claim 32, integrated into a device selected from a group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a transportation component; avionics; a drone; and a multicopter.

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