Shock absorber utilization
By employing a multi-stage approach and different raster scan sequences in a single buffer, the problem of excessive memory requirements of the ping-pong buffer is solved, achieving more efficient buffer utilization and throughput.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-03
- Publication Date
- 2026-03-27
AI Technical Summary
Ping-pong buffers require two buffers, which increases memory resource requirements, becoming a significant drawback, especially in environments with limited memory capacity.
A multi-stage approach is adopted, using a single buffer to write and read image data samples through different arrangements (such as block-based and row-based raster scan orders), and optimizing buffer utilization through selective address allocation.
This reduces memory resource requirements while maintaining the throughput of the ping-pong buffer, resulting in more efficient buffer utilization.
Smart Images
Figure CN121753059A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for writing image data samples and reading image data samples from a buffer. Background Technology
[0002] A ping-pong buffer uses two buffers, and while one buffer is being read from, the other is being written to. By alternating the operation of the buffers, data can be written to one buffer and read from the other simultaneously, preventing unwanted rewriting of the data in the buffers and allowing for a smooth data flow.
[0003] Despite its advantages, the ping-pong buffer has several significant drawbacks. Primarily, the need for two separate buffers necessitates additional memory resources, which can be a considerable disadvantage in environments with limited memory capacity.
[0004] Therefore, there is an urgent need for a method that retains the advantages of ping-pong buffers while addressing at least one of their inherent disadvantages. Summary of the Invention
[0005] This document provides a method for writing image data samples received in a first arrangement to a buffer and reading image data samples from the buffer to create a second arrangement. The writing and reading of image data samples are performed using multiple stages, as well as the first and second arrangements, each stage including a selective address allocation according to that stage.
[0006] According to a first aspect of the invention, a method is provided for writing image data samples received in a first arrangement to a buffer and reading image data samples from the buffer to create a second arrangement. The first arrangement differs from the second arrangement. The method includes: during a first stage: writing each image data sample of a first data portion of an image data sample received in the first arrangement to a buffer; during a second stage: reading each image data sample from the buffer from the first data portion of the image data sample by determining a corresponding second-stage buffer address for each read operation according to the first arrangement and the second arrangement, such that each image data sample of the first data portion is read according to the second arrangement; writing each image data sample of a second data portion of the image data sample to the buffer by determining a corresponding buffer address for each write operation as a second-stage buffer address for reading a corresponding image data sample in the first data portion; wherein writing is at least one buffer address after reading; and during a third stage: reading each image data sample from the buffer from the buffer by determining a corresponding third-stage buffer address according to the second stage, the first arrangement, and the second arrangement, such that each image data sample of the second data portion is read according to the second arrangement of the image data sample.
[0007] In this way, compared with the dual-buffer solution of ping-pong buffers, improved buffer utilization is provided, thereby mitigating the previously prominent drawbacks such as additional memory resource requirements, while maintaining the throughput of the ping-pong buffer arrangement.
[0008] Preferably, the first arrangement is based on a block-based raster scan order. In this way, the invention disclosed herein can be used with image processing applications that output image data samples in a block-based raster scan order.
[0009] Preferably, the second arrangement is based on a row-based raster scan order. In this way, the invention disclosed herein can be used in image processing applications that require image data samples in a row-based raster scan order.
[0010] Preferably, the corresponding second-stage buffer address for each read operation is determined based on the block size of the block-based raster scan order and the row size of the row-based raster scan order.
[0011] Preferably, during the second stage, for a read operation that immediately follows a read operation of a row in the row-based raster scan sequence of the second arrangement, the corresponding second stage buffer address is determined to be the block width following the corresponding buffer address of the first read operation of the row.
[0012] Preferably, during the second stage, for a read operation that has been completed after a read operation sequence equal to the block width in a row based on the raster scan order but before the row read operation is completed, the corresponding buffer address of the read operation is determined to be the block following the corresponding buffer address of the first read operation in the read operation sequence.
[0013] Preferably, the address of the corresponding third-stage buffer for each read operation is determined based on the block size and the row size.
[0014] Preferably, during the third stage, for a read operation that immediately follows a read operation that completes a row-based raster scan sequence in the second arrangement, the corresponding third stage buffer address is determined as the block of the corresponding buffer address of the first read operation of the row in the row-based raster scan sequence.
[0015] Preferably, during the third stage, for a read operation that has been completed after a read operation sequence of read operations equivalent to the block width in a row based on the row raster scan order but before the row read operation is completed, the third stage buffer address corresponding to the read operation is half of the block of the corresponding buffer address of the first read operation in the read operation sequence.
[0016] Preferably, the first arrangement is based on a row-based raster scan order, and the second arrangement is based on a block-based raster scan order.
[0017] Preferably, during the second stage, for the first read operation, the corresponding second stage buffer address is determined as the first buffer address used to write the image data sample in the first stage.
[0018] Preferably, during the third stage, for the first read operation, the corresponding third stage buffer address is determined as the first buffer address used to write the image data sample in the second stage.
[0019] Preferably, the reading and writing in the second stage are performed simultaneously.
[0020] Preferably, during the first phase, writing includes writing each image data sample of the first data portion received in the first arrangement into the buffer in raster scan order.
[0021] According to a second aspect of the invention, a hardware module is provided, comprising a buffer, write logic, and read logic, wherein the hardware module is configured to perform any of the method steps stated above.
[0022] According to a third aspect of the invention, a computer-readable storage medium is provided that includes instructions which, when executed by a processor, cause the processor to perform any of the aforementioned method steps. Attached Figure Description
[0023] The invention will now be described by way of example only with reference to the accompanying drawings, in which:
[0024] Figure 1 It is a block diagram depicting the arrangement of ping-pong buffers; Figure 2 It is a block diagram depicting a single buffer arrangement according to an embodiment of the present invention; Figure 3 It is a description based on Figure 2 A block diagram showing the use of a single buffer arrangement to process the input stream; and Figure 4 Depicting according to Figure 2 The functionality of the control logic for a single buffer arrangement. Detailed Implementation
[0025] Figure 1 A ping-pong buffer arrangement 100 is depicted. The ping-pong buffer arrangement 100 receives an input stream 110 including image data samples and outputs an output stream 120 that also includes image data samples. The ping-pong buffer arrangement 100 includes two buffers, namely buffer 130 and buffer 140. Furthermore, the ping-pong buffer arrangement 100 includes write logic 150, read logic 160, and control logic 170.
[0026] Image data samples in this article refer to data representing pixels in an image or video frame. Image data samples may contain any of the following pixel-specific attributes: color, intensity, or others.
[0027] Buffers 130 and 140 operate one after the other, with one being written to (from input stream 110) and the other being read from (feeding to output stream 120). The alternating write and read operations of buffers 130 and 140 optimize the data flow, thereby ensuring no interruption or delay in processing, while preventing unwanted data in the buffers from being overwritten.
[0028] Furthermore, write logic 150 manages the process of storing data from input stream 110 in these buffers based on the operating state of buffer 130 or buffer 140. Conversely, read logic 160 manages reading data from non-write buffers to feed output stream 120.
[0029] Control logic 170 controls the changing states of buffers 130 and 140, write logic 150, and read logic 160 to ensure that the write and read processes are always separated in different buffers, in order to maintain data integrity and prevent rewriting or data loss.
[0030] While ping-pong buffers have advantages, they also have significant disadvantages. For example, maintaining two separate buffers (buffers 130 and 140) requires additional memory resources, which can be a significant drawback in memory-constrained environments.
[0031] Figure 2 This is a block diagram depicting a single buffer arrangement 200 according to an embodiment of the present invention. Similar to the ping-pong buffer arrangement 100, the single buffer arrangement 200 receives an input stream 110 and outputs an output stream 120. Likewise, similar to the ping-pong buffer arrangement 100, the single buffer arrangement 200 includes write logic 250, read logic 260, and control logic 270. However, unlike the ping-pong buffer arrangement 100, the single buffer arrangement 200 includes a single buffer (buffer 230).
[0032] A single buffer arrangement 260 implements a multi-stage method for writing image data samples received in a first arrangement into buffer 230 and reading image data samples received in a different second arrangement from the same buffer 230.
[0033] The arrangement of image data samples refers to the order in which image data samples are received or generated, respectively, from or to a data stream. The first arrangement and the second arrangement refer to the order of image data samples in a block-based raster scan order, a line-based raster scan order, or any other specific order. The first and second arrangements are different arrangements, allowing the buffer arrangement 200 to be used for bridging between two systems that process image data samples in different ways. For example, a block-by-block encoder or decoder may output image data samples in the data stream based on a block-based raster scan order, while a display output may require outputting those same image data samples in the data stream in a line-based raster scan order.
[0034] In this example, the first arrangement is based on a block-based raster scan order, and the second arrangement is based on a row-based raster scan order.
[0035] The multi-stage method operates as follows: In the first phase of this method, write logic 250 coordinates the writing of each image data sample of the first data portion of the input stream 110 received in the first arrangement to buffer 230. Here, the data portion refers to a subset of the image data samples received at buffer 230 for processing. Typically, the data portion consists of valuable image data samples of the buffer; that is, the image data portion comprises the same number of image data samples as the buffer has a buffer address.
[0036] In this example, the writing process involves writing each image data sample, received in the first arrangement, into buffer 230 in raster scan order. However, any other order may be used.
[0037] During the second phase, read logic 260 coordinates the reading of each image data sample from the first data section from buffer 230. A specific buffer address for each read operation is determined by considering a first and a second arrangement of the image data samples to ensure that each image data sample from the first data section is read from buffer 230 to formulate output stream 120 according to the second arrangement.
[0038] In parallel with the second-stage read operation, write logic 250 coordinates the writing of each image data sample from the second data portion of the input stream 110 to a buffer, wherein the buffer address for each write operation is the same as the buffer address used to read the corresponding image data sample from the first data portion. Control logic 270 is configured to ensure that a write operation always occurs at least one buffer address after a read operation to prevent data corruption.
[0039] In this example, the buffer address for each read operation during the second phase is determined based on the block size of the block-based raster scan order and the row size of the row-based raster scan order. However, those skilled in the art will recognize that other sizes may be used depending on the specific arrangement employed to produce output stream 120 in the second arrangement.
[0040] In this example using block-based raster scan input and row-based raster scan output, for a read operation immediately following a read operation of a row in the second row-based raster scan sequence, the buffer address for the read operation is the block width immediately following the buffer address for the first read operation of the row.
[0041] Next, for a read operation that has been completed but not yet completed after a read operation of a sequence of read operations equal to the block width in a row based on the raster scan order, the buffer address of the read operation is the block from the corresponding buffer address of the first read operation in the read operation sequence.
[0042] The buffer address used for the first read operation in the second stage is the same buffer address used for writing image data samples in the first stage.
[0043] In this example, the read and write operations in the second phase are simultaneous.
[0044] In the third stage, read logic 260 coordinates the reading of each image data sample from the second data portion of the image data samples. The buffer address for each read operation is determined based on the second stage determination, the first arrangement, and the second arrangement, such that each image data sample of the second data portion is read according to the second arrangement.
[0045] In this example, the buffer address for each read operation is the block size and row size, respectively, based on the first and second layouts. Other sizes may be used based on the first and second layouts.
[0046] In this example using block-based raster scan input and row-based raster scan output, for a read operation immediately following a read operation that completes a row read operation in the second row-based raster scan sequence, the buffer address of the read operation is a block from the corresponding buffer address of the first read operation for a row in the row-based raster scan sequence.
[0047] Next, for a read operation that has been completed but not completed after a read operation sequence of read operations equivalent to the block width in a row based on the row raster scan order, the buffer address of the read operation is the block from the corresponding buffer address of the first read operation in the read operation sequence.
[0048] The buffer address used for the first read operation in the third stage is the same buffer address used for writing image data samples in the second stage.
[0049] Compared to the dual-buffer solution of the ping-pong buffer, the single buffer arrangement 200 consisting of a single buffer 230 provides an improved data management approach, thereby mitigating previously prominent drawbacks such as additional memory resource requirements while maintaining the throughput of the ping-pong buffer.
[0050] Figure 3 The diagram depicts the use of a single buffer arrangement 200 to process the input stream 110. Figure 3 In this process, the input stream 110 is fed into a single buffer arrangement 200, which is then configured with respect to... Figure 2 The described method generates output stream 120. Input stream 110 includes image data samples in a first arrangement, and output stream 120 includes image data samples in a different second arrangement.
[0051] exist Figure 3 The image shows input surface 310 to illustrate a first arrangement configured with a block-based raster scan sequence. Figure 3The diagram illustrates an output surface 320 to illustrate a second arrangement configured in a row-based raster scan order. It should be noted that these are merely illustrative examples. In other cases, the first arrangement may be based on a row-based raster scan order, while the second arrangement may be based on a block-based raster scan order. As those skilled in the art will understand, other types of data arrangements may also be employed. A block-based raster scan order refers to a scheme in which image data samples are processed (e.g., generated, written, or read) within blocks in a raster scan order, and each block itself is processed in a raster scan order. A row-based raster scan order refers to a scheme in which image data samples are processed (e.g., generated, written, or read) row by row.
[0052] To further illustrate, image data samples from the input surface 310 are processed according to a block-based raster scan order. References B1, B2, B3, B4, B5, and B6 are used on the input surface 310 to illustrate the block-based raster scan order. Arrows on the input surface 310 indicate the sequence in which image data samples appear in the input stream 110, and thus the sequence of image data samples is fed to the single buffer arrangement 200 via the input stream 110. Therefore, the image data sample located at the upper left corner of the input surface 310, in block B1, will be received and processed first by the single buffer arrangement 200, while the image data sample at the upper right corner of block B2 will follow the image data sample at the lower left corner of block B1, and so on. The lower right corner of the input surface 310 is the last in the block-based raster scan arrangement and is the last one to be passed to the single buffer arrangement 200 in the input stream 110.
[0053] The output surface 320 is filled with image data samples according to the row-based raster scan sequence. The rows of the row-based raster scan sequence are illustrated on the output surface 320 using references L1, L2, L3, L4, L5, and L6, arranged sequentially from top to bottom. Arrows on the output surface 320 indicate the sequence in which image data samples leave the single buffer arrangement 200 to form the output stream 120. Therefore, the image data sample residing in the upper left corner of the output surface 320 in the row-based raster scan sequence will be the first to exit the single buffer arrangement 200 for the output surface 320, while the first image data sample residing in the leftmost part of row L2 follows the final image data sample of the previous row L1. The final sample to be read from the buffer 230 for the output surface 320 will be the image data sample occupying the lower right corner of the output surface 320.
[0054] The write logic 250, read logic 260, and control logic 270 of a single buffer arrangement 200 manage the writing of image data samples from the input stream 110 to the buffer 230 and the reading of image data samples from the buffer 230 to create the output stream 120. This is achieved through implementation as described above... Figure 2 The multi-stage method for writing and reading image data samples outlined in the text allows for the generation of an output stream 120 with a different image data sample arrangement compared to the arrangement of image data samples in the input stream 110.
[0055] Figure 4 The functionality of the control logic 270 for a single buffer arrangement 200 is described. The control logic 270 manages the operations of the write logic 250 and the read logic 260.
[0056] Each complete write to buffer 230 defines a write cycle. Each complete read from buffer 230 defines a read cycle. According to an exemplary embodiment having a block-based raster scan order arranged as an input stream, the number of write and read cycles required to process an image or frame by buffer arrangement 200 is determined by the ratio of image / frame height to block height, as this ratio indicates how many write and read cycles the buffer will undergo to process a single image / frame.
[0057] Phase 1 - Write Only When control logic 270 is reset, for example when a new image or frame is about to be processed by a single buffer arrangement 200, control logic 270 enters phase 1, in which the write state is set to active (WRITE_ACTIVE) and the read state is paused (READ_WAIT). This causes a portion of the input stream 110 to be written to buffer 230, which typically has the same size as buffer 230. After buffer 230 is filled for the first time (which signals the end of phase 1), the write state transitions to the paused state (WRITE_WAIT), and control logic 270 then transitions to phase 2.
[0058] Phase 2 - Pseudo-simultaneous Read and Write When the write state transitions to the paused state (WRITE_WAIT), the read state transitions to the active state (READ_ACTIVE), causing reads from buffer 230 to begin in the order of creating the second arrangement from the data samples written in buffer 230, and the write state transitions back to the active state (WRITE_ACTIVE), which in turn causes the next portion of the input stream to be written to buffer 230. The buffer address for each read and write is determined as explained elsewhere in this disclosure. For simplicity, each corresponding write (e.g., the third write operation of this portion) is for the buffer address from which the corresponding read is performed (e.g., the buffer address of the third read of the previous portion).
[0059] Stage N - Read Only During the final stage N, the state machine activates a read state to read the last part of the input stream.
[0060] Except for the first phase, the read and write phases begin simultaneously. The first write phase begins when the read process is inactive (READ_WAIT).
[0061] Additionally, if a cell in buffer 230 has not been read during a phase (e.g., a read / write cycle), the scheme does not allow image data samples to be written to that cell. To do this, the number of read and write operations in each phase is counted, and writing is allowed when the write count is less than the read count.
[0062] Work Example To provide a working example of the above principle, an exemplary input stream or frame is presented, wherein image data values are received or arranged in a block-based raster scan order. Those skilled in the art will understand based on... Figures 2 to 4 As will be clear from the description, after processing by a single buffer arrangement 200, an exemplary output stream or frame with, for example, image data samples in a row-based raster scan order will be generated.
[0063] The following illustrates an exemplary input stream or frame divided into four data portions to demonstrate how data is written to buffer 230 in each write loop (each data portion is the same size as buffer 230). In this example, each data portion includes two 8×8 image data sample blocks. Each data portion includes an image data value that will depend on the actual image data represented. To illustrate a change from a first arrangement such as a block-based raster scan order to a second arrangement such as a row-based raster scan order, the exemplary input stream uses image data values corresponding to the positions of the image data values within the frame. For example, the image data value "1" will be found in the top-left corner of the frame initially created and / or output for viewing, while the image data value "16" will be found in the top-right corner of the frame initially created and / or output for viewing. enter: First Data Section
[0064] enter: Second Data Section
[0065] enter: Third Data Section
[0066] enter: Fourth Data Section
[0067] An example input stream or frame is received by a single buffer arranged in 200 sequences (i.e., in the order in which they are received).
[0068] The following are exemplary output streams or reframes shown in the four data sections to illustrate the output of each read loop.
[0069] Output: First Data Section
[0070] Output: Second Data Section
[0071] Output: Third Data Section
[0072] Output: Fourth Data Section
[0073] As can be seen, data samples are read from the buffer in a second arrangement corresponding to the row-based raster scan order. In other words, in this example, the image data samples are rearranged at the output to be in their original or output positions. Of course, some processing may be unknown to the actual input or output arrangement, but these arrangements are known so that the read and write addresses are determined during each stage.
[0074] Typically, in a decoder pipeline, image data samples are output sequentially by the decoding process in a block-based raster scan order, but subsequent processing requires output in a row-based raster scan order.
[0075] The following paragraphs provide information on... Figures 2 to 4 More details on the above working example in the context of the stages discussed in the article.
[0076] Phase 1 - Write Only The first stage is a write-only stage, in which the first portion of the input data is written to buffer 230. The first stage ends when the buffer is full.
[0077] Image data samples are stored in a buffer in a block-based raster scan order.
[0078] The state of buffer 230 at the end of phase 1 is as follows: (Italic numbers are buffer addresses, and bold numbers are...) Image data values within the buffer
[0079] Phase 2 - Pseudo-simultaneous Read and Write In the second stage, the output value is read from buffer 230 to generate the second output data portion (described in more detail below). The same buffer address is then used to write the corresponding next data value from the next data portion of the input stream or frame (e.g., if the first data sample of the output portion of the data stream is read, the buffer address is used for the first data sample of the next input portion; if the tenth data sample of the output portion of the data stream is read, the buffer address is used for the tenth data sample of the next input portion, and so on).
[0080] The first buffer address (read address) read in stage 2 is address 0, and the read address value is incremented by 1 until read address 7, which is the end of the line in a block of 8 data samples in the input data stream.
[0081] Output: The first data section – showing the end of a sample of block image data
[0082] The image data samples highlighted in bold in the first data section of the output frame are samples located at the end of each line in the corresponding block of the input data stream or frame.
[0083] When buffer address 7 is read, the next required data sample in the first input data portion stored in buffer 230 (indicated by image data sample = 9, showing the position of the image data sample in the original image frame) is exactly one block away from buffer address 0 (the block is 8×8 data samples = 64). Buffer address 0 is the beginning of the current line being read in buffer 230, and a block-size jump is performed to reach the next output.
[0084] Jump = Block size = 64 Read buffer address 64, then increment the buffer address by 1, and read each data value until the next end of the line in the block is reached (i.e., 7 data reads after buffer address 64). After 7 data reads, the end of the line in the first output data section is reached, and another jump is required to read the next image data sample according to the line-based raster scan order.
[0085] Output: First data section - shows the end of the first output data section of the row.
[0086] The image data samples shown in bold above are image data samples located at the end of the rows in the first output data section.
[0087] The next output value required for the output frame is in buffer address 8 in buffer 230. Buffer address 8 in buffer 230 is the block width away from the starting point of buffer 230 at buffer address 0 (buffer address 0 also corresponds to the beginning of the line in the output data portion that has just been filled).
[0088] start_of_line(0) = 0 Therefore, the address of the next buffer read is determined based on the following: start_of_line(1) = start_of_line(0) + block width = 8 The invention is extended to the end of each calculation of the next buffer address for the row in this phase: start_of_line(i) = start_of_line(i-1) + block width Following this example, execution proceeds by incrementing address 8 in buffer 230 by 1 until the end of the line in the block is reached (i.e., 8 reads), which ends at address 15. Similarly, a jump of the block size from the beginning of the current line in the block (address 8) is performed. 8 + 64 = 72, this address stores the value 25, which is the next output sequence. Again, the buffer address is incremented by 1 until the end of the line in the block is reached (another 7 reads), which is also the end of the line in the output data portion. The address to the next start_of_line is updated as follows: start_of_line(2) = start_of_line(1) + block width start_of_line(2) = 8 + 8 = 16 The next address after 79 is 16, which has the correct output value.
[0089] Repeat the above process until all values in the buffer have been read. A single buffer arrangement tracks how many values have been read by, for example, using a read counter.
[0090] After the buffer address in the buffer is read, the next corresponding data value in the next input data part can be written to the same buffer address.
[0091] Additionally, if a cell in buffer 230 has not been read during a phase (e.g., a read / write cycle), the scheme does not allow image data samples to be written to that cell. To do this, the number of read (using a read counter) and write operations in each phase is counted, and writing is allowed when the write count is less than the read count.
[0092] The buffer at the end of Phase 2 will look like this:
[0093] Phase 3 - Pseudo-simultaneous Read and Write The read begins at buffer address 0, and the address value increments by 1 in each clock cycle until it reaches address 7 (holding value 136), which is the address when the end of the line in the block is reached. Then, a jump is performed.
[0094] The next output value is 137, which is now in buffer address 32. The value 137 in the input frame represents a block halfway from the beginning of the current line. In the previous stage, a jump was performed to reach the next line in the block when the end of a line in the block was reached. Now, to obtain the value of the block size in the previous stage, a new jump must be calculated: Jump = previous_jump Block width.
[0095] Jump = block size Block width The result of multiplication must not exceed the maximum value that the buffer can handle, i.e.: (buffer width) Block width - block width). Therefore, jump = (previous_jump) Block width) % (Buffer width) (block width - block width) Jump = 64 8% (16) 8 – 8) = 32 Starting from buffer address 32, this address is incremented by 1 until the next end of the line in the block is reached, which is also the end of the line, i.e., address 39.
[0096] The next output value is 145. This value is the line of the block furthest from the start of the current line in the input. During the previous write of this value in the buffer of the previous stage, previous_jump = 64 is executed to reach the next line of the block. In this stage, start_of_line is calculated: start_of_line(0) = 0 start_of_line(i) = start_of_line(i-1) + 64 start_of_line(1) = 64 In summary: start_of_line(i) = start_of_line(i-1) + previous_jump) % (Width of buffer) (block width - block width) Modular operations are also applied to the calculation of start_of_line to ensure that the multiplication result does not exceed the maximum value that start_of_line can take.
[0097] Repeat the above process until the end of the current stage is reached, and then begin the next stage with a new jump value. Processing continues in each stage until the end of the frame is reached (i.e., stage N).
[0098] In this implementation, to generalize the method and avoid special cases, the first phase is treated the same as other phases, and the jump and start of the lines for the first phase are defined.
[0099] Based on the explanations in this and the last chapter, these are examples of frame transitions and the calculation of the starting line. value:
[0100] This is what the buffer will look like after the first stage: (Italic numbers are buffer addresses, and bold numbers are...) (The number is the value inside the buffer)
[0101] The address used for writing in phase 1:
[0102] Buffer after Phase 2:
[0103] The addresses used for reading and writing in phase 2:
[0104] Buffer after Phase 3:
[0105] The addresses used for reading and writing in phase 3:
[0106] The addresses used for reading and writing in phase 4:
[0107] The processing of each of the above stages continues until the end of the frame or stream is reached (i.e., stage N).
[0108] Avoid MODs As discussed earlier, to ensure that the value calculated for the jump does not exceed (the width of the buffer) (Block width - block width) requires a modulo operation. Modulo operations are expensive, and in the LCEVC implementation, with 16 rasterizers (single buffer array modules) per quality level, having modulo blocks within the rasterizers is impractical. Furthermore, it's impossible to perform subtraction to obtain the same result as using modulo operations, as 16 adders are needed in each rasterizer.
[0109] To address the aforementioned issue, jump values are calculated and stored (within a register array) for future jump calculations.
[0110] In some implementations, the rasterizer must be able to handle input streams with different block sizes. The rasterizer receives the block dimensions and writes to and reads from the input stream accordingly. Examples of this implementation are DD and DDS transforms, where the input stream associated with the DD transform includes a different block dimension than the input stream of the DDS transform.
[0111] The above embodiments should be understood as illustrative examples. Other embodiments are contemplated. It should be understood that any feature described with respect to any embodiment may be used alone or in combination with other described features, and may also be used in combination with one or more features of any other embodiment or any combination of any other embodiment. Furthermore, equivalents and modifications not described above may be employed without departing from the scope of the invention as defined by the appended claims.
Claims
1. A method for writing image data samples received in a first arrangement to a buffer and reading the image data samples from the buffer to create a second arrangement, wherein the first arrangement is different from the second arrangement, the method comprising: During the first phase: Each image data sample of the first data portion of the image data samples received in the first arrangement is written to the buffer; During the second phase: Each image data sample from the first data portion of the image data sample is read from the buffer by determining the corresponding second-stage buffer address for each read operation according to the first arrangement and the second arrangement, such that each image data sample of the first data portion is read according to the second arrangement; Each image data sample of the second data portion of the image data sample is written to the buffer by determining the corresponding buffer address of each write operation as the second-stage buffer address for reading the corresponding image data sample in the first data portion; The write refers to at least one buffer address following the read; and During the third phase: Each image data sample of the second data portion of the image data sample is read from the buffer by determining the corresponding third-stage buffer address according to the second stage determination, the first arrangement, and the second arrangement, such that each image data sample of the second data portion is read according to the second arrangement of the image data sample.
2. The method of claim 1, wherein the first arrangement is based on a block-based raster scan sequence.
3. The method of claim 2, wherein the second arrangement is based on a row-based raster scan order.
4. The method of claim 3, wherein the corresponding second-stage buffer address is determined for each read operation based on the block size of the block-based raster scan order and the row size of the row-based raster scan order.
5. The method of claim 4, wherein during the second stage, for a read operation immediately following a read operation of a row in the row-based raster scan sequence of the second arrangement, the corresponding second-stage buffer address is determined as the block width following the corresponding buffer address of the first read operation of the row.
6. The method according to claim 4 or 5, wherein during the second stage, for a block after a read operation of a read operation sequence equal to the block width in the row based on the raster scan order has been completed but before the read operation of the row has been completed, the corresponding buffer address of the read operation is determined to be the block after the corresponding buffer address of the first read operation of the read operation sequence.
7. The method according to any one of claims 4 to 6, wherein the corresponding third-stage buffer address is determined for each read operation based on the block size and the row size.
8. The method of claim 7, wherein during the third stage, for a read operation immediately following a read operation of a row in the row-based raster scan sequence of the second arrangement, the corresponding third stage buffer address is determined as a block of the corresponding buffer address of the first read operation of the row in the row-based raster scan sequence.
9. The method according to any one of claims 7 or 8, wherein during the third stage, for a read operation after a read operation of a sequence of read operations equivalent to the block width in the row based on the raster scan order but before the read operation of the row is completed, the corresponding third-stage buffer address of the read operation is half of the block of the corresponding buffer address of the first read operation of the read operation sequence.
10. The method of claim 1, wherein the first arrangement is based on a row-based raster scan order, and the second arrangement is based on a block-based raster scan order.
11. The method according to any of the preceding claims, wherein during the second stage, for the first read operation, the corresponding second stage buffer address is determined as the first buffer address for writing image data samples in the first stage.
12. The method according to any of the preceding claims, wherein during the third stage, for the first read operation, the corresponding third stage buffer address is determined as the first buffer address for writing image data samples in the second stage.
13. The method according to any of the preceding claims, wherein the reading and writing in the second stage are simultaneous.
14. The method according to any preceding claim, wherein during the first stage, the writing comprises writing each image data sample of the first data portion received in the first arrangement into the buffer in raster scan order.
15. A hardware module comprising a buffer, write logic, and read logic, wherein the hardware module is configured to perform the method according to any of the preceding claims.
16. A computer-readable storage medium comprising instructions that, when executed by a processor, perform the method according to any one of claims 1 to 14.