Manufacturing method of semiconductor strain gauge and semiconductor strain gauge

Abstract

The invention discloses a manufacturing method of a semiconductor strain gauge. The manufacturing method comprises the following steps: S1, epitaxially growing a boron-doped silicon epitaxial layer on a (110)-oriented P-type monocrystalline silicon substrate; s2, depositing a passivation layer on the surface of the epitaxial layer in the step S1; s3, exposing the position where metal deposition needs to be carried out through a first photoetching step; s4, depositing an aluminum metal layer on the surface of the epitaxial layer exposed in the step S3 to form a metal short circuit part and a lead bonding pad; s5, patterning the passivation layer through a third photoetching step to form a hard mask pattern for deep silicon etching; and S6, performing deep reactive ion etching to form a strain gauge wire grid. The strain gauge is simple in structure, can be reduced in size, and is suitable for the fields of force sensors, pressure sensors, miniature force measurement assemblies and the like.

Description

Technical Field

[0001] This invention relates to the field of miniature force / torque sensor technology, and more specifically to a method for manufacturing a semiconductor strain gauge and the semiconductor strain gauge itself. Background Technology

[0002] With the increasing demands for accuracy and size in tactile and force feedback from robots, collaborative robots (cobots), and micro / nano manufacturing equipment, miniaturized, highly integrated multi-axis force / torque sensors have become a hot topic in research and engineering applications. To achieve high-precision multi-component measurements within the confined space of mechanical structures, researchers typically employ strain gauge-based approaches: strain-sensitive elements are placed on the strain beam or sensitive region of an elastic body, and the force and torque acting on the sensor are deduced by measuring the resistance change caused by strain. Silicon-based (MEMS) strain gauges are widely used in the realization of miniature sensors due to their excellent microfabrication compatibility, high sensitivity, and mass production feasibility.

[0003] Common strain gauge arrangements in existing technologies include full-bridge, half-bridge, and multi-terminal / star networks. While the Wheatstone bridge structure facilitates temperature compensation and differential measurement, it often faces challenges in miniaturized designs, such as complex wiring, large space requirements, and high manufacturing and assembly difficulties. To reduce the number of wires and improve redundancy and reliability, some solutions have proposed "star" or multi-terminal strain gauge patterns. By integrating multiple wire grid regions on a single strain gauge and setting common nodes, the number of external leads can be reduced while maintaining differential measurement capabilities. This facilitates the arrangement of multiple sensing units in a small structure and enables redundant output and fault rejection. However, existing star patterns still have limitations in terms of size and manufacturing complexity.

[0004] Therefore, under the current technological background, how to further reduce the size of strain gauge patterns without significantly increasing external wiring and packaging space, while maintaining or improving the multi-component measurement capability, temperature drift characteristics, manufacturability and assembly reliability of sensors, remains a practical problem for micro force sensing technology. In particular, for scenarios such as robot dexterity hands that require the integration of high-density sensors at the fingertips / joints, new balances and innovations must be achieved in terms of pattern geometry and wire grid layout to meet the comprehensive requirements of high precision, multi-component, environmental resistance and easy calibration. Summary of the Invention

[0005] To address the aforementioned problems, the objective of this invention is to provide a method for manufacturing a semiconductor strain gauge and a semiconductor strain gauge that enables the strain gauge to have a compact size, low residual stress, excellent electrical consistency, and high bonding reliability, making it suitable for MEMS applications such as high-precision stress sensors and pressure sensors.

[0006] This was achieved through the following technical solutions: On the one hand, a method for manufacturing a semiconductor strain gauge is provided, comprising the following steps: S1. A boron-doped silicon epitaxial layer is grown on a (110) oriented P-type single-crystal silicon substrate; S2. A passivation layer is deposited on the surface of the epitaxial layer in step S1; S3. The location where metal deposition is required is exposed by a first photolithography step, and the passivation layer in step S2 is opened by reactive ion etching to expose the surface of the epitaxial layer; S4. An aluminum metal layer is deposited on the surface of the epitaxial layer exposed in step S3, and a metal short-circuit and lead pad pattern is formed by a second photolithography step. Unwanted deposited metal is removed by reactive ion etching to form a metal layer. S5. The passivation layer is patterned using the third photolithography step, and the passivation layer is opened using reactive ion etching in step S4 to expose the epitaxial layer surface, forming a hard mask pattern for deep silicon etching; S6. Deep reactive ion etching is used to etch through the silicon under the epitaxial layer exposed in step S5 to form the strain gauge wire grid; S7. The back side of the wafer of the strain gauge in step S6 is thinned by mechanical polishing; S8. The back side of the wafer in step S7 is further thinned by chemical wet etching until the individual strain gauges are separated from the wafer. By designing the size of the strain gauges, smaller strain gauge patterns can be fabricated, which not only allows more sensors to be integrated in the narrow spaces of robot fingertips and joints, but also effectively improves the resolution and coverage of force sensing.

[0007] Preferably, in step S1, the resistivity of the substrate is 10 Ω·cm ~ 20 Ω·cm, the resistivity of the epitaxial layer is 0.02 Ω·cm ~ 0.09 Ω·cm, and the thickness of the epitaxial layer is 3.2 ± 0.1 µm. This can reduce thermal noise while maintaining a high carrier concentration, increase the piezoresistive coefficient of the strain gauge in the direction of force, and improve the resistance change rate.

[0008] Preferably, in step S2, the passivation layer is a composite layer formed by sequentially depositing a silicon oxide layer and a silicon nitride layer on the surface of the epitaxial layer, with a thickness of less than 1.5 µm and a surface stress of less than 1 × 10⁻⁶. 9 dyne / cm². It balances passivation protection with device structural compatibility, avoiding stress damage and performance interference.

[0009] Preferably, in step S4, the silicon is kept in air for 30 minutes before depositing the aluminum metal layer, allowing an oxide film to form naturally on the exposed silicon surface, thereby balancing surface stability and bonding reliability and creating suitable pretreatment conditions for the formation of the aluminum bonding layer.

[0010] Preferably, in step S6, the depth of the etched trench is 10µm to 13µm, the sidewall perpendicularity is ≥88°, and the lateral dimensional error is ±0.3µm. Backside grinding ensures uniform wafer thickness and optimized stress distribution.

[0011] Preferably, before step S7, the wafer is annealed in a hydrogen atmosphere at a temperature of 400°C to 450°C for 15 to 60 minutes. This is used to repair the damaged layer caused by DRIE, improve the surface roughness of silicon, and enhance the long-term stability of the strain gauge.

[0012] On the other hand, a semiconductor strain gauge is provided, manufactured by the method described above, comprising a substrate, an epitaxial layer formed on the substrate, and a passivation layer and a conductive connection layer formed on the surface of the epitaxial layer; the epitaxial layer defines a first resistance wire gate region and a second resistance wire gate region, the extension directions of the first resistance wire gate region and the second resistance wire gate region being perpendicular to each other, forming a half-bridge structure; the conductive connection layer includes a common lead pad, a first lead pad and a second lead pad that are electrically isolated from each other; the common lead pad is arranged at the middle position of the strain gauge and electrically connected to one end of the first resistance wire gate region and one end of the second resistance wire gate region; the first lead pad and the second lead pad are respectively arranged in two corner regions of the strain gauge and electrically connected to the other ends of the first resistance wire gate region and the second resistance wire gate region, respectively; the conductive connection layer covers the surface region of the strain gauge, and both the first lead pad and the second lead pad have wing-shaped extensions extending toward the side of the strain gauge, thereby forming a geometrically enclosing structure of the first resistance wire gate region and the second resistance wire gate region together with the common lead pad. This strain gauge features low residual stress, excellent electrical consistency, and high bonding reliability, making it suitable for MEMS applications such as high-precision stress sensors and pressure sensors.

[0013] Preferably, the conductive connection layer is made of aluminum alloy and serves as a heat dissipation layer and mechanical support layer for the resistance wire grid region. It not only acts as a channel for electrical signal transmission but also maintains a minimum electrical safety distance between the wing-shaped extensions of the first and second lead pads and the internal resistance wire grid region, thereby maximizing the metal coverage area.

[0014] Preferably, the extension direction of one of the resistance wire grids of the strain gauge is relative to the silicon wafer. <111> The orientation is offset at a preset angle, ranging from 5° to 12°, specifically 9.735°. This design can correct for lateral effects and improve measurement linearity.

[0015] The beneficial effects of this invention compared to the prior art are: 1. First, controlling the resistivity of the epitaxial layer to 0.02–0.09 Ω·cm and using P-type silicon can improve the contribution of the piezoresistive coefficient and reduce intrinsic noise, thereby enhancing sensitivity. Second, the resistance wire grid relative to... <111> A crystal orientation bias of 5°–12° utilizes the anisotropy of silicon to increase the strain projection component, thereby improving the gauge value and output amplitude. Furthermore, before depositing the aluminum metal layer, the wafer is left to stand in air for 30 minutes to form a uniform natural oxide film, which improves the uniformity of metal nucleation, inhibits interfacial interdiffusion, and enhances the adhesion of the metal layer, resulting in more stable pad contact resistance. The metal interconnect layer covers at least 60% of the surface, effectively redistributing the surface stress field and reducing output drift caused by temperature gradients and external stresses. Additionally, higher sensitivity, lower temperature drift, more stable long-term performance, and more reliable packaging and lifespan can be achieved without adding extra compensation structures.

[0016] 2. The use of a smaller strain gauge pattern design not only allows for the integration of more sensors within confined spaces such as the robot's dexterous fingertips and joints, effectively improving the resolution and coverage of force sensing, but also eliminates the need for increased external wiring and packaging space. This reduces assembly difficulty and the risk of component interference, while simultaneously enhancing the compactness and installation flexibility of the sensor module. Furthermore, this design maintains or even improves the sensor's multi-component measurement capabilities and low-temperature drift characteristics while maintaining miniaturization, ensuring high-precision detection requirements are met and further enhancing the overall performance stability of the device. Attached Figure Description

[0017] Figure 1 This is a flowchart of the manufacturing method of the present invention; Figure 2 This is a schematic diagram of the epitaxial layer grown on the wafer surface according to the present invention; Figure 3 This is a schematic diagram of the passivation layer deposited on the wafer surface according to the present invention; Figure 4 This is a first photolithography schematic diagram of the present invention; Figure 5 This is a schematic diagram of the second photolithography forming of the metal short-circuit portion and lead pad of the present invention; Figure 6 This is a schematic diagram of the third photolithography step in this invention; Figure 7 This is a schematic diagram of the deep reactive ion etching method of the present invention; Figure 8 This is a schematic diagram of wafer thinning according to the present invention; Figure 9 This is a schematic diagram of the strain gauge of the present invention; Figure 10 This is a schematic diagram of the three-layer structure of the strain gauge of the present invention; Figure 11 This is a schematic diagram of the front structure of the present invention; Figure 12 This is a schematic diagram of the metal short-circuit section of the present invention; Figure 13 This is a schematic diagram showing the arrangement angle of the strain gauges of the present invention in the wafer. Detailed Implementation

[0018] The technical solutions of the present invention will now be described in detail with reference to the accompanying drawings.

[0019] like Figure 1 The diagram shown is a flowchart of the manufacturing method of this invention, specifically a method for manufacturing a semiconductor strain gauge. By designing the dimensions of the strain gauge, a smaller strain gauge pattern is created. This not only allows for the integration of more sensors within confined spaces such as the dexterous fingertips and joints of robots, effectively improving the resolution and coverage of force sensing, but also eliminates the need to expand external wiring and packaging space, thereby reducing assembly difficulty, minimizing the risk of component interference, and improving the compactness and installation flexibility of the sensor module. The specific steps of this method are as follows: S1. A boron-doped silicon epitaxial layer is grown on a (110) oriented P-type single-crystal silicon substrate.

[0020] like Figure 2 As shown, a P-type silicon single crystal with a (110) crystal plane is selected as the substrate, with a resistivity of 10 ~ 20 Ω·cm and boron doping. The diameter of the substrate silicon wafer can be 150mm or 200mm, which can balance production capacity and yield, and can produce more chips at once. At the same time, it can avoid the problem of increased crystal defects in large-diameter silicon wafers. The thickness is 625±20µm, which is sufficient to support multiple processes such as photolithography and etching in device manufacturing, and avoid wafer deformation or damage. A single crystal silicon material with a crystal plane index of 110 is used as the substrate on the silicon substrate in the semiconductor strain gauge. The (110) crystal plane is selected because the atomic arrangement density and surface energy of the (110) crystal plane are moderate, which is conducive to the uniform growth of semiconductor thin films (such as silicon oxide and metal electrodes), and provides high mechanical strength and the required mechanical support.

[0021] A P-type silicon epitaxial layer was grown on the substrate. The thickness of the epitaxial layer was 3.2 ± 0.1 μm, and the resistivity of the epitaxial layer was 0.035 Ω·cm. The single-crystal silicon was P-type silicon, and the dopant in the substrate was boron, with a resistivity of 10 Ω·cm ~ 20 Ω·cm. Details are as follows: The substrate was cleaned using the RCA method (a standard wet cleaning process in the semiconductor industry). 7%–10% hydrofluoric acid was used to remove the oxide layer from the silicon surface. After rinsing with a large amount of deionized water, it was dried with clean nitrogen gas. The resistivity of the deionized water used was greater than 10 MΩ·cm, meeting the high purity requirements of semiconductor cleaning and photolithography processes, ensuring substrate surface cleanliness and not affecting thin film growth or pattern formation. A 3.2 µm thick P-type silicon layer was then epitaxially grown as the epitaxial layer using low-pressure chemical vapor deposition (LPCVD) in an H2 atmosphere (reaction chamber pressure 10–1000 Pa) at 1000–1100 °C. The boron doping concentration of the epitaxial layer was controlled at 1.5 × 10⁻⁶. 18 cm -3 The boron doping concentration can precisely match the conductivity requirements of semiconductor devices. At this resistance, both conductivity efficiency and lattice defects caused by excessive impurity aggregation are ensured. The corresponding resistivity is 0.035 Ω·cm, and the epitaxial layer thickness is uniformly controlled within ±1%.

[0022] As the functional layer of the piezoresistive gate, the epitaxial layer's resistance characteristics and thickness are strictly controlled to ensure consistent strain gauge sensitivity and temperature characteristics. By controlling the epitaxial layer thickness and achieving extreme thickness uniformity, highly consistent parameters such as resistance and breakdown voltage can be ensured across different regions within the wafer, significantly reducing device performance dispersion. After the epitaxial layer growth is complete, the wafers are removed in reverse order using magnetic rods. Removing them in reverse order not only avoids contamination of the later-removed wafers on the surface of the first wafer removed, but also prevents wafer deformation and edge chipping caused by improper ordering.

[0023] S2. A passivation layer is deposited on the surface of the epitaxial layer in step S1.

[0024] like Figure 3 As shown, a passivation layer composed of silicon oxide and silicon nitride is sequentially deposited on the surface of the epitaxial layer of the substrate. Among them: SiO2: thickness is about 500 nm; Si3N4: thickness is about 700 nm; the dielectric layer is completed by PECVD (Plasma-Enhanced Chemical Vapor Deposition).

[0025] This passivation layer serves both as an isolation layer for subsequent metal interconnects and as a hard mask layer for deep silicon etching (DRIE), forming a passivation layer covering the epitaxial layer. The stress of the thin film is controlled at 1×10⁻⁶. 9 With a dyne / cm² or lower, thin film cracking, peeling, or impact on device electrical performance can be avoided.

[0026] S3. The location where metal deposition is to be performed is exposed through the first photolithography step, and the passivation layer in step S2 is opened by reactive ion etching to expose the surface of the epitaxial layer.

[0027] like Figure 4 As shown, photoresist is spin-coated onto the surface of the passivation layer, and the aluminum metal deposition sites are exposed and developed using a first photolithographic mask to obtain the metal contact window pattern. Subsequently, the SiO2 / Si3N4 composite passivation layer is selectively etched using RIE (Reactive Ion Etching) until the epitaxial layer is exposed, thereby forming the contact window required for the metal interconnect.

[0028] S4. An aluminum metal layer is deposited on the epitaxial layer surface exposed in step S3. A metal short-circuit portion and lead pad pattern are formed by a second photolithography step. Unwanted deposited metal is removed by reactive ion etching to form the metal short-circuit portion and lead pad.

[0029] like Figure 5 As shown, after the metal contact window is formed, an aluminum thin film of approximately 1000 nm is deposited using sputtering. A second photolithography step is then performed, using a second mask to define the pattern of the lead pads and the metal short circuit, as shown. Figure 12 As shown. Metal etching (using RIE or wet etching methods) is used to remove the metal in the non-patterned areas, preserving the metal short-circuit portions and lead pad structures required for the semiconductor strain gauge. After aluminum deposition, annealing at approximately 400 °C can improve the metal / silicon contact resistance. Pre-depositing the aluminum layer in air for 30 minutes allows for the formation of a controllable natural oxide film, improving the wettability and uniformity of the deposited aluminum, thereby balancing surface stability and bonding reliability, and creating suitable pretreatment conditions for the formation of the aluminum bonding layer.

[0030] S5. The passivation layer is patterned through the third photolithography step, and the passivation layer is opened by reactive ion etching in step S4 to expose the surface of the epitaxial layer, forming a hard mask pattern for deep silicon etching.

[0031] like Figure 6 As shown, after metal deposition, the geometry of the strain gate is defined by a third photolithography step. After photolithography, the exposed SiO2 / Si3N4 layer is subjected to RIE etching to form the hard mask pattern required for DRIE deep silicon etching, thereby defining the final shape of the strain gate.

[0032] S6. Using deep reactive ion etching, the silicon under the epitaxial layer exposed in step S5 is etched through to form a strain gauge wire grid.

[0033] like Figure 7 As shown, the exposed silicon region is deeply etched using the Deep Reactive Ion Etching (DRIE) method. The strain gauge pattern is defined by photolithography, and DRIE is used to etch trenches 10µm to 13µm deep. The etching depth can also be determined according to the device design.

[0034] The direction of the deep trench is parallel to the crystal orientation index. <111> Monocrystalline silicon materials can utilize crystal anisotropy to improve etching uniformity and reduce sidewall roughness because <111> The dense arrangement of atoms in the single-crystal silicon crystal orientation results in a more stable sidewall structure after etching, making it less prone to edge chipping or lattice damage. The sidewall perpendicularity is ≥88°, which maximizes the effective space utilization of the trench, adapts to the integrity of subsequent filling processes, avoids filling voids, and reduces device electrical parameter deviations caused by sidewall tilt. The lateral dimension error is ±0.3µm, which reduces device performance dispersion and precisely matches the three-dimensional structural requirements of semiconductor devices, balancing etching accuracy, structural stability, and electrical performance.

[0035] In the DRIE process, high aspect ratio silicon microstructures are achieved through alternating etching and sidewall passivation. The resulting semiconductor strain gauge wire grid constitutes the core sensing structure of the strain gauge. After DRIE is completed, a hard mask layer remains above the strain gauge wire grid to protect the structural integrity.

[0036] S7. The back side of the strain gauge wafer from step S6 is thinned by mechanical grinding.

[0037] like Figure 8 As shown, after DRIE, the wafer is annealed in a hydrogen atmosphere at a temperature of 400℃ to 450℃ for 15 to 60 minutes. High-temperature annealing of the wafer in a hydrogen atmosphere (400–500℃) can be used to repair the damaged layer caused by DRIE, improve the surface roughness of silicon, and enhance the long-term stability of the strain gauge.

[0038] The back of the strain gauge is ground to 180±6µm using a Disco IF-01-1-5 / 10-B-k04 (IF series longitudinal cut-in diamond grinding wheel) grinding disc. The precise thickness dimension is adapted to the installation requirements of the measured part surface, which facilitates bonding and fixation and reduces measurement errors caused by bonding gaps. The total thickness variation is less than 6µm, avoiding installation difficulties caused by excessive thickness or insufficient mechanical strength caused by excessive thinness, thus balancing structural stability and bonding tightness.

[0039] S8. Continue thinning the back side of the wafer in step S7 by chemical wet etching until the individual strain gauges are separated from the wafer.

[0040] like Figure 9 As shown, a combination of mechanical polishing and spin etching was used. Mechanical polishing reduced the wafer thickness from approximately 625 μm to approximately 180 μm. Spin etching further reduced it to approximately 10-20 μm, allowing the strain gauge microstructure to be separated while removing the damage layer introduced by mechanical polishing.

[0041] like Figure 10 As shown, using this design, the smaller strain gauge pattern not only allows for the integration of more sensors within confined spaces such as the robot's dexterous fingertips and joints, effectively improving the resolution and coverage of force sensing, but also eliminates the need for increased external wiring and packaging space, thereby reducing assembly difficulty and the risk of component interference. Simultaneously, it enhances the compactness and installation flexibility of the sensor module. Furthermore, this design maintains or even improves the sensor's multi-component measurement capabilities and low-temperature drift characteristics while maintaining miniaturization, ensuring that high-precision detection requirements are met and further improving the overall performance stability of the device.

[0042] like Figure 11 As shown, this embodiment also provides a semiconductor strain gauge, which is prepared according to the above-mentioned method for a semiconductor strain gauge. The overall size of the strain gauge is approximately 0.58 mm in height and 0.62 mm in width. The smaller strain gauge pattern not only allows for the integration of more sensors in narrow spaces such as the robot's dexterous fingertips and joints, but also effectively improves the resolution and coverage of force sensing. The strain gauge includes a substrate, an epitaxial layer formed on the substrate, and a passivation layer and a conductive connection layer formed on the surface of the epitaxial layer. A single crystal silicon with a crystal plane index of (110) is used as the substrate. The resistivity of the substrate is 10 Ω·cm ~ 20 Ω·cm, which has a high degree of matching with the electrical characteristics of the epitaxial layer, passivation layer and other films, reducing the accumulation of interface charge, reducing the leakage current of the device, and improving the insulation reliability. Furthermore, an epitaxial layer with boron dopant is formed on the substrate. The resistivity of the epitaxial layer is 0.035 Ω·cm ~ 0.038 Ω·cm, and the thickness is 3.2±0.1µm. The low resistivity characteristic reduces signal attenuation, which is suitable for the acquisition of weak signals in high-precision strain detection and reduces measurement error. At the same time, the thickness design can avoid affecting the overall deformation response of the strain gauge, ensuring the sensing sensitivity when external force is applied, and not weakening the stress transmission efficiency.

[0043] The epitaxial layer defines a first resistance wire gate region and a second resistance wire gate region. The extension directions of the first resistance wire gate region and the second resistance wire gate region are perpendicular to each other, forming a half-bridge structure.

[0044] like Figure 13 As shown, the first resistance wire grid extension direction or the second resistance wire grid extension direction is relative to the silicon wafer. <111> The orientation is offset at a preset angle, which is 5°~12°, specifically 9.735°. This offset angle is the optimal solution calculated based on the anisotropy theory of the piezoresistive effect of the (110) crystal plane of single-crystal silicon. This design can correct the lateral effect and improve the linearity of the measurement.

[0045] In the usual <111> In the crystal orientation, the lateral piezoresistive coefficient of P-type silicon is often non-zero. This causes strain gauges to experience lateral strain interference caused by Poisson's ratio when subjected to uniaxial stress, resulting in nonlinear errors. By rotating the wire grid to 9.735°, utilizing the anisotropy of the crystal, the lateral piezoresistive coefficient is smaller at this angle, effectively "decoupling" the interference of lateral stress on the strain output and significantly improving the purity and linearity of the sensor's principal axis stress sensing. Simultaneously, this angle also helps balance the thermal stress caused by the mismatch between the conductive interconnects and the silicon substrate's thermal expansion coefficient, allowing the strain gauge's first-order temperature coefficient (TCR) and the temperature drift (TCS) of the piezoresistive sensitivity to compensate for each other, thereby improving the device's zero-point stability in a wide temperature range.

[0046] like Figure 11 As shown, the conductive connection layer includes a common lead pad, a first lead pad, and a second lead pad that are electrically isolated from each other. The common lead pad is located in the middle of the strain gauge and is electrically connected to one end of the first resistance wire grid region and one end of the second resistance wire grid region. The first lead pad and the second lead pad are respectively located in two corner regions of the strain gauge and are electrically connected to the other ends of the first resistance wire grid region and the second resistance wire grid region, respectively.

[0047] The conductive connection layer is made of aluminum or aluminum alloy, which serves not only as an electrical signal transmission channel, but also as a heat dissipation layer and mechanical support layer for the resistance wire grid area; the wing-shaped extensions of the first and second lead pads maintain a minimum electrical safety distance from the internal resistance wire grid area to maximize the metal coverage area.

[0048] A conductive connection layer covers the surface area of ​​the strain gauge, with an area covering more than 60% of the strain gauge surface. Both the first lead pad and the second lead pad have wing-shaped extensions extending toward the side of the strain gauge, thereby forming a geometrically enclosing structure for the first and second resistance wire grid areas together with the common lead pad. This is used to homogenize the stress distribution and provide a heat dissipation channel. By adopting a special pattern design, the temperature gradient on the strain gauge grid area is effectively reduced, thereby improving the temperature characteristics of subsequent sensors.

[0049] The above-mentioned method for semiconductor strain gauges can also be used to prepare more strain gauge patterns. In addition to the different designs of the extended portions, some of these strain gauge patterns can also be extended inside the strain gauge.

[0050] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solutions based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. A method of manufacturing a semiconductor strain gauge, characterized by, The steps are as follows: S1, epitaxially growing a boron-doped silicon epitaxial layer on a P-type monocrystalline silicon substrate oriented at (110); S2, depositing a passivation layer on the surface of the epitaxial layer in step S1; S3, exposing the positions requiring metal deposition by a first photolithography step, and opening the passivation layer in step S2 to expose the surface of the epitaxial layer by reactive ion etching; S4, depositing an aluminum metal layer on the surface of the epitaxial layer exposed in step S3, forming a metal short circuit part and a lead pad pattern by a second photolithography step, and removing the unnecessary deposited metal by reactive ion etching to form the metal short circuit part and the lead pad; S5, patterning the passivation layer by a third photolithography step, and opening the passivation layer to expose the surface of the epitaxial layer by the reactive ion etching in step S4 to form a hard mask pattern for deep silicon etching; S6, etching through the silicon under the exposed epitaxial layer in step S5 by deep reactive ion etching to form a strain gauge grid; S7, thinning the back surface of the wafer of the strain gauge by mechanical grinding; S8, continuing to thin the back surface of the wafer in step S7 by chemical wet etching until the single strain gauge is separated from the wafer.

2. The method of manufacturing a semiconductor strain gauge according to claim 1, wherein In step S1, the resistivity of the silicon substrate is 10Ω·cm ~ 20Ω·cm, the resistivity of the epitaxial layer is 0.02Ω·cm ~ 0.09Ω·cm, and the thickness of the epitaxial layer is 3.2±0.1µm.

3. The method of manufacturing a semiconductor strain gauge according to claim 1, wherein In step S2, the passivation layer is a composite layer formed by sequentially depositing a silicon oxide layer and a silicon nitride layer on the surface of the epitaxial layer, with a thickness less than 1.5 µm, and the surface stress of the passivation layer is less than 1×10 9 dyne / cm².

4. The method of manufacturing a semiconductor strain gauge according to claim 1, wherein In step S4, the aluminum metal layer is deposited in air for 30 minutes before deposition.

5. The method of manufacturing a semiconductor strain gauge according to claim 1, wherein In step S6, the etched groove depth is 10µm ~ 13µm, the sidewall perpendicularity is ≥88°, and the lateral size error is ±0.3µm.

6. The method of manufacturing a semiconductor strain gauge according to claim 1, wherein Before step S7, the wafer is subjected to annealing treatment, the annealing atmosphere is hydrogen, the annealing temperature is 400℃ ~ 450℃, and the time is 15~60 minutes.

7. The method of manufacturing a semiconductor strain gauge according to claim 1, wherein In step S7, the thickness of the back surface of the strain gauge wafer after mechanical grinding treatment is 180±6µm.

8. A semiconductor strain gauge produced by the method of any one of claims 1 to 7, characterized by The substrate, the epitaxial layer formed on the substrate, and the passivation layer and the conductive connection layer formed on the surface of the epitaxial layer are included. The epitaxial layer defines a first resistance wire grid area and a second resistance wire grid area, the extension directions of the first resistance wire grid area and the second resistance wire grid area are perpendicular to each other, and a half-bridge structure is formed. The conductive connection layer includes a common lead pad, a first lead pad and a second lead pad which are electrically isolated from each other. The common lead pad is arranged at the middle position of the strain gauge, and electrically connects one end of the first resistance wire grid area and one end of the second resistance wire grid area. The first lead pad and the second lead pad are respectively arranged at two corner regions of the strain gauge, and respectively electrically connect the other end of the first resistance wire grid area and the second resistance wire grid area. The conductive connection layer covers the surface area of the strain gauge, and the first lead pad and the second lead pad both have wing-shaped extensions extending to the side of the strain gauge, thereby forming a surrounding structure with the common lead pad on the geometric space for the first resistance wire grid area and the second resistance wire grid area.

9. The semiconductor strain gauge of claim 8, wherein: The conductive connection layer is made of aluminum alloy material, which is used as a heat dissipation layer and a mechanical support layer for the resistance wire grid area.

10. The semiconductor strain gauge of claim 8, wherein, One of the resistance wire grids of the strain gauge is arranged with a preset angle offset relative to the <111> direction of the silicon wafer, and the preset angle is 5°~12°.

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