Dynamic navigation system with heterogeneous acceleration and time delay compensation

Abstract

The invention provides a dynamic navigation system with heterogeneous acceleration and time delay compensation, which adopts a layered distributed heterogeneous computing architecture, acquires data through a magnetic sensor array of a sensing layer, and realizes hardware synchronization and timestamp injection through an FPGA (Field Programmable Gate Array) of a synchronous control layer. And the data processing layer constructs a parallel contraction array by using DSP slices in the FPGA, and carries out hardware-level acceleration on a filtering algorithm. And the calculation layer dynamically compensates accumulated delay generated by the data in a full link through an integrated time delay compensation engine based on a hardware anchoring timestamp and a reverse kinematics model. According to the method, the problem of precision reduction caused by sampling jitter, communication fluctuation and system scheduling uncertainty is effectively solved, end-to-end delay is reduced, submillimeter-level dynamic positioning precision is realized, and the real-time performance, precision and robustness of the system in a complex dynamic environment are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of intelligent navigation and real-time computing technology, specifically to a dynamic navigation system with heterogeneous acceleration and latency compensation. Background Technology

[0002] Dynamic navigation systems are a core supporting technology for advanced applications such as modern precision surgery and robotic control. By tracking the target's pose in real time and guiding the operation, they directly impact surgical safety and operational accuracy. The core performance indicators of the system lie in end-to-end latency and dynamic positioning accuracy: latency must be sufficiently low to ensure real-time operation, and accuracy must be sufficiently high to meet sub-millimeter positioning requirements. However, existing technologies struggle to achieve both objectives simultaneously in complex dynamic scenarios, primarily due to the following technical bottlenecks: 1. Centralized processing architecture cannot meet high real-time requirements; traditional navigation systems mostly rely on general-purpose CPUs for centralized data processing, which easily leads to processing congestion and scheduling delays when facing high-frequency, multi-channel sensor data streams. Although introducing GPUs can accelerate some computations, for highly real-time tasks such as data acquisition synchronization and deterministic filtering, traditional computing architectures lack hardware-level parallelism and fixed timing guarantees, making it difficult to stably control the overall system latency within milliseconds.

[0003] 2. Lack of effective compensation mechanism for accumulated end-to-end latency: Throughout the entire data acquisition, transmission, processing, and display process, there are multiple sources of latency, including sampling jitter, communication fluctuations, and processing time. Existing methods often focus on local optimization of single stages, lacking latency measurement and dynamic compensation methods based on a globally unified time reference. The random superposition of latency in each stage leads to unpredictable deviations between the output pose and the actual state, severely limiting the system's accuracy in high-speed dynamic scenarios.

[0004] 3. Time synchronization and scheduling challenges in heterogeneous computing environments: To improve performance, systems often employ heterogeneous hardware platforms such as MCUs, FPGAs, CPUs, and GPUs. Different hardware operates in different clock domains and scheduling systems (such as RTOS and general-purpose operating systems), making it difficult to align cross-platform data timestamps. Software scheduling uncertainties further introduce timing disturbances, leading to a decrease in the accuracy of trajectory prediction and compensation algorithms that rely on time consistency.

[0005] 4. The computational demands of high-dimensional filtering algorithms clash significantly with real-time processing requirements. To achieve high-precision data fusion and noise reduction, computationally intensive algorithms such as Kalman filtering are necessary. These algorithms, when run purely in software on a CPU, are time-consuming and cannot meet the requirements of high-frequency real-time processing. They often force a compromise between "reducing the sampling rate" or "increasing latency," failing to balance dynamic response and accuracy.

[0006] Therefore, existing dynamic navigation technologies are limited by problems such as insufficient real-time performance of the architecture, uncompensated latency accumulation, asynchronous heterogeneous platforms, and algorithm computing power bottlenecks. There is an urgent need for a solution that can achieve collaborative innovation from multiple levels, including system architecture, hardware acceleration, global synchronization, and dynamic compensation, in order to achieve a balance between high real-time performance, high accuracy, and high robustness. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the purpose of this invention is to provide a dynamic navigation system with heterogeneous acceleration and time delay compensation.

[0008] A dynamic navigation system with heterogeneous acceleration and time delay compensation provided by the present invention includes: A layered distributed heterogeneous computing architecture, which, from bottom to top, includes a perception layer, a synchronization control layer, a data processing layer, a computing layer, and an application layer. The sensing layer includes a magnetic sensor array and a microcontroller cluster, used to collect raw sensing data and perform front-end preprocessing. The synchronization control layer includes a field-programmable gate array (FPGA) for generating a global reference clock and a synchronization trigger signal to control the sensing layer to perform synchronous data acquisition and inject the acquired data with an original timestamp based on a hardware clock. The data processing layer includes an FPGA, which is used to perform hardware-accelerated filtering processing on the synchronized sensing data. The computing layer includes a central processing unit for running a trajectory prediction module and a latency compensation module; the latency compensation module performs real-time compensation for the cumulative latency generated throughout the data flow based on the original timestamp and the inverse kinematics model. The application layer includes a CPU and a graphics processor, used to implement system interaction, task scheduling, fault diagnosis, and parallel rendering of the navigation interface.

[0009] Preferably, the microcontroller in the sensing layer is a single-chip microcontroller without an operating system, used to realize the concurrent conversion of raw physical quantities into digital signals.

[0010] Preferably, the FPGA in the synchronization control layer generates a global reference clock through its internal high-precision phase-locked loop and generates trigger pulses synchronously through hardware pins to control each sensor node in the magnetic sensor array to complete sampling within the same clock cycle, thereby achieving hardware synchronous jitter within 1 microsecond.

[0011] Preferably, the FPGA in the data processing layer uses slices of its internal digital signal processor to construct a parallel shrink array architecture, and executes the Kalman filter algorithm through a fixed-point pipeline structure to achieve hardware-level acceleration.

[0012] Preferably, the computing layer executes a cross-platform adaptation scheduling strategy, including: In real-time operating system platforms, deterministic preemptive scheduling is achieved through kernel-level task priority locking; On a non-real-time high-performance platform, the current system clock is obtained and the original timestamp in the data packet is read to calculate the total dynamic link latency.

[0013] Preferably, the mathematical model for pose compensation based on the total delay of the dynamic link by the delay compensation module is as follows:

[0014] in, The position output by the trajectory prediction module. The instantaneous velocity of the target For the instantaneous acceleration of the target, The total latency of the dynamic link is [value]. This is the real-time location after compensation.

[0015] Preferably, the end-to-end delay of the system is less than or equal to 20 milliseconds, and the dynamic positioning accuracy reaches the sub-millimeter level.

[0016] Preferably, the application layer is configured to implement system interaction logic, task scheduling and fault diagnosis through a general-purpose CPU, and to use a GPU to assist in the parallel rendering of the navigation interface.

[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. This system utilizes a heterogeneous acceleration architecture to execute key algorithms in hardware within an FPGA, significantly reducing data processing time. Simultaneously, a hardware timestamp-based end-to-end latency compensation mechanism accurately offsets delays introduced during sampling, transmission, and processing. Ultimately, the system achieves sub-millimeter-level dynamic positioning accuracy while drastically reducing end-to-end latency, resolving the challenge of balancing real-time performance and accuracy in high-speed dynamic scenarios using traditional solutions.

[0018] 2. The global timestamp alignment and dynamic compensation method proposed in this invention can effectively suppress and compensate for various delays caused by sampling period jitter, communication fluctuations, and system scheduling uncertainties. This enables the system to maintain stable and accurate positioning output even under non-ideal conditions such as sensor noise and network load changes, and substantially improves its overall anti-interference capability and reliable operation capability in complex environments.

[0019] 3. This invention utilizes the DSP slices within the FPGA to construct a parallel shrinking array, providing hardware-level acceleration for complex algorithms such as Kalman filtering, resulting in a significant improvement in single-channel data processing speed compared to pure software. More importantly, the hardware pipeline design introduces a fixed processing latency, eliminating performance fluctuations caused by task scheduling in general-purpose computing platforms, and providing a predictable, high-performance deterministic computing power foundation for the system.

[0020] 4. The system's layered design and cross-platform scheduling strategy enable it to seamlessly adapt to different operating environments, from embedded real-time operating systems (RTOS) to high-performance non-real-time platforms (such as macOS). Furthermore, the modular architecture allows for flexible replacement or upgrading of sensor types, core algorithms, and other components according to specific application requirements, reducing the costs of customized development and subsequent maintenance for different scenarios. Attached Figure Description

[0021] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is the overall system architecture in the embodiments of the present invention; Figure 2 This is a data flow diagram in an embodiment of the present invention; Figure 3 This is a timing diagram for delay compensation in an embodiment of the present invention. Detailed Implementation

[0022] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0023] I. System Overall Implementation Architecture and Workflow The implementation of this invention system is based on a clearly defined hierarchical distributed heterogeneous computing architecture, referring to... Figure 1 As shown, the architecture comprises, from bottom to top, a perception layer, a synchronization control layer, a data processing layer, a computing layer, and an application layer. Its core implementation lies in achieving end-to-end optimization from data acquisition, processing, compensation to display through the collaboration of heterogeneous hardware (MCU, FPGA, CPU, GPU) and dedicated algorithms.

[0024] Reference Figures 1-3As shown, the overall system implementation process follows a closed loop of "synchronous acquisition → hardware acceleration processing → latency compensation → real-time output". First, the magnetic sensor array in the perception layer completes deterministic data acquisition under hardware triggering of the synchronization control layer. Then, the data undergoes hardware-level filtering and acceleration via FPGA in the data processing layer. The processed data is then used in the computation layer for trajectory prediction and pose regression using a latency compensation engine. Finally, the application layer renders and displays the compensated high-precision position information in real time. The entire implementation process aims to ensure an end-to-end latency of ≤20 ms and sub-millimeter level dynamic positioning accuracy.

[0025] II. Specific Implementation Methods at Each Level 1. Implementation of the perception layer The perception layer is used to achieve deterministic acquisition of multi-point data. The specific implementation is as follows: The sensing layer uses an array of high-precision magnetic sensors (such as TMAG5170, MLX90393, etc.). The number of sensors is configured according to the application requirements, typically between 20 and 200. Each sensor node is driven by a single-chip microcontroller (MCU, such as the STM32F103 series) without an operating system. This MCU is specifically responsible for the concurrent acquisition and analog-to-digital conversion of the raw physical signals. Its operating system-less design eliminates software scheduling uncertainties, ensuring determinism and low latency in the underlying data acquisition.

[0026] After receiving a hardware trigger signal from the synchronization control layer, the MCU synchronously controls the connected sensors to start sampling and performs preliminary preprocessing on the collected raw data, such as data format conversion and invalid data removal, to provide a standardized basic data stream for subsequent layers.

[0027] 2. Implementation of Synchronous Control Layer The goal of implementing the synchronization control layer is to achieve high-precision hardware-level synchronization of sensor sampling and to inject a unified time reference into the data.

[0028] The synchronous control layer uses a field-programmable gate array (FPGA, such as the Xilinx Artix-7 series) as the implementation platform.

[0029] Synchronization mechanisms can be implemented in the following ways: Inside the FPGA, a global reference clock signal is generated using a high-precision phase-locked loop (PLL).

[0030] By programming the FPGA, precise synchronous trigger pulses are derived from this reference clock and simultaneously sent to the MCU nodes of all sensing layers via the FPGA's hardware pins.

[0031] This hardware triggering mechanism forces all sensors to start sampling within the same clock cycle, thereby achieving synchronization of the acquisition actions at the physical level and controlling the synchronization jitter between sensors to within 1μs.

[0032] Timestamp anchoring: When the FPGA synchronously receives data uploaded by each MCU through a high-speed interface (such as SPI, I2C), it adds a raw hardware timestamp based on the global reference clock to each frame of data in real time. This timestamp serves as the absolute starting point for data flow throughout the entire chain, and is the benchmark anchor point for all subsequent latency calculations and compensations.

[0033] 3. Data processing layer implementation The core of the data processing layer implementation is to use FPGA to accelerate the filtering algorithm at the hardware level in order to improve the data processing speed and determinism.

[0034] Hardware-accelerated architecture: Within the selected FPGA chip, leveraging its abundant DSP slice resources, a parallel shrunk array architecture is constructed. This architecture decomposes complex matrix operations (such as covariance updates in Kalman filtering) into multiple concurrent multiply-accumulate (MAC) operations, which are executed in parallel across multiple DSP slices.

[0035] Algorithm hardware mapping: Using a hardware description language (such as Verilog HDL), the prediction and update equations of algorithms such as Kalman filtering are mapped to a fixed-point pipeline structure that can be executed on the shrinking array. This process realizes the transformation from software instruction flow to hardware data flow.

[0036] Deterministic Pipeline: A deep pipeline is designed to divide the filtering process into multiple sequentially executed hardware stages (such as data input, state prediction, gain calculation, state update, and output). Each stage is handled by a dedicated hardware module, and data is processed continuously like a pipeline, ensuring that the processing time for each frame of data is fixed and eliminating latency jitter caused by system scheduling in software processing.

[0037] Collaborative operation: The CPU is responsible for configuring the initialization parameters of the filtering algorithm (such as initial state and noise covariance) and transmitting them to the FPGA via a high-speed bus. After receiving the parameters, the FPGA performs real-time hardware filtering on the synchronously uploaded sensing data and sends the processed high signal-to-noise ratio data back to the CPU for use by the computing layer. This solution improves the single-channel data processing speed by 5-10 times compared to a pure software implementation.

[0038] 4. Implementation of the computing layer The key implementations at the computational layer are trajectory prediction and end-to-end latency compensation, and they need to be adapted to different computing terminal environments. The trajectory prediction module uses filtered, effective data to predict the target's trajectory using a prediction algorithm. The latency compensation module compensates for issues such as sampling period jitter, communication delay, and signal processing latency, outputting compensated real-time location information. Hardware configuration: It uses a central processing unit (CPU, such as an ARM multi-core processor or Apple Silicon) as the core, responsible for task scheduling and execution of complex algorithms. Some computationally intensive tasks (such as matrix operations in prediction models) can also be accelerated by FPGA.

[0039] Cross-platform scheduling and latency calculation: In real-time operating system (RTOS) platforms: by setting kernel-level task priorities and deterministic preemptive scheduling policies, the microsecond-level interrupt response and execution determinism of critical tasks are guaranteed.

[0040] On non-real-time high-performance platforms (such as Apple Silicon / macOS): Implement a latency calculation mechanism based on hardware-anchored timestamps. The computation layer reads the raw timestamp injected by the perception layer from the data packets. And obtain the current system high-precision clock. Dynamically calculate the total latency experienced by the current data packet. .

[0041] Delay compensation engine implementation: The compensation engine is integrated into the computation layer software and is developed using languages ​​such as C++ / Rust.

[0042] It receives the output from the trajectory prediction module, which contains the prediction time. target location ,speed and acceleration .

[0043] The engine uses the calculated total latency Position compensation is performed based on an inverse kinematics model. The mathematical model formula used is:

[0044] in, The position output by the trajectory prediction module. The instantaneous velocity of the target For the instantaneous acceleration of the target, The total latency of the dynamic link is [value]. That is, the result obtained after compensation, corresponding to the original acquisition time. The estimated actual location of the target. This step effectively offsets the bias caused by sampling jitter, communication delay, and processing delay.

[0045] 5. Application Layer Implementation The application layer implementation provides users with an intuitive system interaction and status monitoring interface.

[0046] Hardware support: The system uses a general-purpose CPU (such as Intel Core or Apple M series) to run the main control logic and utilizes a graphics processing unit (GPU) for graphics rendering acceleration.

[0047] Software implementation: Develop a navigation interface using frameworks such as Qt to display location information in real time and visually after latency compensation. Target motion trajectory, system accuracy indicators, etc.

[0048] Develop a task scheduler program to coordinate and manage task execution and system resource allocation at all levels, from perception to application.

[0049] Develop a fault diagnosis module to monitor the operating status and data flow health of various components such as sensors, processors, and communication links in real time, and realize fault early warning and system self-test.

[0050] III. System Integration, Debugging, and Performance Verification Methods 1. Hardware system setup and integration Sensing layer: Arrange the magnetic sensor array according to the design and connect it to the STM32F103 MCU to complete the hardware circuit soldering and power supply and signal integrity testing.

[0051] Core processing unit: Integrates core chips such as Xilinx Artix-7 FPGA and ARM CPU on the main control board, and designs and implements high-speed communication interfaces (such as PCIe and high-speed SPI) between FPGA and MCU cluster, CPU and GPU.

[0052] System integration testing: Power on and test each subsystem sequentially. First, verify whether the synchronous trigger signal generated by the FPGA can reach all MCUs accurately and simultaneously (measured with an oscilloscope to ensure synchronization error <1μs). Then verify whether the complete path from data acquired by the sensor to the CPU through each level of hardware is unobstructed.

[0053] 2. Software system deployment and integration testing Low-level drivers: Write and burn C language drivers for all hardware (sensors, MCUs, FPGAs, GPUs).

[0054] FPGA logic loading: After compiling the VerilogHDL code containing functions such as synchronization control, timestamp injection, and filter acceleration array, it is downloaded to the FPGA.

[0055] Upper-layer application installation: Install and run trajectory prediction algorithms, latency compensation engines, navigation interface software, and task schedulers on the hosts of the computing and application layers.

[0056] End-to-end debugging: Run the entire system and observe the data flow. Focus on debugging timestamps. To verify the correctness of the transmission across the entire link, the input of the latency compensation engine is checked. Is the output accurate? Is it reasonable?

[0057] 3. Performance testing and optimization verification End-to-end latency test: Apply a known instantaneous physical stimulus to the sensor and record the precise time of the stimulus occurrence. Measure the time elapsed from that moment until the navigation interface correctly displays the corresponding change. Continuously optimize this latency to ≤20 ms through code optimization, pipeline adjustments, and scheduling strategy optimization.

[0058] Dynamic positioning accuracy test: The sensor is mounted on a high-precision motion control platform (such as a linear motor module), and the platform executes motion along a known trajectory and speed. The position is compared with the real-time output of the system. The error is calculated by comparing the position with the actual high-precision encoder feedback position on the platform. By optimizing the filtering algorithm parameters, calibrating the sensor, and refining the time delay compensation model coefficients, the positioning accuracy reaches the sub-millimeter level.

[0059] Robustness testing: During testing, artificial interference is introduced, such as magnetic interference from nearby metal objects (simulating sensor noise), increased bus data load (simulating communication fluctuations), and sudden changes in motion state (simulating environmental abrupt changes). The system's performance under the time delay compensation mechanism and heterogeneous architecture fault-tolerant design is observed to ensure stable positioning output and no significant decrease in accuracy.

[0060] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A dynamic navigation system with heterogeneous acceleration and time delay compensation, characterized in that, include: A layered distributed heterogeneous computing architecture, which, from bottom to top, includes a perception layer, a synchronization control layer, a data processing layer, a computing layer, and an application layer. The sensing layer includes a magnetic sensor array and a microcontroller cluster, used to collect raw sensing data and perform front-end preprocessing. The synchronization control layer includes a field-programmable gate array (FPGA) for generating a global reference clock and a synchronization trigger signal to control the sensing layer to perform synchronous data acquisition and inject the acquired data with an original timestamp based on a hardware clock. The data processing layer includes an FPGA, which is used to perform hardware-accelerated filtering processing on the synchronized sensing data. The computing layer includes a central processing unit for running a trajectory prediction module and a latency compensation module; the latency compensation module performs real-time compensation for the cumulative latency generated throughout the data flow based on the original timestamp and the inverse kinematics model. The application layer includes a CPU and a graphics processor, used to implement system interaction, task scheduling, fault diagnosis, and parallel rendering of the navigation interface.

2. The dynamic navigation system with heterogeneous acceleration and time delay compensation according to claim 1, characterized in that, The microcontroller in the perception layer is a single-chip microcontroller without an operating system, used to achieve concurrent conversion of raw physical quantities into digital signals.

3. The dynamic navigation system with heterogeneous acceleration and time delay compensation according to claim 1, characterized in that, The FPGA in the synchronization control layer generates a global reference clock through its internal high-precision phase-locked loop and generates trigger pulses synchronously through hardware pins to control each sensor node in the magnetic sensor array to complete sampling within the same clock cycle.

4. The dynamic navigation system with heterogeneous acceleration and time delay compensation according to claim 1, characterized in that, The FPGA in the data processing layer uses its internal digital signal processor slices to build a parallel shrink array architecture, and executes the Kalman filter algorithm through a fixed-point pipeline structure to achieve hardware-level acceleration.

5. The dynamic navigation system with heterogeneous acceleration and time delay compensation according to claim 1, characterized in that, The computing layer executes a cross-platform adaptation scheduling strategy, including: In real-time operating system platforms, deterministic preemptive scheduling is achieved through kernel-level task priority locking; On a non-real-time high-performance platform, the current system clock is obtained and the original timestamp in the data packet is read to calculate the total dynamic link latency.

6. The dynamic navigation system with heterogeneous acceleration and time delay compensation according to claim 5, characterized in that, The mathematical model for pose compensation based on the total delay of the dynamic link in the delay compensation module is as follows: in, The position output by the trajectory prediction module. The instantaneous velocity of the target For the instantaneous acceleration of the target, The total latency of the dynamic link is [value]. This is the real-time location after compensation.

7. The dynamic navigation system with heterogeneous acceleration and time delay compensation according to claim 1, characterized in that, The system has an end-to-end latency of less than or equal to 20 milliseconds and a dynamic positioning accuracy of sub-millimeter level.

8. The dynamic navigation system with heterogeneous acceleration and time delay compensation according to claim 1, characterized in that, The application layer is configured to implement system interaction logic, task scheduling and fault diagnosis through a general-purpose CPU, and to use a GPU to assist in the parallel rendering of the navigation interface.

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