Method and system for adjusting pattern density of different structural layers of chip, layout and chip

Abstract

The invention provides a method and system for adjusting pattern density of different structural layers of a chip, a layout and the chip, and belongs to the field of semiconductors. The method for adjusting the pattern density of the different structural layers of the chip comprises the steps that a layout is provided, the layout comprises patterns of the different structural layers of the chip, a target pattern layer is filled with a matrix unit pattern, the matrix unit pattern comprises a plurality of subunit patterns, and the subunit patterns are located in different directions of the center point of the matrix unit pattern; and adjusting parameters of the subunit graphs so as to adjust the graph density of the target graph layer. According to the invention, the added matrix unit patterns are the same, and the plurality of subunit patterns are located in different directions, so that stress concentration and regular parasitic coupling can be avoided, stress can be dispersed in multiple dimensions, distortion of the target pattern layer can be avoided, and the uniformity of CMP can be improved and the parasitic effect can be reduced while the pattern density of the target pattern layer is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method, system, layout, and chip for adjusting the pattern density of different structural layers of a chip. Background Technology

[0002] With the continuous advancement of integrated circuit technology, the linewidth of silicon processes has become smaller than the exposure wavelength, making process stability increasingly difficult. The derivative effects of the process are considered from the early stages of design, leading to numerous Design for Manufacturability (DFM) rules. For example, good pattern density uniformity in silicon wafers, meaning smaller differences in local pattern density, is crucial. Therefore, redundant patterns are added to the chip's structural layer patterning to adjust the pattern density. In semiconductor manufacturing and integrated circuit design, redundant patterns generally refer to patterns or materials without electrical function but with process or structural auxiliary functions. They are mainly used to optimize manufacturing processes, improve yield, or meet design rules, and their core characteristic is that they do not participate in actual circuit operation. Redundant pattern filling is a key technology in integrated circuit manufacturing. Its core objective is to balance the chip's physical characteristics and solve process fluctuations caused by differences in pattern density. It is mainly used to optimize process uniformity (such as CMP planarization) and reduce parasitic effects.

[0003] Adjusting pattern density can first optimize the photolithography process. For example, by filling low-density areas (such as blank areas or wide metal lines) with redundant patterns, the stress distribution during photoresist development becomes more uniform, preventing pattern collapse or deviations in critical dimensions (CD). Secondly, it can improve planarization in chemical mechanical polishing (CMP). For instance, by adjusting local material density and balancing polishing rates through redundant patterns, the uniformity of CMP polishing can be improved. Furthermore, redundant pattern filling can ensure consistent device performance. Adding redundant pattern structures around active devices suppresses edge effects and prevents deviations in electrical parameters (such as fluctuations in the MOSFET threshold voltage Vt). Redundant pattern filling also enables thermal and mechanical stress management. By dispersing stress or optimizing heat conduction paths through redundant pattern filling, chip warpage or reliability failures can be prevented.

[0004] Regarding the layout of redundant patterns, different shapes of fills are typically used within a single layer, such as rectangular fills, square fills, L-shaped fills, T-shaped fills, and strip fills. However, these fill shapes suffer from unidirectional and fixed orientations, easily leading to stress concentration and regular parasitic coupling, and they cannot disperse stress in multiple dimensions. Furthermore, the patterns are prone to distortion, the design rules are complex, requiring manual intervention, and some processes do not yet support certain high-complexity patterns. In semiconductor manufacturing, the shape design of the redundant fill patterns directly affects process uniformity, electrical performance, and reliability. Currently, the redundancy of fill patterns has limited effect on improving CMP uniformity and reducing parasitic effects, and further improvements are needed.

[0005] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a method, system, layout, and chip for adjusting the pattern density of different structural layers of a chip, in order to solve the problem of redundant patterns filling the layers, and the need to improve CMP uniformity and reduce parasitic effects.

[0007] To address the aforementioned technical problems, this invention provides a method for adjusting the pattern density of different structural layers in a chip, comprising:

[0008] A layout is provided, which includes patterns of different structural layers of the chip;

[0009] Based on preset filling rules, the target layer in the structural layer graphics that can be filled with redundant graphics is obtained;

[0010] A matrix unit graphic is filled in the target layer. The matrix unit graphic includes multiple sub-unit graphics. The multiple sub-unit graphics are arranged in multiple directions with the center point of the matrix unit graphic as a reference. The parameters of the sub-unit graphics are adjusted to adjust the graphic density of the target layer.

[0011] Preferably, after filling the target layer with a matrix unit graphic, the matrix unit graphic comprising multiple sub-unit graphics, arranging the multiple sub-unit graphics along multiple directions with the center point of the matrix unit graphic as a reference, and adjusting the parameters of the sub-unit graphics to adjust the graphic density of the target layer, the method further includes:

[0012] Based on the data of the map, obtain the target threshold for the graphic density of the target layer;

[0013] Obtain the dynamic graphic density of the target layer after adding redundant graphics;

[0014] The dynamic graphic density is compared with the target threshold. If the dynamic graphic density is not within the target threshold range, the parameters of the sub-unit graphic are continuously adjusted until the dynamic graphic density of the target layer is within the target threshold range of the target layer.

[0015] Preferably, filling the target layer with matrix unit graphics includes filling the target layer with one or more, or more, matrix unit graphics.

[0016] Preferably, the matrix unit pattern includes four sub-unit patterns, and the four sub-unit patterns are symmetrically distributed along a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other.

[0017] Preferably, the sub-unit graphic includes a rectangle.

[0018] Preferably, the parameters for adjusting the sub-unit graphic include: the width, length, and number of the sub-unit graphic, as well as the spacing between two relatively arranged sub-unit graphics.

[0019] Based on the same inventive concept, this invention also provides a system for adjusting the pattern density of different structural layers of a chip, comprising:

[0020] The acquisition module is used to provide a layout, which includes patterns of different structural layers of the chip;

[0021] Based on preset filling rules, the target layer in the structural layer graphics that can be filled with redundant graphics is obtained;

[0022] A fill module is used to fill the target layer with matrix unit graphics, the matrix unit graphics including multiple sub-unit graphics, the multiple sub-unit graphics are arranged in multiple directions with the center point of the matrix unit graphics as a reference, and the parameters of the sub-unit graphics are adjusted to adjust the graphic density of the target layer.

[0023] Preferably, it further includes:

[0024] The calculation module is used to obtain the target graphic density target threshold of the target layer based on the data of the layout; obtain the dynamic graphic density of the target layer after adding redundant graphics; compare the dynamic graphic density with the target threshold, and if the dynamic graphic density is not within the target threshold range, continuously adjust the parameters of the sub-unit graphics until the dynamic graphic density of the target layer is within the target threshold range of the target layer.

[0025] Based on the same inventive concept, the present invention also provides a layout comprising:

[0026] The pattern density of different structural layers of the chip in the layout is adjusted using the method described above.

[0027] Based on the same inventive concept, the present invention also provides a chip, comprising:

[0028] The different structural layer patterns of the chip are formed using the layout described above.

[0029] Compared with the prior art, the method for adjusting the pattern density of different structural layers of a chip according to the present invention has the following advantages:

[0030] This invention provides a layout that includes patterns of different structural layers of a chip;

[0031] Based on preset filling rules, a target layer that can be filled with redundant graphics in the structural layer graphics is obtained. Matrix unit graphics, comprising multiple sub-unit graphics, are filled into the target layer. These sub-unit graphics are arranged along multiple directions with the center point of the matrix unit graphics as a reference. The parameters of the sub-unit graphics are adjusted to adjust the graphics density of the target layer. Furthermore, each time one, two, or more matrix unit graphics are added, the same rules are used, the design is simple, no manual intervention is required, and graphics processing is also simple. Multiple sub-unit graphics located in different directions can avoid stress concentration and regular parasitic coupling, can disperse stress in multiple dimensions, and can prevent distortion of the target layer. While increasing the graphics density of the target layer, the uniformity of CMP can be improved, and parasitic effects can be reduced.

[0032] The system, layout, and chip for adjusting the pattern density of different structural layers of a chip provided by this invention belong to the same inventive concept as the method for adjusting the pattern density of different structural layers of a chip provided by this invention. Therefore, the system, layout, and chip for adjusting the pattern density of different structural layers of a chip provided by this invention have at least all the advantages of the method for adjusting the pattern density of different structural layers of a chip provided by this invention, which can improve the uniformity of CMP and reduce parasitic effects. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the redundant graphic structure added in one embodiment;

[0034] Figure 2 This is a flowchart of a method for adjusting the pattern density of different structural layers of a chip according to one embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the structure of a matrix unit graphic in one embodiment of the present invention;

[0036] Figure 4This is a schematic diagram of a metal layer pattern after adding a matrix unit pattern in one embodiment of the present invention;

[0037] In the picture,

[0038] 100 - Matrix unit diagram; 110 - Sub-unit diagram;

[0039] 200 - Metal layer pattern. Detailed Implementation

[0040] To make the objectives, advantages, and features of the present invention clearer, the method, system, layout, and chip for adjusting the pattern density of different structural layers of a chip proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only to facilitate and clearly illustrate the objectives of the embodiments of the present invention. It should be understood that the accompanying drawings do not necessarily show the specific structure of the present invention to scale, and the illustrative features used to illustrate certain principles of the present invention in the accompanying drawings will also be drawn in a slightly simplified manner. Specific design features of the present invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0042] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0043] As shown in Figure 1 FIG. 0, in some embodiments, in order to improve the uniformity of CMP polishing, redundant patterns such as those shown in Figure 1 FIG. 1 are usually added to the pattern. As can be seen from Figure 1 FIG. 2, in the pattern of a single-layer structural layer, when adding a pattern combining a square and a rectangle as shown in Figure 1 FIG. 3(a), when adjusting the density of the pattern of this layer, there will be a problem that the added redundant pattern is in a single direction, resulting in stress concentration and regular parasitic coupling. For example, when adding a square as shown in Figure 1 FIG. 3(b) and adjusting the pattern density of this layer, pattern distortion may be caused due to the proximity effect of lithography. For another example, when adding a strip pattern as shown in Figure 1 FIG. 3(c), since the direction of the strip pattern is fixed, stress cannot be dispersed in multiple dimensions. When adding a T-shaped pattern as shown in Figure 1 FIG. 3(d), due to the complex design rules, manual intervention is required, reducing the efficiency of pattern density adjustment. If adding a circular or elliptical pattern as shown in Figure 1 FIG. 3(e), the complexity of pattern processing is high, and some processes do not support it. Therefore, the currently filled patterns are limited in improving CMP uniformity and reducing parasitic effects, and further improvement is needed.

[0044] The core idea of the present invention is to provide a method for adjusting the pattern density of different structural layers of a chip, which can improve the electrical performance and reliability of the chip, improve CMP uniformity, and at the same time achieve the purpose of reducing parasitic effects.

[0045] To achieve the above idea, the present invention provides a method for adjusting the pattern density of different structural layers of a chip, referring to Figures 2 to 4 a specific implementation manner of a method for adjusting the pattern density of different structural layers of a chip disclosed in FIG. 4. The method for adjusting the pattern density of different structural layers of a chip includes the following steps S1 to step S3.

[0046] Step S1: Provide a layout, and the layout includes patterns of different structural layers of the chip.

[0047] Specifically, as shown in Figure 2 FIG. 5, provide a layout, which includes patterns of different structural layers of the chip. For example, different metal layer patterns 200, different via layer patterns, contact hole patterns, gate patterns, etc. Hereinafter, the metal layer pattern 200 will be used as an example for explanation.

[0048] Step S2: Based on a preset filling rule, obtain a target layer for filling redundant patterns in different structural layers of the chip.

[0049] Specifically, referring to Figure 2 FIG. 6 and Figure 4 As shown, from the original layout design data, the data for each metal layer pattern 200, including the pattern density of different regions of the metal layer pattern 200, can be obtained. Based on the pattern density of different regions in the metal layer pattern 200, a target threshold for the pattern density of the metal layer pattern 200 can be defined. Based on the filling rules, the target layers in different structural layers of the chip that can be filled with redundant patterns can be obtained. By obtaining the pattern density of different regions of the metal layer, and based on the redundant pattern filling rules, it is possible to determine whether different regions of the metal layer need to be filled with redundant patterns. Target layers that need to be filled with redundant patterns are marked.

[0050] Step S3: Fill the target layer with matrix unit graphics 100, which includes multiple sub-unit graphics 110. Using the center point of the matrix unit graphics 100 as a reference, arrange the multiple sub-unit graphics 110 in multiple directions. Adjust the parameters of the sub-unit graphics 110 to adjust the graphic density of the target layer.

[0051] Specifically, refer to Figures 2 to 4 As shown, the target area in the target layer that needs to be filled with redundant graphics is filled with rectangular unit graphics 100. This rectangular unit graphic 100 includes multiple sub-unit graphics 110. The rectangular unit graphic 100 includes four sub-unit graphics 110, and the four sub-unit graphics 110 are located in different directions from the center point of the matrix unit graphic 100. The four sub-unit graphics 110 are symmetrically distributed along a first direction and a second direction. The first direction and the second direction are perpendicular to each other. Each sub-unit graphic 110 is a rectangle. The first direction is along the length of the rectangle. The second direction is along the width of the rectangle. When adding the rectangular unit graphic 100, the target area of ​​the metal layer graphic 200 can have one, two, or more rectangular unit graphics 100 added.

[0052] Adjusting the parameters of the rectangle can adjust the graphic density of the target layer. The parameters of the sub-unit graphic 110 include: the width of the sub-unit graphic 110 (i.e., Figure 3 W in the text), length (i.e., Figure 3 The L in the figure), the quantity, and the spacing between the two relatively set sub-unit patterns 110 (i.e., Figure 3 S in (the part).

[0053] After adjusting the graphic density of the target layer, the method further includes:

[0054] Based on the data of the map, obtain the target threshold for the graphic density of the target layer.

[0055] To obtain the dynamic graphic density of the target layer after adding redundant graphics, first, based on layout design rules, select the length L1, width W1, and spacing S1 of two relatively set rectangles. Then, obtain the dynamic graphic density of the target area after adding redundant graphics through a simulation system.

[0056] The dynamic graphic density is compared with the target threshold. If the dynamic graphic density is not within the target threshold range, the parameters of the sub-unit graphic 110 are continuously adjusted until the dynamic graphic density of the target layer is within the target threshold range. If the dynamic graphic density is within the target threshold range, the redundant graphic addition is complete. If the dynamic graphic density is not within the graphic density threshold range, the length L1, width W1, number, and spacing S1 of the two relatively set rectangles are adjusted to further adjust the graphic density of the target layer until the dynamic graphic density of the target area is within the target threshold range. The theoretical density formula is: 4W(L+S) / unit area, where W is the line width of the rectangle, L is the length of the rectangle, and S is the spacing between the two relatively set rectangles. The unit area is the area of ​​the rectangle.

[0057] As shown in Table 1, Table 1 shows the different graphic densities obtained by adjusting the line width (W) and spacing (S) of the rectangle.

[0058] Table 1 shows the different graphic densities obtained by adjusting the line width (W) and spacing (S) of the rectangles. W / μm S / μm density Layout 1 0.25 0.12 54.3% Layout 2 0.25 0.1 52.6% Layout 3 0.2 0.1 48.98% Layout 4 0.18 0.08 45.62% Layout 5 0.15 0.08 41.2%

[0059] As can be seen from Table 1, different graphic densities can be obtained by adjusting W and S.

[0060] Using traditional redundant graphics and the matrix unit graphics 100 disclosed in this embodiment as examples of redundant graphics, the graphics density was obtained through a simulation system, and the coupling capacitance was extracted using Cadence Quantus QRC. The obtained data is shown in Table 2.

[0061] Table 2 shows a comparison of pattern density and coupling capacitance obtained by adding traditional redundant patterns and adding the redundant patterns disclosed in this embodiment. Group <![CDATA[Total coupling capacitance (F / mm 2 )]]> Reduced compared to commonly used redundant graphics density(%) Commonly used redundant graphics 32.5 - 50 Experimental group 1 (W=0.15) 14.8 54.5% 41.2 Experimental group 2 (W=0.2) 16.3 49.8% 48.6 Experimental group 3 (W=0.25) 18.7 42.5% 54.3

[0062] As can be seen from Table 2, the parasitic capacitance of matrix unit pattern 100 is reduced by 42% to 55% within the density range of 40% to 55%. The capacitance is weakly correlated with the density (the capacitance only increases by 26% when the density is greater than 54%). The matrix unit pattern 100 disclosed in this embodiment balances low capacitance and controllable density.

[0063] The method for adjusting the pattern density of different structural layers of a chip disclosed in this embodiment involves filling the target layer with matrix unit patterns 100, which include multiple sub-unit patterns 110. These sub-unit patterns 110 are arranged along multiple directions with the center point of the matrix unit pattern 100 as a reference. Adjusting the length, number, width, and spacing of the sub-unit patterns 110 allows for adjustment of the pattern density of the target layer. Furthermore, each time one, two, or more matrix unit patterns 100 are added, they are identical, resulting in a simple design rule that requires no manual intervention and simplifies pattern processing. The multiple sub-unit patterns 110 are located in different directions, avoiding stress concentration and regular parasitic coupling, dispersing stress in multiple dimensions, and preventing distortion of the target layer. This improves the uniformity of CMP (Chip Motion Processing) and reduces parasitic effects while increasing the pattern density of the target layer. This method for adjusting the pattern density of different structural layers of a chip disclosed in this embodiment improves the efficiency of redundant pattern filling by only changing the pattern structure of the redundant patterns without modifying the filling script.

[0064] To achieve the above idea, this embodiment also discloses a system for adjusting the pattern density of different structural layers of a chip, including:

[0065] The acquisition module is used to provide a layout, which includes patterns of different structural layers of the chip; and to acquire target layers in the structural layer patterns that can be filled with redundant patterns based on filling rules.

[0066] A fill module is used to fill the target layer with a matrix unit graphic 100, the matrix unit graphic 100 including a plurality of sub-unit graphics 110, the plurality of sub-unit graphics 110 being arranged in multiple directions with the center point of the matrix unit graphic 100 as a reference, and adjusting the parameters of the sub-unit graphics 110 to adjust the graphic density of the target layer.

[0067] It also includes a calculation module for obtaining a target threshold for the graphic density of the target layer based on the data of the layout; obtaining the dynamic graphic density of the target layer after adding redundant graphics; comparing the dynamic graphic density with the target threshold, and if the dynamic graphic density is not within the target threshold range, continuously adjusting the parameters of the sub-unit graphic 110 until the dynamic graphic density of the target layer is within the target threshold range of the target layer.

[0068] To achieve the above idea, this embodiment also discloses a layout, including:

[0069] The pattern density of different structural layers of the chip in the layout is adjusted using the method described above.

[0070] To achieve the above idea, this embodiment also discloses a chip, including:

[0071] The different structural layer patterns of the chip are formed using the layout described above.

[0072] The system, layout, and chip for adjusting the pattern density of different structural layers of a chip provided in this embodiment belong to the same inventive concept as the method for adjusting the pattern density of different structural layers of a chip provided in this embodiment. Therefore, the system, layout, and chip for adjusting the pattern density of different structural layers of a chip provided in this embodiment have at least all the advantages of the method for adjusting the pattern density of different structural layers of a chip provided in this embodiment, which can improve the uniformity of CMP and reduce parasitic effects.

[0073] In summary, the above embodiments have provided a detailed description of the method and system for adjusting the pattern density of different structural layers of a chip, the layout, and different chip configurations. Of course, the above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure are within the scope of protection of the claims.

Claims

1. A method for adjusting the pattern density of different structural layers of a chip, characterized in that, The method comprises the following steps: providing a layout, wherein the layout comprises different structural layer patterns of a chip; obtaining a target layer of the structural layer patterns which can be filled with redundant patterns based on a preset filling rule; filling a matrix unit pattern in the target layer, wherein the matrix unit pattern comprises a plurality of sub-unit patterns, the plurality of sub-unit patterns are arranged along a plurality of directions based on a center point of the matrix unit pattern, and parameters of the sub-unit patterns are adjusted to adjust a pattern density of the target layer.

2. The method of claim 1, wherein, After the step of filling the matrix unit pattern in the target layer, the method further comprises the following steps: obtaining a target threshold of the pattern density of the target layer based on data of the layout; obtaining a dynamic pattern density of the target layer after adding the redundant patterns; comparing the dynamic pattern density with the target threshold, and continuously adjusting the parameters of the sub-unit patterns until the dynamic pattern density of the target layer is within the target threshold range of the target layer if the dynamic pattern density is not within the target threshold range.

3. The method of claim 1, wherein, The step of filling the matrix unit pattern in the target layer comprises the following steps:

4. The method of claim 3, wherein, filling one or two, or more than two matrix unit patterns in the target layer.

5. The method of claim 1, wherein, The matrix unit pattern comprises four sub-unit patterns, and the four sub-unit patterns are symmetrically distributed along a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other.

6. The method of claim 1, wherein, The sub-unit pattern comprises a rectangle.

7. A system for adjusting the pattern density of different structural layers of a chip, characterized by: The step of adjusting the parameters of the sub-unit pattern comprises the following steps: adjusting a width, a length, a number, and a spacing between two sub-unit patterns arranged in a relative manner of the sub-unit pattern. The method comprises the following steps: providing a layout, wherein the layout comprises different structural layer patterns of a chip; 8. The system for adjusting the pattern density of different structural layers of a chip according to claim 7, wherein, obtaining a target layer of the structural layer patterns which can be filled with redundant patterns based on a preset filling rule; filling a matrix unit pattern in the target layer, wherein the matrix unit pattern comprises a plurality of sub-unit patterns, the plurality of sub-unit patterns are arranged along a plurality of directions based on a center point of the matrix unit pattern, and parameters of the sub-unit patterns are adjusted to adjust a pattern density of the target layer. The method further comprises the following steps:

9. A layout characterized by, obtaining a target threshold of the pattern density of the target layer based on data of the layout; obtaining a dynamic pattern density of the target layer after adding the redundant patterns; comparing the dynamic pattern density with the target threshold, and continuously adjusting the parameters of the sub-unit patterns until the dynamic pattern density of the target layer is within the target threshold range of the target layer if the dynamic pattern density is not within the target threshold range.

10. A chip, characterized by The method comprises the following steps: adjusting the pattern density of the different structural layers of the chip in the layout by using the method according to any one of claims 1-6. The method comprises the following steps: forming the different structural layer patterns of the chip by using the layout according to claim 9.

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