Regulator and display device

Abstract

The embodiment of the invention discloses a voltage stabilizer and a display device. The voltage stabilizer is configured to supply power to a load through a power supply line after inputting a reference voltage; the power supply line has line impedance; the voltage stabilizer comprises a sampling resistor and a compensating circuit. The compensation circuit is electrically connected with the sampling resistor and is set to obtain compensation voltage according to voltage signals at the two ends of the sampling resistor, and the compensation voltage is used for compensating voltage drop caused by the sampling resistor and the line impedance, so that the voltage input to the load is equal to the reference voltage.

Description

Technical Field

[0001] This disclosure relates to the field of display panel driving technology, and more specifically, to a voltage regulator and a display device. Background Technology

[0002] A voltage regulator, also known as a voltage regulator, is an electronic device that can automatically maintain an output voltage that is approximately constant when the input voltage or load changes. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a voltage regulator and a display device.

[0005] This disclosure provides a voltage regulator configured to supply power to a load via a power supply line after receiving an input reference voltage; the power supply line has line impedance. The voltage regulator includes a sampling resistor and a compensation circuit; The compensation circuit is electrically connected to the sampling resistor and is configured to obtain a compensation voltage based on the voltage signal across the sampling resistor. The compensation voltage is used to compensate for the voltage drop caused by the sampling resistor and the line impedance, so that the voltage input to the load is equal to the reference voltage.

[0006] In one exemplary embodiment, the resistance value of the sampling resistor is determined based on the impedance value of the line impedance and the amplification factor of the compensation circuit.

[0007] In one exemplary embodiment, the compensation voltage is equal to the amplification factor of the voltage drop across the sampling resistor when current flows through it.

[0008] In one exemplary embodiment, the resistance value R of the sampling resistor is... S Calculate according to the following formula: R S =R line / (A-1); Where A represents the magnification factor, R line The impedance value represents the impedance of the line.

[0009] In one exemplary embodiment, the sampling resistor includes a first end away from the line impedance and a second end close to the line impedance; The compensation circuit includes a first differential circuit, a first amplifier, and an adder; The first differential is electrically connected to the sampling resistor and is configured to sample the voltage signal across the sampling resistor and obtain a first difference signal between the voltage signal at the first end and the voltage signal at the second end. The first amplifier is electrically connected to the first differential, and is configured to amplify the first difference signal; The adder is electrically connected to the first amplifier and the first end of the sampling resistor, respectively, and is configured to superimpose the amplified first difference signal with the reference voltage to provide the superimposed signal to the first end of the sampling resistor.

[0010] In one exemplary embodiment, the compensation circuit includes an instrumentation amplifier circuit; The instrumentation amplifier circuit includes a first operational amplifier, a second operational amplifier, a third operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; the sampling resistor includes a first end away from the line impedance and a second end close to the line impedance; The non-inverting input terminal of the first operational amplifier is electrically connected to the first terminal of the sampling resistor, and the inverting input terminal of the first operational amplifier is electrically connected to the output terminal of the first operational amplifier through the first resistor. The non-inverting input terminal of the second operational amplifier is electrically connected to the second terminal of the sampling resistor, and the inverting input terminal of the second operational amplifier is electrically connected to the output terminal of the second operational amplifier through the second resistor; The third resistor is electrically connected to the first resistor and the second resistor respectively; the third resistor is also electrically connected to the inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier respectively. The non-inverting input terminal of the third operational amplifier is electrically connected to the output terminal of the first operational amplifier through a fourth resistor; the non-inverting input terminal of the third operational amplifier is also configured to be connected to the reference voltage through a seventh resistor; The inverting input terminal of the third operational amplifier is electrically connected to the output terminal of the second operational amplifier through a fifth resistor; the inverting input terminal of the third operational amplifier is also electrically connected to the output terminal of the third operational amplifier through a sixth resistor; the output terminal of the third operational amplifier is electrically connected to the first terminal of the sampling resistor.

[0011] In one exemplary embodiment, the magnification includes a first magnification A1; A1 = (1 + 2R1 / R3); Wherein, R1 represents the resistance value of the first resistor; R3 represents the resistance value of the third resistor.

[0012] In one exemplary embodiment, the voltage regulator further includes a reference voltage enhancement circuit; the reference voltage enhancement circuit is electrically connected to the seventh resistor and configured to receive the reference voltage; The reference voltage enhancement circuit includes a fourth operational amplifier; The non-inverting input of the fourth operational amplifier is connected to the reference voltage, and the inverting input of the fourth operational amplifier is electrically connected to the output of the fourth operational amplifier; the output of the fourth operational amplifier is electrically connected to the seventh resistor.

[0013] In one exemplary embodiment, the second end of the line impedance; The compensation circuit includes a second differential circuit, a second amplifier, and a third differential circuit. The second differential is electrically connected to the sampling resistor and is configured to sample the voltage signal across the sampling resistor and obtain a second difference signal by subtracting the voltage signal at the first end from the voltage signal at the second end. The second amplifier is electrically connected to the second differential, and is configured to amplify the second difference signal; The third differential is electrically connected to the second amplifier and the first terminal of the sampling resistor, respectively, and is configured to provide the first terminal of the sampling resistor with a third difference signal between the reference voltage and the amplified second difference signal.

[0014] In one exemplary embodiment, the compensation circuit includes a first circuit and a second circuit; The first circuit includes a fifth operational amplifier, an eighth resistor, and a ninth resistor; the sampling resistor includes a first end away from the line impedance and a second end close to the line impedance; The non-inverting input terminal of the fifth operational amplifier is electrically connected to the second terminal of the sampling resistor, and the inverting input terminal of the fifth operational amplifier is electrically connected to the first terminal of the sampling resistor through the eighth resistor; the inverting input terminal of the fifth operational amplifier is also electrically connected to the output terminal of the fifth operational amplifier through the ninth resistor. The second circuit includes a sixth operational amplifier; the non-inverting input of the sixth operational amplifier is configured to be connected to the reference voltage, and the inverting input of the sixth operational amplifier is electrically connected to the output of the fifth operational amplifier; the output of the sixth operational amplifier is electrically connected to the first end of the sampling resistor.

[0015] In one exemplary embodiment, the magnification includes a second magnification. ; =1+R9 / R8; Wherein, R8 represents the resistance value of the eighth resistor; R9 represents the resistance value of the ninth resistor.

[0016] This disclosure also provides a display device, including: Display panels, flexible substrates, printed circuit boards, and voltage regulators; The display panel is bonded to the printed circuit board via the flexible substrate; the display panel includes pixels and pixel driving circuitry. The voltage regulator is disposed on the printed circuit board and is electrically connected to the input signal line of the pixel driving circuit of at least one pixel on the display panel. The voltage regulator is the voltage regulator described in any of the foregoing embodiments.

[0017] In one exemplary embodiment, the input signal line includes an initial signal line.

[0018] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0019] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0020] Figure 1 A schematic diagram of power supply for the voltage regulator in an embodiment of this disclosure; Figure 2 This is one of the schematic diagrams of a voltage regulator according to an embodiment of this disclosure; Figure 3 This is one of the schematic diagrams of the voltage regulator according to an embodiment of this disclosure; Figure 4 for Figure 3 A schematic diagram of the equivalent power supply circuit of the voltage regulator shown. Figure 5 This is a second schematic diagram of a voltage regulator according to an embodiment of this disclosure; Figure 6 This is a third schematic diagram of a voltage regulator according to an embodiment of this disclosure; Figure 7 This is a second schematic diagram of the voltage regulator according to an embodiment of this disclosure; Figure 8 for Figure 7 A schematic diagram of the equivalent power supply circuit of the voltage regulator shown. Figure 9 This is a fourth schematic diagram of a voltage regulator according to an embodiment of this disclosure; Figure 10 This is one of the schematic diagrams of a display device according to an embodiment of the present disclosure; Figure 11 This is a second schematic diagram of a display device according to an embodiment of the present disclosure; Figure 12 This is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure; Figure 13 for Figure 12 The timing diagram of the circuit shown. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0022] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0023] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0024] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0025] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0026] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0027] In this specification, the first electrode can be the drain electrode, the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. The third electrode can be the gate electrode. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0028] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0029] Figure 1 A schematic diagram of an existing voltage regulator power supply is shown. Figure 1 In the circuit, the voltage regulator, line impedance RLine, and load impedance RLoad are connected in series along the current flow direction. Figure 1 middle This is the reference voltage.

[0030] Regulator output voltage ; and, ;in, This is the loop current; The impedance value is the line impedance. This is the impedance value of the load impedance; The actual voltage obtained at the load end for ; It is related to both load impedance and line impedance, resulting in unstable voltage on the load.

[0031] Figure 2 This is one of the schematic diagrams of a voltage regulator according to an embodiment of this disclosure. Figure 2 As shown, the load is powered through a power supply line after being configured to input a reference voltage; the power supply line has a line impedance RLine. The voltage regulator includes a compensation circuit 10 and a sampling resistor 20; The compensation circuit 10 is electrically connected to the sampling resistor 20 and is configured to obtain a compensation voltage based on the voltage signal across the sampling resistor 20. The compensation voltage is used to compensate for the voltage drop caused by the sampling resistor 20 and the line impedance RLine, so that the voltage input to the load is equal to the reference voltage.

[0032] The voltage regulator in this embodiment of the present disclosure sets up a sampling resistor and a compensation circuit. By obtaining a compensation voltage based on the voltage signal across the sampling resistor, the voltage drop caused by the sampling resistor and line impedance is compensated by the compensation voltage, so that the voltage input to the load is equal to the voltage regulator's own reference voltage, and is independent of the load impedance, line impedance and loop current, thereby ensuring the stability of the load voltage.

[0033] In one exemplary embodiment, the resistance value of the sampling resistor is determined based on the impedance value of the line impedance and the amplification factor of the compensation circuit.

[0034] The amplification function of the compensation circuit is achieved by a corresponding amplifier circuit.

[0035] Figure 3 This is a schematic diagram of the voltage regulator according to an embodiment of the present disclosure, as shown below. Figure 3As shown, the voltage regulator includes a first differential circuit D1, a first amplifier Am1, an adder Ad1, and a first sampling resistor RS1. The first differential circuit D1 can be a two-input, single-output device, with the output voltage being the difference between the two input voltages (i.e., the "+" terminal minus the "-" terminal). The two input terminals of the first differential circuit D1 are a non-inverting input ("+") and an inverting input ("-"). The non-inverting input terminal of the first differential circuit D1 is electrically connected to the first end of the first sampling resistor RS1 furthest from the line impedance RLine, and the inverting input terminal of the first differential circuit D1 is electrically connected to the second end of the first sampling resistor RS1 closest to the line impedance RLine. The first amplifier Am1 is a single-input, single-output device, with the output voltage being A1 times the input voltage. The input terminal of the first amplifier Am1 is electrically connected to the output terminal of the first differential circuit D1. The adder Ad1 can be a two-input, single-output device, with the output voltage being the sum of the voltages at both input terminals. One of the two input terminals of adder Ad1 is electrically connected to the output terminal of first amplifier Am1; the other of the two input terminals of adder Ad1 is configured to be connected to a reference voltage. The output terminal of adder Ad1 is electrically connected to the first terminal of first sampling resistor RS1 away from the line impedance RLine; This represents the voltage value at the second end of the first sampling resistor RS1, which is close to the line impedance RLine, and is the output voltage of the voltage regulator. This represents the voltage value at the first terminal of the first sampling resistor RS1 that is furthest from the line impedance RLine. equal - , This represents the voltage drop across the first sampling resistor RS1. Figure 3 The first differential D1, the first amplifier Am1, and the adder Ad1 in the circuit correspond to the compensation circuit described above.

[0036] Figure 4 for Figure 3 The schematic diagram of the equivalent power supply circuit of the voltage regulator shown is as follows: Figure 4 As shown, the first sampling resistor RS1, the line impedance RLine, and the load impedance RLoad are connected in series. Assuming the current in the load impedance RLoad loop is I, then... ; Assumption Figure 3 The amplification factor of the first amplifier Am1 is A1, and the voltage drop across the first sampling resistor RS1 is... According to Figure 3 have: ; Compensation voltage = In this case, ,at this time = .in, This represents the reference voltage of the voltage regulator. This indicates the resistance value of the first sampling resistor RS1. This represents the impedance value of the line impedance RLine. This represents the impedance value of the load impedance RLoad.

[0037] As can be seen from the above, the compensation voltage is equal to the first amplification factor of the voltage drop across the sampling resistor when the current flows through it.

[0038] Figure 5 This is a second schematic diagram of a voltage regulator according to an embodiment of this disclosure. Figure 5 As shown, the voltage regulator includes a first sampling resistor RS1 and a compensation circuit. The compensation circuit includes an instrumentation amplifier circuit 40. The instrumentation amplifier circuit 40 is equivalent to the aforementioned first differential circuit, first amplifier, and adder.

[0039] The instrumentation amplifier circuit 40 includes a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7; the first sampling resistor RS1 includes a first end away from the line impedance RLine and a second end close to the line impedance RLine. The non-inverting input terminal of the first operational amplifier U1 is electrically connected to the first terminal of the first sampling resistor RS1, and the inverting input terminal of the first operational amplifier U1 is electrically connected to the output terminal of the first operational amplifier U1 through the first resistor R1. The non-inverting input terminal of the second operational amplifier U2 is electrically connected to the second terminal of the first sampling resistor RS1, and the inverting input terminal of the second operational amplifier U2 is electrically connected to the output terminal of the second operational amplifier U2 through the second resistor R2. The third resistor R3 is electrically connected to the first resistor R1 and the second resistor R2 respectively; the third resistor R3 is also electrically connected to the inverting input terminal of the first operational amplifier U1 and the inverting input terminal of the second operational amplifier U2 respectively. The non-inverting input of the third operational amplifier U3 is electrically connected to the output of the first operational amplifier U1 through the fourth resistor R4; the non-inverting input of the third operational amplifier U3 is also configured to be connected to a reference voltage through the seventh resistor R7. The inverting input terminal of the third operational amplifier U3 is electrically connected to the output terminal of the second operational amplifier U2 through the fifth resistor R5; the inverting input terminal of the third operational amplifier U3 is also electrically connected to the output terminal of the third operational amplifier U3 through the sixth resistor R6; the output terminal of the third operational amplifier U3 is electrically connected to the first terminal of the first sampling resistor RS1. In this example, the resistance of the first resistor R1 is equal to the resistance of the second resistor R2; in some other embodiments, the resistance of the first resistor R1 may not be equal to the resistance of the second resistor R2.

[0040] Among them, the resistance value of the fourth resistor R4 is equal to that of the seventh resistor R7.

[0041] for Figure 5 ,have: + (1) (2) The resistance value of the fourth resistor R4 The resistance value of the seventh resistor R7 When they are equal: (3) Substituting equations (1) and (2) into equation (3) yields the following: ; The resistance value of the first resistor R1 The resistance value of the second resistor R2 Under the same circumstances, ; Because there are: - ; therefore, ; in, This represents the voltage value at point P1. This represents the voltage value at point P2. This represents the voltage value at point P3. This represents the voltage value at point P4. This represents the voltage value at point P5.

[0042] Figure 5 The amplification factor of the instrumentation amplifier circuit 40 shown is equal to (1+2R1 / R3) (corresponding to the aforementioned first amplification factor A1), where R1 represents the resistance value of the first resistor and R3 represents the resistance value of the third resistor.

[0043] Figure 6 This is a third schematic diagram of a voltage regulator according to an embodiment of this disclosure. Figure 6 As shown, with Figure 5 The difference lies in the fact that the voltage regulator also includes a reference voltage enhancement circuit 50. The reference voltage enhancement circuit 50 is electrically connected to the seventh resistor R7 and is configured to receive a reference voltage. The reference voltage enhancement circuit 50 includes a fourth operational amplifier U4. The non-inverting input of the fourth operational amplifier U4 is configured to be connected to a reference voltage. The inverting input terminal of the fourth operational amplifier U4 is electrically connected to the output terminal of the fourth operational amplifier U4. The output terminal of the fourth operational amplifier U4 is electrically connected to one end of the seventh resistor, and the other end of the seventh resistor is electrically connected to the non-inverting input terminal of the third operational amplifier U3.

[0044] The reference voltage enhancement circuit in this embodiment can achieve electrical isolation between the preceding and following stages, enhance signal driving capability, and reduce the load effect on the signal source.

[0045] In one exemplary embodiment, at least one of the first resistor, the second resistor, the sampling resistor, and the third resistor is a digital potentiometer; The voltage regulator also includes a controller; the controller is electrically connected to the digital potentiometer. The controller is configured to adjust the digital potentiometer according to the line impedance, such that the compensation voltage is equal to a first amplification factor of the voltage drop across the sampling resistor when current flows through it.

[0046] That is, the first resistor Second resistor The first sampling resistor RS1 and the third resistor At least one of the resistors is adjustable, and when the line impedance changes, if the first resistor... Second resistor The first sampling resistor RS1 and the third resistor If at least one of the resistance values ​​remains unchanged, it will be impossible to satisfy the requirement. =R line / ( A1-1). Therefore, in this case, the controller controls the first resistor. Second resistor The first sampling resistor RS1 and the third resistor Adjusting at least one of the resistance values ​​can restore the desired performance. =R line / ( A1-1).

[0047] Figure 7 This is a second schematic diagram of the voltage regulator according to an embodiment of this disclosure, as shown below. Figure 7As shown, the voltage regulator includes a second differential circuit D2, a second amplifier Am2, a third differential circuit D3, and a second sampling resistor RS2. The second differential circuit D2 is a two-input, single-output device; the output voltage is the difference between the two input voltages (i.e., the "+" terminal minus the "-" terminal). The two input terminals of the second differential circuit D2 include a non-inverting input and an inverting input. The non-inverting input of the second differential circuit D2 is electrically connected to the second end of the second sampling resistor RS2 closest to the line impedance, and the inverting input of the second differential circuit D2 is electrically connected to the first end of the second sampling resistor RS2 furthest from the line impedance. The second amplifier Am2 is a single-input, single-output device; the output voltage is a second amplification factor of the input voltage. The output of the second differential circuit D2 is electrically connected to the input of the second amplifier Am2. The third differential circuit D3 can be a dual-input, single-output device, with the output voltage being the difference between the two input voltages. The two inputs of the third differential circuit D3 include a non-inverting input and an inverting input. The non-inverting input of the third differential circuit D3 is set to be connected to a reference voltage, and the inverting input of the third differential circuit D3 is electrically connected to the output of the second amplifier Am2. The output of the third differential circuit D3 is electrically connected to the first end of the second sampling resistor RS2 that is furthest from the line impedance RLine.

[0048] This represents the voltage value of the second sampling resistor RS2 near the second end of the line impedance RLine, which is the output voltage of the voltage regulator. This represents the voltage value at the first terminal of the second sampling resistor RS2 that is furthest from the line impedance RLine. equal - , This represents the voltage drop across the second sampling resistor RS2.

[0049] Figure 8 for Figure 7 The schematic diagram of the equivalent power supply circuit of the voltage regulator shown is as follows: Figure 8 As shown, the second sampling resistor RS2, the line impedance RLine, and the load impedance RLoad are connected in series. Assuming the current in the load impedance RLoad loop is I, then... ; according to Figure 7 have: ; Compensation voltage = In this case, . At this time, among them, This represents the reference voltage of the voltage regulator. This indicates the resistance value of the second sampling resistor RS2. This represents the impedance value of the line impedance RLine. This represents the impedance value of the load impedance RLoad. express Figure 7 The amplification factor of the second amplifier Am2 is shown.

[0050] Figure 9 This is a fourth schematic diagram of a voltage regulator according to an embodiment of this disclosure. Figure 9 As shown, the voltage regulator includes a second sampling resistor RS2, a first circuit 60, and a second circuit 70. Figure 9 The function of the first circuit 60 shown is equivalent to Figure 7 The function of the second differential circuit D2 and the second amplifier Am2. The second circuit 70 is equivalent to... Figure 7 The role of the third differential in the circuit.

[0051] The first circuit 60 includes a fifth operational amplifier U5, an eighth resistor R8, and a ninth resistor R9; the second sampling resistor RS2 includes a first end away from the line impedance RLine and a second end close to the line impedance RLine. The non-inverting input of the fifth operational amplifier U5 is electrically connected to the second terminal of the second sampling resistor RS2, and the inverting input of the fifth operational amplifier U5 is electrically connected to the first terminal of the second sampling resistor RS2 through the eighth resistor R8; the inverting input of the fifth operational amplifier U5 is also electrically connected to the output terminal of the fifth operational amplifier U5 through the ninth resistor R9. The second circuit 70 includes a sixth operational amplifier U6, the non-inverting input of which is configured to be connected to a reference voltage. The inverting input of the sixth operational amplifier U6 is electrically connected to the output of the fifth operational amplifier U5; the output of the sixth operational amplifier U6 is electrically connected to the first terminal of the second sampling resistor RS2.

[0052] Those skilled in the art will know that, due to the "virtual short" of the operational amplifier in deep negative feedback, the non-inverting input of the operational amplifier... and inverting input voltage same. That is, the above Figure 7 In .

[0053] For the fifth operational amplifier, then we have ;in, This represents the input voltage at the non-inverting input terminal of the fifth operational amplifier. This represents the input voltage at the inverting input terminal of the second operational amplifier.

[0054] Furthermore, due to the "virtual open circuit" of the operational amplifier in deep negative feedback, both the non-inverting and inverting input terminals are in a high-impedance state. The voltage is directly determined by the voltage division between the eighth resistor R8 and the ninth resistor R9: ; The resistance of the eighth resistor R8 is... The resistance of the ninth resistor R9 is ; This is the voltage at the output terminal of the fifth operational amplifier U5. Right now Figure 7 In .

[0055] Then there is, ; because Right now Figure 7 In , That is, the above Figure 7 In , = Therefore, we have: ; For the sixth operational amplifier U6, we have: ; therefore, ; And because ; Then we have: ; In order to Then there is, ;Right now .

[0056] Combination Figures 7 to 8 We can conclude that: ; because ; When the voltage value of the compensation signal is In the case of, there are .at this time, = ; = .

[0057] Figure 10 This is a schematic diagram of a display device according to an embodiment of the present disclosure, such as... Figure 10 As shown, the display device includes a display panel 100, a flexible substrate 200, a printed circuit board 300, and a voltage regulator 310; The display panel 100 is bonded to the printed circuit board 300 via a flexible substrate 200; the display panel 100 includes pixels and pixel driving circuitry. A voltage regulator 310 is disposed on a printed circuit board 300 and is electrically connected to the input signal line of the pixel driving circuit of at least one pixel on the display panel 100; exemplarily, the input signal line includes an initial signal line.

[0058] The voltage regulator 310 is the voltage regulator described in any of the foregoing embodiments.

[0059] For example, the display panel and the flexible substrate are bonded using FOG (Film On Glass, i.e., flexible circuitry mounted on a glass panel). The printed circuit board and the flexible substrate are bonded using FOB (Film On Board, i.e., flexible circuitry mounted on a printed circuit board) (e.g.) Figure 11 (As shown).

[0060] The line impedance on the connection line between the voltage regulator and the input signal line includes the trace impedance on the display panel, the bonding impedance between the display panel and the flexible substrate, and the bonding impedance between the printed circuit board and the flexible substrate.

[0061] For example, the sampling resistor RS is located on the display panel, typically on the flexible substrate FPC or printed circuit board PCB of the display device.

[0062] The following methods can be considered to obtain it; 1) Perform line impedance simulation on the display panel; 2) Use a resistance measuring instrument to test the impedance from the end closest to the load to the load point across the sampling resistor RS; 3) Measurement may be omitted when simulation or measurement is inconvenient. Instead of adjusting the resistance value, the optical characteristics of the display panel are monitored in real time by continuously adjusting the resistance value of the sampling resistor RS until a better optical characteristic is achieved. The corresponding resistance value of the sampling resistor RS at this point is the optimal value of the sampling resistor RS.

[0063] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure, and this disclosure does not limit it in any way.

[0064] Figure 12 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. (Example) Figure 12As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 capacitor C. Specifically, the gate electrode of the first transistor T1 is electrically connected to the reset signal line Reset, the first terminal of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second terminal of the first transistor T1 is electrically connected to the first node N1; the gate electrode of the second transistor T2 is electrically connected to the scan signal line Gate, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the third node N3; the gate electrode of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3; the gate electrode of the fourth transistor T4 is electrically connected to the scan signal line Gate, the first terminal of the fourth transistor T4 is electrically connected to the data signal line Data, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2; the gate electrode of the fifth transistor T5 is electrically connected to the light emission signal line EM, the first terminal of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2; the sixth transistor T... The gate electrode of transistor T6 is electrically connected to the light-emitting signal line EM. The first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate electrode of the seventh transistor T7 is electrically connected to the reset signal line Reset. The first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The first plate of capacitor C is electrically connected to the first node N1, and the second plate of capacitor C is electrically connected to the first power supply line VDD.

[0065] The light-emitting device L can be electrically connected to the fourth node N4 and the second power line VSS, respectively.

[0066] The first power line VDD continuously provides a high-level signal, and the second power line VSS continuously provides a low-level signal.

[0067] Figure 13 for Figure 12 The provided timing diagram shows the operation of the pixel driving circuit. The following is a demonstration of its operation. Figure 12 The operation of the example pixel driving circuit during the display phase illustrates an exemplary embodiment of this disclosure. Figure 13 This explanation is based on the example that the first transistor T1 to the seventh transistor M7 can be P-type transistors.

[0068] Combination Figure 12 and Figure 13 As shown, the operation of the pixel driving circuit can include: In the first stage, P1, also known as the initialization stage, the signals on the scan signal line Gate and the light emission signal line EM are high-level signals, while the signals on the reset signal line Reset and the data signal line Data are low-level signals. The first transistor T1 and the seventh transistor T7 are turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0069] When the first transistor T1 is turned on, the signal of the first initial signal line INIT1 is written to the first node N1 through the turned-on first transistor T1, initializing (resetting) the first node N1, clearing its internal pre-stored voltage, and completing the initialization. When the seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4 through the turned-on seventh transistor T7, initializing (resetting) the first electrode of the light-emitting device L, clearing its internal pre-stored voltage, and completing the initialization.

[0070] The second stage, P2, is called the data writing stage or threshold compensation stage. The Reset signal line, the EM signal line, and the Data signal line are all high-level signals, while the Gate signal line is low-level. The second transistor T2 and the fourth transistor T4 are turned on, while the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0071] The fourth transistor T4 is turned on, the second transistor T2 is turned on, and the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vdata-|Vth|, where Vdata is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor T3.

[0072] In the third stage, P3, also known as the light-emitting stage, the signals of the Reset signal line, the Gate signal line, and the Data signal line are high-level signals, while the signal of the EM light-emitting signal line is low-level. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned off.

[0073] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device L to emit light.

[0074] For example, the input signal line may include the initial signal line of the pixel driving circuit. The load at this time can be... Figure 13 The capacitance C in the pixel driving circuit when it is in the P1 stage, or the parasitic capacitance of the OLED.

[0075] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0076] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0077] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0078] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0079] In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0080] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0081] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0082] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0083] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A voltage regulator, characterized in that, The voltage regulator is configured to supply power to the load via a power supply line after receiving an input reference voltage; the power supply line has line impedance. The voltage regulator includes a sampling resistor and a compensation circuit; The compensation circuit is electrically connected to the sampling resistor and is configured to obtain a compensation voltage based on the voltage signal across the sampling resistor. The compensation voltage is used to compensate for the voltage drop caused by the sampling resistor and the line impedance, so that the voltage input to the load is equal to the reference voltage.

2. The voltage regulator as described in claim 1, characterized in that, The value of the sampling resistor is determined based on the impedance value of the line impedance and the amplification factor of the compensation circuit.

3. The voltage regulator as described in claim 2, characterized in that, The compensation voltage is equal to the amplification factor of the voltage drop across the sampling resistor when current flows through it.

4. The voltage regulator as described in claim 2, characterized in that, The resistance value R of the sampling resistor S Calculate according to the following formula: R S =R line / (A-1); Where A represents the magnification factor, R line The impedance value represents the impedance of the line.

5. The voltage regulator according to any one of claims 1-4, characterized in that, The sampling resistor includes a first end that is far from the line impedance and a second end that is close to the line impedance; The compensation circuit includes a first differential circuit, a first amplifier, and an adder; The first differential is electrically connected to the sampling resistor and is configured to sample the voltage signal across the sampling resistor and obtain a first difference signal between the voltage signal at the first end and the voltage signal at the second end. The first amplifier is electrically connected to the first differential, and is configured to amplify the first difference signal; The adder is electrically connected to the first amplifier and the first end of the sampling resistor, respectively, and is configured to superimpose the amplified first difference signal with the reference voltage to provide the superimposed signal to the first end of the sampling resistor.

6. The voltage regulator as described in any one of claims 2-4, characterized in that, The compensation circuit includes an instrumentation amplifier circuit; The instrumentation amplifier circuit includes a first operational amplifier, a second operational amplifier, a third operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; the sampling resistor includes a first end away from the line impedance and a second end close to the line impedance; The non-inverting input terminal of the first operational amplifier is electrically connected to the first terminal of the sampling resistor, and the inverting input terminal of the first operational amplifier is electrically connected to the output terminal of the first operational amplifier through the first resistor. The non-inverting input terminal of the second operational amplifier is electrically connected to the second terminal of the sampling resistor, and the inverting input terminal of the second operational amplifier is electrically connected to the output terminal of the second operational amplifier through the second resistor; The third resistor is electrically connected to the first resistor and the second resistor respectively; the third resistor is also electrically connected to the inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier respectively. The non-inverting input terminal of the third operational amplifier is electrically connected to the output terminal of the first operational amplifier through a fourth resistor; the non-inverting input terminal of the third operational amplifier is also configured to be connected to the reference voltage through a seventh resistor; The inverting input terminal of the third operational amplifier is electrically connected to the output terminal of the second operational amplifier through a fifth resistor; the inverting input terminal of the third operational amplifier is also electrically connected to the output terminal of the third operational amplifier through a sixth resistor; the output terminal of the third operational amplifier is electrically connected to the first terminal of the sampling resistor.

7. The voltage regulator as described in claim 6, characterized in that, The magnification factor includes a first magnification factor A1; A1 = (1 + 2R1 / R3); Wherein, R1 represents the resistance value of the first resistor; R3 represents the resistance value of the third resistor.

8. The voltage regulator as described in claim 6, characterized in that, The voltage regulator further includes a reference voltage enhancement circuit; the reference voltage enhancement circuit is electrically connected to the seventh resistor and is configured to receive the reference voltage; The reference voltage enhancement circuit includes a fourth operational amplifier; The non-inverting input of the fourth operational amplifier is connected to the reference voltage, and the inverting input of the fourth operational amplifier is electrically connected to the output of the fourth operational amplifier; the output of the fourth operational amplifier is electrically connected to the seventh resistor.

9. The voltage regulator according to any one of claims 1-4, characterized in that, The sampling resistor includes a first end that is far from the line impedance and a second end that is close to the line impedance; The compensation circuit includes a second differential circuit, a second amplifier, and a third differential circuit. The second differential is electrically connected to the sampling resistor and is configured to sample the voltage signal across the sampling resistor and obtain a second difference signal by subtracting the voltage signal at the first end from the voltage signal at the second end. The second amplifier is electrically connected to the second differential, and is configured to amplify the second difference signal; The third differential is electrically connected to the second amplifier and the first terminal of the sampling resistor, respectively, and is configured to provide the first terminal of the sampling resistor with a third difference signal between the reference voltage and the amplified second difference signal.

10. The voltage regulator as described in any one of claims 2-4, characterized in that, The compensation circuit includes a first circuit and a second circuit; The first circuit includes a fifth operational amplifier, an eighth resistor, and a ninth resistor; the sampling resistor includes a first end away from the line impedance and a second end close to the line impedance; The non-inverting input terminal of the fifth operational amplifier is electrically connected to the second terminal of the sampling resistor, and the inverting input terminal of the fifth operational amplifier is electrically connected to the first terminal of the sampling resistor through the eighth resistor; the inverting input terminal of the fifth operational amplifier is also electrically connected to the output terminal of the fifth operational amplifier through the ninth resistor. The second circuit includes a sixth operational amplifier; the non-inverting input of the sixth operational amplifier is configured to be connected to the reference voltage, and the inverting input of the sixth operational amplifier is electrically connected to the output of the fifth operational amplifier; the output of the sixth operational amplifier is electrically connected to the first end of the sampling resistor.

11. The voltage regulator as described in claim 10, characterized in that, The magnification includes a second magnification. ; =1+R9 / R8; Wherein, R8 represents the resistance value of the eighth resistor; R9 represents the resistance value of the ninth resistor.

12. A display device, characterized in that, include: Display panels, flexible substrates, printed circuit boards, and voltage regulators; The display panel is bonded to the printed circuit board via the flexible substrate; the display panel includes pixels and pixel driving circuitry. The voltage regulator is disposed on the printed circuit board and is electrically connected to the input signal line of the pixel driving circuit of at least one pixel on the display panel. The voltage regulator is the voltage regulator as described in any one of claims 1 to 11.

13. The display device as claimed in claim 12, characterized in that, The input signal lines include the initial signal lines.

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