Low-power-consumption low-voltage detector

Abstract

The invention provides a low-power-consumption low-voltage detector, which relates to the technical field of detectors and comprises a detection branch, a bias branch and an output shaping module, the first end of the detection branch is connected with power supply voltage, the second end is connected with the bias branch, and the detection branch is used for outputting an overturning signal when the power supply voltage reaches set detection voltage; the bias branch is used for providing stable bias voltage for the detection branch and has a temperature compensation function; and the output shaping module is connected with the output end of the detection branch and is used for shaping the overturning signal and then outputting a detection signal. In the mode, ultralow detection voltage, ultralow power consumption, temperature stability, high process angle robustness and small chip area are realized, and the detection voltage is programmable.

Description

Technical Field

[0001] This invention relates to the field of detector technology, and in particular to a low-power, low-voltage detector. Background Technology

[0002] As IoT nodes evolve towards self-powered operation, energy harvesting systems become crucial. Voltage detectors in such systems are responsible for core functions such as monitoring power status and controlling cold starts, directly impacting system reliability and energy efficiency.

[0003] In related technologies, voltage detectors are mostly based on bandgap references or simple dual-tube comparison structures, which generally suffer from problems such as high power consumption (microwatt level), high minimum operating voltage (often higher than 0.4V), poor temperature stability, weak process robustness, and fixed detection voltage. These issues make it difficult to meet the stringent requirements of energy harvesting systems for ultra-low voltage, nanowatt-level power consumption, and high stability. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a low-power, low-voltage detector that achieves ultra-low detection voltage, ultra-low power consumption, temperature stability, high process corner robustness, small chip area, and programmable detection voltage.

[0005] In a first aspect, embodiments of the present invention provide a low-power, low-voltage detector, comprising: a detection branch, a bias branch, and an output shaping module; a first end of the detection branch is connected to a power supply voltage, and a second end is connected to the bias branch, for outputting a flip signal when the power supply voltage reaches a set detection voltage; the bias branch is used to provide a stable bias voltage for the detection branch and has a temperature compensation function; the output shaping module is connected to the output end of the detection branch and is used to shape the flip signal and output a detection signal.

[0006] In a preferred embodiment of the present invention, the detection branch described above includes: a first PMOS transistor and a first NMOS transistor; the first PMOS transistor and the first NMOS transistor are connected in series; the source of the first PMOS transistor is connected to the power supply voltage, and the gate is connected to a programmable bias voltage; the gate of the first NMOS transistor is connected to the bias voltage output by the bias branch, and the drain is connected to the drain of the first PMOS transistor, serving as the output node of the detection branch.

[0007] In a preferred embodiment of the present invention, the first PMOS transistor is a medium threshold voltage transistor, and the first NMOS transistor is a low threshold voltage transistor.

[0008] In a preferred embodiment of the present invention, the bias branch described above includes: a second PMOS transistor and a second NMOS transistor; the second PMOS transistor and the second NMOS transistor are connected in series in a diode-like manner; the gate and drain of the second PMOS transistor are connected together and connected to the gate and drain of the second NMOS transistor; the source of the second NMOS transistor is grounded, and the source of the second PMOS transistor is connected to the power supply voltage.

[0009] In a preferred embodiment of the present invention, the second PMOS transistor is a low threshold voltage transistor, and the second NMOS transistor is a medium threshold voltage transistor.

[0010] In a preferred embodiment of the present invention, a programmable bias voltage generation module is further included, which is used to provide a programmable bias voltage to the gate of the first PMOS transistor.

[0011] In a preferred embodiment of the present invention, the programmable bias voltage generation module includes a resistor divider network to obtain a programmable bias voltage from the power supply voltage.

[0012] In a preferred embodiment of the present invention, the programmable bias voltage generation module includes: an on-chip programmable voltage divider; The on-chip programmable voltage divider consists of a resistor ladder formed by multiple PMOS transistors connected by diodes and a multiplexer, used to realize the detection voltage setting for digital programming.

[0013] In a preferred embodiment of the present invention, the output shaping module includes at least one inverter chain for buffering and shaping the flip signal output by the detection branch.

[0014] The embodiments of the present invention bring the following beneficial effects: This invention provides a low-power, low-voltage detector, comprising: a detection branch, a bias branch, and an output shaping module. The first end of the detection branch is connected to a power supply voltage, and the second end is connected to the bias branch, for outputting a flip signal when the power supply voltage reaches a set detection voltage. The bias branch provides a stable bias voltage for the detection branch and has temperature compensation functionality. The output shaping module is connected to the output end of the detection branch and shapes the flip signal before outputting a detection signal. This method achieves ultra-low detection voltage, ultra-low power consumption, temperature stability, high process corner robustness, small chip area, and programmable detection voltage.

[0015] Other features and advantages of this disclosure will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0016] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a structural diagram of a low-power, low-voltage detector provided in an embodiment of the present invention; Figure 2 This is a structural diagram of another low-power, low-voltage detector provided in an embodiment of the present invention; Figure 3 A circuit diagram of a low-power, low-voltage detector provided for an embodiment of the present invention; Figure 4 This is a schematic diagram of the measured results of a low-power, low-voltage detector provided in an embodiment of the present invention.

[0019] Illustration: 10 - Detection branch; 20 - Bias branch; 30 - Output shaping module; 40 - Programmable bias voltage generation module; PM2 - First PMOS transistor; NM1 - First NMOS transistor; PM1 - Second PMOS transistor; NM2 - Second NMOS transistor; VDD - Power supply voltage; 31 - Inverter chain. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] With the explosive growth of IoT smart nodes, traditional battery-powered solutions are becoming unsustainable due to high maintenance costs. Energy harvesting technology has thus become crucial for realizing self-powered IoT nodes. In energy harvesting systems, voltage detectors play a vital role in monitoring system voltage, controlling cold starts, and assisting in maximum power point tracking. Their performance directly impacts the reliability and energy conversion efficiency of the entire system.

[0022] However, existing voltage detector technologies suffer from the following key bottlenecks: Traditional bandgap reference schemes are complex in structure and require a supply voltage greater than 1V. They need modules such as a bandgap reference source, comparator, and voltage divider network, resulting in high power consumption (usually in the microwatt range), high startup voltage (usually >1V), and large chip area, which cannot meet the requirements of energy harvesting systems for extremely low static power consumption and ultra-low operating voltage.

[0023] The simplified scheme using two transistors to form a current comparator has poor temperature characteristics. Although the structure is simple, the detection voltage changes significantly with temperature, the temperature coefficient is high, and the temperature stability is insufficient over a wide temperature range (e.g., -40°C to 125°C).

[0024] Poor process robustness: In a scheme where two transistors form a current comparator, the detection voltage is determined by the threshold difference, which is easily affected by process variations, seriously impacting the consistency and reliability of the system in mass production.

[0025] Limited lower operating voltage: Most solutions require a supply voltage of at least 0.4V to operate normally, which is not suitable for the ultra-low voltage operating environment of less than 0.3V commonly found in advanced energy harvesting systems.

[0026] Lack of flexibility: The detection voltage is fixed, making it difficult to adapt to the diverse requirements of different energy harvesting scenarios for detection thresholds.

[0027] Based on this, an embodiment of the present invention provides a low-power, low-voltage detector, comprising: a detection branch, a bias branch, and an output shaping module; a first end of the detection branch is connected to a power supply voltage, and a second end is connected to the bias branch, for outputting a flip signal when the power supply voltage reaches a set detection voltage; the bias branch provides a stable bias voltage for the detection branch and has a temperature compensation function; the output shaping module is connected to the output end of the detection branch and is used to shape the flip signal before outputting a detection signal. This approach achieves ultra-low detection voltage, ultra-low power consumption, temperature stability, high process corner robustness, small chip area, and programmable detection voltage.

[0028] To facilitate understanding of this embodiment, a low-power, low-voltage detector disclosed in this embodiment of the invention will first be described in detail.

[0029] Example 1 This invention provides a low-power, low-voltage detector. Figure 1 This is a structural diagram of a low-power, low-voltage detector provided in an embodiment of the present invention. Figure 1 As shown, the low-power, low-voltage detector may include the following structure: a detection branch 10, a bias branch 20, and an output shaping module 30; The first end of the detection branch 10 is connected to the power supply voltage VDD, and the second end is connected to the bias branch 20, which is used to output a flip signal when the power supply voltage VDD reaches the set detection voltage.

[0030] The bias branch 20 is used to provide a stable bias voltage for the detection branch 10 and has a temperature compensation function.

[0031] The output shaping module 30 is connected to the output terminal of the detection branch 10 and is used to shape the flip signal and output the detection signal.

[0032] This invention provides a low-power, low-voltage detector, comprising: a detection branch 10, a bias branch 20, and an output shaping module 30. The first terminal of the detection branch 10 is connected to a power supply voltage VDD, and the second terminal is connected to the bias branch 20, for outputting a flip signal when the power supply voltage VDD reaches a set detection voltage. The bias branch 20 provides a stable bias voltage for the detection branch 10 and has a temperature compensation function. The output shaping module 30 is connected to the output terminal of the detection branch 10 and is used to shape the flip signal before outputting a detection signal. This method achieves ultra-low detection voltage, ultra-low power consumption, temperature stability, high process corner robustness, small chip area, and programmable detection voltage.

[0033] Example 2 This invention also provides another low-power low-voltage detector; this low-power low-voltage detector is implemented based on the low-power low-voltage detector of the above embodiments.

[0034] Figure 2 A structural diagram of another low-power, low-voltage detector provided in an embodiment of the present invention is shown below. Figure 2 As shown, the low-power low-voltage detector may also include the following structure: a programmable bias voltage generation module 40.

[0035] The programmable bias voltage generation module 40 is used to provide a programmable bias voltage to the gate of the first PMOS transistor PM2.

[0036] The programmable bias voltage generation module 40 includes a resistor divider network to obtain a programmable bias voltage from the power supply voltage VDD.

[0037] The programmable bias voltage generation module 40 includes: an on-chip programmable voltage divider; The on-chip programmable voltage divider consists of a resistor ladder formed by multiple PMOS transistors connected by diodes and a multiplexer, used to realize the detection voltage setting for digital programming.

[0038] For example, Figure 3 A circuit diagram of a low-power, low-voltage detector provided for an embodiment of the present invention is shown below. Figure 3 As shown.

[0039] The detection branch 10 includes a first PMOS transistor PM2 and a first NMOS transistor NM1.

[0040] Specifically, the first PMOS transistor PM2 and the first NMOS transistor NM1 are connected in series. The source of the first PMOS transistor PM2 is connected to the power supply voltage VDD, and the gate is connected to a programmable bias voltage. The gate of the first NMOS transistor is connected to the bias voltage output by the bias branch 20, and the drain is connected to the drain of the first PMOS transistor PM2, serving as the output node of the detection branch 10.

[0041] Among them, the first PMOS transistor PM2 is a medium threshold voltage transistor, and the first NMOS transistor NM1 is a low threshold voltage transistor.

[0042] In this circuit, the first NMOS transistor NM1 serves as a constant current source. The detection principle is based on the comparison of the currents in the two branches: when the power supply voltage VDD rises to a certain level, and the current of the first PMOS transistor PM2 exceeds the current of the first NMOS transistor NM1, the output node flips.

[0043] Specifically, the bias branch 20 includes: a second PMOS transistor PM1 and a second NMOS transistor NM2.

[0044] Specifically, the second PMOS transistor PM1 and the second NMOS transistor NM2 are connected in series in a diode configuration; the gate and drain of the second PMOS transistor PM1 are connected together and connected to the gate and drain of the second NMOS transistor NM2; the source of the second NMOS transistor NM2 is grounded, and the source of the second PMOS transistor PM1 is connected to the power supply voltage VDD.

[0045] Among them, the second PMOS transistor PM1 is a low threshold voltage transistor, and the second NMOS transistor NM2 is a medium threshold voltage transistor.

[0046] Specifically, the subthreshold leakage current of the PMOS transistor is used to provide bias for the NMOS transistor, generating a bias voltage that is relatively insensitive to process and temperature changes, thus providing a stable operating point for the first NMOS transistor NM1 in the detection branch 10.

[0047] The output shaping module 30 includes at least one inverter chain 31 for buffering and shaping the flip signal output by the detection branch 10.

[0048] Regarding the mechanism for achieving ultra-low detection voltage and high stability: Threshold voltage difference as a detection benchmark: Through theoretical derivation, the constant part of the detection voltage V_DET expression in this embodiment mainly depends on the difference between the medium and low threshold values ​​of the same type of transistor (ΔV_th=V_th_medium-V_th_low). Since the V_th changes of the two threshold devices are strongly correlated under the same process angle, the sensitivity of the difference ΔV_th to process fluctuations is much lower than that of the absolute value of a single V_th, thereby significantly improving the process robustness of the detection voltage from a physical perspective.

[0049] Built-in temperature compensation mechanism: The ΔV_th term in the detection voltage expression has a positive temperature coefficient (PTAT), while by carefully designing the dimensions of each transistor (width / length ratio W / L), the logarithmic term related to the thermal voltage V_T can be adjusted to produce a compensation voltage with a negative temperature coefficient (CTAT). The superposition of these two factors achieves temperature compensation of the detection voltage over a wide temperature range. Through optimization, the embodiments of this application achieve an extremely low average temperature coefficient of only 33.8 μV / °C in the range of -40°C to 125°C.

[0050] Unique biasing technology enhances robustness: The proposed 2T biasing circuit not only provides a stable bias point (bias voltage) V_BN for the detection branch, but also ensures that the threshold difference originates from transistors of the same type (N or P) with different threshold voltages, rather than transistors of different types with different threshold voltages. This improves process robustness and enhances the accuracy of detecting the flip point.

[0051] Regarding methods for achieving flexible programmability of the detection voltage: Gate bias is introduced: A programmable bias voltage with an independent bias control terminal is set at the gate of the first PMOS transistor in the detection transistor. This is the key to realizing the programmable function. According to theoretical analysis, the final detection voltage satisfies the linear relationship: V_DET = V_DET0 + V_BP, where V_DET0 is the basic detection voltage determined by the core circuit when the programmable bias voltage V_BP = 0.

[0052] Voltage divider network programming: In practical applications, different programmable bias voltage values ​​can be obtained from the power supply voltage using a simple external or on-chip resistor voltage divider network, thus linearly adjusting the detection threshold. This invention further demonstrates how to combine this external voltage divider network with the core detection circuit to form a power-on reset circuit with hysteresis functionality, where both the power-on detection voltage V_POR and the undervoltage detection voltage V_BOD can be precisely set through the voltage divider ratio.

[0053] Advanced Programmable Solution: For applications requiring multi-level detection voltages, this invention proposes integrating an on-chip programmable voltage divider. This divider can be configured as a resistance ladder using a series of diode-connected PMOS transistors, and different tap voltages can be selected as programmable bias voltages via a digitally controlled multiplexer. This allows the detection voltage to be digitally programmed in discrete steps, greatly enhancing the circuit's applicability and flexibility.

[0054] 4. Achieving ultra-low power consumption and small area core design Subthreshold operating mode: All core transistors operate in the subthreshold region, utilizing the exponential drain current characteristics to operate normally at extremely low supply voltages (as low as 0.3V), while limiting the quiescent current to the nanoampere level (typically 5nA), ultimately achieving ultra-low quiescent power consumption in the 1.5nW range.

[0055] Extremely minimal component count: The entire voltage detection function is implemented using only 4 MOS transistors and a few inverters (for output buffering and signal shaping). Compared to traditional solutions, it saves a large number of components such as reference sources, comparators, and precision voltage divider resistors. Under 65nm CMOS technology, it occupies an extremely small chip area of ​​only 20μm×13μm=260μm², making it ideal for integration into area-constrained energy harvesting chips.

[0056] Figure 4 This is a schematic diagram of the measured results of a low-power, low-voltage detector provided in an embodiment of the present invention.

[0057] like Figure 4 As shown, through the combination of the above-mentioned technical means, the embodiments of this application have successfully overcome many difficulties in existing voltage detector technologies. Experimental (post-simulation) results show that this voltage detector can operate at a power supply voltage of 0.3V, achieving an ultra-low detection voltage of 240mV with a standard deviation of only 6.6mV (process corner and mismatch). Its average temperature coefficient is as low as 33.8 μV / °C within the temperature range of -40°C to 125°C, while its power consumption is only 1.5nW. Its performance achieves an excellent balance between the detection voltage lower limit, power consumption, area, and robustness, making it particularly suitable for key functions such as cold start, voltage monitoring, and mode switching in energy harvesting systems such as photovoltaics, thermoelectrics, and radio frequency. It provides a reliable power management solution for the development of ultra-low voltage self-powered IoT nodes.

[0058] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low-power, low-voltage detector, characterized in that, include: Detection branch, bias branch, and output shaping module; The first end of the detection branch is connected to the power supply voltage, and the second end is connected to the bias branch, which is used to output a flip signal when the power supply voltage reaches the set detection voltage. The bias branch is used to provide a stable bias voltage for the detection branch and has a temperature compensation function; The output shaping module is connected to the output terminal of the detection branch and is used to shape the flip signal and output the detection signal.

2. The low-power, low-voltage detector according to claim 1, characterized in that, The detection branch includes: a first PMOS transistor and a first NMOS transistor; the first PMOS transistor and the first NMOS transistor are connected in series; The source of the first PMOS transistor is connected to the power supply voltage, and the gate is connected to a programmable bias voltage. The gate of the first NMOS is connected to the bias voltage output by the bias branch, and the drain is connected to the drain of the first PMOS transistor, serving as the output node of the detection branch.

3. The low-power, low-voltage detector according to claim 2, characterized in that, The first PMOS transistor is a medium threshold voltage transistor, and the first NMOS transistor is a low threshold voltage transistor.

4. The low-power, low-voltage detector according to claim 2, characterized in that, The bias branch includes: a second PMOS transistor and a second NMOS transistor; the second PMOS transistor and the second NMOS transistor are connected in series in a diode-like manner; The gate and drain of the second PMOS transistor are connected together, and are also connected to the gate and drain of the second NMOS transistor; The source of the second NMOS transistor is grounded, and the source of the second PMOS transistor is connected to the power supply voltage.

5. The low-power, low-voltage detector according to claim 4, characterized in that, The second PMOS transistor is a low threshold voltage transistor, and the second NMOS transistor is a medium threshold voltage transistor.

6. The low-power, low-voltage detector according to claim 2, characterized in that, It also includes a programmable bias voltage generation module for providing a programmable bias voltage to the gate of the first PMOS transistor.

7. The low-power, low-voltage detector according to claim 6, characterized in that, The programmable bias voltage generation module includes a resistor divider network to obtain a programmable bias voltage from the power supply voltage.

8. The low-power, low-voltage detector according to claim 6, characterized in that, The programmable bias voltage generation module includes: an on-chip programmable voltage divider; The on-chip programmable voltage divider consists of a resistor ladder formed by multiple PMOS transistors connected by diodes and a multiplexer, used to realize the detection voltage setting for digital programming.

9. The low-power, low-voltage detector according to claim 1, characterized in that, The output shaping module includes at least one inverter chain for buffering and shaping the flip signal output from the detection branch.

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