Apparatus and method for managing memory access

Abstract

The invention relates to a device and a method for managing memory access. Various memory access management schemes are described. The access requests received from a plurality of processing units in a particular order may be responded by providing instructions requested by the access requests or by providing alternative instructions (or any combination thereof) that cause the processing units to later re-access. When a timing requirement associated with the access request is expected not to be met, the alternative instruction may be provided to ensure a continuous flow of access requests that may be compromised if the timing requirement is ultimately met.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to electronic systems, and more specifically to devices and methods for managing memory access. Background Technology

[0002] Various types of electronic devices, such as logic circuits, can store and process data. A logic circuit is an electronic circuit that processes digital signals or binary information, which can take two possible values ​​(usually represented as 0 and 1). Logic circuits use logic gates to manipulate and transform signals or binary information. Digital logic circuits can be used in a wide range of electronic devices, including, for example, computers, calculators, digital clocks, and many other electronic devices that employ digital processing. Digital logic circuits can be designed to perform specific logical operations on digital inputs to produce digital outputs, and in some cases, they can be combined to form more complex circuits to perform more complex operations. Summary of the Invention

[0003] In one aspect, this disclosure provides a method for managing memory access, comprising: sequentially receiving, from a plurality of processing units, a plurality of access requests, each comprising a plurality of addresses of memory, for accessing a plurality of first instructions from the plurality of addresses; retrieving, from memory locations corresponding to the plurality of addresses, the plurality of first instructions; and providing, based on a determination of whether a corresponding timing requirement associated with each of the plurality of first instructions is expected to be satisfied, the plurality of first instructions or a plurality of second instructions, or any combination thereof, to one or more respective processing units of the plurality of processing units in the order of receiving the plurality of access requests; wherein each second instruction, when executed by the respective processing unit, causes the respective processing unit to access a corresponding address among the plurality of addresses.

[0004] In another aspect, this disclosure provides an apparatus for managing memory access, comprising: a controller including a plurality of caches; wherein the controller is further configured to: receive, respectively, a plurality of addresses corresponding to corresponding locations of memory shared by the plurality of processing units in a specific order from a plurality of processing units; fetch a plurality of first instructions from the corresponding locations of the memory; and provide, at each location in the specific order, a corresponding first instruction of a plurality of first instructions or a corresponding second instruction of a plurality of second instructions to one or more corresponding processing units based on a determination of whether timing requirements of each processing unit are expected to be met.

[0005] In another aspect, this disclosure provides a system for managing memory access, comprising: a plurality of processing units; a memory shared by the plurality of processing units and configured to store instructions; and a controller configured to: sequentially receive a plurality of addresses from the plurality of processing units, each address corresponding to a corresponding instruction among a plurality of instructions; fetch a plurality of instructions from the memory; and respond to each of the plurality of processing units in the order in which the plurality of addresses are received from the plurality of processing units at the controller: in response to determining that a timing requirement associated with the provision of the corresponding instruction is expected to be met, providing the corresponding instruction among the plurality of instructions to the corresponding processing unit; and in response to determining that a timing requirement associated with the corresponding instruction is expected not to be met, providing the corresponding alternative instruction to the corresponding processing unit to replace the corresponding instruction, wherein the corresponding alternative instruction, when executed by the corresponding processing unit, causes the corresponding processing unit to access the address corresponding to the corresponding instruction. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 Examples of portions of a computing system for managing memory access according to some embodiments of the present disclosure are shown.

[0008] Figure 2A-2C The process of managing memory access according to some embodiments of the present disclosure is illustrated.

[0009] Figure 3 This is a flowchart corresponding to a method for managing memory access according to various embodiments of the present disclosure. Detailed Implementation

[0010] Various aspects of this disclosure relate to apparatus and methods for managing memory access. Instruction memory is a dedicated type of memory in a computing system designed to store the instructions required by processing units (such as CPUs or microcontrollers) to execute programs. The efficiency of this fetching process is critical to overall system performance because the speed and timing of instruction retrieval and execution directly affect the ability of processing units to perform operations without delay or interruption. Instruction memory is typically optimized for fast access to ensure that processing units can retrieve and execute instructions in a timely manner, maintaining a smooth and efficient workflow within the system.

[0011] In a multi-core processing system, multiple processing units or "cores" can be integrated within a single processor. Each core can independently execute instructions and run tasks, allowing the system to perform multiple operations simultaneously, thereby increasing overall processing power and efficiency. These systems are designed to handle more complex workloads, improve performance in multitasking environments, and enhance parallel processing capabilities, making them ideal for applications that require powerful computing capabilities, such as gaming, data processing, and scientific simulations.

[0012] In some multi-core processing systems, a dedicated instruction memory is provided that can be shared by multiple processing units within the system. This architecture allows each processing unit to access instructions independently, even when multiple processing units are executing the same code. However, this approach has several limitations. A significant problem is the lack of flow control for memory responsiveness to processing latency. If memory data is not provided in a timely manner, this deficiency can cause the entire processing unit to pause, resulting in inefficiency in processing speed and overall performance.

[0013] In some other multi-core processing systems, a separate instruction memory is provided for each processing unit of the system. While this approach may not compromise performance and simplifies implementation, it is highly inefficient in terms of both the area occupied by the processing unit and its power consumption. Even when running the same task, each processing unit is coupled to its own memory, resulting in significant waste of resources, especially in systems with many processing units deployed. For example, in a system with up to 16 identical NAND flash controller (NFC) blocks, each equipped with its own embedded processing unit, the duplication of instruction memory represents a huge overhead in terms of silicon area and power usage.

[0014] In another alternative approach, multiple processing units may share a single memory, which introduces the risk of conflicts when multiple processing units attempt to access memory simultaneously. This is particularly problematic when the processing unit's memory interface lacks flow control, often requiring clock gating across the entire processing unit to manage latency in the instruction stream, which can severely degrade performance. For example, clock gating can pause the execution of the current instruction, which can be especially detrimental in cases where delayed instructions are never used (e.g., in cases of branch misprediction or instruction flushing). Given that processing units typically employ instruction prefetching and each instruction may require more than one clock cycle on average, the performance impact of such latency can be significant.

[0015] Various embodiments of this disclosure address these challenges by introducing a solution that efficiently incorporates flow control into the memory interface, making it readily adaptable to a wide range of processing units, controllers, etc. More specifically, embodiments are specifically designed to manage conflicts without requiring a pause during processing unit operation.

[0016] As used herein, the term "conflict" refers to an event in which two or more processing units or controllers simultaneously attempt to access the same resource (e.g., memory or communication channel), resulting in a potential conflict. Such conflicts, if left unmanaged, can disrupt system operation by causing delays, data corruption, or other unintended consequences. In various embodiments, when a conflict occurs, the system does not halt the processing unit but instead returns an alternative instruction, such as a jump instruction (alternatively referred to as a "pseudo-jump instruction"), thereby ensuring the continuous operation of the processing unit. This provides a practical and effective means of enhancing the performance of computing systems and optimizing their resource utilization, particularly in systems with multiple processing units operating simultaneously.

[0017] Nevertheless, this spurious jump instruction may cause a slight performance degradation because it essentially introduces a NOP (no-op) loop into the execution sequence of the processing unit. However, there are examples where the processing unit can simply discard the spurious jump instruction without adversely affecting performance.

[0018] In one instance, more complex processing units typically exhibit higher clock-per-instruction ratios, where each instruction can span several clock cycles due to the complexity of operations such as decoding, execution, and memory access. This is especially true for instructions involving multiple processing stages, such as floating-point operations, memory accesses, or instructions that require interaction with multiple functional units within the processing unit. Because these instructions naturally extend over multiple clock cycles, the processing unit pipeline is often busy processing these instructions in parallel stages, meaning that spurious jump instructions, which function similarly to NOPs (No Operation), can be easily absorbed into the gaps between these stages. Therefore, spurious jump instructions do not significantly degrade system operation or overall performance.

[0019] In another instance where the latency caused by a spurious jump is effectively masked by other instructions that have already consumed multiple clock cycles, the impact on performance can be minimal. The processing unit can continue executing complex instructions without noticeable interruptions, thus maintaining stable throughput. Therefore, the overall system performance can remain largely unaffected by instructions containing spurious jumps, as the natural latency and overlap of multi-cycle instructions provide ample opportunity to hide such latency.

[0020] Figure 1Examples of portions of a computing system for managing memory access according to some embodiments of the present disclosure are shown. The computing system 100 may be a computing device, such as a desktop computer, laptop computer, server, web server, mobile computing device, vehicle (e.g., airplane, drone, train, car, or other transport vehicle), Internet of Things (IoT) enabled device, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment, or networked business device), system-on-a-chip (SoC), chipset (e.g., a collection of integrated circuits), tile, field-programmable gate array (FPGA) architecture (e.g., a segmented FPGA architecture), or such computing device including memory and processing means. As used herein, the term "mobile computing device" generally refers to a handheld computing device having a tablet or phablet form factor. Generally, a tablet form factor may include a display screen between approximately 3 inches and 5.2 inches (diagonally measured), while a phablet form factor may include a display screen between approximately 5.2 inches and 7 inches (diagonally measured). However, examples of "mobile computing device" are not limited thereto, and in some embodiments, "mobile computing device" may refer to an IoT device, as well as other types of edge computing devices.

[0021] like Figure 1 As shown, computing system 100 includes initiator components 102-1, ..., 102-N. Initiator component 102 (alternatively referred to as initiator, host, processing unit, etc.) is an entity that provides access requests. For example, initiator component 102 may generate and issue (e.g., provide) access requests to access a location within memory 106 (e.g., to write data to or to read data from said location). Although embodiments are not limited thereto, initiator component 102 may be a processing resource, including various processing units such as a central processing unit (CPU), a direct memory access (DMA) processor, a digital signal processor (DSP), etc.

[0022] In some embodiments, the initiator component 102 may each be a separate processor, which may be implemented as different intellectual property (IP) cores (e.g., separate blocks of data and / or logic within an application-specific integrated circuit or field-programmable gate array). Alternatively, the initiator component 102 may be multiple cores (e.g., a CPU) within a single IP core, such as in a multi-core processor design.

[0023] Computing system 100 includes memory 106. In various embodiments, memory 106 may be tightly coupled memory (TCM), which refers to memory located near initiator 102 and / or intermediate component 104 and having constant access time (e.g., deterministic), while cache memory has variable access time due to the possibility of cache "hit" or "miss". TCM is typically used for critical routines and / or real-time tasks that may require constant access time. In the example where memory 106 is TCM, it may be implemented as, for example, DRAM or SRAM. Memory 106 may store data, information, instructions, etc., that can be accessed by initiator component 102.

[0024] Accessing memory 106 via initiator component 102 may include fetching instructions from memory 106. For example, initiator component 102 may each be a processing unit (e.g., CPU) that can access memory 106 to fetch instructions and execute the instructions upon receipt. Fetching instructions from memory 106 may involve providing an address (via intermediate component 104) to memory 106 from which the instructions will be fetched.

[0025] The types of instructions that can be retrieved from memory 106 include, but are not limited to, data transfer instructions (such as load, store, move, push, and pop), arithmetic instructions (such as add, subtract, multiply, divide, increment, and decrement), logical instructions (including AND, OR, XOR, NOT, and shift operations), control flow instructions (such as jump, conditional jump, call, return, and loop), comparison instructions (compare and test), bit manipulation instructions (set / clear bits and rotate), input / output instructions (enter and leave), special instructions (NOP and pause), floating-point instructions (for arithmetic operations on floating-point numbers and load / store operations), and vector / multimedia instructions (SIMD and multimedia-specific operations).

[0026] like Figure 1 As shown, the computing system 100 includes an intermediate component 104 (alternatively referred to as controller 104), through which the initiator component 102 can access memory 106. The intermediate component 104 may include hardware circuitry for performing the operations described herein. For example, the intermediate component 104 may include a dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry.

[0027] like Figure 1 As shown, memory 106 can be “shared” by multiple initiator components 102. In other words, data stored in the same memory 106 can be accessed (e.g., retrieved and utilized) by multiple initiator components 102. In a particular instance where memory 106 stores instructions, these instructions can be fetched to multiple initiator components 102 and executed at multiple initiator components 102.

[0028] Intermediate component 104 may include and / or provide caches 107-1, ..., 107-N (collectively referred to as cache 107) and queues 109-1, ..., 109-N (collectively referred to as queue 109) for the respective initiator components 102-1, ..., 102-N. Cache 107 may temporarily store data for the corresponding initiator component 102, such as recently and / or frequently accessed data retrieved from memory 106. Queue 109 may temporarily store access requests provided by and received from the respective initiator component 102. In an instance where memory 106 stores instructions that can be retrieved by initiator component 102, cache 107 may store instructions retrieved from memory 106, while queue 109 may store access requests provided by and received from initiator component 102 (which may take the form of an address of the memory 106 to be accessed).

[0029] For example, intermediate component 104 includes a conflict manager 108 operable to satisfy requirements associated with access requests received from initiator component 102. In a non-limiting example, conflict manager 108 may arrange accesses to memory 106 and organize data accessed (e.g., retrieved) from memory 106 such that the data can be sent to cache 107 in the same order as received at intermediate component 104 (e.g., queue 109). Additionally, intermediate component 104 includes a size resolver 105 (alternatively referred to as an "instruction length resolver") that can identify the size (e.g., the length of an instruction) of the data retrieved from memory 106. Conflict manager 108 and size resolver 105 may each include hardware circuitry for performing the operations described herein. For example, conflict manager 108 and size resolver 105 may each include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry.

[0030] Utilizing various circuits (e.g., those mentioned above), intermediate component 104 can manage data retrieval (e.g., instruction fetching) from memory 106 to provide conflict-free access for multiple initiator components 102. More specifically, intermediate component 104 can manage access requests from initiator components 102 in a manner that ensures various requirements associated with the access requests (e.g., timing requirements) are still met, even if data retrieval is delayed due to memory 106 being accessed by multiple initiator components 102. Further details related to the management of access requests are detailed in [the relevant section]. Figure 2A-2C As shown in the image.

[0031] Figure 2A-2C The process of managing memory access according to some embodiments of the present disclosure is illustrated. Figure 2A-2CThe processing units 202-1 and 202-2 (collectively referred to as processing unit 202), instruction caches 207-1 and 207-2 (collectively referred to as instruction cache 207), conflict manager 208, and memory 206 shown in the figure can be respectively similar to Figure 1 The shown components are the initiator component 102, cache 107, conflict manager 108, and memory 106. Although in Figure 2A-2C Two processing units 202-1 and 202-2 are shown, but the embodiments are not limited to a specific number of processing units (e.g., processing units 102 and 202) whose access requests can be managed when instructions are fetched from memory 106 and 206.

[0032] like Figure 2A As shown, access requests are provided from processing unit 202-1 in the form of addresses 222-1, 222-2, 222-3, and 222-4 (e.g., “A1”, “A2”, “A3”, and “A4”), and from processing unit 202-2 in the form of addresses 222-5, 222-6, and 222-7 (e.g., “B5”, “B6”, and “B7”). Addresses “A1”, …, “A4” and “B5”, …, “B7” may correspond to the locations in memory 206 where the instructions to be fetched are stored, respectively. More specifically, (e.g., during the first round 223-1) addresses may be provided from processing unit 202-1 in the order of “A1”, “A2”, “A3”, and “A4”, and from processing unit 202-2 in the order of “B5”, “B6”, and “B7”, to an intermediate component (e.g., intermediate component 104).

[0033] Each "time slot" (where an address 222-1, ..., 222-7, instruction 224-1, ..., 224-7 and / or instruction 226-1, 226-2, 226-4, 226-5, 226-6, 226-7 is located, such as...) Figure 2B-2CThe numbers shown may represent clock cycle units (e.g., one or more clock cycles). For example, from processing unit 202-1 to intermediate component 104, address "A1" is provided during a first clock cycle unit; address "A2" is provided during a second clock cycle unit; address "A3" is provided during a fourth clock cycle unit (after a third clock cycle unit, which is "empty"); and address "A4" is provided during a sixth clock cycle unit (after a fifth clock cycle unit, which is "empty"). Similarly, from processing unit 202-2 to intermediate component 104, address "B5" is provided during a first clock cycle unit; address "B6" is provided during a fifth clock cycle unit (after the second, third, and fourth clock cycle units, which are "empty"); and address "B7" is provided during a sixth clock cycle unit. Although the embodiments are not limited thereto, the clock cycles for the operation of processing units 202-1 and 202-2 may be the same.

[0034] In (for example, Figure 1 The conflict manager 208 of the intermediate component 104 shown receives these addresses 222 provided by the processing units 202-1 and 202-2. For example... Figure 2B As shown, the conflict manager 208 manages conflicts between timings that receive addresses substantially simultaneously from different processing units 202, and typically provides these addresses to memory 206 in the order they are received at intermediate component 104 (address 222). Figure 2B In the non-limiting example shown, the conflict manager 208 may prioritize address "A1" over address "B5" (which is received substantially simultaneously with address "A1") and address "B7" over address "A4" (which is received substantially simultaneously with address "B7"); thus, address 222 is provided to memory 206 in the order of "A1" (e.g., in the first position of the order), "B5" (e.g., in the second position of the order), "A2" (e.g., in the third position of the order), "A3" (e.g., in the fourth position of the order), "B6" (e.g., in the fifth position of the order), "B7" (e.g., in the sixth position of the order), and "A4" (e.g., in the seventh position of the order).

[0035] Providing address 222 to memory 206 causes instructions to be fetched from address 222 of memory 206 to intermediate component 104. For example... Figure 2B As shown, instructions 224-1, ..., 224-7, such as "D1", ..., "D7" (corresponding to addresses "A1", "A2", "A3", "A4", "B5", "B6", and "B7" respectively), are fetched from memory 206 (and sent to intermediate component 104). Figure 2A-2C In the non-limiting example shown, instructions 224-1, ..., 224-7 are fetched from memory 206 at locations corresponding to addresses 222-1, ..., 222-7, respectively. Although the embodiment is not limited to a specific order in which instructions are fetched from memory 206, instructions 224 are fetched in the order of "D1", "D5", "D2", "D3", "D6", "D7", and "D4".

[0036] Instructions stored in and retrieved from memory 206 can have various lengths, such as single-length or multi-length (or alternatively referred to as "variable-length"). For example, such as Figure 2B As shown, instructions "D2", "D4", "D5" and "D7" are indicated as having a single length ("single"), instructions "D1" and "D6" are indicated as having a double length ("double"), and instruction "D3" is indicated as "option", as... Figure 2B As shown in the image.

[0037] As used herein, each single-length instruction can have a fixed size, such as a word in the architecture (e.g., 32 bits or 4 bytes, but other sizes are possible). Additionally, multi-length instructions can consist of two or more of these single-length units (e.g., more than the size of a word), allowing for the encoding of more complex operations. More specifically, instructions with double lengths can be twice the size of single-length instructions.

[0038] exist Figure 2A-2C In the non-limiting example shown, "D1" indicating "double" and "D2" indicating "single" can be part of the same instruction, where "D1" is the first part of the instruction (alternately referred to as the "head") and "D2" is the second part of the instruction (alternately referred to as the "tail"). Similarly, in Figure 2A-2C In the non-limiting example shown, “D6” indicating “double” and “D7” indicating “single” can be part of the same instruction, wherein “D6” is the first part of the instruction (alternately referred to as the “head”) and “D7” is the second part of the instruction (alternately referred to as the “tail”).

[0039] Instruction 224 fetched from memory 206 may be (e.g., temporarily) stored in an instruction cache, such as instruction caches 207-1 and 207-2 (e.g., corresponding to processing units 202-1 and 202-2, respectively). Access requests provided by processing units 202-1 and 202-2 (e.g., in the form of addresses “A1”, ..., “A4” and “B5”, ..., “B7”) may be responded to in the order in which they are received at intermediate component 104. Additionally, responses to access requests (e.g., address 222) may be implemented according to timing requirements set by processing units 202-1 and 202-2.

[0040] In a non-limiting example, the timing requirements that can be set by each processing unit 202 may include the requirement to provide instructions (e.g., corresponding to each address provided from processing unit 202) within a specific time period (e.g., a clock cycle). While intermediate component 104 may provide processing unit 202 with instructions (e.g., instruction 224) obtained from an address (e.g., address 222) if doing so still satisfies the timing requirements, intermediate component 104 may instead provide processing unit 202 with alternative instructions (e.g., instruction 226) to ensure that the timing requirements are met and the flow of operation of the processing unit is maintained. For example, when a corresponding instruction (e.g., “D1”, ..., “D7”) is required to satisfy a timing requirement, instruction cache 207 may provide the corresponding instruction if it is available at instruction cache 207, or instruction cache 207 may provide an alternative instruction (e.g., a jump instruction) if the corresponding instruction is unavailable (or expected to be unavailable) when it is required to satisfy the timing requirement.

[0041] exist Figure 2C In the non-limiting example shown, since instruction 224-1 is double-length and another part of the double-length instruction (e.g., "D2") is not yet available, jump instruction 226-1 ("J1") returns to processing unit 202-1 in place of instruction 224-1 (e.g., "D1"). Similarly, since instruction 224-1 was not previously returned, jump instruction 226-2 ("J2") returns to processing unit 202-1 in place of instruction 224-2 (e.g., "D2").

[0042] Continuing with a non-limiting example, since instruction 224-3 is received in time at instruction cache 207-1 and is available to satisfy the timing requirements of processing unit 202-2, instruction 224-3 (e.g., "D3") may return to processing unit 202-1. In some embodiments, the return instruction 224-3 may be redundant because, depending on the prefetch architecture of processing unit 202-1, instruction 224-3 may be ignored after issuing two jump instructions 226-1 and 226-2. Therefore, intermediate component 104 may intentionally choose to provide another jump instruction (instead of "D3") (along with "J1" and "J2") to processing unit 202-2 during the first round 223-1, even though instruction 224-3 is available in instruction cache 207-1. In this case, "D3" along with other instructions "D1", "D2", and "D4" may be provided to processing unit 202-1 during the "second" round 223-2. On the other hand, if instruction 224-3 has already been sent to processing unit 202-1 during the “first” round 223-1, instruction cache 207-1 may optionally choose to store or discard instruction 224-3 based on instruction relevance after the jump instruction is issued.

[0043] Furthermore, since instruction "D4" is not yet available in a timely manner (e.g., in instruction cache 207-1) to meet the timing requirements of processing unit 202-1, jump instruction "J4" returns to processing unit 202-1. Similarly, since instruction "D5" is not yet available in a timely manner (e.g., in instruction cache 207-2) to meet the timing requirements of processing unit 202-2, jump instruction "J5" returns to processing unit 202-2.

[0044] Furthermore, since instruction "D6" is a double-length instruction and the other part of the double-length instruction ("D7") is not yet available, in response to access request "B6" from processing unit 202-2, jump instruction "J6" returns to processing unit 202-2. Similarly, since instruction "D6" has not been returned previously, in response to access request "B7" from processing unit 202-2, jump instruction "J7" returns to processing unit 202-2.

[0045] Each jump instruction, when executed by the corresponding processing unit 202, causes the corresponding processing unit 202 to "jump" (e.g., access) the address specified by the jump instruction in memory 206. More specifically, jump instructions 226-1, 226-2, 226-4, 226-5, 226-6, and 226-7 can respectively cause processing units 202-1 and 202-2 to "jump," and during the second round 223-2, issue access requests to intermediate component 104 corresponding to (e.g., in the form of) "A1," "A2," "A4," "B5," "B6," and "B7," respectively. Figure 2AAs shown in the illustration. Although the embodiments are not limited thereto, jump instructions (e.g., jump instruction 226) may be generated at the corresponding cache (e.g., instruction cache 207-1, 207-2).

[0046] After the first round 223-1, if instructions 224-1, 224-2, 224-4, 224-5, 224-6, and 224-7 are already available in instruction caches 207-1 and 207-2, then instruction caches 207-1 and 207-2 can respond to access requests corresponding to (in the form) "A1", "A2", "A4", "B5", "B6", and "B7" (which are triggered by providing "J1", "J2", "J4", "J5", "J6", and "J7") without issuing additional jump instructions. For example, as Figure 2C As shown, instructions "D1", "D2", and "D4" triggered by providing "J1", "J2", and "J4" can be provided to processing unit 202-1, while instructions "D5", "D6", and "D7" triggered by providing "J5", "J6", and "J7" can be provided to processing unit 202-2. In some embodiments, instruction "D3" may optionally be provided to processing unit 202-1 together with instructions "D1", "D2", and "D4".

[0047] The embodiments are not limited to executing a specific number of "rounds" (rounds 223-1, 223-2) of the access requests (corresponding to "A1", "A2", "A3", "A4", "B5", "B6", and "B7") initially issued from processing units 202-1, 202-2 during their execution. For example, the execution of these access requests (corresponding to "A1", "A2", "A3", "A4", "B5", "B6", and "B7") may take more than two rounds 223-1, 223-2, especially when there are more processing units (e.g., more than two processing units 202-1, 202-2) attempting to access memory 106. On the other hand, the execution of these access requests (corresponding to "A1", "A2", "A3", "A4", "B5", "B6", and "B7") may be completed in a single round without issuing any spurious jump instructions.

[0048] Figure 3 This is a flowchart corresponding to a method 350 for managing memory access according to various embodiments of the present disclosure. Method 350 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 350 is performed by… Figure 1 , 2AThe intermediate component 104 (alternately referred to as the "controller") of 2B and 2C executes. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0049] At position 352, it can be obtained from multiple processing units (e.g., Figure 1 , 2A The processing units 102, 202-1, and 202-2 shown in -2C sequentially receive memory (e.g., ...) Figure 1 , 2A Multiple addresses of memories 106, 206 shown in -2C (e.g., Figure 2A-2C Multiple access requests to addresses 222-1, ..., 222-7 shown in the figure are used to access multiple first instructions (e.g., ...) from said multiple addresses. Figure 2A-2C Instructions 224-1, ..., 224-7 are shown in the diagram. At 354, multiple first instructions 224 can be retrieved (e.g., fetched) from locations in memory 106, 206 corresponding to multiple addresses 222.

[0050] At 356, based on a determination of whether a corresponding timing requirement associated with each of the plurality of first instructions 224 is expected to be met, one or more corresponding processing units 102, 202 among the plurality of processing units may be provided (e.g., in the order of receiving multiple access requests) with respect to the plurality of first instructions 224. Figure 2A-2C The jump instructions 226-1, 226-2, 226-4, 226-5, 226-6, and 226-7, or any combination thereof, are shown in the diagram. Each second instruction 226, when executed by the corresponding processing unit 102, 202, causes the corresponding processing unit 102, 202 to access a corresponding address among a plurality of addresses 222. The corresponding first instruction 224 may be provided to the corresponding processing unit 102, 202 in response to determining that a timing requirement associated with the corresponding first instruction 224 is expected to be met.

[0051] Alternatively, in response to determining that a timing requirement associated with the corresponding first instruction 224 is not expected to be met, a corresponding second instruction 226 may be provided to the corresponding processing unit 202 in place of the corresponding first instruction 224. This may be done in intermediate component 104 (e.g., Figure 2A-2C The corresponding second instruction 226 is generated at the cache 107, 207 shown in the figure, instead of retrieving the corresponding second instruction from the memory 106, 206.

[0052] In one instance, when a corresponding first instruction 224 needs to be sent to satisfy a timing requirement associated with the corresponding first instruction 224, in response to determining that the corresponding first instruction 224 is unavailable, a corresponding second instruction 226 may be provided to the corresponding processing units 102, 202. In another instance, when a corresponding first instruction 224 needs to be sent to satisfy a timing requirement associated with the corresponding first instruction 224, in response to determining that multiple parts of the first instruction 224 (e.g., Figure 2A-2C If at least one of the instructions 224-2, 224-7 shown is unavailable, a corresponding second instruction 226 may be provided to the corresponding processing unit 102, 202. After providing a plurality of first instructions 224 or a plurality of second instructions 226 or any combination thereof, in response to determining that a timing requirement associated with the corresponding first instruction 224 is now expected to be met, a corresponding first instruction 224 (previously provided as a substitute for the corresponding first instruction) may be provided to the corresponding processing unit 102, 202.

[0053] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have already been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm here and generally is considered a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0054] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system, or other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0055] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0056] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0057] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0058] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for managing memory accesses, comprising: sequentially receiving, from a plurality of processing units (102-1,..., 102-N; 202-1, 202-2), respectively, a plurality of access requests respectively including a plurality of addresses (222-1,..., 222-7) of a memory (106; 206) to access a plurality of first instructions (224-1,..., 224-7) from the plurality of addresses; retrieving the plurality of first instructions from locations of the memory corresponding to the plurality of addresses; and providing the plurality of first instructions or a plurality of second instructions (226-1, 226-2, 226-4, 226-5, 226-6, 226-7) or any combination thereof to one or more respective processing units of the plurality of processing units in an order in which the plurality of access requests are received based on a determination of whether respective timing requirements associated with each of the plurality of first instructions are expected to be met; wherein each second instruction, when executed by the respective processing unit, causes the respective processing unit to access a respective address of the plurality of addresses.

2. The method of claim 1, further comprising: providing the respective first instruction to the respective processing unit in response to determining that the timing requirement associated with the respective first instruction is expected to be met.

3. The method of any one of claims 1-2, further comprising: providing a respective second instruction to the respective processing unit in place of the respective first instruction in response to determining that the timing requirement associated with the respective first instruction is expected not to be met.

4. The method of claim 3, further comprising: providing the respective second instruction to the respective processing unit in response to determining that the respective first instruction is not available when the respective first instruction needs to be sent to meet the timing requirement associated with the respective first instruction.

5. The method of claim 3, further comprising: providing the respective second instruction to the respective processing unit in response to determining that at least one of a plurality of portions (224-2, 224-7) of the first instruction is not available when the respective first instruction needs to be sent to meet the timing requirement associated with the respective first instruction.

6. The method of claim 3, further comprising: generating the respective second instruction in response to determining that the timing requirement associated with the respective first instruction is expected not to be met, rather than retrieving the respective second instruction from the memory and providing it to the respective processing unit.

7. The method of claim 3, further comprising, after providing the plurality of first instructions or the plurality of second instructions or any combination thereof: providing the respective first instruction to the respective processing unit in response to determining that the timing requirement associated with the respective first instruction is now expected to be met, previously providing the respective second instruction in place of the respective first instruction.

8. An apparatus for managing memory accesses, comprising: ​ a controller (104) comprising a plurality of cache registers (107-1,..., 107-N; 207-1, 207-2); wherein the controller is further configured to: receive a plurality of addresses (222-1,..., 222-7) from a plurality of processing units (102-1,..., 102-N; 202-1, 202-2) in a particular order, each address corresponding to a respective location of a memory (106; 206) shared by the plurality of processing units; retrieve a plurality of first instructions (224-1,..., 224-7) from the respective locations of the memory; and provide a respective first instruction of the plurality of first instructions or a respective second instruction of a plurality of second instructions (226-1, 226-2, 226-4, 226-5, 226-6, 226-7) at each location of the particular order to one or more respective processing units based on a determination of whether timing requirements of each processing unit are expected to be met.

9. The apparatus of claim 8, wherein: the controller is configured to provide the respective second instruction in place of the respective first instruction; and the respective second instruction, when executed by the respective processing unit, causes the respective processing unit to subsequently issue to the controller a respective address (222-1, 222-2, 222-4, 222-5, 222-6, 222-7) of the plurality of addresses corresponding to the respective first instruction.

10. The apparatus of claim 9, wherein the controller is configured to: provide the respective first instruction in response to a determination that the respective first instruction is available at a respective cache register of the plurality of cache registers when the respective first instruction needs to be sent to meet the timing requirements associated with the respective first instruction.

11. The apparatus of claim 9, wherein the controller is configured to: provide the respective second instruction in place of the respective first instruction in response to a determination that the respective first instruction is not available at a respective cache register of the plurality of cache registers when the respective first instruction needs to be sent to meet the timing requirements associated with the respective first instruction.

12. The apparatus of claim 9, wherein the controller is configured to: provide the respective second instruction in place of the respective first instruction in response to a determination that a respective second instruction was provided at a previous location of the particular order despite the respective first instruction being available in a respective cache register of the plurality of cache registers.

13. A system for managing memory accesses, comprising: a plurality of processing units (102-1,..., 102-N; 202-1、202-2)； a memory (106; 206) shared by the plurality of processing units and configured to store instructions; and a controller (104) configured to: receive a plurality of addresses (222-1,..., 222-7) from the plurality of processing units in sequence, each address corresponding to a respective instruction of a plurality of instructions (224-1,..., 224-7); obtaining the plurality of instructions from the memory; and responding to each processing unit of the plurality of processing units in an order in which the plurality of addresses is received at the controller from the plurality of processing units: in response to determining that timing requirements associated with provision of the respective instruction are expected to be satisfied, providing the respective instruction of the plurality of instructions to the respective processing unit; and in response to determining that the timing requirements associated with the respective instruction are expected to not be satisfied, providing a respective alternative instruction (226-1, 226-2, 226-4, 226-5, 226-6, 226-7) to the respective processing unit in place of the respective instruction, wherein the respective alternative instruction, when executed by the respective processing unit, causes the respective processing unit to access an address corresponding to the respective instruction.

14. The system of claim 13, wherein the controller is configured to: sequentially receive a first address and a second address of the plurality of addresses; in response to receipt of the first address and the second address, obtain a first instruction and a second instruction of the plurality of instructions respectively corresponding to the first address and the second address; and in response to determining that the timing requirements associated with the first instruction are expected to not be satisfied, provide a first alternative instruction in place of the first instruction.

15. The system of claim 14, wherein the first alternative instruction is provided in place of the first instruction in response to determining that: the first instruction is part of a particular instruction (224-1, 224-6); and at least a remaining portion of the particular instruction (224-2, 224-7) is not available for provision to the respective processing unit when the first instruction needs to be provided to the respective processing unit to satisfy the timing requirements.

16. The system of claim 14, wherein the controller is configured to: in response to determining that the first instruction has not previously been provided to the respective processing unit, provide a second alternative instruction in place of the second instruction; wherein: the first alternative instruction, when executed by the respective processing unit, causes the respective processing unit to access a location of the memory corresponding to the first address; and the second alternative instruction, when executed by the respective processing unit, causes the respective processing unit to access a location of the memory corresponding to the second address.

17. The system of claim 16, wherein the first instruction, the second instruction, or both correspond to a jump instruction.

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