Data storage method, data reading method, data transmission system, chip, storage medium and computer equipment
By employing multiple upstream queues with corresponding priorities for data storage and retrieval in the chip, the problem of urgent task delivery order is solved, improving the chip's processing performance and resource utilization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-23
- Publication Date
- 2026-03-31
AI Technical Summary
In existing technologies, when a chip processes tasks of varying urgency, urgent tasks may be delivered later in the order of being received, making it difficult to acquire and process them in a timely manner, thus affecting the chip's processing performance.
A data storage method with multiple upstream queues corresponding to priorities is adopted. After the upstream module obtains the data, it stores the data in the matching queue according to the priority information, and the downstream module reads and transmits the data in priority order.
It improves the flexibility and processing performance of data transmission between upstream and downstream of the chip, ensures that urgent tasks are prioritized, reduces software blockage, and improves the utilization of hardware resources.
Smart Images
Figure CN121764536A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of artificial intelligence chip technology, and in particular to a data storage and data retrieval method, a data transmission system, a chip, a storage medium, and a computer device. Background Technology
[0002] During chip operation, there are a large number of tasks that need to be processed by the various units of the chip.
[0003] In related technologies, downstream units of a chip can read the task data sequentially according to the order in which the upstream units of the chip store the task data, thereby realizing the transmission of the task data until the task data is transmitted to the corresponding unit for relevant processing.
[0004] However, since different tasks may have different levels of urgency during chip operation, the above method of transmitting task data sequentially according to the storage order may result in urgent tasks being transmitted later, making it difficult for the corresponding unit to obtain and process the data of the urgent task in a timely manner. This makes the chip less flexible in handling tasks during operation and affects the chip's processing performance. Summary of the Invention
[0005] To address the aforementioned technical problems, embodiments of this application propose a data storage and data retrieval method, a data transmission system, a chip, a storage medium, and a computer device, which can improve the flexibility of data transmission in the upstream and downstream of the chip, thereby improving the chip's processing performance.
[0006] In a first aspect, embodiments of this application provide a data storage method applicable to an upstream module, wherein the upstream module is associated with multiple first upstream queues, the multiple first upstream queues corresponding to multiple priorities, and the method includes: Get the first data; The priority information corresponding to the first data is obtained from the first data. The first data is stored in the second upstream queue, wherein the second upstream queue is the queue among the plurality of first upstream queues that matches the priority information; In the case where the upstream module is a host module, the correspondence between the multiple first upstream queues and the multiple priorities is configured based on the priority information of all first data within a preset time period.
[0007] Optionally, all of the plurality of first upstream queues are first-in-first-out (FIFO) queues.
[0008] Optionally, the step of reading the priority information corresponding to the first data from the first data includes: Read the priority field segment of the first data to obtain the priority information.
[0009] Optionally, when the upstream module is a host module, obtaining the first data includes: The data packet is read from memory and used as the first data.
[0010] Secondly, embodiments of this application provide a data reading method applicable to downstream modules, the method comprising: The second data is read from multiple first upstream queues according to multiple priorities; Wherein, the plurality of first upstream queues correspond to the plurality of priorities, the plurality of first upstream queues are associated with an upstream module, the upstream module is used to read the priority information corresponding to the first data from the first data it obtains, and store the first data in a second upstream queue, the second upstream queue being the queue among the plurality of first upstream queues that matches the priority information; In the case where the upstream module is a host module, the correspondence between the multiple first upstream queues and the multiple priorities is configured based on the priority information of all first data within a preset time period.
[0011] Optionally, all of the plurality of first upstream queues are FIFO queues.
[0012] Optionally, the method further includes: Query the real-time status of each of the multiple first upstream queues; The step of reading the second data from multiple first upstream queues according to multiple priorities includes: Based on the multiple priorities and the real-time status being queried, the second data is read from the multiple first upstream queues.
[0013] Optionally, the step of reading the second data from the plurality of first upstream queues based on the plurality of priorities and the queried real-time status includes: According to the multiple priorities in descending order, perform the following operations for each priority level in sequence: Based on the real-time status queried, determine whether the first upstream queue corresponding to this priority is an empty queue. If not, the second data is read from the first upstream queue that corresponds to the priority and is not an empty queue; If so, then perform the operation for the next lower priority.
[0014] Optionally, if the upstream module is a host module, the downstream module is a command processing engine (CPE). In the case that the upstream module is CPE and the downstream module is arbitration module RR, the method further includes: in response to reading the second data, transmitting the second data to execution unit EU.
[0015] Optionally, the number of EUs is at least one, and each EU corresponds to at least one of the plurality of first upstream queues; The step of transmitting the second data to the execution unit EU includes: Based on the first upstream queue from which the second data originates, a target EU matching the second data is determined from at least one of the EUs; The second data is then transmitted to the target EU.
[0016] Thirdly, embodiments of this application provide a data transmission system, including: An upstream module, associated with multiple first upstream queues corresponding to multiple priorities, is configured to: acquire first data; read priority information corresponding to the first data from the first data; and store the first data in a second upstream queue, wherein the second upstream queue is a queue among the multiple first upstream queues that matches the priority information; and The downstream module is configured to read second data from the plurality of first upstream queues according to the plurality of priorities; In the case where the upstream module is a host module, the correspondence between the multiple first upstream queues and the multiple priorities is configured based on the priority information of all first data within a preset time period.
[0017] Optionally, if the upstream module is a host module, the first data is a data packet read from memory by the host module.
[0018] Optionally, all of the plurality of first upstream queues are FIFO queues.
[0019] Optionally, the step of reading the priority information corresponding to the first data from the first data includes: Read the priority field segment of the first data to obtain the priority information.
[0020] Optionally, the downstream module is further configured to: Query the real-time status of each of the multiple first upstream queues; The step of reading the second data from the plurality of first upstream queues according to the plurality of priorities includes: Based on the multiple priorities and the real-time status being queried, the second data is read from the multiple first upstream queues.
[0021] Optionally, the step of reading the second data from the plurality of first upstream queues based on the plurality of priorities and the queried real-time status includes: According to the multiple priorities in descending order, perform the following operations for each priority level in sequence: Based on the real-time status queried, determine whether the first upstream queue corresponding to this priority is an empty queue. If not, the second data is read from the first upstream queue that corresponds to the priority and is not an empty queue; If so, then perform the operation for the next lower priority.
[0022] Optionally, if the upstream module is a host module, the downstream module is a CPE; In the case that the upstream module is CPE, the downstream module is RR, and the downstream module is further configured to: in response to reading the second data, transmit the second data to EU.
[0023] Optionally, the number of EUs is at least one, and each EU corresponds to at least one of the plurality of first upstream queues; The step of transmitting the second data to the execution unit EU includes: Based on the first upstream queue from which the second data originates, a target EU matching the second data is determined from at least one of the EUs; The second data is then transmitted to the target EU.
[0024] Fourthly, embodiments of this application provide a chip that includes the system described in any of the preceding claims.
[0025] Fifthly, embodiments of this application provide a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method described in any of the preceding claims.
[0026] Sixthly, embodiments of this application provide a computer device including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the steps of the method described in any of the preceding claims.
[0027] In summary, the embodiments of this application have at least the following beneficial effects: In this embodiment, the upstream module is associated with multiple first upstream queues corresponding to multiple priorities. After acquiring the first data, the upstream module stores the first data into a second upstream queue that matches the priority information read from the first data. In this way, the upstream module considers the priority of different data when storing data and stores it in the queue with the corresponding priority. This enables data to be transmitted in priority order in each unit of the chip, thereby improving the flexibility of data transmission between upstream and downstream of the chip. In addition, when the upstream module is a host module, the correspondence between each first upstream queue and each priority can be configured according to the priority information of all first data within a preset time period, thereby improving the efficiency of hardware data reception and thus improving the processing performance of the chip. Attached Figure Description
[0028] Figure 1 This is a schematic diagram illustrating the data transmission within the chip provided by related technologies; Figure 2 This is a flowchart illustrating the data storage method provided in an embodiment of this application; Figure 3 This is a flowchart illustrating the data reading method provided in an embodiment of this application; Figure 4 This is a schematic diagram illustrating the data transfer within the chip according to an embodiment of this application; Figure 5 This is a schematic diagram of the data transmission system provided in an embodiment of this application; Figure 6 This is a schematic diagram of the GPGPU architecture provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of the computer device provided in the embodiments of this application. Detailed Implementation
[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments / examples are only a part of the embodiments / examples of this application, and not all of the embodiments / examples. Based on the embodiments / examples in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0030] In the description of this application, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," "third," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more. In the description of this application, the term "comprising" and its variations are open-ended, meaning "including but not limited to." The term "based on" means "at least partially based on." The term "according to" means "at least partially according to." The term "one embodiment / example" means "at least one embodiment / example"; the term "another embodiment / example" means "at least one additional embodiment / example"; the term "some embodiments / examples" means "at least some embodiments / examples."
[0031] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0032] In the description of this application, it should be noted that, unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the application. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0033] First, the following explains some terms and concepts involved in the embodiments of this application.
[0034] First-In-First-Out (FIFO) queues are a type of data buffer structure where the earliest written data is read first. The depth of a FIFO represents the bit width of the data that the FIFO can store.
[0035] The Command Processing Engine (CPE) contains a Microcontroller Unit (MCU) that can be used to execute firmware (FW).
[0036] An execution unit (EU) is the hardware core in a chip that actually executes computational instructions (such as memory loading / storage and special functions).
[0037] In some cases, chips can be applied across various industries, and the workload they need to process can be very large, which may lead to all tasks being queued and executed sequentially. However, by rationally prioritizing different tasks according to user needs to optimize the task execution order, task execution can be optimized, hardware resources can be flexibly allocated, and the processing of tasks on the chip can be made more flexible, thereby improving the overall processing performance of the chip.
[0038] See also Figure 1 In related technologies, the chip design scheme is that after each Host Command Queue Driver (Hcqd) receives a data packet (pkt), it places the data packet in the Hcqd-FIFO. The downstream CPE then reads the data in the Hcqd-FIFO sequentially in a first-in-first-out order, classifies the read data, and delivers it to the downstream EU-cmd (Command)-FIFO. In the EU-cmd-FIFO, the data can also be sequentially queued and passed to the downstream EU for execution. For example, taking a Command Processing Device (Cpd) as an example, the EU-cmd-FIFO passes the task to the Cpd-sub. When eight pipelines in the Cpd simultaneously compete for splitting resources, the task of each of these eight pipelines can be distinguished to determine whether it is a priority task. If a priority task has already entered the Cpd-sub, then the Cpd-sub will prioritize splitting that task. Here, the Cpd-sub can split the task into multiple tasks (such as a priority P-task and a normal N-task) and store them in the Jobpool-FIFO (task pool queue).
[0039] However, in the chip design schemes provided by the relevant technologies, from obtaining the pkt from Hcqd to passing it to the EU for execution, the priority privilege of the pkt with higher priority is not actually reflected; it is all queued serially downwards in the transmission path.
[0040] In some example scenarios, suppose Hcqd retrieves 10 pkts, with only the last one being a high-priority pkt (i.e., P-pkt), and the first 9 being normal pkts (i.e., N-pkt). It can be understood that when Hcqd retrieves the last high-priority P-pkt, Hcqd is not able to skip the first 9 normal N-pkts and execute the P-pkt quickly. Instead, it will store all 10 pkts sequentially into the Hcqd-FIFO.
[0041] In EU-internal priority arbitration, the priority between different pkts generally takes effect when the EU detects P-pkt transfers between different pkts at the same time, and this takes effect during inter-pipe arbitration within the EU.
[0042] Furthermore, we can assume that the current Command Processor (cp) has n pipes, each pipe has m Hcqds, the depth of the Hcqd-FIFO is x pkts, and the depth of the Cpd-cmd-FIFO is y cmds. When all these FIFOs are full, if a high-priority pkt is obtained, and assuming that the execution time of all pkts is the same, they will take turns participating in arbitration. Thus, to execute the last high-priority P-pkt, we need to wait for the sum of the execution times of x*n*m+y*n pkts before the high-priority P-pkt can be executed. Therefore, the priority is not actually effective at this time.
[0043] In view of this, the embodiments of this application subsequently provide a data storage and data retrieval method, a data transmission system, a chip, a storage medium, and a computer device, aiming to at least partially solve the shortcomings existing in the above-mentioned related technologies.
[0044] In a first aspect, embodiments of this application provide a data storage method applicable to an upstream module, wherein the upstream module is associated with multiple first upstream queues, and the multiple first upstream queues correspond to multiple priorities.
[0045] In some examples, each first upstream queue corresponds to a priority, and different first upstream queues correspond to different priorities, that is, the multiple first upstream queues can correspond one-to-one with the multiple priorities; or, since the data volume of some priorities may be relatively large, and the bit width of data that a single queue can store may be limited, the same priority can also correspond to one or more of the multiple first upstream queues. The embodiments of this application are not unique in this regard.
[0046] See also Figure 2The diagram shows a flowchart of a data storage method provided in an embodiment of this application. The method includes steps S201-S203, as detailed below.
[0047] S201, Obtain the first data.
[0048] It is understood that, since data is transmitted sequentially in each unit of the chip to form a data transmission path, some units in this data transmission path can be upstream of some units or downstream of other units. In other words, some downstream modules can also exist as upstream modules under certain circumstances. Therefore, the embodiments of this application do not uniquely limit the specific composition of the upstream module.
[0049] In some examples, the upstream module can be a host module or a CPE. If the upstream module is a host module, the first data can be a data packet read from memory by the host module; for example, the host module may include the Hcqd mentioned above. If the upstream module is a CPE, the first data can be data read from the queue corresponding to the host module by the CPE.
[0050] S202, Read the priority information corresponding to the first data from the first data.
[0051] In some examples, priority information can be added to the first data. For example, priority information can be added to a specific field of the first data. This priority information can be used to characterize the priority corresponding to / possessing the first data. Thus, the priority information corresponding to the first data can be adapted to multiple priorities. For example, the priority corresponding to / possessing the first data can be one of the multiple priorities. Therefore, a queue matching the priority information can be selected from multiple first upstream queues as the subsequent second upstream queue. In this embodiment, before the first data is obtained by the upstream module, during the data generation process of the first data, corresponding priorities can be assigned to different first data according to actual needs. Even different data of the same type can have different priorities. This application embodiment does not specifically limit this.
[0052] S203, the first data is stored in the second upstream queue, wherein the second upstream queue is the queue among the plurality of first upstream queues that matches the priority information.
[0053] Understandably, the upstream module can store the first data in a second upstream queue with a matching priority. This allows the priority of different data to be considered when storing data, and the data to be stored in the queue with the corresponding priority. Furthermore, the downstream module corresponding to the upstream module can read the queues of different priorities according to their priorities, and the upstream module can also pass the data in each of the first upstream queues to the downstream module according to their priorities. This enables data to be passed in priority order in each unit of the chip, thereby improving the flexibility of data transfer between upstream and downstream components of the chip and ultimately improving the chip's processing performance.
[0054] In the case where the upstream module is a host module, the correspondence between the multiple first upstream queues and the multiple priorities is configured based on the priority information of all first data within a preset time period.
[0055] It is understandable that in the actual data transmission process, the data to be transmitted can be generated by software, and the generated data is generally first transmitted to the host module (for example, the data packet transmitted to the host module through memory in the following embodiment), and then handed over to the host module and other hardware resources to complete the transmission.
[0056] However, assuming that within a preset time period, most of the data generated by the software (i.e., the first data obtained by the host module as described in this application embodiment) is data of the same priority, or even all of it is data of the same priority, if each first upstream queue is configured with a fixed priority, it is easy to result in too few queues matching the priority of the data generated by the software. As a result, there are not enough queues to receive the data generated by the software, and the rate at which the hardware receives data is much lower than the rate at which the software generates data. Before the software has sent all the data to the host module, it cannot process other matters, thus causing software blockage.
[0057] Accordingly, in this embodiment, when the upstream module is a host module, the host module can serve as the first hardware resource for receiving data generated by the software. The correspondence between the multiple first upstream queues and multiple priorities in this embodiment can be configured by the software according to the priority information of all first data within a preset time period. In this way, after configuring the correspondence between the multiple first upstream queues and multiple priorities to adapt to the priority information of all first data within the preset time period, the host module can quickly accept the data generated by the software, release the software as soon as possible to handle other matters, and reduce the probability of software blocking.
[0058] Furthermore, if all the data generated by the software within a preset time period are of the same priority (referred to as the target priority), then the multiple first upstream queues can be configured to all correspond to the target priority, thereby enabling the configuration of the correspondence between the multiple first upstream queues and multiple priorities.
[0059] Furthermore, if all the data generated by the software within a preset time period corresponds to at least two priorities, the above correspondence can be configured according to the proportion of the data corresponding to each of the at least two priorities in all the data generated by the software within the preset time period.
[0060] In one alternative implementation, the plurality of first upstream queues are all first-in-first-out (FIFO) queues.
[0061] In this embodiment, each first upstream queue is set as a FIFO queue, so that the data that enters the queue first in the same first upstream queue can be passed to the downstream first. This ensures that different data with the same priority can be passed in the order they are stored as much as possible. It can also effectively avoid logical errors that may be caused by out-of-order execution of data with the same priority (such as instruction streams that depend on timing in the chip), improve the accuracy of the chip's data processing, and thus improve the chip's processing performance.
[0062] In one optional implementation, the step of reading the priority information corresponding to the first data from the first data includes: Read the priority field segment of the first data to obtain the priority information.
[0063] In this embodiment, priority information can be directly embedded in the dedicated priority field of the first data, which is equivalent to embedding a priority tag into each piece of first data. At this time, the upstream module does not need to deduce the priority through complex algorithms (such as parsing data content and associating with external configuration tables). Instead, it can accurately match the corresponding queue by reading the value of the field. This effectively avoids priority misjudgment caused by data content parsing deviations and external configuration table synchronization delays, improves the reliability of the chip during operation, and thus improves the chip processing performance.
[0064] In some examples, the priority field can be a fixed-length sub-region within the data frame structure, which can be used to store priority information, which can be represented by binary values.
[0065] It is worth noting that the priority field in this embodiment can be an independent area in the data structure specifically used to store priority identifiers (for example, it can be 1 to 4 bits of binary data at a specified position), and its value can be dynamically set by the user according to their needs.
[0066] However, related technologies may adopt a scheme that forcibly binds priority to data type. That is, the priority is uniquely determined by the data type, and the corresponding priority is pre-configured for different data types. Then, the data is stored in a priority queue that matches the data type. Therefore, the data type and the queue priority are also in a one-to-one correspondence.
[0067] Compared with related technologies, the priority configuration of this embodiment is more flexible. For example, in this embodiment, different priorities can be configured for different data of the same data type, that is, the priority is not limited by the data type. Specifically, the following examples can be given to explain this.
[0068] (1) Taking video data type as an example, data packets belonging to the same video data type may correspond to different business scenarios. For example, it may be a video stream of a real-time meeting or a synchronous backup of a background video file. For the real-time meeting scenario, in order to ensure smooth picture and reduce latency, the data packets of this scenario need to be assigned a higher priority to avoid lag caused by data transmission or processing delays. The background video backup scenario has lower real-time requirements and can be assigned a lower priority to avoid occupying too many resources and affecting core business. Taking text data type as another example, data packets belonging to the same text data type may be key instruction text initiated by users (such as financial transaction confirmation instructions) or ordinary log text (such as system running status records). Key instruction text needs to be processed first to ensure timeliness and accuracy, while ordinary log text can be processed later.
[0069] As can be seen, compared with related technologies, this embodiment can achieve differentiated scheduling of the same type of data by embedding different priority information into the same type of data.
[0070] (2) When the chip's internal resources are scarce (such as insufficient cache or excessive load on the processing module), this embodiment can dynamically adjust the priority of the corresponding data according to the urgency of the data. For example, data collected from sensors can be processed with the normal priority when the system load is low. However, when the system experiences a sudden load peak, sensor data related to equipment safety monitoring (such as temperature over-limit alarm data) can be temporarily embedded with a higher priority to ensure that such critical data is processed first and to avoid safety risks caused by resource crowding. Other routine monitoring data can be given a lower priority and processed after the system load is relieved.
[0071] In one optional implementation, when the upstream module is a host module, acquiring the first data includes: The data packet is read from memory and used as the first data.
[0072] In this embodiment, since the host module usually undertakes the core scheduling function of the chip system and is responsible for coordinating the distribution and processing of various types of data, and the memory can be a storage area directly managed by the host module, reading data packets from the memory allows the host module to more conveniently control the generation, storage and reading rhythm of data, so that the host module can control the process of data entering the hardware, which is conducive to better leveraging the scheduling advantages of multi-priority queues and improving the overall processing performance of the chip.
[0073] In some examples, taking video sequences as an example, a single data packet / single first data can refer to the data to be processed corresponding to a frame in the video sequence. Similarly, taking audio modal data as an example, a single data packet / single first data can refer to the data to be processed corresponding to a pre-defined duration of audio within the audio modal data.
[0074] Secondly, embodiments of this application provide a data reading method applicable to downstream modules, see [link to relevant documentation]. Figure 3 The diagram shows a flowchart of a data reading method provided in an embodiment of this application. The method includes step S301, as detailed below.
[0075] S301, according to multiple priorities, reads the second data from multiple first upstream queues.
[0076] In this embodiment, the downstream module can actively read the second data from multiple first upstream queues according to multiple priorities.
[0077] Furthermore, it is easy to understand that as the downstream module reads the second data from the first upstream queue, the data read from the first upstream queue will be cleared from the first upstream queue.
[0078] Wherein, the plurality of first upstream queues correspond to the plurality of priorities, the plurality of first upstream queues are associated with an upstream module, the upstream module is used to read the priority information corresponding to the first data from the first data it obtains, and store the first data in a second upstream queue, the second upstream queue being the queue among the plurality of first upstream queues that matches the priority information; In the case where the upstream module is a host module, the correspondence between the multiple first upstream queues and the multiple priorities is configured based on the priority information of all first data within a preset time period.
[0079] It is understood that the relevant descriptions involved in this embodiment can be referred to in the description provided in the first aspect above, and will not be repeated here.
[0080] In one alternative implementation, the plurality of first upstream queues are all FIFO queues.
[0081] In an optional implementation, the method further includes: querying the real-time status of each of the plurality of first upstream queues.
[0082] In some examples, this real-time state can be stored in a buffer (cache or register) for querying by the downstream module.
[0083] In some examples, the downstream module can use polling to query the real-time status of multiple first upstream queues.
[0084] In some examples, the downstream module can query the real-time status of each of the multiple first upstream queues via its internal firmware (FW).
[0085] The step of reading the second data from multiple first upstream queues according to multiple priorities includes: Based on the multiple priorities and the real-time status being queried, the second data is read from the multiple first upstream queues.
[0086] In this embodiment, the downstream module can also query the status of each of the multiple first upstream queues in real time to obtain the real-time status, and can read data from the first upstream queues by combining the real-time status with the priority. In this way, the downstream module can read data only after knowing whether there is data available for reading in each queue, so as to avoid invalid data reading operations and reduce the waste of computing power and time of the downstream module. In addition, the downstream module can skip empty queues and directly read the queue with data and the highest priority, so as to significantly reduce invalid read attempts and improve the efficiency of data reading.
[0087] In some examples, the downstream module can identify the highest priority queue among the currently non-empty queues in multiple first upstream queues based on the real-time status of the query, and read at least part of the second data from the highest priority queue.
[0088] In some examples, the real-time status of each first upstream queue can be used to characterize whether the first upstream queue is an empty queue.
[0089] In one optional implementation, the step of reading the second data from the plurality of first upstream queues based on the plurality of priorities and the queried real-time status includes: According to the multiple priorities in descending order, perform the following operations for each priority level in sequence: Based on the real-time status queried, determine whether the first upstream queue corresponding to this priority is an empty queue. If not, the second data is read from the first upstream queue that corresponds to the priority and is not an empty queue; If so, then perform the operation for the next lower priority.
[0090] In this embodiment, queues are checked sequentially from highest to lowest priority. Only when all queues of the current priority are empty does the next priority queue begin to be checked. This ensures that high-priority data is not preempted by low-priority data. Furthermore, downstream modules can check the corresponding priority queue for emptiness before each read and skip attempts to read empty queues. Compared to reading directly by priority without checking real-time status, this reduces unnecessary operations such as addressing and accessing empty queues. It allows downstream modules to focus their computing power and time on reading queues with data, avoiding resource waste from repeatedly reading empty queues and improving the overall operating efficiency of downstream modules.
[0091] In some examples, the multiple first upstream queues can be one-to-one with the multiple priorities. In this case, each priority corresponds to a first upstream queue. The upstream module can determine whether the first upstream queue corresponding to the current priority is empty based on the real-time status of the query. If the first upstream queue is not empty, at least part of the second data can be read from the first upstream queue. Otherwise, it can jump to the operation for the next priority.
[0092] In some examples, the same priority can also correspond to one or more of the multiple first upstream queues. In this case, the situation where each priority corresponds to one first upstream queue can be referred to the previous example. Here, it is assumed that each priority corresponds to two or more first upstream queues. The upstream module can determine whether all the first upstream queues corresponding to the current priority are empty queues based on the real-time status of the query. If they are all empty queues, it can jump to the operation for the next priority. Otherwise, it means that at least one of the first upstream queues corresponding to the current priority is not empty. Therefore, the upstream module can read at least part of the second data from the first upstream queue that corresponds to the priority and is not empty.
[0093] In one alternative implementation, when the upstream module is a host module, the downstream module is a command processing engine (CPE).
[0094] In this embodiment, the upstream module is used as a host module at the top level of the chip hardware. In this way, data can be classified as soon as it enters the chip hardware, and priorities can be distinguished from the top level of the hardware. This allows the top level to allocate hardware resources according to different priorities, and the subsequent data transmission process can be processed separately according to queues of different priorities. This can effectively reduce the burden on software usage, and the hardware can perform priority classification to ensure that when high-priority data enters the hardware, low-priority data can be skipped, thus enabling priority and faster execution.
[0095] In some examples, when the upstream module is a host module and the downstream module is a CPE, the first upstream queue can be represented as Hcqd-Pi-FIFO, where Pi can represent the Pi-th EU-cmd-FIFO, that is, the Pi-th first upstream queue. Furthermore, the i in Pi can also be used to represent the priority level. The larger the i is, the higher the priority can be. i = 0, 1, ..., n.
[0096] In an alternative implementation, where the upstream module is a CPE and the downstream module is an arbitration module RR (Round Robin Arbiter), the method further includes: in response to reading the second data, transmitting the second data to the execution unit EU.
[0097] In this embodiment, the process of storing data according to priority in the upstream module (CPE), reading data according to priority in the downstream module (RR), and then passing the data to the EU for execution in the downstream module (RR) forms a complete closed loop of priority scheduling. This can ensure that high-priority data receives priority in storage, reading, and final execution, effectively preventing high-priority data from being squeezed out by low-priority data when it flows between modules, and prioritizing the execution of high-priority data.
[0098] In some examples, where the downstream module is an RR, the second data can be passed to the EU that matches the second data each time it is read for execution.
[0099] In some examples, when the upstream module is CPE and the downstream module is RR, the first upstream queue can be represented as EU-cmd-Pi-FIFO, where Pi can represent the Pi-th EU-cmd-FIFO, that is, the Pi-th first upstream queue. Furthermore, the i in Pi can also be used to represent the priority level. The larger the i is, the higher the priority can be. i = 0, 1, ..., n.
[0100] Furthermore, the aforementioned technologies require mandatory binding of priorities to data types. Therefore, in practical implementation, in addition to mandatory binding of priority queues to data types to achieve data transmission paths of different priorities, it is generally also necessary to bind data types in the downstream data processing stage. That is, different cores inside the chip need to be grouped according to priority (equivalent to grouping according to data types), and the cores in each group can generally only process data of the corresponding priority. In other words, the cores in each group can only process data of the corresponding data type. At this time, even if some cores are in an idle state, those cores cannot process data of data types unrelated to them, resulting in serious waste of the core resources inside the chip during actual use.
[0101] Accordingly, in this embodiment, the CPE can identify the priority of the currently acquired data through its internal FW and assign it to downstream processing according to the priority. The processing unit (e.g., EU) used to process the data in the downstream can be a processing unit dynamically allocated to the data when it is generated or during the transmission process (selected and allocated from the currently idle processing units). That is, it does not need to be bound to the data type and can make full use of the idle processing units inside the chip, thereby improving the resource utilization rate of the chip in actual use.
[0102] From a practical design perspective, since cores are one of the main contributors to chip area, under the same process node, if other conditions remain unchanged, there is a positive correlation between the number of cores and the chip area (hereafter, we assume an approximate linear growth relationship). Therefore, when dealing with data of the same data type, this application embodiment can dynamically call all processing units (i.e., all cores) within the chip to process the data of that data type. However, if the chips of the aforementioned related technologies are to achieve the same performance, the number of cores configured for that data type needs to be equal to the total number of cores of the chip in this application embodiment. At this time, the chips of the related technologies also need to take into account the cores of other data types (other priorities). If the number of cores for each data type is the same, it is equivalent to the total number of cores of the chips of the related technologies being K times that of the chips in this application embodiment, where K is the number of data types. This leads to a significant increase in chip area, which may need to be increased by K times, making it practically impossible to achieve.
[0103] Furthermore, the intra-chip data transfer process provided in this embodiment can be described by combining the host module, CPE, and RR mentioned above. Taking Hcqd as the host module as an example, see [link to relevant documentation]. Figure 4 The specific description is as follows.
[0104] First, after a pkt enters Hcqd, Hcqd determines the priority field information of the pkt. This priority field can be N or Pi as mentioned above. N represents a normal pkt (without priority or the lowest priority), and pi contains i = 0, 1, ..., n, where a larger i indicates a higher priority. Thus, Hcqd can store each pkt in its corresponding Hcqd-N-FIFO or Hcqd-Pi-FIFO based on the N or Pi it reads. Figure 4 As can be seen, the pkts stored in the same Hcqd-N-FIFO or Hcqd-Pi-FIFO are all pkts with the same priority field segment.
[0105] Secondly, the real-time status (empty / full status) of each Hcqd-N-FIFO or Hcqd-Pi-FIFO can be stored in a buffer (buffer or register). The CPE can query the real-time status of each FIFO from this buffer. For example, the CPE can query the real-time status of each Hcqd-N-FIFO and Hcqd-Pi-FIFO at a time, and make a judgment based on the priority of each queue. If the highest priority FIFO is not empty, it can read the highest priority FIFO first, until the status is confirmed. All FIFOs are assumed to be empty. That is, starting from i=n in Hcqd-Pi-FIFO (i.e. Hcqd-Pn-FIFO), it is determined whether the Hcqd-Pi-FIFO is not empty. If it is not empty, CPE reads pkt from the Hcqd-Pi-FIFO. If it is not empty, it continues to the next Hcqd-Pi-FIFO (i.e., i-1), until it is determined that the last Hcqd-N-FIFO is not empty (i.e., Hcqd-N-FIFO is an empty queue).
[0106] Next, the CPE will continue to store the PKT in the corresponding FIFO, either EU-cmd-N-FIFO or EU-cmd-Pi-FIFO, according to the priority field segment in the read PKT. Correspondingly, the RR will read the PKT from the EU-cmd-N-FIFO or EU-cmd-Pi-FIFO, with a process similar to that described above for reading the PKT from the Hcqd-N-FIFO or Hcqd-Pi-FIFO, and will not be repeated here. It is worth noting that from... Figure 4 As can be seen, both EU-cmd-N-FIFO and Hcqd-N-FIFO store N-pkt, while both EU-cmd-Pi-FIFO and Hcqd-Pi-FIFO store Pi-pkt.
[0107] Finally, RR can pass the read pkt to Cpd-sub for splitting to obtain individual tasks (such as normal N-tasks and Pi-tasks with Pi priority) and store them in Jobpool-FIFO, thereby realizing the processing of pkt.
[0108] As can be seen, in this embodiment, the hardware architecture can prioritize different priorities from the initial Hcqd to the final EU, allowing high-priority PKTs to be prioritized and skipped by low-priority PKTs upon entering the CP, until they are passed to the corresponding EU for execution. This achieves effective priority management, and the architecture is simple and clear, with top-down hierarchical classification making the hardware priority management architecture within the CP simpler and clearer. Furthermore, this priority differentiation is mainly implemented by the hardware architecture, which can automatically classify priorities without the need for complex software algorithms, thus reducing software development difficulty and eliminating reliance on fixed hardware for execution.
[0109] Comparing this embodiment with the example scenarios provided in the aforementioned related technologies, it can be seen that the delivery time of high priority can be improved from the total execution time of x*n*m+y*n pkts in the related technologies to the fact that in this embodiment, as long as the priority of the pkt is high enough (the highest priority), it can theoretically be delivered to the corresponding EU for execution with the highest priority (i.e., as the first pkt to be executed by the EU among the 10 pkts in this scenario), which greatly enhances the role of priority.
[0110] In one alternative implementation, the number of EUs is at least one, and each EU corresponds to at least one of the plurality of first upstream queues; The step of transmitting the second data to the execution unit EU includes: Based on the first upstream queue from which the second data originates, a target EU matching the second data is determined from at least one of the EUs; The second data is then transmitted to the target EU.
[0111] It should be noted that when the upstream module is CPE and each EU corresponds to at least one first upstream queue, these multiple first upstream queues can be multiple EU-cmd-FIFOs. In this case, each EU corresponds to at least one EU-cmd-FIFO. EU-cmd-FIFOs corresponding to the same EU can be called EU FIFOs of the same type. When RR reads data from each first upstream queue according to priority (reading the second data from multiple first upstream queues according to multiple priorities), it is equivalent to the RR arbitrating EU-cmd-FIFOs of multiple priorities. After arbitration, RR responds to the read second data and passes the read second data to the corresponding target EU for execution.
[0112] In this embodiment, the data types and / or processing requirements corresponding to different upstream queues may differ. For example, some data may require complex calculations, while other data may require simple forwarding or storage. This embodiment enables precise mapping between EUs and queues, allowing for the allocation of matching computing power, storage, and other resources to the EUs corresponding to the upstream queues based on their data types and / or processing requirements. This reduces resource redundancy caused by high-performance EUs processing simple tasks and prevents execution stuttering caused by low-performance EUs processing complex tasks. This on-demand allocation mode can effectively improve the overall utilization of chip resources, allowing limited hardware resources to play a greater role.
[0113] Thirdly, see Figure 5 The diagram illustrates the structure of a data transmission system 500 provided in an embodiment of this application. The data transmission system 500 includes: An upstream module 501, associated with multiple first upstream queues corresponding to multiple priorities, is configured to: acquire first data; read priority information corresponding to the first data from the first data; and store the first data in a second upstream queue, wherein the second upstream queue is a queue among the multiple first upstream queues that matches the priority information; and Downstream module 502 is configured to read second data from the plurality of first upstream queues according to the plurality of priorities; In the case where the upstream module 501 is a host module, the correspondence between the multiple first upstream queues and the multiple priorities is configured based on the priority information of all first data within a preset time period.
[0114] In an optional implementation, if the upstream module 501 is a host module, the first data is a data packet read from memory by the host module.
[0115] In one alternative implementation, the plurality of first upstream queues are all FIFO queues.
[0116] In one optional implementation, the step of reading the priority information corresponding to the first data from the first data includes: Read the priority field segment of the first data to obtain the priority information.
[0117] In an optional implementation, the downstream module 502 is further configured to: Query the real-time status of each of the multiple first upstream queues; The step of reading the second data from the plurality of first upstream queues according to the plurality of priorities includes: Based on the multiple priorities and the real-time status being queried, the second data is read from the multiple first upstream queues.
[0118] In one optional implementation, the step of reading the second data from the plurality of first upstream queues based on the plurality of priorities and the queried real-time status includes: According to the multiple priorities in descending order, perform the following operations for each priority level in sequence: Based on the real-time status queried, determine whether the first upstream queue corresponding to this priority is an empty queue. If not, the second data is read from the first upstream queue that corresponds to the priority and is not an empty queue; If so, then perform the operation for the next lower priority.
[0119] In one optional implementation, when the upstream module 501 is a host module, the downstream module 502 is a CPE; In the case that the upstream module 501 is a CPE, the downstream module 502 is an RR, and the downstream module 502 is further configured to: in response to reading the second data, transmit the second data to the EU.
[0120] In one alternative implementation, the number of EUs is at least one, and each EU corresponds to at least one of the plurality of first upstream queues; The step of transmitting the second data to the execution unit EU includes: Based on the first upstream queue from which the second data originates, a target EU matching the second data is determined from at least one of the EUs; The second data is then transmitted to the target EU.
[0121] It is understood that the specific principles or examples of the data transmission system provided in the third aspect of the embodiments of this application can be referred to the corresponding embodiments in the first and second aspects above, and will not be repeated here.
[0122] Fourthly, embodiments of this application provide a chip that includes the system described in any of the preceding claims.
[0123] In some examples, the chip can be an artificial intelligence processor, which can be any of the following: CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit).
[0124] For example, see Figure 6 Taking GPGPU as an example, GPGPU may include a host module, a command processing engine (CPE), an arbitration module (RR), and multiple execution units (EUs) (e.g., first execution unit EU1, second execution unit EU2, ..., nth execution unit EUUn). Taking the transmission process of the same data in GPGPU as an example, the data is first acquired by the host module and stored in the second upstream queue corresponding to the host module. Then, the CPE reads the data from the second upstream queue corresponding to the host module and stores the data in the second upstream queue corresponding to the CPE. After the arbitration module (RR) reads the data from the second upstream queue corresponding to the CPE, it can pass the data to the EU that matches the data among the multiple execution units (EUs).
[0125] Fifthly, embodiments of this application provide a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method described in any of the preceding claims.
[0126] Sixthly, embodiments of this application provide a computer device including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the steps of the method described in any of the preceding claims.
[0127] See Figure 7 The computer device of this embodiment includes a processor 701, a memory 702, and a computer program stored in the memory 702 and executable on the processor 701, such as a data storage program and a data retrieval program. When the processor 701 executes the computer program, it implements the steps in the various data storage methods and data retrieval methods embodiments described above.
[0128] For example, the computer program may be divided into one or more modules / units, which are stored in the memory 702 and executed by the processor 701 to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the computer device.
[0129] The computer device may be a desktop computer, laptop, handheld computer, or cloud server, etc. The computer device may include, but is not limited to, a processor 701 and a memory 702. Those skilled in the art will understand that the schematic diagram is merely an example of a computer device and does not constitute a limitation on the computer device. It may include more or fewer components than illustrated, or combine certain components, or different components. For example, the computer device may also include input / output devices, network access devices, buses, etc.
[0130] The processor 701 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or processor 701 can be any conventional processor. The processor 701 is the control center of the computer device, connecting various parts of the entire computer device through various interfaces and lines.
[0131] The memory 702 can be used to store the computer programs and / or modules. The processor 701 implements various functions of the computer device by running or executing the computer programs and / or modules stored in the memory 702 and calling the data stored in the memory 702. The memory 702 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, phonebook, etc.). In addition, the memory 702 may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.
[0132] Wherein, if the modules / units integrated into the computer device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a non-transitory computer-readable storage medium. When the computer program is executed by the processor 701, it can implement the steps of the various method embodiments described above. Wherein, the computer program includes computer program code, which can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc.
[0133] In summary, the embodiments of this application have at least the following beneficial effects: In this embodiment, the upstream module is associated with multiple first upstream queues corresponding to multiple priorities. After acquiring the first data, the upstream module stores the first data into a second upstream queue that matches the priority information read from the first data. In this way, the upstream module considers the priority of different data when storing data and stores it in the queue with the corresponding priority. This enables data to be transmitted in priority order in each unit of the chip, thereby improving the flexibility of data transmission between upstream and downstream of the chip. In addition, when the upstream module is a host module, the correspondence between each first upstream queue and each priority can be configured according to the priority information of all first data within a preset time period, thereby improving the efficiency of hardware data reception and thus improving the processing performance of the chip.
[0134] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary hardware platforms, or it can be implemented entirely by hardware. Based on this understanding, all or part of the technical solutions of this application that contribute to the background technology can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM (Read-Only Memory) / RAM (Random Access Memory), magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.
[0135] The above description is the preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.
Claims
1. A data storage method, characterized by, The method is suitable for an upstream module associated with a plurality of first upstream queues corresponding to a plurality of priorities, and comprises: obtaining first data; reading priority information corresponding to the first data from the first data; storing the first data in a second upstream queue, wherein the second upstream queue is a queue matched with the priority information among the plurality of first upstream queues; wherein, in the case that the upstream module is a host module, the correspondence between the plurality of first upstream queues and the plurality of priorities is configured according to priority information of all first data within a preset time period.
2. The method of claim 1, wherein: the plurality of first upstream queues are all first-in-first-out (FIFO) queues.
3. The method of claim 1, wherein, The reading of the priority information corresponding to the first data from the first data comprises: reading a priority domain segment of the first data to obtain the priority information.
4. The method of claim 1, wherein, In the case that the upstream module is a host module, the obtaining of the first data comprises: reading a data packet from a memory to serve as the first data.
5. A data reading method characterized by, The method is suitable for a downstream module, and comprises: reading second data from a plurality of first upstream queues according to a plurality of priorities; wherein the plurality of first upstream queues correspond to the plurality of priorities, and the plurality of first upstream queues are associated with an upstream module configured to read priority information corresponding to first data from the first data obtained by the upstream module, and store the first data in a second upstream queue, wherein the second upstream queue is a queue matched with the priority information among the plurality of first upstream queues; wherein, in the case that the upstream module is a host module, the correspondence between the plurality of first upstream queues and the plurality of priorities is configured according to priority information of all first data within a preset time period.
6. The method of claim 5, wherein: the plurality of first upstream queues are all FIFO queues.
7. The method of claim 5, wherein, The method further comprises: inquiring real-time states of the plurality of first upstream queues respectively; wherein the reading of the second data from the plurality of first upstream queues according to the plurality of priorities comprises: reading the second data from the plurality of first upstream queues based on the plurality of priorities and the inquired real-time states.
8. The method of claim 7, wherein, The reading of the second data from the plurality of first upstream queues based on the plurality of priorities and the inquired real-time states comprises: in a descending order of the plurality of priorities, sequentially performing the following operation for each priority in the plurality of priorities: determining, according to the inquired real-time states, whether a first upstream queue corresponding to the priority is empty or not; if not, reading the second data from the first upstream queue corresponding to the priority and not empty; if yes, performing the operation for a next priority.
9. The method of any one of claims 5-8, wherein: In a case that the upstream module is a host module, the downstream module is a command processing engine (CPE); In a case that the upstream module is a CPE, the downstream module is a resolution module (RR), and the method further comprises: in response to reading the second data, delivering the second data to an execution unit (EU).
10. The method of claim 9, wherein, The number of the EUs is at least one, and each of the EUs corresponds to at least one first upstream queue in the plurality of first upstream queues; The delivering the second data to the EU comprises: determining a target EU matching the second data from the EUs according to a first upstream queue from which the second data comes; delivering the second data to the target EU.
11. A data transmission system, characterized by comprises: an upstream module associated with a plurality of first upstream queues, the plurality of first upstream queues corresponding to a plurality of priorities, the upstream module configured to: obtain first data, read priority information corresponding to the first data from the first data, and store the first data in a second upstream queue, wherein the second upstream queue is a queue in the plurality of first upstream queues matching the priority information; and a downstream module configured to: read second data from the plurality of first upstream queues according to the plurality of priorities; In a case that the upstream module is a host module, the correspondence between the plurality of first upstream queues and the plurality of priorities is configured according to priority information of all first data in a preset time period.
12. The system of claim 11, wherein, In a case that the upstream module is a host module, the first data is a data packet read by the host module from a memory.
13. The system of claim 11, wherein, The plurality of first upstream queues are all FIFO queues.
14. The system of claim 11, wherein, The reading the priority information corresponding to the first data from the first data comprises: reading a priority domain segment of the first data to obtain the priority information.
15. The system of claim 11, wherein, The downstream module is further configured to: query real-time states of the plurality of first upstream queues respectively; The reading the second data from the plurality of first upstream queues according to the plurality of priorities comprises: reading the second data from the plurality of first upstream queues based on the plurality of priorities and the queried real-time states.
16. The system of claim 15, wherein, The reading the second data from the plurality of first upstream queues based on the plurality of priorities and the queried real-time states comprises: in order of the plurality of priorities from high to low, sequentially performing the following operation for each priority in the plurality of priorities: determining, according to the queried real-time states, whether first upstream queues corresponding to the priority are all empty queues; if not, reading the second data from the first upstream queues corresponding to the priority and not being empty queues; if yes, performing the operation for a next priority.
17. The system of any one of claims 11-16, wherein, In the case that the upstream module is a host module, the downstream module is a CPE; In the case that the upstream module is a CPE, the downstream module is an RR, and the downstream module is further configured to, in response to reading the second data, transfer the second data to an EU.
18. The system of claim 17, wherein, The number of the EUs is at least one, and each of the EUs corresponds to at least one first upstream queue in the plurality of first upstream queues; The transferring of the second data to an execution unit (EU) comprises: According to the first upstream queue from which the second data comes, determining a target EU matching the second data from at least one of the EUs; Transferring the second data to the target EU.
19. A chip, characterized by The system of any one of claims 11-18. 20.A non-transitory computer-readable storage medium having stored thereon a computer program. The computer program, when executed by a processor, implements the method of any one of claims 1-10.
21. A computer device, comprising: The system comprises a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the method of any one of claims 1-10 when executing the computer program.