Streamline command distribution method and device, computer equipment and storage medium
By dynamically adjusting the read request length in the pipelined command distribution, the problems of low FIFO cache efficiency and bus jamming are solved, resulting in more efficient instruction execution and improved system performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-26
- Publication Date
- 2026-03-31
AI Technical Summary
In pipelined command distribution, issues such as low FIFO caching efficiency or bus freezing can lead to performance degradation.
By checking the number of currently valid data items in the first-in-first-out queue, the read burst length of read requests is dynamically adjusted to ensure that the queue is kept close to full, preventing the backpressure bus from being overwritten.
It improves cache efficiency, prevents bus jamming, optimizes instruction execution, and enhances system performance.
Smart Images
Figure CN121764537A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and more specifically, to a method, apparatus, computer device, and storage medium for pipelined command distribution. Background Technology
[0002] Pipeline instruction dispatch is a technique that breaks down instruction execution into multiple stages (such as fetch, decode, execute, memory access, and write-back) for parallel processing, aiming to improve CPU throughput. However, this parallelism relies on conflict-free execution between instructions. Once a data hazard occurs (such as an instruction needing the result of a previous instruction), bubbles can form in the pipeline, leading to performance degradation.
[0003] First-In-First-Out (FIFO) queue buffering is a data management mechanism used to buffer data between modules with different processing speeds, ensuring that data is processed in sequence.
[0004] If the rate at which pipeline commands are dispatched does not match the read and write rate of the FIFO, the FIFO will either frequently idle (low cache efficiency) or remain full (bus stall). For example, when the pipeline is blocked due to data hazards, write operations to the FIFO may stall while read operations continue, eventually causing the FIFO to become empty, preventing subsequent commands from being written, and causing the bus to stall while waiting for data. Summary of the Invention
[0005] This application provides a method, apparatus, computer device, and storage medium for pipelined command distribution.
[0006] A first aspect of this application provides a method for pipelined command distribution, comprising: After retrieving a complete command from the first-in-first-out queue each time, determine whether the number of valid data in the first-in-first-out queue is less than a preset threshold; If the number of used address spaces in the first-in-first-out queue is less than a preset threshold, determine N. inflight +(M AX_PLD *32 / DW) +usedw≤2 AW Whether it is true or not, where N inflight M represents the number of response data reads. AX_PLD The maximum length of a single command, DW is the width of the first-in-first-out queue, and usedw is the number of currently valid data items in the first-in-first-out queue; In N inflight +(M AX_PLD *32 / DW) +usedw≤2 AW If the condition is met, set the read burst length arlen = P-1 for the read request and initiate a read operation, where P=2. AW-usedw; In N inflight +(M AX_PLD *32 / DW) +usedw≤2 AW If the condition is not met, check again after retrieving a complete command from the first-in-first-out queue.
[0007] In an optional embodiment of this application, the method further includes: When first reading commands from the preset memory into the first-in-first-out queue, set the read burst length arlen for the read request to 2. AW -1, where 2 AW The depth of the first-in-first-out queue.
[0008] In an optional embodiment of this application, the number of read response data is the number of data for which a read request has been initiated but a read response has not yet been received. In the case of an initiated read request, the number of read response data N is... inflight =arlen+1, for each read response data returned, N inflight = N inflight -1, when all read response data is returned, N inflight It is 0.
[0009] In an optional embodiment of this application, the number of currently valid data items in the first-in-first-out queue is determined by the following steps: Each time a read operation is initiated, arlen+1 is added to the current number of valid data in the first-in-first-out queue; Each time a number is read from the first-in-first-out queue, the number of currently valid data in the first-in-first-out queue is decremented by 1. When a read operation is initiated and the bus returns one data item simultaneously, arlen is incremented to the current number of valid data items in the first-in-first-out queue.
[0010] In an optional embodiment of this application, the preset threshold is determined by the following expression: T usedw = 2 AW -ceil(M AX_PLD *32 / DW) Among them, T usedw As a preset threshold, 2 AW M represents the depth of the first-in-first-out queue, where ceil represents rounding up. AX_PLD DW is the maximum length of a single command and the width of the first-in-first-out queue.
[0011] In an optional embodiment of this application, the relationship between the width of the first-in-first-out queue and the maximum length of the command is expressed by the following expression: DW*2 AW ≥N*MAX_PLD*32 N=ceil(t ddr_latency / t core_latency ) Where DW is the width of the first-in-first-out queue, 2 AW M represents the depth of the first-in-first-out queue. AX_PLD The maximum length of a single command, ceil indicates rounding up, t ddr_latency t is the average latency for reading commands from preset memory. core_latency The delay required for the kernel to process a single command after reading.
[0012] In an optional embodiment of this application, reading commands from a preset memory into a first-in-first-out queue includes: Commands stored in preset memory are prefetched into a first-in-first-out queue by the command handler, where kernel-processed commands are executed after the command handler.
[0013] A second aspect of this application provides an apparatus for pipelined command distribution, comprising: The first determining module is used to determine whether the number of valid data in the first-in-first-out queue is less than a preset threshold after each complete command is retrieved from the first-in-first-out queue. The second determining module is used to determine N when the number of used address spaces in the first-in-first-out queue is less than a preset threshold. inflight +(M AX_PLD *32 / DW) +usedw≤2 AW Whether it is true or not, where N inflight M represents the number of response data reads. AX_PLD The maximum length of a single command, DW is the width of the first-in-first-out queue, and usedw is the number of currently valid data items in the first-in-first-out queue; The inspection module is used to check N inflight +(M AX_PLD *32 / DW) +usedw≤2 AW If the condition is not met, check again after retrieving a complete command from the first-in-first-out queue next time. The configuration module is used in N inflight +(M AX_PLD *32 / DW) +usedw≤2 AW If the condition is met, set the read burst length arlen = P-1 for the read request and initiate a read operation, where P=2. AW -usedw.
[0014] A third aspect of this application provides a computer device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above-mentioned pipelined command distribution methods.
[0015] A fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of any of the above-described pipelined command distribution methods.
[0016] Compared with the prior art, the technical solutions provided in this application have at least some or all of the following advantages: The pipelined command distribution method described in this application, after retrieving one complete command from the first-in-first-out (FIFO) queue each time, determines whether the number of currently valid data items in the FIFO queue is less than a preset threshold; if the number of used address spaces in the FIFO queue is less than the preset threshold, determines N. inflight +(M AX_PLD *32 / DW) +usedw≤2 AW Whether it is true or not, where N inflight M represents the number of response data reads. AX_PLD Where N is the maximum length of a single command, DW is the width of the FIFO queue, and usedw is the number of currently valid data items in the FIFO queue; inflight +(M AX_PLD *32 / DW) +usedw≤2 AW If the condition is met, set the read burst length arlen = P-1 for the read request and initiate a read operation, where P=2. AW -usedw; in N inflight +(M AX_PLD *32 / DW) +usedw≤2 AW If the condition is not met, the system will check again after retrieving a complete command from the FIFO queue. The system will then compare the current number of valid data entries in the FIFO queue with a preset threshold to determine whether to initiate a read operation. If a read operation is initiated, the system will set the read burst length of the read request to keep the FIFO queue in a dynamically full state. At the same time, it will ensure that the total number of valid data entries to be processed does not exceed the depth of the FIFO queue, thus preventing the FIFO queue from being filled and causing back pressure on the bus. Attached Figure Description
[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1A flowchart of a pipelined command distribution method provided in one embodiment of this application; Figure 2 A schematic diagram of a first-in-first-out queue provided for one embodiment of this application; Figure 3 A schematic diagram of a device structure for pipelined command distribution provided in one embodiment of this application; Figure 4 This is a schematic diagram of a computer device structure provided in one embodiment of this application. Detailed Implementation
[0018] In the process of developing this application, the inventors discovered that the current pipelined command distribution method is poor in terms of caching efficiency and bus freezing.
[0019] To address the aforementioned issues, this application provides a method, apparatus, computer device, and storage medium for pipelined command distribution to improve caching efficiency and resolve bus jamming problems.
[0020] The solutions in this application embodiment can be implemented using various hardware description languages for integrated circuit design, such as C language, VHDL, Verilog, and SystemVerilog.
[0021] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.
[0022] Please see Figure 1 The pipelined command distribution method provided in this application includes the following steps S100~S400: S100: After retrieving one complete command from the first-in-first-out queue each time, determine whether the number of valid data in the first-in-first-out queue is less than a preset threshold. S200, if the number of used address spaces in the first-in-first-out queue is less than a preset threshold, determine N. inflight +(M AX_PLD *32 / DW) +usedw≤2 AW Whether it is true or not, where N inflight M represents the number of response data reads. AX_PLD The maximum length of a single command, DW is the width of the first-in-first-out queue, and usedw is the number of currently valid data items in the first-in-first-out queue; S300, in N inflight +(M AX_PLD*32 / DW) +usedw≤2 AW If the condition is met, set the read burst length arlen = P-1 for the read request and initiate a read operation, where P=2. AW -usedw; S400, in N inflight +(M AX_PLD *32 / DW) +usedw≤2 AW If this condition is not met, and a read operation is initiated at this time, and the subsequent bus return data has a large delay, the first-in-first-out queue will be filled. Therefore, a read operation will not be initiated, and the check will be performed after a complete command is retrieved from the first-in-first-out queue next time.
[0023] In an optional embodiment of this application, the standard definition for a full FIFO queue is usedw + P = 2. AW That is, the sum of the actual cached data in the FIFO, the bus inflight data, and the number of data to be read is exactly enough to fill the FIFO.
[0024] In an optional embodiment of this application, the First-In-First-Out (FIFO) queue supports simultaneous read and write operations and can output `empty` / `full` to indicate whether the FIFO is empty or full, and `freedw` / `usedw` to indicate the number of unused and used address spaces, respectively. Specifically, `usedw` represents the number of currently valid data items in the FIFO. See also... Figure 2 FIFO depth is 2 AW The width is DW, and its total size is DW*2. AW .
[0025] In an optional embodiment of this application, the maximum length of a single command is M. AX_PLD Each command has a different actual length, varying within a specific range. All commands can be stored in the ring buffer of Double Data Rate (DDR) memory (a 32-bit (4-byte) data type), and are prefetched into the on-chip FIFO by the command processor. (The ring buffer is typically a dynamically allocated contiguous physical memory area in DDR memory used for efficient data write and read operations.)
[0026] The pipelined command distribution method of this application checks the corresponding conditions for each command retrieved from the FIFO and initiates a bus read operation in a timely manner, which can supplement data and reduce cavitation during operation.
[0027] The pipelined command distribution method of this application dynamically prefetches once for each command consumed, and the prefetch length is dynamically adjusted, which can improve prefetch performance, ensure that the on-chip cache FIFO is close to full, and adjust the number of read requests according to the number of data not returned by the bus to prevent the FIFO from being filled and the backpressure bus from being pushed.
[0028] The pipelined command distribution method of this application determines whether a threshold check is met based on the number of read response data on the bus and the actual number of valid data in the FIFO, confirms in real time whether a read operation needs to be initiated, and determines the number of data requested for the read operation, i.e., arlen = P - 1 = 2. AW -usedw-1 calculates the number of unreturned responses on the bus, adjusts the number of read requests and the length of data read on the bus, ensures that the cache is not filled, prevents backpressure on the bus from causing the program to freeze, and can prevent backpressure on the bus.
[0029] In an optional embodiment of this application, the method further includes: When first reading commands from the preset memory into the first-in-first-out queue, set the read burst length arlen for the read request to 2. AW -1, where 2 AW The depth of the first-in-first-out queue.
[0030] When first reading commands from the preset memory into the first-in-first-out queue, set the read burst length arlen for the read request to 2. AW -1 means that the inflight read response data can fill the FIFO completely without back-pressure on the bus.
[0031] In an optional embodiment of this application, the number of read response data is the number of data for which a read request has been initiated but a read response has not yet been received. In the case of an initiated read request, the number of read response data N is... inflight =arlen+1, for each read response data returned, N inflight = N inflight -1, when all read response data is returned, N inflight It is 0.
[0032] In an optional embodiment of this application, the number of currently valid data items in the first-in-first-out queue is determined by the following steps: Each time a read operation is initiated, arlen+1 is added to the current number of valid data in the first-in-first-out queue; Each time a number is read from the first-in-first-out queue, the number of currently valid data in the first-in-first-out queue is decremented by 1. When a read operation is initiated and the bus returns one data item simultaneously, arlen is incremented to the current number of valid data items in the first-in-first-out queue, where the actual number of data items read is arlen+1.
[0033] In an optional embodiment of this application, the preset threshold is determined by the following expression: T usedw = 2 AW -ceil(M AX_PLD *32 / DW) Among them, T usedw As a preset threshold, 2 AW M represents the depth of the first-in-first-out queue, where ceil represents rounding up. AX_PLD DW is the maximum length of a single command and the width of the first-in-first-out queue.
[0034] The pipelined command distribution method of this application has a preset threshold of the number of data bits corresponding to the maximum command's DW width. If the preset threshold is set too low, it may result in a situation where one command is retrieved from the FIFO but the data is not replenished in time. If the preset threshold is set too high, it may result in too many read requests being sent to the bus, but the arlen for each read is small, causing bus congestion.
[0035] In an optional embodiment of this application, the relationship between the width of the first-in-first-out queue and the maximum length of the command is expressed by the following expression: DW*2 AW ≥N*MAX_PLD*32 N=ceil(t ddr_latency / t core_latency ) Where DW is the width of the first-in-first-out queue, 2 AW M represents the depth of the first-in-first-out queue. AX_PLD The maximum length of a single command, ceil indicates rounding up, t ddr_latency t is the average latency for reading commands from preset memory. core_latency The delay required for the kernel to process a single command after reading.
[0036] The pipelined command distribution method of this application sets the on-chip cache size based on the relationship between the width of the first-in-first-out queue and the maximum length of the command, i.e., the ratio of DDR latency to CORE processing latency, which can guarantee pipelined execution.
[0037] In an optional embodiment of this application, reading commands from a preset memory into a first-in-first-out queue includes: Commands stored in preset memory are prefetched into a first-in-first-out queue by the command handler. Kernel-processed commands are executed after the command handler, which retrieves commands from preset memory and distributes them to the kernel.
[0038] In an optional embodiment of this application, the pipelined command distribution method of this application is applied to bitonic sorting, wherein bitonic sorting includes: Divide all resources used for bitonic sorting into bitonic sorting modules with multiple input types; Construct the correspondence between the bitonic sorting task and the bitonic sorting time sequence, wherein the bitonic sorting time sequence consists of bitonic sorting modules sorted according to time. Upon receiving the target bitonic sorting task, the target bitonic sorting timing is determined based on the correspondence between the bitonic sorting task and the bitonic sorting timing. The bitonic sorting module in the target bitonic sorting time sequence is retrieved based on the input data in the target bitonic sorting task, and the bitonic sorting task is executed according to the time sorting of the bitonic sorting module.
[0039] In an optional embodiment of this application, the bitonic sorting module, which divides all resources used for bitonic sorting into multiple input types, includes: All resources used for bitonic sorting are divided into multiple 8-input bitonic sorting modules, multiple 16-input bitonic sorting modules, multiple 32-input bitonic sorting modules, and multiple 64-input bitonic sorting modules. The sorting directions of two adjacent 8-input bitonic sorting modules are opposite, the sorting directions of two adjacent 16-input bitonic sorting modules are opposite, the sorting directions of two adjacent 32-input bitonic sorting modules are opposite, and the sorting directions of two adjacent 64-input bitonic sorting modules are opposite.
[0040] In an optional embodiment of this application, the bitonic sorting sequence consists of a time-ordered bitonic sorting module, including: The bitone sorting sequence is composed of 8-input bitone sorting modules, 16-input bitone sorting modules, 32-input bitone sorting modules, and 64-input bitone sorting modules arranged and combined according to time order. The 8-input bitone sorting module is formed by the following steps: two adjacent 2-input bitone sorting modules with opposite sorting directions form a 4-input bitone sorting module, and two adjacent 4-input bitone sorting modules with opposite sorting directions form an 8-input bitone sorting module; the 16-input bitone sorting module is formed by two adjacent 8-input bitone sorting modules with opposite sorting directions; the 32-input bitone sorting module is formed by two adjacent 16-input bitone sorting modules with opposite sorting directions; and the 64-input bitone sorting module is formed by two adjacent 32-input bitone sorting modules with opposite sorting directions.
[0041] In an optional embodiment of this application, the bitonic sorting task includes 8-to-8, 16-to-8, 32-to-8, 64-to-8, 128-to-8, 16-to-16, 32-to-16, 64-to-16, 128-to-16, 32-to-32, 64-to-32, 128-to-32, and 512-to-32. The step of constructing the correspondence between the bitonic sorting task and the bitonic sorting time sequence includes: For the same bitonic sorting task, the 8-input bitonic sorting module, 16-input bitonic sorting module, 32-input bitonic sorting module and 64-input bitonic sorting module in the bitonic sorting sequence are arranged in various combinations according to time, and the current bitonic sorting task is executed. Based on the execution results, select the bitonic sorting sequence corresponding to the current bitonic sorting task from multiple permutations and combinations.
[0042] In an optional embodiment of this application, the step of determining the target bitonic sorting sequence corresponding to the target bitonic sorting task based on the correspondence between bitonic sorting tasks and bitonic sorting sequences upon receiving the target bitonic sorting task includes: The timing sequence for the 8-to-8 bitone sorting is an 8-input bitone sorting module, while the timing sequence for the 16-to-8 bitone sorting is two parallel 8-input bitone sorting modules and a 16-input bitone sorting module.
[0043] In an optional embodiment of this application, the step of retrieving the bitonic sorting module in the target bitonic sorting time sequence based on the input data in the target bitonic sorting task, and executing the bitonic sorting task according to the time order of the bitonic sorting module, includes: When all resources used for bitonic sorting are divided into eight 8-input bitonic sorting modules, four 16-input bitonic sorting modules, two 32-input bitonic sorting modules, and two 64-input bitonic sorting modules, at least one bitonic sorting module from the 8-input bitonic sorting module, 16-input bitonic sorting module, 32-input bitonic sorting module, and 64-input bitonic sorting module in the target bitonic sorting time sequence is called according to the input data in the target bitonic sorting task. The retrieved bitone sorting modules are sorted according to their time order to obtain the first to the Nth bitone sorting modules. The input data A bit in the target bitone sorting task is divided into A / bit groups in 8-bit units. 64 bits of data are received at a time and input to the first bitone sorting module. The output of the first bitone sorting module is used as the input of the second bitone sorting module, and so on, until the output of the (N-1)th bitone sorting module is used as the input of the Nth bitone sorting module.
[0044] In an optional embodiment of this application, when A is 128, the step of sorting the retrieved bitone sorting modules according to their time order to obtain the sorted first to Nth bitone sorting modules includes: When A is 128, the first bitone sorting module consists of eight 8-input bitone sorting modules, the second bitone sorting module consists of eight 8-input bitone sorting modules, the third bitone sorting module consists of four 16-input bitone sorting modules, the fourth bitone sorting module consists of four 16-input bitone sorting modules, the fifth bitone sorting module consists of four 16-input bitone sorting modules, the sixth bitone sorting module consists of two 16-input bitone sorting modules, and the sixth bitone sorting module consists of one 16-input bitone sorting module. The sorting directions are opposite between adjacent 8-input bitone sorting modules, adjacent 16-input bitone sorting modules, adjacent 32-input bitone sorting modules, and adjacent 64-input bitone sorting modules.
[0045] In high-performance computing, when implementing bitone sorting on a graphics processing unit, optimizing instruction scheduling through pipelined command distribution not only improves sorting efficiency but also significantly enhances system performance through collaborative optimization.
[0046] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.
[0047] Please see Figure 3 One embodiment of this application provides a pipelined command distribution apparatus 300, comprising: The first determining module 310 is used to determine whether the number of valid data in the first-in-first-out queue is less than a preset threshold after each complete command is taken out from the first-in-first-out queue. The second determining module 320 is used to determine N when the number of used address spaces in the first-in-first-out queue is less than a preset threshold. inflight +(M AX_PLD *32 / DW) +usedw≤2 AW Whether it is true or not, where N inflight M represents the number of response data reads.AX_PLD The maximum length of a single command, DW is the width of the first-in-first-out queue, and usedw is the number of currently valid data items in the first-in-first-out queue; Inspection module 330, used in N inflight +(M AX_PLD *32 / DW) +usedw≤2 AW If the condition is not met, check again after retrieving a complete command from the first-in-first-out queue next time. Setting module 340, used in N inflight +(M AX_PLD *32 / DW) +usedw≤2 AW If the condition is met, set the read burst length arlen = P-1 for the read request and initiate a read operation, where P=2. AW -usedw.
[0048] In an optional embodiment of this application, the standard definition for a full FIFO queue is usedw + P = 2. AW That is, the sum of the actual cached data in the FIFO, the bus inflight data, and the number of data to be read is exactly enough to fill the FIFO.
[0049] In an optional embodiment of this application, the First-In-First-Out (FIFO) queue supports simultaneous read and write operations and can output `empty` / `full` to indicate whether the FIFO is empty or full, and `freedw` / `usedw` to indicate the number of unused and used address spaces, respectively. Specifically, `usedw` represents the number of currently valid data items in the FIFO. See also... Figure 2 FIFO depth is 2 AW The width is DW, and its total size is DW*2. AW .
[0050] In an optional embodiment of this application, the maximum length of a single command is M. AX_PLD Each command has a different actual length, varying within a specific range. All commands can be stored in the ring buffer of Double Data Rate (DDR) memory (a 32-bit (4-byte) data type), and are prefetched into the on-chip FIFO by the command processor. (The ring buffer is typically a dynamically allocated contiguous physical memory area in DDR memory used for efficient data write and read operations.)
[0051] The pipelined command distribution device of this application checks the corresponding conditions for each command retrieved from the FIFO and initiates a bus read operation in a timely manner, which can replenish data to reduce cavitation during operation.
[0052] The pipelined command distribution device of this application dynamically prefetches once for each command consumed, and the prefetch length is dynamically adjusted, which can improve prefetch performance, ensure that the on-chip cache FIFO is close to full, and adjust the number of read requests according to the number of data not returned by the bus to prevent the FIFO from being filled and the backpressure bus from being pushed.
[0053] The pipelined command distribution device of this application determines whether a threshold check is met based on the number of read response data on the bus and the actual number of valid data in the FIFO, confirms in real time whether a read operation needs to be initiated, and determines the number of data requested for the read operation, i.e., arlen = P - 1 = 2. AW -usedw-1 calculates the number of unreturned responses on the bus and adjusts the number of read requests to ensure that the cache is not filled, preventing backpressure on the bus from causing the program to freeze.
[0054] In an optional embodiment of this application, the apparatus further includes: The configuration module is used to set the read burst length arlen=2 when the command in the preset memory is first read into the first-in-first-out queue. AW -1, where 2 AW The depth of the first-in-first-out queue.
[0055] In an optional embodiment of this application, in the second determining module, the number of read response data is the number of data for which a read request has been initiated but a read response has not yet been received. In the case of an initiated read request, the number of read response data N is... inflight =arlen+1, for each read response data returned, N inflight = N inflight -1, when all read response data is returned, N inflight It is 0.
[0056] In an optional embodiment of this application, the number of currently valid data items in the first-in-first-out queue is determined in the first determining module through the following steps: Each time a read operation is initiated, arlen+1 is added to the current number of valid data in the first-in-first-out queue; Each time a number is read from the first-in-first-out queue, the number of currently valid data in the first-in-first-out queue is decremented by 1. When a read operation is initiated and the bus returns one data item simultaneously, arlen is incremented to the current number of valid data items in the first-in-first-out queue.
[0057] In an optional embodiment of this application, the bus returns one data item, which is equivalent to returning one read response.
[0058] In an optional embodiment of this application, in the first determining module, a preset threshold is determined by the following expression: T usedw = 2 AW -ceil(M AX_PLD *32 / DW) Among them, T usedw As a preset threshold, 2 AW M represents the depth of the first-in-first-out queue, where ceil represents rounding up. AX_PLD DW is the maximum length of a single command and the width of the first-in-first-out queue.
[0059] The pipelined command distribution device of this application has a preset threshold of the number of data bits corresponding to the maximum command's DW width. If the preset threshold is set too low, it may result in a situation where one command is retrieved from the FIFO but the data is not replenished in time. If the preset threshold is set too high, it may result in too many read requests being sent to the bus, but the arlen for each read is small, causing bus congestion.
[0060] In an optional embodiment of this application, in the second determining module, the relationship between the width of the first-in-first-out queue and the maximum length of the command is expressed by the following expression: DW*2 AW ≥N*MAX_PLD*32 N=ceil(t ddr_latency / t core_latency ) Where DW is the width of the first-in-first-out queue, 2 AW M represents the depth of the first-in-first-out queue. AX_PLD The maximum length of a single command, ceil indicates rounding up, t ddr_latency t is the average latency for reading commands from preset memory. core_latency The delay required for the kernel to process a single command after reading.
[0061] The pipelined command distribution device of this application sets the on-chip cache size based on the relationship between the width of the first-in-first-out queue and the maximum length of the command, i.e., the ratio of DDR latency to CORE processing latency, which ensures pipelined execution.
[0062] In an optional embodiment of this application, the setting module reads commands from preset memory into a first-in-first-out queue, including: Commands stored in preset memory are prefetched into a first-in-first-out queue by the command handler, where kernel-processed commands are executed after the command handler.
[0063] For specific limitations regarding the aforementioned device 300, please refer to the limitations of the pipelined command distribution method described above, which will not be repeated here. Each module in the aforementioned device 300 can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.
[0064] In one embodiment, a computer device is provided, the internal structure of which can be as follows: Figure 4 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements a pipelined command distribution method as described above. This includes: a memory and a processor; the memory stores a computer program; and the processor executes the computer program to implement any step of the pipelined command distribution method described above.
[0065] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, can perform any step of the method for pipelined command distribution as described above.
[0066] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0067] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0068] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0069] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0070] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.
[0071] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.
Claims
1. A method of pipelining the dispatch of commands, the method comprising: The method comprises: After taking out one complete command from the first-in first-out queue each time, it is determined whether the current valid data quantity in the first-in first-out queue is less than a preset threshold value; In a case where the used address space number of the first-in first-out queue is less than a preset threshold, determining N inflight + (M AX_PLD * 32 / DW) + usedw≤2 AW is established, wherein N inflight is the read response data number, M AX_PLD is the maximum length of a single command, DW is the width of the first-in first-out queue, and usedw is the current valid data number in the first-in first-out queue. In N inflight +(M AX_PLD *32 / DW) +usedw≤2 AW , set the read burst length arlen= P-1 of the read request, and initiate the read operation, where P=2 AW -usedw; In N inflight + (M AX_PLD * 32 / DW) + usedw≤2 AW If not, check again after the next complete command is fetched from the FIFO.
2. The method of claim 1, wherein, The method further comprises: In case of first reading of a command in the pre-set memory to the first-in-first-out queue, set the read burst length arlen=2 of the read request AW -1, wherein 2 AW is the depth of the first-in-first-out queue.
3. The method of claim 1, wherein, The read response data number is the number of data that has initiated a read request but has not received a read response. In the case of initiating a read request, the read response data number N inflight = arlen + 1, every time 1 read response data is returned, N inflight = N inflight - 1, all read response data is returned, N inflight = 0.
4. The method of claim 1, wherein, The current valid data quantity in the first-in first-out queue is determined by the following steps: In the case of initiating a read operation each time, arlen+1 is added to the current valid data quantity in the first-in first-out queue; In the case of reading one number from the first-in first-out queue each time, the current valid data quantity in the first-in first-out queue is reduced by 1; In the case of initiating a read operation and the bus returning one data occurring simultaneously each time, arlen is added to the current valid data quantity in the first-in first-out queue.
5. The method of claim 1, wherein, The preset threshold value is determined by the following expression: T usedw = 2 AW -ceil(M AX_PLD *32 / DW) wherein T usedw is a preset threshold, 2 AW is the depth of the first-in-first-out queue, ceil denotes rounding up, M AX_PLD is the maximum length of a single command, and DW is the width of the first-in-first-out queue.
6. The method of claim 2, wherein, The relationship between the width of the first-in first-out queue and the maximum length of the command is the following expression: DW*2 AW ≥N*MAX_PLD*32 N = ceil(t ddr_latency / t core_latency ) where DW is the width of the first-in-first-out queue, 2 AW is the depth of the first-in-first-out queue, M AX_PLD is the maximum length of a single command, ceil denotes rounding up, t ddr_latency is the average latency of reading a command from the preset memory, t core_latency is the latency required by the kernel to process a single command after reading.
7. The method of claim 6, wherein, The commands in the preset memory are read to the first-in first-out queue, comprising: The commands stored in the preset memory are prefetched to the first-in first-out queue by a command processing program, wherein the kernel processes the commands after the command processing program.
8. An apparatus for pipelining commands, the apparatus comprising: The method comprises: The first determination module is configured to determine, after taking out one complete command from the first-in first-out queue each time, whether the current valid data quantity in the first-in first-out queue is less than a preset threshold value; a second determining module, configured to determine N inflight + (M AX_PLD *32 / DW) + usedw≤2 AW , wherein N inflight is the number of read response data, M AX_PLD is the maximum length of a single command, DW is the width of the FIFO queue, and usedw is the number of current valid data in the FIFO queue. a check module for checking whether N inflight + (M AX_PLD * 32 / DW) + usedw≤2 AW If not, check again after the next complete command is fetched from the FIFO. The configuration module is used in N inflight +(M AX_PLD *32 / DW) +usedw≤2 AW If the condition is met, set the read burst length of the read request arlen = P-1, and initiate a read operation, where P=2. AW -usedw.
9. A computer device comprising: The computer program is stored in the memory and comprises a computer program product, and the processor executes the computer program to realize the steps of the method for pipelining and distributing commands according to any one of claims 1 to 7.
10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is stored in the memory and comprises a computer program product, and the processor executes the computer program to realize the steps of the method for pipelining and distributing commands according to any one of claims 1 to 7.