Memory chip interface signal integrity enhancement method supporting multiple rates

Abstract

The invention relates to the technical field of signal integrity, in particular to a storage chip interface signal integrity enhancing method supporting multiple rates. The method comprises the following steps: acquiring a multi-rate interface integrity index, and performing classified management on acquired data; based on the collected and classified multi-rate interface integrity indexes, the association rule of different interface rates and the integrity indexes is analyzed, and an interface signal core enhancement target under each rate is output; constructing a quantitative mapping model, specifically configuring interface parameters according to an interface signal core enhancement target, switching different rates to verify an optimization effect, and outputting an optimal configuration strategy under each rate; according to the method, integrity indexes under multiple rates are obtained and classified, the association rule of the rates and the indexes is analyzed to determine a core enhancement target, and then based on the target, parameters are configured through a quantitative model and iterative optimization verification is carried out, so that accurate enhancement of the interface signal integrity of the storage chip under a multi-rate scene is realized.

Description

Technical Field

[0001] This invention relates to the field of signal integrity technology, and in particular to a method for enhancing the signal integrity of a multi-rate memory chip interface. Background Technology

[0002] As storage technology develops towards higher speeds and multi-scenario adaptability, storage chip interfaces (such as DDR series, PCIe, eMMC, etc.) need to support multi-rate switching to meet the differentiated requirements of different applications for transmission rate and power consumption. In storage chip interfaces, signal integrity is particularly important to ensure that data is transmitted without distortion or errors, and to avoid data loss or errors caused by reflection, crosstalk, and other problems. Therefore, it directly determines the accuracy and reliability of data transmission.

[0003] However, when switching between multiple data rates, the signal integrity degradation mechanism of the memory chip interface differs at different data rates. In low-speed scenarios, reflection and power supply noise are more prominent, while in medium- and high-speed scenarios, transmission loss, crosstalk, and timing offset are significantly aggravated. Existing technologies rely solely on the experience of staff to configure fixed or single parameters, lacking analysis of the relationship between interface signal integrity and data rate in multiple data rate scenarios. This makes it impossible to perform targeted configurations, resulting in limited enhancement of the signal integrity of the memory chip interface. Summary of the Invention

[0004] The purpose of this invention is to provide a method for enhancing the signal integrity of a memory chip interface that supports multiple rates. This method aims to solve the technical problem in the prior art where fixed parameter configuration or single parameter configuration relies on the experience of staff, lacks analysis of the relationship between interface signal integrity and rate in multi-rate scenarios, and thus cannot be configured in a targeted manner, resulting in limited enhancement effect on the signal integrity of the memory chip interface.

[0005] To achieve the above objectives, the present invention employs a method for enhancing the signal integrity of a memory chip interface that supports multiple data rates, comprising the following steps: Obtain interface integrity metrics at multiple rates and classify and manage the collected data; Based on the multi-rate interface integrity index after data acquisition and classification, the correlation between different interface rates and integrity indices is analyzed, and the core enhancement targets of interface signals at each rate are output. Construct a quantization mapping model, configure interface parameters according to the core enhancement target of the interface signal, and switch between different rates to verify the optimization effect, and output the optimal configuration strategy at each rate.

[0006] Among the steps involved in acquiring multi-rate interface integrity metrics and classifying and managing the collected data: Deploy interface monitoring equipment to obtain the integrity indicators of the memory chip interface at the current rate. The integrity indicators include reflection, crosstalk, timing offset, power supply noise, and transmission loss. Switch the memory chip interface rate and obtain the integrity index again to get the interface integrity index at each rate.

[0007] In the step of switching the memory chip interface rate and obtaining the integrity index again to obtain the interface integrity index at each rate: Modify and save the interface rate parameters using the firmware configuration tool, then restart the device equipped with the storage chip normally. After the device completes initialization and the rate configuration is successfully loaded, collect the interface integrity index at that rate.

[0008] After switching the memory chip interface speed and obtaining the integrity index again to get the interface integrity index at each speed: The signal integrity index data collected at the corresponding rate is classified and stored according to the different rate levels of the storage chip interface.

[0009] Among them, in the step of analyzing the correlation between different interface rates and integrity indices based on multi-rate interface integrity indices after data acquisition and classification, and outputting the core enhancement targets of interface signals at each rate: The linear regression model was used to analyze the changing patterns between each rate and each integrity index; Based on the storage interface protocol standard, the actual values ​​of each type of integrity index at each speed are compared with the standard values ​​of the protocol, and the deviation rate is calculated. For each type of integrity indicator, a deviation weight is preset for the deviation rate, and the excess score of each type of integrity indicator is calculated based on the deviation weight and the deviation rate. The highest score at each rate was selected as the core enhancement target.

[0010] Before the steps of analyzing the correlation between different interface rates and integrity indices based on multi-rate interface integrity indices after data acquisition and classification, and outputting the core enhancement targets of interface signals at each rate: Feature extraction is performed on the multi-rate integrity index of the classification, outlier data is removed, and standardization transformation is performed.

[0011] Among them, the steps of constructing a quantization mapping model, configuring interface parameters according to the core enhancement target of the interface signal, switching different rates to verify the optimization effect, and outputting the optimal configuration strategy at each rate are as follows: The initial configuration parameters of the integrity index at each rate are calculated using a quantification formula. The MOPSO algorithm is used to iteratively fine-tune the parameters and optimize the parameter combination; The optimized parameters were configured to the memory chip interface for testing, and the speeds were switched sequentially. Data on the five integrity indicators after the parameters were iteratively optimized were collected to obtain the optimized integrity indicator data. The optimization achievement rate is calculated based on the optimized integrity index data to determine whether the enhancement effect has been achieved. If the enhancement effect is not achieved, continue to optimize and iterate the parameter combination.

[0012] In the step of iteratively fine-tuning the parameters and optimizing the parameter combination using the MOPSO algorithm: Based on the exceedance scores of the five integrity indicators at each rate, the parameter combination is iteratively adjusted through the MOPSO algorithm to minimize the deviation between the integrity indicators and the protocol standard values.

[0013] In the step of calculating the optimization achievement rate based on the optimized integrity index data and determining whether the enhancement effect has been achieved: Using the method for calculating the excess score of the integrity index, the excess score of the optimized integrity index data is calculated, and the optimized excess score is obtained. The optimization achievement rate is calculated by comparing the optimized score with the score before optimization. The enhancement effect is achieved when the optimization achievement rate of the core enhancement objective is >90% and the optimization achievement rate of the other four integrity indicators is >85%.

[0014] Specifically, after the step where the optimization achievement rate of the core enhancement objective is >90%, and the optimization achievement rate of the other four integrity indicators is >85%, the enhancement effect is achieved: The optimized parameter combination that meets the standard is used to conduct stability tests on the memory chip under multiple temperature conditions, and 30 sets of data are collected. When the fluctuation range of the integrity index is less than 5%, this optimized parameter combination is listed as the optimal configuration strategy.

[0015] This invention provides a method for enhancing the signal integrity of memory chip interfaces supporting multiple rates. The method acquires multi-rate interface integrity indicators and classifies the collected data. Based on the classified multi-rate interface integrity indicators, it analyzes the correlation between different interface rates and integrity indicators, outputting the core enhancement targets for interface signals at each rate. A quantization mapping model is constructed, and interface parameters are configured specifically according to the core enhancement targets. The optimization effect is verified by switching between different rates, and the optimal configuration strategy for each rate is output. By acquiring and classifying integrity indicators at multiple rates, analyzing the correlation between rates and indicators to determine the core enhancement targets, and then configuring parameters through a quantization model and iteratively optimizing and verifying based on the targets, precise enhancement of memory chip interface signal integrity in multi-rate scenarios is achieved. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of the steps of the method for enhancing the signal integrity of a multi-rate memory chip interface according to the present invention.

[0018] Figure 2 This is a flowchart of steps S100 of the present invention.

[0019] Figure 3 This is a flowchart of steps S200 of the present invention.

[0020] Figure 4 This is a flowchart of steps S300 of the present invention.

[0021] Figure 5 This is a flowchart of steps S304 of the present invention.

[0022] Figure 6 This is a schematic diagram of the signal integrity enhancement system for multi-rate memory chip interface according to the present invention.

[0023] Figure 7 This is a schematic diagram of the electronic device of the present invention.

[0024] 401 - Interface indicator acquisition module, 402 - Interface enhancement target output module, 403 - Interface configuration strategy output module. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0026] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0027] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0028] Please see Figures 1-4 This invention provides a method for enhancing the signal integrity of a memory chip interface that supports multiple data rates, comprising the following steps: S100: Acquires interface integrity metrics at multiple rates and classifies and manages the collected data.

[0029] In this implementation, multi-rate interface integrity metrics are acquired, and the collected data is categorized and managed. The specific process is as follows: S101: Deploy interface monitoring equipment to obtain the integrity indicators of the memory chip interface at the current rate. The integrity indicators include reflection, crosstalk, timing offset, power supply noise, and transmission loss. S102: Switch the storage chip interface rate, obtain the integrity index again, and obtain the interface integrity index at each rate; modify the interface rate parameter through the firmware configuration tool and save it, restart the running device equipped with the storage chip normally, and after the device completes initialization and the rate configuration is successfully loaded, collect the interface integrity index at that rate again; then classify and store the signal integrity index data collected at the corresponding rate according to the different rate levels of the storage chip interface.

[0030] In the above process, a dedicated interface monitoring device is integrated internally or externally into the testing platform for the memory chip. This device is equipped with a high-bandwidth signal acquisition port and a multi-protocol analysis interface, and is compatible with different types of memory chip interfaces, such as PCIe (3.0 / 4.0 / 5.0), SATA (Ⅲ), NVMe, DDR (4 / 5), etc. The interface monitoring device performs real-time signal capture and integrity index detection on the currently connected memory chip interface according to preset trigger conditions (such as automatic start after the device is powered on and initialized, or at a cycle of once every 100ms).

[0031] In acquiring reflection parameters, a time-domain reflectometer (TDR) or the built-in reflection monitoring register of the storage controller is used to measure the reflection characteristics of the signal at impedance discontinuities. The core indicators are the reflection coefficient (in dB) and the overshoot amplitude (in %VDDQ). The smaller the absolute value of the reflection coefficient and the lower the overshoot amplitude, the weaker the damage to signal integrity caused by reflection. It must comply with the interface protocol standard (e.g., the DDR series requires a reflection coefficient ≤ -15dB and an overshoot amplitude ≤ 10%VDDQ). For example, in a low-speed 4800Mbps storage interface, if the measured reflection coefficient is -10dB and the overshoot amplitude is 18%, the reflection problem is significant and it is easy to cause signal waveform oscillation.

[0032] In acquiring crosstalk parameters, an oscilloscope with a differential probe and crosstalk analysis software are used to measure the coupling interference between adjacent signal lines. The core indicators are the peak crosstalk (in mV) and the common-mode rejection ratio (in dB). The smaller the peak crosstalk and the larger the common-mode rejection ratio, the stronger the signal's anti-interference capability. Typically, the peak crosstalk should be ≤100mV and the common-mode rejection ratio should be ≥40dB. For example, in a mid-range 5600Mbps storage interface, if the measured peak crosstalk of adjacent DQ lines reaches 200mV, it will cause signal superposition interference waveforms, increasing the risk of sampling errors.

[0033] In acquiring timing offset parameters, the timing difference and timing margin of the signal arriving at the receiving end are captured using a logic analyzer or the timing calibration feedback register of the storage controller. The core indicators are signal skew (in ps), setup margin (in ps), and hold margin (in ps). The smaller the signal skew and the larger the timing margin, the higher the reliability of signal sampling. Protocol standards often require skew ≤ 50 ps, ​​setup margin ≥ 50 ps, ​​and hold margin ≥ 30 ps. For example, in a mid-range 5600 Mbps storage interface, if the measured signal skew reaches 100 ps and the setup margin is only 30 ps, ​​it will exceed the timing safety threshold and cause data transmission misalignment.

[0034] In acquiring power supply noise parameters, a power oscilloscope probe or the power monitoring register of the storage controller is used to collect fluctuation data of the interface power supply voltage (such as VDDQ). The core indicators are power supply ripple (in mV) and ground bounce voltage (in mV). The smaller the noise amplitude, the stronger the signal level stability. Typically, power supply ripple ≤ 50mV and ground bounce voltage ≤ 30mV are required. For example, in a low-speed 4800Mbps storage interface, if the measured VDDQ power supply ripple reaches 100mV, it will cause the high / low level judgment threshold of the signal to drift, increasing the probability of bit errors.

[0035] In obtaining transmission loss parameters, an eye diagram analyzer (derived by measuring eye diagram opening) or a vector network analyzer is used to quantify the attenuation of the signal after passing through the transmission line. The core indicator is transmission loss (in dB), and the loss increases with the interface speed (e.g., as the DDR5 speed increases from 4800Mbps to 7200Mbps, the loss typically increases by 3-4dB). The lower the transmission loss, the better the integrity of the signal reaching the receiving end. High-speed (e.g., 7200Mbps) requires transmission loss ≤6dB. For example, in a high-speed 7200Mbps storage interface, if the measured transmission loss reaches 9dB, it will cause the signal amplitude to attenuate below the threshold, resulting in eye diagram closure and a bit error rate soaring to over 1e-7.

[0036] Modify and save the interface speed parameters using the firmware configuration tool. The firmware configuration tool is a dedicated software tool designed for memory chip interfaces (such as DDR, PCIe, etc.). It establishes a connection with the communication interface of the memory chip / controller (such as JTAG, SPI, I2C, or a dedicated debug bus), reads the current interface speed configuration (such as 4800Mbps, 6400Mbps, etc. for DDR5), provides a visual interface or instruction set, allowing users to input target speed parameters (which must conform to the interface protocol specification, such as the speed levels defined by the JEDEC standard), and writes the modified speed parameters to the controller's non-volatile configuration register (or firmware Flash), ensuring that the parameters remain effective after a device reboot.

[0037] S200: Extract features from the classified multi-rate integrity indicators, remove outlier data and perform standardization transformation; based on the collected classified multi-rate interface integrity indicators, analyze the correlation between different interface rates and integrity indicators, and output the core enhancement targets of interface signals at each rate.

[0038] In this embodiment, feature extraction is performed on the classified multi-rate integrity indicators, outlier data is removed, and standardization transformation is applied. Based on the collected and classified multi-rate interface integrity indicators, the correlation between different interface rates and integrity indicators is analyzed, and the core enhancement targets of the interface signals at each rate are output. The specific process is as follows: S201: Use a linear regression model to analyze the changing patterns between each rate and each integrity index; S202: Based on the storage interface protocol standard, compare the actual values ​​of each type of integrity index at each speed with the standard values ​​of the protocol, and calculate the deviation rate; S203: Preset deviation weights for the deviation rate of each type of integrity indicator, and calculate the excess score of each type of integrity indicator based on the deviation weights and deviation rates; S204: Select the highest out-of-standard score at each rate as the core enhancement target; The linear regression model is Y = k × f + b, where Y is an SI index (e.g., transmission loss IL, logarithm of bit error rate log(BER)); f is the interface rate (in Gbps); k is the rate coefficient (positive / negative indicates positive / negative correlation, e.g., IL increases with f, k > 0); and b is a constant term (the baseline value when the rate is 0). The storage interface protocol standard clearly defines the electrical characteristics, signal integrity requirements, speed levels, and communication logic of different types of storage chip interfaces (such as DDR, PCIe, eMMC / UFS) to ensure compatibility and interoperability between storage chips from different manufacturers and host control devices. Specifically, it specifies requirements for reflection (e.g., DDR5 protocol requires reflection coefficient ≤ -15dB and overshoot amplitude ≤ 10%VDDQ), crosstalk (e.g., crosstalk peak value ≤ 100mV), timing skew (e.g., signal skew ≤ 50ps and setup margin ≥ 50ps), and power supply. The five integrity indicators—noise (e.g., VDDQ power ripple ≤ 50mV, ground bounce voltage ≤ 30mV), transmission loss (e.g., ≤ 4dB for DDR5 4800Mbps, ≤ 6dB for 7200Mbps)—have their acceptable thresholds at different speed levels. The compliant ranges for each speed level (e.g., 4800Mbps, 5600Mbps, and 7200Mbps for DDR5, and 16GB / s for PCIe 5.0) are clearly defined to provide an authoritative basis for subsequent calculations of deviation rates, out-of-specification scores, and the selection of core enhancement targets.

[0039] In the deviation rate calculation, the deviation rate = (actual value - standard value) / |standard value| × 100% (where "|standard value|" is the absolute value of the standard value, ensuring the denominator is positive); when the actual value > the standard value, the deviation rate is positive, indicating that it exceeds the standard, and the larger the value, the more serious the exceedance; when the actual value ≤ the standard value, the deviation rate ≤ 0, indicating that it meets the standard. For example: the DDR5 protocol specifies that the standard value of the reflection coefficient is ≤ -15dB (absolute value 15dB). If the actual value is -10dB (absolute value 10dB, actual value > standard value), then the deviation rate = (-10 - (-15)) / 15 × 100% = 5 / 15 × 100% ≈ 33.3% (a positive value indicates that it exceeds the standard).

[0040] In the preset deviation weights, based on the degree of impact of the five integrity indicators on the signal integrity of the storage interface (based on signal transmission principles and engineering practices), a fixed deviation weight is preset for each type of indicator (the sum of the weights is 1). For example: transmission loss has the greatest impact on the integrity of high-speed signals, and the weight is set to 0.3; timing offset directly affects sampling reliability, and the weight is set to 0.25; reflection affects signal waveform stability, and the weight is set to 0.2; crosstalk is a secondary interference factor, and the weight is set to 0.15; power supply noise has a relatively weak impact, and the weight is set to 0.1 (the weights can be fine-tuned according to the interface type, such as the weight allocation for DDR and PCIe may be slightly different, but the weights are fixed under the same interface type).

[0041] In the score for exceeding the standard, the score for exceeding the standard = deviation rate × deviation weight.

[0042] S300: Construct a quantization mapping model, configure interface parameters according to the core enhancement target of the interface signal, switch different rates to verify the optimization effect, and output the optimal configuration strategy at each rate.

[0043] In this embodiment, a quantization mapping model is constructed. Based on the core enhancement target of the interface signal, interface parameters are configured accordingly, and the optimization effect is verified by switching between different rates. The optimal configuration strategy at each rate is then output. The specific process is as follows: S301: Calculate the initial configuration parameters of the integrity index at each rate using a quantification formula; S302: The MOPSO algorithm is used to iteratively fine-tune the parameters and optimize the parameter combination. Based on the exceedance scores of the five integrity indicators at each rate, the parameter combination is iteratively adjusted through the MOPSO algorithm to minimize the deviation between the integrity indicators and the protocol standard values. S303: Configure the optimized parameters to the memory chip interface for testing, and switch between different speeds in sequence to collect data on the five integrity indicators after parameter iteration and optimization, and obtain the optimized integrity indicator data; S304: Calculate the optimization achievement rate based on the optimized integrity index data to determine whether the enhancement effect has been achieved; The specific process is as follows: S3041: Using the method for calculating the excess score of the integrity index, calculate the excess score of the optimized integrity index data to obtain the optimized excess score; S3042: Compare the optimized score for exceeding the standard with the score for exceeding the standard before optimization to obtain the optimization achievement rate; S3043: When the optimization achievement rate of the core enhancement target is >90%, and the optimization achievement rate of the other four integrity indicators is >85%, the enhancement effect is achieved; S3044: The optimized parameter combination that meets the standard is used to conduct stability tests on the memory chip under multiple temperature conditions, and 30 sets of data are collected. When the fluctuation range of the integrity index is less than 5%, this optimized parameter combination is listed as the optimal configuration strategy.

[0044] In calculating the achievement rate, the formula for the achievement rate is: ;in, For the first The optimization achievement rate of each indicator is determined by the following criteria: the core enhancement target (the highest priority indicator) at each rate. ≥90%, the other four major indicators A crosstalk rate of ≥85% is considered to be in compliance with the overall standard; if it is not in compliance (e.g., crosstalk Ri=75%), then return to step S302 to adjust the corresponding indicator. The coefficients are used to recalculate the initial parameters and iterate.

[0045] S305: If the enhancement effect is not achieved, continue to optimize and iterate the parameter combination.

[0046] In calculating the initial configuration parameters, the specific configurable soft parameters corresponding to the five major indicators are clearly defined (reflection → ODT level / drive strength; crosstalk → scrambling code enable / channel delay offset value; timing offset → read / write calibration compensation value; power supply noise → dynamic voltage regulation amount / load balancing interval; transmission loss → CTLE gain / pre-emphasis level). Based on the degree of exceedance and sensitivity of each indicator, the initial values ​​of the parameters are calculated through quantitative formulas.

[0047] The core formula is: ; in, The initial values ​​of the parameters corresponding to the target indicators (such as ODT resistance, CTLE gain, calibration compensation value, etc.). These are the baseline values ​​for the parameters at this speed (chip default configuration, such as DDR54800Mbps default ODT=30Ω, CTLE=2dB). The sensitivity coefficients for the indicators are set according to the indicator's responsiveness to parameter adjustments: timing offset k=0.9, transmission loss k=1.0, reflection k=0.8, crosstalk k=0.7, and power supply noise k=0.6. The excess value is (|measured value − target value|, such as a reflection overshoot of 18% VDDQ in the actual measurement and 10% VDDQ in the target, ΔI=8%; a timing offset of 30ps in the actual measurement and 50ps in the target, ΔI=20ps). The target values ​​for the indicators are based on interface protocol standards, such as overshoot ≤10%VDDQ, crosstalk peak ≤100mV, and transmission loss ≤4dB. The maximum adjustable range of the parameters (e.g., ODT is adjustable from 12Ω to 40Ω, ΔPmax=28Ω; CTLE gain is adjustable from 0dB to 8dB, ΔPmax=8dB). Example: Low-speed 4800Mbps reflection enhancement target with overshoot ≤10% VDDQ (measured 18%, ΔI=8%), ODT reference value 30Ω, k=0.8. =28Ω, then =30+0.8×(8% / 10%)×28=30+17.92=47.92Ω, take the 40Ω level supported by the chip as the initial configuration.

[0048] In the iterative fine-tuning of the MOPSO algorithm, the comprehensive optimization deviation of the five major indicators is taken as the objective. The parameter combination is iteratively adjusted through the Multi-Objective Particle Swarm Optimization (MOPSO) algorithm to minimize the deviation between the indicators and the target values. Specifically: in, The weights for the indicators are: transmission loss 0.3, timing offset 0.25, reflection 0.2, crosstalk 0.15, and power supply noise 0.1, with a total weight of 1. To optimize the indicator values, To enhance the target value; The iteration rule is as follows: +1=ω Where ω is the inertia weight, initially 0.9 and decreasing to 0.4; = =2 learning factors; , A random number between 0 and 1; For the optimal position of an individual, The globally optimal position; The position update formula is: +1= + +1; When the fitness function F≤0.1 (or the number of iterations≥20), the iteration is terminated. The specific operation is as follows: for each speed range, adjust the parameter combination → switch the speed (no need to restart, the firmware is dynamically loaded) → collect the five major indicators after optimization → calculate the fitness value and iterate until F reaches the target. For example, the core target of the medium speed range 5600Mbps is the timing offset ≥50ps (the actual measurement is 30ps). After 6 iterations, the read and write calibration compensation value is adjusted to 48ps, the timing offset reaches 53ps, F drops to 0.07, and the iteration stops.

[0049] In this invention, firstly, multi-rate interface integrity indicators are acquired, and the collected data is classified and managed. Secondly, based on the classified multi-rate interface integrity indicators, the correlation between different interface rates and integrity indicators is analyzed, and the core enhancement targets for interface signals at each rate are output. Finally, a quantization mapping model is constructed, and interface parameters are configured specifically according to the core enhancement targets for interface signals. The optimization effect is verified by switching between different rates, and the optimal configuration strategy at each rate is output. By acquiring and classifying integrity indicators at multiple rates, analyzing the correlation between rates and indicators to determine the core enhancement targets, and then configuring parameters through a quantization model based on the targets and iteratively optimizing and verifying them, accurate enhancement of the integrity of memory chip interface signals in multi-rate scenarios is achieved.

[0050] Corresponding to the aforementioned embodiments of the method for enhancing the signal integrity of a multi-rate memory chip interface, this application also provides embodiments of a system for enhancing the signal integrity of a multi-rate memory chip interface.

[0051] Figure 5 This is a block diagram illustrating a multi-rate memory chip interface signal integrity enhancement system according to an exemplary embodiment. (Refer to...) Figure 5 The system may include: an interface metric acquisition module 401, an interface enhancement target output module 402, and an interface configuration strategy output module 403, wherein: The interface indicator acquisition module 401 is used to acquire interface integrity indicators at multiple rates and classify and manage the acquired data. The interface enhancement target output module 402 is used to analyze the correlation between different interface rates and integrity indicators based on the multi-rate interface integrity indicators after acquisition and classification, and output the core enhancement targets of the interface signals at each rate. The interface configuration strategy output module 403 is used to construct a quantization mapping model, configure interface parameters in a targeted manner according to the core enhancement target of the interface signal, switch different rates to verify the optimization effect, and output the optimal configuration strategy at each rate.

[0052] In this embodiment, the interface indicator acquisition module 401 is used to acquire interface integrity indicators at multiple rates and classify and manage the acquired data; the interface enhancement target output module 402 is used to analyze the correlation between different interface rates and integrity indicators based on the acquired and classified multi-rate interface integrity indicators, and output the core enhancement targets for interface signals at each rate; the interface configuration strategy output module 403 is used to construct a quantization mapping model, configure interface parameters in a targeted manner according to the core enhancement targets for interface signals, and switch between different rates to verify the optimization effect, and output the optimal configuration strategy at each rate; by acquiring and classifying integrity indicators at multiple rates, analyzing the correlation between rates and indicators to determine the core enhancement targets, and then configuring parameters through a quantization model and iteratively optimizing and verifying based on the targets, accurate enhancement of the integrity of the memory chip interface signals in multi-rate scenarios is achieved.

[0053] Regarding the system in the above embodiments, the specific ways in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0054] For the system embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0055] Accordingly, this application also provides an electronic device, including: one or more processors; a memory for storing one or more programs; and when the one or more programs are executed by the one or more processors, causing the one or more processors to implement the above-described method for enhancing the signal integrity of a multi-rate memory chip interface. Figure 6 The diagram shown is a hardware structure diagram of any device with data processing capabilities in which a multi-rate memory chip interface signal integrity enhancement system provided by an embodiment of the present invention is located. Except for... Figure 6 In addition to the processor, memory, and network interface shown, any data processing device in the embodiment may also include other hardware depending on the actual function of the data processing device, which will not be described in detail here.

[0056] Accordingly, this application also provides a computer-readable storage medium storing computer instructions thereon, which, when executed by a processor, implement the signal integrity enhancement method for supporting multi-rate memory chip interfaces as described above. The computer-readable storage medium can be an internal storage unit of any data-processing device as described in any of the foregoing embodiments, such as a hard disk or memory. The computer-readable storage medium can also be an external storage device, such as a plug-in hard disk, smart media card (SMC), SD card, flash card, etc., equipped on the device. Furthermore, the computer-readable storage medium can include both internal storage units of any data-processing device and external storage devices. The computer-readable storage medium is used to store the computer program and other programs and data required by the data-processing device, and can also be used to temporarily store data that has been output or will be output.

[0057] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0058] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A method for enhancing the signal integrity of a memory chip interface supporting multiple data rates, characterized in that, The method comprises the following steps: acquiring multi-rate interface integrity indicators, and classifying and managing collected data; based on the classified multi-rate interface integrity indicators after collection, analyzing the correlation between different interface rates and integrity indicators, and outputting interface signal core enhancement targets under each rate; constructing a quantitative mapping model, configuring interface parameters according to the interface signal core enhancement targets, verifying the optimization effect by switching different rates, and outputting optimal configuration strategies under each rate.

2. The method for supporting multiple rate of memory chip interface signal integrity enhancement as recited in claim 1, wherein, In the step of acquiring multi-rate interface integrity indicators and classifying and managing collected data: deploy an interface monitoring device to acquire the integrity indicators of the storage chip interface under the current rate, wherein the integrity indicators include reflection, crosstalk, timing offset, power noise and transmission loss; switch the storage chip interface rate, and acquire the integrity indicators again to obtain the interface integrity indicators under each rate.

3. The method for supporting multiple rate of memory chip interface signal integrity enhancement as recited in claim 2, wherein, In the step of switching the storage chip interface rate, acquiring the integrity indicators again, and obtaining the interface integrity indicators under each rate: modify the interface rate parameters through a firmware configuration tool and save them, normally restart the running device carrying the storage chip, and after the device completes initialization and rate configuration loading is successful, collect the interface integrity indicators under the rate again.

4. The method for supporting multiple rate of memory chip interface signal integrity enhancement of claim 3, wherein, After the step of switching the storage chip interface rate, acquiring the integrity indicators again, and obtaining the interface integrity indicators under each rate: classify according to different rate gears of the storage chip interface, and classify and store the signal integrity indicator data collected under the corresponding rate.

5. The method for supporting multiple rate of memory chip interface signal integrity enhancement of claim 4, wherein, In the step of analyzing the correlation between different interface rates and integrity indicators based on the classified multi-rate interface integrity indicators after collection, and outputting interface signal core enhancement targets under each rate: use a linear regression model to analyze the change law between each rate and each integrity indicator; compare the actual value of each type of integrity indicator under each rate with the protocol standard value based on the storage interface protocol standard, and calculate the deviation rate; preset a deviation weight for the deviation rate of each type of integrity indicator, and calculate the over-standard score of each type of integrity indicator based on the deviation weight and the deviation rate; select the highest over-standard score under each rate as the core enhancement target.

6. The method for supporting multiple rate of memory chip interface signal integrity enhancement of claim 5, wherein, Before the step of analyzing the correlation between different interface rates and integrity indicators based on the classified multi-rate interface integrity indicators after collection, and outputting interface signal core enhancement targets under each rate: extract features from the classified multi-rate integrity indicators, eliminate abnormal data, and perform standardization conversion.

7. The method for supporting multiple rate of memory chip interface signal integrity enhancement of claim 6, wherein, In the step of constructing a quantitative mapping model, configuring interface parameters according to the interface signal core enhancement targets, verifying the optimization effect by switching different rates, and outputting optimal configuration strategies under each rate: calculate the initial configuration parameters of the integrity indicators under each rate through a quantitative formula; use the MOPSO algorithm to iteratively fine-tune the parameters and optimize the parameter combination; test the storage chip interface by configuring the optimized parameters, switch each rate in turn, collect data of the five integrity indicators after parameter iteration optimization, and obtain the optimized integrity indicator data; calculate the optimization achievement rate according to the optimized integrity indicator data to determine whether the enhancement effect is achieved. If the enhancement effect is not achieved, continue to optimize the iteration parameter combination.

8. The method for supporting multiple rate of memory chip interface signal integrity enhancement of claim 7, wherein, In the step of adopting the MOPSO algorithm to iteratively fine-tune parameters and optimize the parameter combination: According to the exceeding score of the five integrity indicators at each rate, the parameter combination is iteratively adjusted by the MOPSO algorithm to minimize the deviation of the integrity indicators from the protocol standard values.

9. The method for supporting multiple rate of memory chip interface signal integrity enhancement of claim 8, wherein, In the step of calculating the optimization achievement rate according to the optimized integrity indicator data and determining whether the enhancement effect is achieved: The exceeding score of the optimized integrity indicator data is calculated using the exceeding score calculation method of the integrity indicators, and the optimized exceeding score is obtained. The optimized exceeding score is compared with the pre-optimization exceeding score to obtain the optimization achievement rate. When the optimization achievement rate of the core enhancement target is > 90%, and the optimization achievement rates of the remaining four integrity indicators are > 85%, the enhancement effect is achieved.

10. The method for supporting multiple rate of a memory chip interface signal integrity enhancement of claim 9, wherein, After the step of achieving the enhancement effect when the optimization achievement rate of the core enhancement target is > 90%, and the optimization achievement rates of the remaining four integrity indicators are > 85%: The optimized parameter combination that meets the standard is used for stability testing of the memory chip under multiple temperature conditions, and 30 groups of data are collected. When the integrity indicator swing is < 5%, the optimized parameter combination is listed as the optimal configuration strategy.

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