Tracking accesses to memory using ring buffer structure

Abstract

The invention relates to tracking accesses to a memory using a ring buffer structure. In some embodiments, a memory system controller may receive a memory access request from a host system. A memory system controller may store an identifier associated with a memory access request in a ring buffer structure. The memory system controller may determine whether the data structure contains an entry associated with the identifier. The memory system controller may perform one of updating the memory access counter stored at the entry when the data structure does contain the entry, or creating an entry in the data structure and initializing the memory access counter stored at the entry when the data structure does not contain the entry. The memory system controller may receive a request from the host system to read the data structure and / or may transmit an indication of a respective identifier and a respective memory access counter for each entry with a respective flag setting to the host system based on the request.

Description

Technical Field

[0001] This disclosure generally relates to memory systems, memory system operations, and, for example, to using a circular buffer structure to track accesses to memory. Background Technology

[0002] Memory devices are widely used to store information in various electronic devices. A memory device comprises memory cells. A memory cell is an electronic circuit that can be programmed into a data state of two or more data states. For example, a memory cell can be programmed to represent a single binary value (typically represented by a binary "1" or binary "0"). As another example, a memory cell can be programmed to represent a small value (e.g., 0.5, 1.5, or similar). To store information, an electronic device can write to or program a set of memory cells. To access the stored information, the electronic device can read from or sense the stored state of the set of memory cells.

[0003] Various types of memory devices exist, including Random Access Memory (RAM), Read-Only Memory (ROM), Dynamic RAM (DRAM), Static RAM (SRAM), Synchronous Dynamic RAM (SDRAM), Ferroelectric RAM (FeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Holographic RAM (HRAM), Flash memory (such as NAND and NOR memory), and others. Memory devices can be volatile or non-volatile. Non-volatile memory (such as flash memory) can store data for extended periods, even without external power. Volatile memory (such as DRAM) loses stored data over time unless refreshed by power. In some instances, memory devices may be associated with the Compute Fast Link (CXL) protocol and / or CXL-compatible memory systems. Summary of the Invention

[0004] On one hand, this disclosure provides a memory system comprising: one or more components configured to: receive from a host system a memory access request associated with a memory of the memory system; store an identifier associated with the memory access request in a circular buffer structure; determine whether a data structure associated with the circular buffer structure contains an entry associated with the identifier; and perform one of the following: updating a memory access counter stored at the entry in response to determining that the data structure contains the entry, or creating the entry in the data structure and initializing the memory access counter stored at the entry in response to determining that the data structure does not contain the entry.

[0005] On the other hand, this disclosure further provides a method comprising: receiving, by a memory system controller, a memory access request associated with memory of a memory system from a host system; storing, by the memory system controller, an identifier associated with the memory access request in a circular buffer structure; determining, by the memory system controller, whether a data structure associated with the circular buffer structure contains an entry associated with the identifier; and performing, by the memory system controller, one of the following: updating a memory access counter stored at the entry in response to determining that the data structure contains the entry, or creating the entry in the data structure and initializing the memory access counter stored at the entry in response to determining that the data structure does not contain the entry. Attached Figure Description

[0006] Figure 1 This is a diagram illustrating an instance system that can use a circular buffer structure to track accesses to memory.

[0007] Figure 2 This is a diagram illustrating another instance of a system that can use a circular buffer structure to track accesses to memory.

[0008] Figure 3A to 3G It is a graph that uses a circular buffer structure to track instances of memory access.

[0009] Figure 4 This is a flowchart of an instance method associated with using a circular buffer structure to track accesses to memory. Detailed Implementation

[0010] Properly managing memory resources can be crucial for maintaining the performance and scalability of efficient memory systems, such as in large data center operations or similar scenarios. In some instances, memory-based applications require high memory capacity, driving the development of tiered memory system topologies and similar memory solutions. These tiered memory system topologies and / or similar solutions combine dynamic random access memory (DRAM) with high-capacity volatile memory and slower non-volatile memory to balance cost and performance. For example, an emerging standard called Compute Fast Link (CXL) facilitates advanced memory configurations by enabling scalable interconnects that allow for efficient resource sharing and system-level optimization.

[0011] However, as system architectures evolve, effectively managing these complex memory hierarchies remains a challenge. Specifically, optimizing memory utilization by strategically placing "hot" (e.g., frequently accessed) and "cold" (e.g., infrequently accessed) memory pages has become a focus for reducing the total cost of ownership (TCO) and / or enhancing memory system performance. Identifying hot and cold pages may be necessary to enable intelligent data migration within tiered memory systems, thereby helping to improve user experience and accommodate workloads such as artificial intelligence (AI), machine learning (ML), analytics, and / or high-performance computing (HPC), as well as other instances.

[0012] Existing technologies for identifying and managing hot and cold pages face certain limitations. Software-based approaches (such as those at the operating system (OS) and / or hypervisor level) typically require complex, dedicated tuning, presenting challenges in scalability and resulting in trade-offs between identification resolution and performance impact. On the other hand, hardware-based analytics and sampling methods can impact central processing unit (CPU) performance. Therefore, in the ever-growing and diversifying context of data center environments, these methods may not provide the optimal solution for dynamic and efficient memory access monitoring.

[0013] Some implementations described herein improve the management of memory resource utilization in data center operations and / or other applications through queue-based hot data detection mechanisms (e.g., queue-based hot data detection mechanisms within CXL-compatible memory systems or similar memory systems). In some implementations, a memory system controller (e.g., a CXL controller and / or a CXL application-specific integrated circuit (ASIC) and other instances) may receive memory access requests (e.g., from a host system, such as a CXL host or similar host system), and the memory system controller may align the request with an identifier (ID) (sometimes referred to herein as a page ID) and / or store the ID along with the request in a circular buffer structure. In some implementations, the memory system controller may maintain a data structure separate from the circular buffer structure (sometimes referred to herein as a hot list), for example, to store access counters (e.g., hot counters) associated with various page IDs. In such implementations, the memory system controller may determine whether the data structure associated with the circular buffer contains an existing entry for the page ID associated with the incoming request. If the data structure contains an existing entry for the page ID, the memory system controller may update (e.g., increment) the memory access counter for the existing entry accordingly. On the other hand, if the data structure does not contain existing entries, the memory system controller can create a new entry for the page ID in the data structure, and the memory system controller can initialize the memory access counter at the new entry (e.g., set it to 1). In some implementations, after updating the memory access counter corresponding to the page ID in the data structure (e.g., a hot list), the memory system controller can determine whether the memory access counter meets a threshold (sometimes referred to herein as a hot threshold). If the threshold is met, the memory system controller can set a bit (sometimes referred to herein as a hot flag) in the entry to indicate that the corresponding memory location is hot, and / or the memory system controller can periodically transmit an indication to the host system of any pages for which a hot flag has been set.

[0014] In this way, the techniques described herein achieve memory resource savings by facilitating intelligent memory access tracking and hot data identification with minimal processing overhead. A deterministic approach to the memory system controller ensures that the heat of all memory access requests is assessed, which optimizes memory page prioritization and placement. In some implementations, a queue-based approach reduces latency and / or improves the efficiency of handling frequent memory accesses, thereby reducing the overall memory footprint and / or lowering the costs associated with memory resources in a tiered memory architecture. In some implementations, by improving the efficiency of memory utilization and page management, the techniques described herein alleviate the need for additional memory capacity expansion, leading to more sustainable data center environments and optimized resource allocation for high-demand applications such as AI, ML, analytics, and / or HPC workloads, as well as other instances. The techniques described herein achieve this functional performance without imposing additional computational burden on the host system, reflecting advancements in memory technology that support growing scalability needs and ensure reduced TCO for data center operations and / or similar applications.

[0015] Figure 1 This diagram illustrates an example system 100 capable of using a circular buffer structure to track access to memory. System 100 may include one or more means, devices, and / or components for performing the operations described herein. System 100 may include a host system 105 and a memory system 110. Memory system 110 may include a memory system controller 115 and one or more memory devices 120, shown as memory devices 120-1 to 120-N (where N≥1). Memory devices may include a local controller 125 and one or more memory arrays 130. Host system 105 may communicate with memory system 110 (e.g., memory system controller 115 of memory system 110) via a host interface 140. Memory system controller 115 and memory devices 120 may communicate via corresponding memory interfaces 145 (shown as memory interfaces 145-1 to 145-N (where N≥1)).

[0016] System 100 can be any electronic device configured to store data in memory. For example, system 100 can be a computer, mobile phone, wired or wireless communication device, network device, server, device in a data center, device in a cloud computing environment, vehicle (e.g., car or airplane), and / or Internet of Things (IoT) device. Host system 105 may include host processor 150. Host processor 150 may include one or more processors configured to execute instructions and store data in memory system 110. For example, host processor 150 may include a CPU, graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and / or another type of processing component.

[0017] The memory system 110 can be any electronic device or apparatus configured to store data in memory. For example, the memory system 110 can be a hard disk drive, a solid-state drive (SSD), a flash memory system (such as a NAND flash memory system or a NOR flash memory system), a universal serial bus (USB) drive, a memory card (such as a secure digital card (SD) card), an auxiliary storage device, a non-volatile memory fast (NVMe) device, an embedded multimedia card (eMMC) device, a dual in-line memory module (DIMM), a CXL memory module, and / or a random access memory (RAM) device, such as a dynamic RAM (DRAM) device or a static RAM (SRAM) device.

[0018] The memory system controller 115 may be any device configured to control the operation of the memory system 110 and / or the operation of the memory device 120. For example, the memory system controller 115 may include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some embodiments, the memory system controller 115 may communicate with the host system 105 and may instruct one or more memory devices 120 regarding memory operations performed by these memory devices 120 based on one or more instructions from the host system 105. For example, the memory system controller 115 may provide instructions to a local controller 125 regarding memory operations performed by the local controller 125 in conjunction with corresponding memory devices 120.

[0019] Memory device 120 may include a local controller 125 and one or more memory arrays 130. In some embodiments, memory device 120 includes a single memory array 130. In some embodiments, each memory device 120 of memory system 110 may be implemented in a separate semiconductor package or on a separate die, the die including the corresponding local controller 125 and corresponding memory array 130 of that memory device 120. Memory system 110 may include multiple memory devices 120.

[0020] Local controller 125 may be any device configured to control memory operations of memory device 120 containing local controller 125 (e.g., without controlling memory operations of other memory devices 120). For example, local controller 125 may include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, a CXL controller connected to DRAM, and / or one or more processing components. In some embodiments, local controller 125 may communicate with memory system controller 115 and may control operations performed on memory array 130 coupled to local controller 125 based on one or more instructions from memory system controller 115. As an example, memory system controller 115 may be an SSD controller, and local controller 125 may be a NAND controller.

[0021] Memory array 130 may include an array of memory cells configured to store data. For example, memory array 130 may include a non-volatile memory array (e.g., a NAND memory array or a NOR memory array) or a volatile memory array (e.g., an SRAM array or a DRAM array). In some embodiments, memory system 110 may include one or more volatile memory arrays 135. Volatile memory array 135 may include SRAM arrays and / or DRAM arrays, and other examples. One or more volatile memory arrays 135 may be included in memory system controller 115, one or more memory devices 120, and / or both memory system controller 115 and one or more memory devices 120. In some embodiments, memory system 110 may include both non-volatile memory capable of retaining stored data after power failure of memory system 110 and volatile memory (e.g., volatile memory array 135) requiring power to retain stored data and losing stored data after power failure of memory system 110. For example, the volatile memory array 135 may cache data read from or written to non-volatile memory, and / or may cache instructions executed by the controller of the memory system 110.

[0022] Host interface 140 enables communication between host system 105 (e.g., host processor 150) and memory system 110 (e.g., memory system controller 115). Host interface 140 may include, for example, a Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Fast (PCIe) interface, NVMe interface, USB interface, Universal Flash Storage (UFS) interface, eMMC interface, Double Data Rate (DDR) interface, DIMM interface, and / or CXL interface (e.g., PCIe / CXL interface, hereinafter referred to in conjunction with...). Figure 2 (More detailed description).

[0023] Memory interface 145 enables communication between memory system 110 and memory device 120. Memory interface 145 may include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Alternatively, memory interface 145 may include a volatile memory interface (e.g., for communicating with volatile memory), such as a DDR interface.

[0024] Although the above-described example memory system 110 includes a memory system controller 115, in some embodiments, the memory system 110 does not include a memory system controller 115. For example, an external controller (e.g., included in host system 105) and / or one or more local controllers 125 included in one or more corresponding memory devices 120 may perform the operations described herein as being performed by the memory system controller 115. Furthermore, as used herein, "controller" may refer to memory system controller 115, local controller 125, or external controller. In some embodiments, a set of operations described herein as being performed by a controller may be performed by a single controller. For example, the entire set of operations may be performed by a single memory system controller 115, a single local controller 125, or a single external controller. Alternatively, a set of operations described herein as being performed by a controller may be performed by more than one controller. For example, a first subset of operations may be performed by memory system controller 115 and a second subset of operations may be performed by local controller 125. Furthermore, depending on the context, the term "memory device" may refer to memory system 110 or memory device 120.

[0025] A controller (e.g., memory system controller 115, local controller 125, or external controller) can control operations performed on memory (e.g., memory array 130), such as by executing one or more instructions. For example, memory system 110 and / or memory device 120 may store one or more instructions as firmware in memory, and the controller may execute these instructions. Alternatively, the controller may receive one or more instructions from host system 105 and / or from memory system controller 115, and may execute these instructions. In some embodiments, a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory) may store a set of instructions (e.g., one or more instructions or codes) for execution by the controller. The controller may execute the set of instructions to perform one or more operations or methods described herein. In some embodiments, execution of the set of instructions by the controller causes the controller, memory system 110, and / or memory device 120 to perform one or more operations or methods described herein. In some embodiments, a hardwired circuit system is used in place of or in combination with one or more instructions to perform one or more operations or methods described herein. Alternatively or concurrently, the controller may be configured to perform one or more operations or methods described herein. Instructions are sometimes referred to as “commands”.

[0026] For example, a controller (e.g., memory system controller 115, local controller 125, or external controller) may transmit signals to and / or receive signals from a memory (e.g., one or more memory arrays 130) based on one or more instructions, such as transferring (e.g., writing or programming) data to all or part of the memory (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes), transferring (e.g., reading) data from all or part of the memory, erasing all or part of the memory, and / or refreshing all or part of the memory. Alternatively or additionally, the controller may be configured to control access to the memory and / or provide a translation layer (e.g., for mapping logical addresses to physical addresses of the memory array 130) between the host system 105 and the memory. In some embodiments, the controller may translate host interface commands (e.g., commands received from the host system 105) into memory interface commands (e.g., commands for performing operations on the memory array 130).

[0027] In some implementation schemes, Figure 1One or more systems, apparatuses, devices, components, and / or controllers may be configured to: receive from a host system a memory access request associated with the memory of a memory system; store an identifier associated with the memory access request in a circular buffer structure; determine whether a data structure associated with the circular buffer structure contains an entry associated with the identifier; and perform one of the following: updating a memory access counter stored at the entry in response to determining that the data structure contains an entry, or creating an entry in the data structure and initializing the memory access counter stored at the entry in response to determining that the data structure does not contain an entry.

[0028] In some implementation schemes, Figure 1 One or more systems, apparatuses, devices, components, and / or controllers may be configured to: receive a CXL.mem request associated with a memory of a CXL-compatible memory system from a host system; store the page ID associated with the CXL.mem request in a ring buffer structure; determine whether a hot list associated with the ring buffer structure contains an entry associated with the page ID; and perform one of the following: updating a heat counter stored at the entry in response to determining that the hot list contains an entry, or creating an entry in the hot list and initializing a heat counter stored at the entry in response to determining that the hot list does not contain an entry.

[0029] Figure 1 The number and arrangement of components shown are for illustrative purposes only. In reality, the actual number and arrangement of components are... Figure 1 Compared to the components shown, there may be additional components, fewer components, different components, or components arranged differently. Furthermore, Figure 1 The two or more components shown can be implemented within a single component, or Figure 1 The single component shown can be implemented as multiple distributed components. Alternatively, Figure 1 The set of components shown (e.g., one or more components) can be described as being by Figure 1 The other set of components shown in the diagram performs one or more operations.

[0030] Figure 2This is a diagram illustrating another example of a system 200 capable of using a circular buffer structure to track access to memory. System 200 may include one or more means, devices, and / or components for performing the operations described herein. In some instances, system 200 may be associated with CXL standards and / or protocols (e.g., system 200 may utilize the CXL protocol to communicate between a host device (sometimes referred to as a CXL-compatible host or simply a CXL host) and a memory system (sometimes referred to as a CXL-compatible memory system or simply a CXL memory system). In this regard, system 200 may include a CXL host 202 (which may correspond to host system 105) and a CXL-compatible memory system 204 (which may correspond to memory system 110). CXL host 202 and CXL-compatible memory system 204 may communicate via an interface 203 (e.g., host interface 140), which may include a CXL bus 208 (e.g., a PCIe / CXL interface) and other instances.

[0031] In some instances, the CXL-compliant memory system 204 may be a system compliant with the CXL standard and / or protocol, for example, for communicating with one or more host devices (e.g., CXL-compliant hosts, such as CXL host 202). CXL is an open standard that enables high-speed CPU-to-device and CPU-to-memory interconnects designed to accelerate next-generation performance. The CXL standard enables memory coherence between the CPU memory space and the memory on the attached device, allowing resource sharing to improve performance, reduce software stack complexity, and lower overall system cost. CXL is designed as an industry-open standard for implementing high-speed communication interfaces. CXL technology leverages the PCIe infrastructure, thereby utilizing the PCIe physical and electrical interfaces to provide regional high-level protocols, such as input / output (I / O) protocols, memory protocols, and coherence interfaces.

[0032] In some instances, system 200 may include a PCIe / CXL interface (e.g., a CXL bus 208 may be associated with the PCIe / CXL interface), which may be a physical interface configured to connect CXL-compatible memory system 204 to a CXL-compatible host device (e.g., CXL host 202). In such instances, the PCIe / CXL interface may conform to the CXL standard specification for physical connectivity, thereby ensuring broad compatibility and ease of integration into existing systems using the CXL protocol. Alternatively, CXL-compatible memory system 204 may be designed to efficiently interface with computing systems (e.g., CXL host 202 and / or host system 105) by utilizing the CXL protocol. For example, CXL-compatible memory system 204 may be configured to utilize the high-speed, low-latency interconnect capabilities of CXL, for example, to make CXL-compatible memory system 204 suitable for high-performance computing, data center applications, artificial intelligence (AI) applications, and / or similar applications.

[0033] In some instances, the CXL-compatible memory system 204 may include a CXL memory system controller (e.g., a CXL ASIC, which may correspond to memory system controller 115 and / or local controller 125) that can be configured to manage data flow between a memory array (shown as CXL device attached memory 218, which may correspond to volatile memory array 135 and / or memory array 130) and a CXL interface (e.g., CXL bus 208). In some instances, the CXL memory system controller may be configured to handle one or more CXL protocol layers, such as I / O layers (e.g., layers associated with the CXL.io protocol, which may be used for purposes such as device discovery, configuration, initialization, I / O virtualization, direct memory access (DMA) using non-uniform load memory semantics, and / or similar purposes), cache coherence layers (e.g., layers associated with the CXL.cache protocol, which may be used for purposes such as caching host memory using Modified, Exclusive, Shared, Invalid (MESI) coherence protocols, or similar purposes), or memory protocol layers (e.g., layers associated with the CXL.memory (sometimes referred to as CXL.mem) protocol, which may enable CXL memory devices to expose host-managed device memory (HDM) to allow host devices to manage and access memory similar to native DDR connected to the host), and other instances.

[0034] CXL-compatible memory system 204 may further include and / or be associated with one or more high-bandwidth memory modules (HBMMs) or similar memory arrays (e.g., CXL device attached memory 218). For example, CXL-compatible memory system 204 may include multilayer DRAM (e.g., stacked and / or interconnected via advanced through-silicon via (TSV) technology) to maximize storage density and / or increase data transfer speeds between memory layers. Alternatively, CXL-compatible memory system 204 (e.g., a CXL ASIC of CXL-compatible memory system 204) may include a power management unit configured to regulate power consumption associated with CXL-compatible memory system 204 and / or configured to improve the energy efficiency of CXL-compatible memory system 204. Alternatively, CXL-compatible memory system 204 (e.g., a CXL ASIC of CXL-compatible memory system 204) may include additional components, such as one or more error correction code (ECC) engines, for example for detecting and / or correcting data errors to ensure data integrity and / or improve the overall reliability of CXL-compatible memory system 204. The CXL-compatible memory system 204 can be implemented using a combination of hardware and firmware blocks and / or components. In such instances, the firmware can execute on one or more embedded CPUs within the CXL-compatible memory system 204.

[0035] Alternatively or concurrently, the CXL-compatible memory system 204 and / or its CXL memory system controller (e.g., a CXL ASIC) may include CXL host interface hardware 210, I / O path hardware logic and DMA controller 212, master management subsystem 214 and / or host interface (HIF) management subsystem 216, and other instances. In some instances, the CXL host interface hardware 210 may be a hardware component that enables physical connectivity between the CXL-compatible memory system 204 and one or more external devices, such as via the CXL bus 208 to the CXL host 202. In some instances, the CXL host interface hardware 210 may include the necessary physical interfaces and protocol logic required to establish and / or maintain communication via a CXL link (e.g., via the CXL bus 208). In some cases, the CXL host interface hardware 210 may ensure that the CXL host 202 can efficiently access and / or control the CXL-compatible memory system 204.

[0036] The I / O path hardware logic and DMA controller 212 handles data transfers between the CXL-compatible memory system 204 and external devices (such as other memory modules and / or peripheral components). In some instances, the DMA controller portion of the I / O path hardware logic and DMA controller 212 allows for efficient data transfers without directly involving the CPU of the CXL-compatible memory system 204. In other words, the DMA controller portion of the I / O path hardware logic and DMA controller 212 manages data movement between the CXL-compatible memory system 204 and other system components, which can improve overall system performance by offloading data transfer tasks from the CPU.

[0037] The main management subsystem 214 can serve as the central control and management unit within the CXL-compatible memory system 204. In some instances, the main management subsystem 214 may encompass various functionalities and tasks, such as memory access control, error detection and / or correction, power management, and / or similar system management functionalities and / or tasks. Alternatively or concurrently, the main management subsystem 214 may ensure the proper operation and / or reliability of the CXL-compatible memory system 204 and / or optimize the performance of the CXL-compatible memory system 204 under various operating conditions.

[0038] HIF management subsystem 216 is responsible for managing and / or controlling CXL host interface hardware 210 and other tasks. In some instances, HIF management subsystem 216 may handle tasks related to link initialization configuration negotiation with CXL host 202, error handling, and / or other protocol-specific functionalities. Alternatively, HIF management subsystem 216 may ensure smooth communication between CXL-compatible memory system 204 and / or CXL host 202, for example, by maintaining CXL link compatibility and / or reliability, and other instances.

[0039] In some instances, the CXL-compatible memory system 204 can be classified as a CXL 1 device, a CXL 2 device, or a CXL 3 device. A CXL 1 device can be a device that implements a coherent cache using the CXL.cache protocol. A CXL 2 device can be a device that implements a coherent cache using the CXL.cache protocol and host-managed device memory using the CXL.mem protocol. For example, a CXL 2 device can be a hardware accelerator device. A CXL 3 device can be a device that implements host-managed device memory using the CXL.mem protocol. For example, a CXL 3 device can be a memory expander device.

[0040] Figure 2 The number and arrangement of components shown are for illustrative purposes only. In reality, the actual number and arrangement of components are... Figure 2 Compared to the components shown, there may be additional components, fewer components, different components, or components arranged differently. Furthermore, Figure 2 The two or more components shown can be implemented within a single component, or Figure 2 The single component shown can be implemented as multiple distributed components. Alternatively, Figure 2 The set of components shown (e.g., one or more components) can be described as being by Figure 2 The other set of components shown in the diagram performs one or more operations.

[0041] Figure 3A to 3G This is a graph of instance 300 that uses a circular buffer structure to track memory accesses. Combined with... Figure 3A to 3G The described operations can be performed by memory system 110 and / or one or more components of memory system 110 (e.g., memory system controller 115, one or more memory devices 120 and / or one or more local controllers 125) and / or CXL-compatible memory system 204 and / or one or more components of CXL-compatible memory system 204 (e.g., main management subsystem 214, CXL device attached memory 218 and / or one or more local controllers associated with CXL device attached memory 218).

[0042] like Figure 3AAs shown, Example 300 includes a memory system (not shown in connection with Example 300 for ease of description, but in some embodiments it corresponds to memory system 110 and / or CXL-compatible memory system 204) that receives memory access requests 302 (e.g., CXL.mem requests, such as read requests, write requests, and / or similar requests) from a host system (not shown in connection with Example 300 for ease of description, but in some embodiments it corresponds to host system 105 and / or CXL host 202). Upon receiving a memory access request 302, the memory system may associate the request with a portion of memory in the memory system (e.g., a portion of memory to be written to and / or read from), for example by aligning the request with an identifier (e.g., a page ID) according to the configuration tracking granularity. In other words, an incoming memory access request (which is sometimes referred to herein as an incoming device physical address (DPA), where the DPA corresponds to a portion of memory that can be accessed by the memory system controller during a single memory access) may be aligned with a page ID corresponding to the configuration tracking granularity. In this regard, in embodiments where the memory system is configured to track memory accesses at a granularity equal to or greater than the DPA, the memory system can align each incoming memory access request with a single page ID. In embodiments where the memory system is configured to track memory accesses at a granularity less than the DPA, the memory system can align each incoming memory access request with multiple page IDs.

[0043] In some implementations, the memory system may use a circular buffer structure 304 to track memory accesses. In other words, the memory system may use the circular buffer structure 304 to store page IDs associated with incoming memory access requests (e.g., memory access request 302 and / or similar requests), wherein the circular buffer structure 304 includes multiple portions 306 ( Figure 3A The first part is shown as 306-1 to sixteenth part as 306-16, but may include more or fewer parts in other embodiments. In such embodiments, each page ID associated with memory access request 302 may be stored in a circular buffer structure 304, and more specifically, in a corresponding part 306 of the circular buffer structure 304.

[0044] In some implementations, the circular buffer structure 304 may be managed using one or more pointers (sometimes referred to herein as cursors), including a memory access pointer 308 (sometimes referred to herein as a DPA tracking pointer and / or cursor) and a data structure pointer 310 (sometimes referred to herein as a hot list tracking pointer and / or cursor), and other instances. The memory access pointer 308 and / or the data structure pointer 310 may begin at a start position 312 and / or may move around the circular buffer structure 304 as page IDs are added to the circular buffer structure 304 (more specifically, to the corresponding portion 306 of the circular buffer structure 304) and / or as a data structure 314 (e.g., a hot list) is used to track page IDs stored in the circular buffer structure 304. In this way, at any given time, the memory access pointer 308 can point to the first available entry (e.g., section 306) in the circular buffer structure 304 for storing the current page ID (e.g., the page ID associated with the incoming memory access request 302) and / or the data structure pointer 310 can point to the last element scanned to construct the data structure 314 (e.g., a hot list). In other words, the memory access pointer 308 can be used to identify the next available entry in the circular buffer structure 304 for the incoming page ID associated with the memory access request, and / or the data structure pointer 310 can be used to indicate the most recently analyzed section in the circular buffer structure 304 containing page IDs that have been scanned, counted, and added to the data structure 314.

[0045] As indicated by the arrow pointed to by reference numeral 316, when a memory access request 302 is received at the memory system, the page ID occurrence rate can be counted and stored in a fully associative structure (e.g., data structure 314), which may contain multiple entries, such as one of each of the multiple page IDs being tracked. In such embodiments, each entry may contain an associated page ID, a memory access counter (sometimes referred to herein as a heat counter), and / or a flag (sometimes referred to herein as a hot flag). In such embodiments, the memory access counter may correspond to the number of accesses to the page ID indicated in the entry during a given time period (sometimes referred to herein as an epoch), and / or the flag may be a 1-bit flag used to identify whether the number of accesses to a portion of memory corresponding to the page ID meets a threshold (e.g., a heat threshold). That is, the hot flag may be a 1-bit flag used to identify whether the corresponding page ID is hot. In such implementations, each time the memory access counter is updated in a given entry, the memory access counter can be compared with a threshold (e.g., a heat threshold), and if the memory access counter meets the threshold, then the corresponding flag (e.g., the corresponding heat flag) can be set to "1".

[0046] In this regard, for a given incoming memory access request 302, the memory system can align the DPA with the page ID and store the page ID in portion 306 of the circular buffer structure 304 pointed to by the memory access pointer 308. Then, as the data structure pointer 310 advances to this specific portion 306 of the circular buffer structure 304, the memory system can determine whether the data structure 314 (e.g., a hot list) already has an entry corresponding to the page ID associated with the memory access request 302. If the entry already exists in the data structure 314, the memory system can update (e.g., increment) the corresponding memory access counter stored at the entry. On the other hand, if no entry exists, the memory system can create a new entry in the data structure 314 and / or initialize the value of the memory access counter in the newly created entry (e.g., set the memory access counter to 1).

[0047] In some implementations, the host system can configure the memory system using certain parameters associated with using the circular buffer structure 304 and / or data structure 314 to track memory accesses. For example, the host system can selectively use the circular buffer structure 304 and / or data structure 314 to enable memory access tracking, and the host system can set an aging factor and / or epoch duration (hereinafter combined with) associated with the circular buffer structure 304 and / or data structure 314. Figure 3G (In more detail), the host system can set the tracking granularity associated with the circular buffer structure 304 and / or data structure 314 (e.g., tracking granularity for aligning incoming DPAs with page IDs, and other instances), the host system can set the type of memory request to track (e.g., read and / or write requests, and other instances), the host system can set thresholds associated with memory access counters (e.g., hot thresholds) in the data structure, and / or the host system can configure other settings associated with the circular buffer structure 304 and / or data structure 314. Additional aspects of the circular buffer structure 304 and data structure 314 will be discussed below. Figure 3B to 3G Describe it.

[0048] More specifically, Figure 3B and 3C This demonstrates how a memory system can track incoming access requests immediately after the initialization of the circular buffer structure 304 and / or data structure 314 (e.g., when portion 306 of the circular buffer structure 304 has not yet stored any page IDs and / or when data structure 314 has not yet stored any entries and / or associated memory access counters). Figure 3BAs shown, at this point in time, the memory access pointer 308 (which points to the first available portion 306 of the circular buffer structure 304 used to store page IDs) may point to the first portion 306-1 of the circular buffer structure 304 because the circular buffer structure 304 has not yet been used to track memory accesses and therefore the page IDs have not yet been stored in the circular buffer structure 304. Furthermore, the data structure pointer 310 (which points to the last portion 306 scanned to build the data structure) may point to the start position 312 and / or may not point to any portion 306 of the circular buffer structure 304 because no memory accesses have yet been added to the data structure 314.

[0049] In some implementations, the memory system can then receive data from the host system from the DPA (e.g., Figure 3B DPA in the examples described K The memory system can process the received memory access request 318 (e.g., a CXL.mem request), for example, by aligning (e.g., converting) the DPA to the corresponding page ID (e.g., page ID). K In addition, such as Figure 3C As shown and as indicated by arrow 320, the memory system may be located as indicated by arrow 320 (e.g., the first portion 306-1 of the circular buffer structure 304, as described above). Figure 3B The time point at which the memory access request 318 is received (as described) will be the page ID (e.g., page ID). K The data is stored in portion 306 of the circular buffer structure pointed to by memory access pointer 308. The memory system can then advance memory access pointer 308 so that it points to the next available portion 306 of the circular buffer structure (e.g., the second portion 306-2 of circular buffer structure 304, such as...). Figure 3C (As shown in the diagram). In other words, after the DPA is converted to the corresponding page ID (e.g., by application configuration tracking granularity) and / or stored in a portion 306 of the circular buffer structure 304 pointed to by the memory access pointer 308, the memory access pointer 308 can be incremented so that it points to the next portion 306 of the circular buffer structure 304. In embodiments where the memory system is configured to track only a certain type of memory access (e.g., read-only access or write-only access), if the incoming memory access request 318 is associated with a memory access type that will not be tracked, then the memory system may omit aligning the DPA with the page ID and / or storing the corresponding page ID in a portion 306 of the circular buffer structure 304.

[0050] Furthermore, the memory system can be configured to periodically check the page IDs stored in the circular buffer structure and / or accordingly create or update the corresponding entries for the page IDs in data structure 314 (e.g., a hot list). For example, when a page ID is inserted into the circular buffer structure 304, the memory system can check data structure 314 to determine if the page ID exists in data structure 314 (e.g., check if the hot list already contains an entry associated with the page ID). If an entry associated with the page ID already exists in data structure 314 (sometimes referred to herein as a "hit"), then the memory access counter (e.g., a hot counter) in the corresponding entry can be updated (e.g., incremented by 1). However, if an entry corresponding to the page ID does not exist in data structure 314 (sometimes referred to herein as a "miss"), for example, in... Figure 3C In the example shown, a new entry can be created in the data structure, and / or the memory system can store the page ID in the new entry, initialize the corresponding memory access counter in the new entry (e.g., set to 1), and / or initialize the corresponding hot flag in the new entry (e.g., set to 0), as indicated by arrow 322. The memory system can then compare the memory access counter with a configuration threshold (e.g., a configuration hotness threshold). If the memory access counter meets the threshold, the hot flag can be set to 1, indicating that the corresponding page ID is "hot". On the other hand, if the memory access counter does not meet the threshold, the hot flag can be set to 0, indicating that the corresponding page ID is not "hot". Alternatively, after processing a given portion 306 of the circular buffer structure 304 (e.g., after scanning portion 306 of the circular buffer structure 304 and updating the corresponding entry in the data structure 314 and / or creating a new entry in the data structure 314, as described above), the data structure pointer 310 can advance to the next position within the circular buffer structure 304 (e.g., the next portion 306).

[0051] In some implementations, the memory system may be configured to overwrite page IDs stored in portions 306 of the circular buffer structure 304, for example, in implementations where all portions 306 of the circular buffer structure 304 are full (e.g., containing page IDs) and subsequent memory access requests are received from the host system (sometimes referred to herein as a circular buffer rollup procedure). More specifically, such as Figure 3D As illustrated by the use of shading, at a certain point in time, all portions 306 of the circular buffer structure 304 (e.g., portions 306-1 to 306-16) may be full (e.g., available for storing corresponding page IDs). For example, at the point when the memory access pointer 308 points to the last open portion 306 of the circular buffer structure 304 (e.g., the sixteenth portion 306-16), the memory system may receive an incoming memory access request 324, such as with DPA. YAssociated incoming memory access requests, such as Figure 3D As shown in the text. Therefore, in conjunction with the above... Figures 3A to 3C In a similar manner, the memory system can store the corresponding page ID (e.g., page ID) in the sixteenth part 316-16 of the circular buffer structure 304. Y The memory access pointer 308 can advance to point to the next portion 306 of the circular buffer structure 304 (e.g., the first portion 306-1). More generally, when the memory access pointer 308 reaches the last entry of the circular buffer structure 304 (e.g., the last entry of the circular buffer structure 304), the memory access pointer 308 can advance to point to the next portion 306 of the circular buffer structure 304 (e.g., the last entry of the circular buffer structure 304). Figure 3D In the example shown (parts 316-16), when the new page ID is stored in this last empty entry, the memory access pointer 308 is incremented, causing the memory access pointer 308 to advance past the start position 312 of the circular buffer structure 304. This corresponds to the operation flow of the circular buffer rewind procedure, whereby after storing the page ID in the last free entry, the memory access pointer 308 is incremented and points to the first circular buffer entry.

[0052] Following this wraparound event, when another memory access request (e.g.) Figure 3D The text is a mix of seemingly unrelated phrases and sentences, making it impossible to translate coherently. It appears to be a collection of fragments from various sources, possibly related to DPA, ... Z When the associated memory access request 326 arrives, the page ID corresponding to the incoming memory access request 326 (e.g., page ID) Z The page ID can be stored in the first circular buffer entry (e.g., the first portion 306-1 of the circular buffer structure 304), thereby effectively overwriting the page ID previously stored in this particular location in the circular buffer structure 304. Optionally, when this rollover occurs, an overflow signal can be transmitted to the host system, as indicated by arrow 332, and / or an overflow counter can be updated to indicate that the memory access pointer 308 has completed a full cycle and / or to indicate that the previously stored page ID has been overwritten in the circular buffer structure 304.

[0053] Furthermore, during the roll-up of the circular buffer structure 304, if data is inserted into the data structure 314 slower than the rate of incoming memory access requests and / or if the memory system otherwise experiences significant delays associated with using the data structure 314 (e.g., a hot list) to track page IDs in the circular buffer structure 304, the memory access pointer 308 may overtake the data structure pointer 310 (e.g., pointing to a portion 306 of the circular buffer structure 304 storing page IDs that have not yet been tracked and / or counted in the data structure 314). In this case, the memory system may overwrite the older page ID stored in the portion of the circular buffer structure 304 with the new page ID before the older page ID is processed and added to the data structure 314. This event can result in the loss of tracking information used to overwrite the page ID. In such embodiments, the memory system may transmit an indication (sometimes referred to herein as an assertion overrun alarm) and / or may otherwise alert the host system that certain page IDs have not been accurately tracked and / or counted.

[0054] In other words, in some implementations, if a new memory access request arrives where the page ID associated with the new memory access request overwrites an older page ID stored in a portion of the circular buffer structure 304 (resulting in the loss of trace information for the older page ID because this page ID has not yet been resolved and inserted into data structure 314), then the memory system can assert a pass notification and / or alarm. In some implementations, the pass notification and / or alarm may remain valid until data structure pointer 310 catches up to the portion 306 immediately preceding memory access pointer 308. Alternatively or additionally, this pass status may prompt the setting or resetting of associated flags. Alternatively or additionally, in some implementations, the memory system may trace (e.g., aggregate) the total number of DPAs and / or page IDs missed in tracing when the pass notification is valid, for example, for the purpose of explaining examples of lost tracing.

[0055] In some implementations, the memory system may evict entries from data structure 314, for example, in implementations where a page ID existing in a circular buffer structure 304 does not yet have an associated entry in data structure 314 (e.g., a hot list) and data structure 314 is otherwise full. More specifically, such as Figure 3E As shown in the image, in conjunction with the above text. Figures 3A to 3D In a similar manner to that described, the memory system can receive memory access requests 334, such as in this example with DPA. L The associated request, and / or the memory system, can provide the corresponding page ID (e.g., page ID). LThe data is stored in a portion 306 of the circular buffer structure 304 (e.g., the twelfth portion 306-12 in this example). Furthermore, when the data structure pointer 310 reaches the corresponding entry in the circular buffer structure 304 (e.g., the twelfth portion 306-12 of the circular buffer structure 304), the memory system can update (e.g., increment) the associated counter in the data structure 314 or the corresponding page ID (e.g., the page ID in this example). L Create an entry, as described above. Figures 3A to 3D As described.

[0056] However, in this example, data structure 314 does not contain a corresponding page ID. L The entries are not present and data structure 314 is otherwise full (e.g., data structure 314 does not contain entries for adding page IDs). L (The associated open entries). Therefore, in such cases (e.g., when there are no available slots in data structure 314, or when a new page is accommodated in ring buffer structure 304), the memory system can use a configured eviction policy to determine which existing entry in data structure 314 should be evictioned. For example, the memory system can use one of the following: Least Recently Used (LRU) eviction policy, Least Frequently Used (LFU) eviction policy, random eviction policy, and / or a similar eviction policy. Figure 3E As shown, using a configured eviction policy, the memory system determines which page ID to evict. X The associated entries, and therefore the memory system can evict the corresponding entries, for example by using the page ID in data structure 314. L Related data (e.g., page ID) L Page ID L Associated memory access counters and / or page IDs L Related hot flags) overwrite and page ID X Related data (e.g., page ID) X , and page ID X Associated memory access counters and / or page IDs X (Associated hot flags). In some implementations, using this configuration eviction policy can maintain a dynamically updated list of hot pages and / or optimize memory utilization.

[0057] In some implementations, the memory system may be configured to periodically report various memory access counters (e.g., hotspot counters) and / or subsets thereof to the host system. For example, such as Figure 3FAs shown, the memory system can receive a hot list read request 340 from the host system, which may be a request to read memory access counters in data structure 314 (e.g., a hot list) that meet a hot threshold (e.g., a request to read memory access counters whose corresponding hot flags have been set). In such embodiments, when the hot list read request 340 is received by the memory system, the memory system can initiate a data structure 314 read process. Therefore, as indicated by arrow 342, the hot flags of entries in data structure 314 can be parsed (e.g., the hot flag bits of each entry in the hot list can be checked). For each entry where the hot flag is set to 0 (e.g., indicating that the associated memory access counter does not meet the threshold), the details of this entry (e.g., page ID and associated memory access counter value) may not be sent to the host system, such as by combining the page ID with reference number 344. M As shown. However, for each entry where the hot flag is set to 1 (e.g., indicating that the associated memory access counter has indeed met a threshold), the corresponding page ID and memory access counter for that entry can be transferred to the host system, as shown by reference number 344 combined with the page ID. K and page ID L As shown. This selective transmission ensures that only relevant entities (such as hot data entries) are transmitted to the host system.

[0058] Alternatively, in some implementations, the memory system may report hot entries to the host system via a list of transfer identifiers (e.g., page IDs) and memory access counter pairs. In such implementations, the list of pairs can be organized in descending order of memory access counter values, thereby providing the host system with an optimized and efficient overview of hot list entries.

[0059] In some implementations, the memory system may be configured (e.g., via a host system) to age a memory access counter stored in data structure 314, for example by aging the memory access counter at the end of an epoch (e.g., a period of time associated with a circular buffer structure 304 and / or data structure 314 configured by the host system to track memory accesses). Figure 3G This illustration illustrates the operational procedure for detecting hot list aging of hot data within a memory controller system (e.g., a memory system implementing the CXL interconnect standard).

[0060] As indicated by reference numeral 346, the memory system can determine the end of the epoch duration. Subsequently, each populated entry of data structure 314 (e.g., a hot list), and more specifically, each memory access counter for each populated entry of data structure 314, can be aged according to a configured aging factor, as shown by reference numeral 348. For example, at the end of the epoch, the counter associated with each page ID (e.g., ...) Figure 3GCounter in the example shown K Counter L and Counter M This can be halved by rounding (as an example of an aging factor), such as by changes in the corresponding counter value (e.g., page ID). K Pages 17 to 9, page ID L Pages 22 to 11 and / or page IDs M As illustrated in sections 13 to 7). Alternatively, in some embodiments, if the aging process causes any memory access counter to be set to 0, the entry in data structure 314 corresponding to that memory access counter can be cleared and / or removed from data structure 314. In such embodiments, removing entries from data structure 314 whose corresponding memory access counters have been aged to 0 prevents unnecessary consumption of space in data structure 314 that would otherwise be used to track past memory access requests. In some aspects, the aging mechanism can ensure the maintenance of relevant hot data detection by reducing the weight of older memory access examples. Alternatively, the aging mechanism can ensure that the memory system prioritizes recent access patterns, thereby promoting efficient and dynamic memory management. In some embodiments, the aging feature reflects intelligent methods of memory access pattern tracking within the evolving field of memory controller technology.

[0061] As indicated above, Figure 3A to 3G For illustrative purposes only. Other examples can be found in the section on... Figure 3A to 3G The descriptions are different.

[0062] Figure 4 This is a flowchart of an example method 400 associated with using a ring buffer structure to track access to memory. In some embodiments, a memory system controller (e.g., memory system controller 115 and / or main management subsystem 214) of a memory system (e.g., memory system 110 and / or CXL-compatible memory system 204) is executable or configurable to perform method 400. In some embodiments, another device or group of devices separate from or including the memory system controller (e.g., one or more local controllers 125 and / or local controllers associated with CXL device attached memory 218) is executable or configurable to perform method 400. Therefore, components for performing method 400 may include a memory system controller, one or more local controllers, and / or one or more components of a memory system controller and / or one or more local controllers. Additionally or alternatively, a non-transitory computer-readable medium may store one or more instructions that, when executed by the memory system controller, cause the memory system controller to perform method 400.

[0063] like Figure 4As shown, method 400 may include receiving a memory access request associated with a memory of a memory system from a host system (block 410). For example, CXL-compatible memory system 204 may receive the above-described combination of... Figure 3A to 3G One of the described memory access requests (e.g., one of memory access requests 302, 318, 324, 326, 334).

[0064] like Figure 4 As further shown, method 400 may include storing an identifier associated with a memory access request in a ring buffer structure (box 420). For example, the master management subsystem 214 of a CXL-compatible memory system 204 may store the page ID associated with a memory request in a portion 306 of a ring buffer structure 304, as described above. Figure 3A to 3G As described.

[0065] like Figure 4 As further shown, method 400 may include determining whether a data structure associated with the ring buffer structure contains an entry associated with an identifier (box 430). For example, the master management subsystem 214 of the CXL-compatible memory system 204 may determine whether a data structure 314 (e.g., a hot list) associated with the ring buffer structure 304 contains an entry associated with a page ID associated with a memory access request, as described above. Figure 3A to 3G As described.

[0066] like Figure 4 As further shown, method 400 may include performing one of the following: updating a memory access counter stored at an entry in response to determining that the data structure contains an entry, or creating an entry in the data structure and initializing a memory access counter stored at the entry in response to determining that the data structure does not contain an entry (box 440). For example, the master management subsystem 214 of CXL-compatible memory system 204 may update a memory access counter (e.g., a hotspot counter) stored at an entry in data structure 314 (e.g., a hot list) in response to determining that the data structure contains an entry associated with a page ID, as described above. Figure 3A to 3G As described above. Alternatively, the main management subsystem 214 of the CXL-compatible memory system 204 may create an entry in the data structure 314 (e.g., a hot list) and / or initialize a memory access counter (e.g., a hot counter) stored at the entry in response to determining that the data structure does not contain an entry, as described above. Figure 3A to 3G As described.

[0067] Method 400 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere herein.

[0068] In the first aspect, method 400 includes determining whether a memory access counter meets a threshold and performing one of the following: setting a flag in the entry in response to determining that the memory access counter meets the threshold, or omitting setting the flag in the entry in response to determining that the memory access counter does not meet the threshold. For example, the main management subsystem 214 of the CXL-compatible memory system 204 may selectively set a hot flag or omit setting a hot flag in an entry in a data structure (e.g., a hot list) depending on whether the corresponding hot counter in the entry meets the threshold, as described above. Figure 3A to 3G As described.

[0069] In the second aspect, either alone or in conjunction with the first aspect, a memory access request is associated with at least one of a read request or a write request. For example, the main management subsystem 214 of the CXL-compatible memory system 204 can be configured to selectively track read requests and / or write requests, as described above. Figure 3A to 3G As described.

[0070] In the third aspect, alone or in combination with one or more of the first and second aspects, method 400 includes receiving configuration information from a host system by a memory system controller. The configuration information indicates at least one of the following: an indication that the memory system can track one or more memory access requests; an aging factor associated with the tracking of one or more memory access requests; an epoch duration associated with the tracking of one or more memory access requests; a tracking granularity associated with the tracking of one or more memory access requests; a memory access counter threshold associated with the tracking of one or more memory access requests; or the type of memory access request tracked by the memory system. For example, the master management subsystem 214 of the CXL-compatible memory system 204 may receive the above-described configuration information from the CXL host 202. Figure 3A to 3G The description indicates the configuration information.

[0071] In the fourth aspect, alone or in combination with one or more of the first to third aspects, the circular buffer structure is associated with a memory access pointer and a data structure pointer, wherein an identifier is stored in the portion of the circular buffer structure pointed to by the memory access pointer, and wherein determining whether a data structure contains an entry associated with the identifier is made when the data structure pointer indicates the portion of the circular buffer structure that contains the entry. For example, circular buffer structure 304 may be combined with the above. Figure 3A to 3G The memory access pointer 308 and / or data structure pointer 310 described are associated.

[0072] In the fifth aspect, either alone or in combination with one or more of the first to fourth aspects, the identifier is stored in a portion of the circular buffer structure by overwriting another identifier stored in a portion of the circular buffer structure. For example, the master management subsystem 214 of the CXL-compatible memory system 204 can overwrite the page ID in portion 306 of the circular buffer structure 304, as described above. Figure 3D As described.

[0073] In the sixth aspect, either alone or in combination with one or more of the first to fifth aspects, method 400 includes at least one of the following: transmitting to the host system an indication that another identifier has been overwritten in a portion of the ring buffer structure; or updating an overflow counter associated with the ring buffer structure based on overwriting another identifier in a portion of the ring buffer structure. For example, the master management subsystem 214 of the CXL-compatible memory system 204 may transmit the above-mentioned combination Figure 3D The overflow signal described by arrow 332 and / or the above combined with the information can be updated based on overwriting another page ID in part 306 of the circular buffer structure 304. Figure 3D The overflow counter described.

[0074] In the seventh aspect, alone or in combination with one or more of the first to sixth aspects, method 400 includes: determining, by the memory system controller, that a memory access associated with another identifier has not yet been traced using a data structure; and transmitting, by the memory system controller, an indication to the host system that the other identifier has been overwritten and is not traced in the data structure. For example, the master management subsystem 214 of the CXL-compatible memory system 204 may transmit an overrun alert to the CXL host 202 indicating that a page ID has been overwritten and is not traced in data structure 314 (e.g., a hot list), as described above. Figure 3D As described.

[0075] In the eighth aspect, creating an entry in a data structure, either alone or in combination with one or more of the first to seventh aspects, involves evicting another entry from the data structure. For example, when a data structure is otherwise full, the master management subsystem 214 of the CXL-compatible memory system 204 may evict entries from data structure 314 (e.g., a hot list) when a new entry is added to data structure 314, as described above. Figure 3E As described.

[0076] In the ninth aspect, evictping another entry from a data structure, alone or in combination with one or more of the first to eighth aspects, includes evictping the other entry based on at least one of a least recently used eviction policy, a least frequently used eviction policy, or a random eviction policy. For example, the master management subsystem 214 of the CXL-compatible memory system 204 may use an eviction policy configured by the CXL host 202 to evict entries from data structure 314 (e.g., a hot list), as described above. Figure 3E As described.

[0077] In the tenth aspect, alone or in combination with one or more of the first to ninth aspects, method 400 includes: receiving a request from a host system by a memory system controller to read data from a data structure; determining by the memory system controller one or more entries in the data structure whose corresponding flags have been set; and transmitting to the host system an indication of a corresponding identifier and a corresponding memory access counter for each entry whose corresponding flag has been set. For example, the master management subsystem 214 of the CXL-compatible memory system 204 may determine which entries will be reported to the CXL host 202 based on whether a hot flag has been set in the corresponding entry of the data structure 314 (e.g., a hot list), and for the entries to be reported, the master management subsystem 214 of the CXL-compatible memory system 204 may transmit to the CXL host 202 an indication of a corresponding identifier (e.g., a page ID) and a corresponding memory access counter (e.g., a hot counter), as described above. Figure 3F As described.

[0078] In the eleventh aspect, individually or in combination with one or more of the first to tenth aspects, the indication that the corresponding identifier and corresponding memory access counter for each entry whose corresponding flag has been set includes a list of one or more identifier and memory access counter pairs transmitted from the memory system controller to the host system, wherein the list of one or more identifier and memory access counter pairs is sorted in descending order of memory access counter values. For example, the main management subsystem 214 of the CXL-compatible memory system 204 can sort the reported entries in descending order of access counter values, as described above in combination with the first aspect. Figure 3F As described.

[0079] In the twelfth aspect, alone or in combination with one or more of the first to eleventh aspects, method 400 includes: determining, by a memory system controller, that an epoch duration has elapsed; and aging one or more memory access counters stored in a data structure by the memory system controller based on the determination that the epoch duration has elapsed. For example, the master management subsystem 214 of the CXL-compatible memory system 204 may age access counter values ​​(e.g., heat counter values) stored in data structure 314 (e.g., a hot list) at the end of an epoch, as described above. Figure 3G As described.

[0080] In the thirteenth aspect, aging one or more memory access counters, individually or in combination with one or more of the first to twelfth aspects, includes aging one or more memory access counters based on an aging factor. For example, the master management subsystem 214 of the CXL-compatible memory system 204 may use an aging factor configured by the CXL host 202 at the end of the epoch to age access counter values ​​(e.g., heat counter values) in data structure 314 (e.g., hot list), as described above. Figure 3G As described.

[0081] In the fourteenth aspect, individually or in combination with one or more of the first to thirteenth aspects, the circular buffer structure is associated with a fixed-size data structure comprising multiple portions logically arranged in a circular manner from a first portion to a last portion. Identifiers of received memory access requests are sequentially stored in the fixed-size data structure from the first portion to the last portion, and the fixed-size data structure is managed in a first-in-first-out (FIFO) manner, such that after an identifier is stored in the last portion, an identifier associated with the next received memory access request is stored in the first portion. For example, the circular buffer structure may be a circular buffer structure 304 comprising multiple portions 306 logically arranged in a circular manner and used to store page IDs in a FIFO manner, such that once a page ID is stored in the sixteenth portion 306-16, the page ID associated with the next received memory access request is stored in the first portion 306-1, as described above. Figure 3D As described.

[0082] although Figure 4 The example box for method 400 is shown, but in some implementations, it is different from... Figure 4 Compared to the boxes depicted herein, method 400 may include additional boxes, fewer boxes, different boxes, or boxes with different arrangements. Alternatively, two or more boxes of method 400 may be executed in parallel. Method 400 is an example of a method that can be performed by one or more means described herein. These means may perform or be configured to perform one or more other methods based on the operations described herein.

[0083] In some embodiments, a memory system includes one or more components configured to: receive from a host system a memory access request associated with memory of the memory system; store an identifier associated with the memory access request in a circular buffer structure; determine whether a data structure associated with the circular buffer structure contains an entry associated with the identifier; and perform one of the following: updating a memory access counter stored at the entry in response to determining that the data structure contains the entry, or creating the entry in the data structure and initializing the memory access counter stored at the entry in response to determining that the data structure does not contain the entry.

[0084] In some implementations, a method includes: receiving a memory access request associated with memory of a memory system from a host system by a memory system controller; storing an identifier associated with the memory access request in a circular buffer structure by the memory system controller; determining whether a data structure associated with the circular buffer structure contains an entry associated with the identifier; and performing one of the following: updating a memory access counter stored at the entry in response to determining that the data structure contains the entry, or creating the entry in the data structure and initializing the memory access counter stored at the entry in response to determining that the data structure does not contain the entry.

[0085] In some implementations, a compute fast link (CXL) compatible memory system includes one or more components configured to: receive a CXL.mem request associated with memory of the CXL compatible memory system from a host system; store a page identifier (ID) associated with the CXL.mem request in a ring buffer structure; determine whether a hot list associated with the ring buffer structure contains an entry associated with the page ID; and perform one of the following: updating a heat counter stored at the entry in response to determining that the hot list contains the entry, or creating the entry in the hot list and initializing the heat counter stored at the entry in response to determining that the hot list does not contain the entry.

[0086] The above disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations may be made in light of the above disclosure or from the practice of the implementation described herein.

[0087] As used herein, the terms “generally” and “approximately” mean “within reasonable tolerances of manufacturing and measurement.” As used herein, “meeting the threshold” may, depending on the context, refer to a value greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, or similar.

[0088] Even though a particular combination of features is recited in the claims and / or disclosed in the specification, such combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in ways not specifically recited in the claims and / or not disclosed in the specification. For example, this disclosure includes each dependent claim in a group of claims in combination with each other individual claim in the group of claims and each combination of multiple claims in the group of claims. As used herein, the phrase “at least one of” in the list of items refers to any combination of these items, including a single member. As an example, “at least one of a, b, or c” is intended to cover a, b, c, a+b, a+c, b+c, and a+b+c, as well as any combination having multiple identical elements (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c or any other ordering of a, b, and c).

[0089] When “a component” or “one or more components” (or another element, such as “a controller” or “one or more controllers”) is described or claimed (within a single claim or across multiple claims) as performing or configured to perform multiple operations, this term is intended to broadly encompass a variety of architectures and environments. For example, unless explicitly claimed otherwise (e.g., by using “first component” and “second component” or other terms distinguishing components in the claims), this term is intended to cover a single component performing or configured to perform all operations, a group of components jointly performing or configured to perform all operations, a first component performing or configured to perform a first operation and a second component performing or configured to perform a second operation, or any combination of components performing or configured to perform operations. For example, when a claim has the form “one or more components configured to: perform X; perform Y; and perform Z”, this claim should be interpreted as meaning “one or more components configured to perform X; one or more (possibly different) components configured to perform Y; and one or more (possibly different) components configured to perform Z.”

[0090] No element, action, or instruction used herein should be construed as critical or essential unless explicitly stated otherwise. Furthermore, as used herein, the article “a” is intended to include one or more items and is interchangeable with “one or more.” Additionally, as used herein, the article “described” is intended to include one or more items referenced in conjunction with the article “described” and is interchangeable with “described one or more.” When only one item is desired, the phrases “only one,” “single,” or similar terms are used. Furthermore, as used herein, the term “having” or similar terms are intended to be open-ended terms that do not limit their modification (e.g., an element “having” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on,” unless otherwise explicitly stated. As used herein, the term “multiple” can be replaced with “a plurality of,” and vice versa. Furthermore, as used herein, the term “or” is intended to be inclusive when used in a series and is interchangeable with “and / or” unless otherwise explicitly stated (e.g., if used in combination with “(two) either of…” or “only one of…”).

Claims

1. A memory system, comprising: one or more components configured to: receive, from a host system, a memory access request associated with a memory of the memory system; store an identifier associated with the memory access request in a ring buffer structure; determine whether a data structure associated with the ring buffer structure includes an entry associated with the identifier; and perform one of: updating a memory access counter stored at the entry in response to determining that the data structure includes the entry, or creating the entry in the data structure and initializing the memory access counter stored at the entry in response to determining that the data structure does not include the entry.

2. The memory system of claim 1, wherein the one or more components are further configured to: determine whether the memory access counter satisfies a threshold; and perform one of: setting a flag in the entry in response to determining that the memory access counter satisfies the threshold, or omitting setting the flag in the entry in response to determining that the memory access counter does not satisfy the threshold.

3. The memory system of claim 1, wherein the memory access request is associated with at least one of a read request or a write request.

4. The memory system of claim 1, wherein the one or more components are further configured to receive configuration information from the host system, the configuration information indicating at least one of: an indication that one or more memory access requests are capable of being tracked by the memory system, an aging factor associated with tracking the one or more memory access requests by the memory system, a duration of an epoch associated with tracking the one or more memory access requests by the memory system, a tracking granularity associated with tracking the one or more memory access requests by the memory system, one or more types of memory access requests to be tracked by the memory system, or a memory access counter threshold value associated with tracking the one or more memory access requests by the memory system.

5. The memory system of claim 1, wherein the ring buffer structure is associated with a memory access pointer and a data structure pointer, wherein to store the identifier in the ring buffer structure, the one or more components are configured to store the identifier in a portion of the ring buffer structure pointed to by the memory access pointer, and wherein to determine whether the data structure includes the entry associated with the identifier, the one or more components are configured to determine whether the data structure includes the entry when the data structure pointer indicates the portion of the ring buffer structure.

6. The memory system of claim 1, wherein to store the identifier in the ring buffer structure, the one or more components are configured to store the identifier in a portion of the ring buffer structure by overwriting another identifier stored in the portion of the ring buffer structure. ​ 7. The memory system of claim 6, wherein the one or more components are further configured to at least one of: transmit, to the host system, an indication that another identifier has been overwritten in the portion of the ring buffer structure, or update an overflow counter associated with ring buffer structure based on overwriting the another identifier in the portion of the ring buffer structure.

8. The memory system of claim 6, wherein the one or more components are further configured to: determine that a memory access associated with the another identifier has not been tracked using the data structure; and transmit, to the host system, an indication that the another identifier has been overwritten without being tracked in the data structure.

9. The memory system of claim 1, wherein to create the entry in the data structure, the one or more components are configured to evict another entry from the data structure.

10. The memory system of claim 9, wherein to evict another entry from the data structure, the one or more components are configured to evict the another entry based on at least one of: a least recently used eviction policy, a least frequently used eviction policy, or a random eviction policy.

11. The memory system of claim 1, wherein the one or more components are further configured to: receive, from the host system, a request to read data from the data structure; determine one or more entries in the data structure whose respective flags have been set; and transmit, to the host system, an indication of a respective identifier and a respective memory access counter of each entry whose respective flag has been set.

12. The memory system of claim 11, wherein to transmit the indication of the respective identifier and the respective memory access counter of each entry whose respective flag has been set, the one or more components are configured to transmit, to the host system, a list of one or more identifier and memory access counter pairs, and wherein the list of one or more identifier and memory access counter pairs is ordered in descending order of memory access counter values.

13. The memory system of claim 1, wherein the one or more components are further configured to: determine that an epoch duration has elapsed; and age one or more memory access counters stored in the data structure based on determining that the epoch duration has elapsed.

14. The memory system of claim 13, wherein to age the one or more memory access counters, the one or more components are configured to age the one or more memory access counters based on an aging factor.

15. The memory system of claim 1, wherein the ring buffer structure is associated with a fixed size data structure that includes a plurality of portions logically arranged in a circular manner from a first portion to a last portion, wherein identifiers of received memory access requests are stored in the fixed size data structure sequentially from the first portion to the last portion, and wherein the fixed-size data structure is managed in a first-in-first-out manner such that, after storing an identifier in the last portion, an identifier associated with a next received memory access request is stored in the first portion.

16. A method comprising: receiving, by a memory system controller from a host system, a memory access request associated with a memory of a memory system; storing, by the memory system controller, an identifier associated with the memory access request in a ring buffer structure; determining, by the memory system controller, whether a data structure associated with the ring buffer structure includes an entry associated with the identifier; and performing, by the memory system controller, one of: updating a memory access counter stored at the entry in response to determining that the data structure includes the entry, or creating the entry in the data structure and initializing the memory access counter stored at the entry in response to determining that the data structure does not include the entry.

17. The method of claim 16, further comprising: determining, by the memory system controller, whether the memory access counter satisfies a threshold; and performing, by the memory system controller, one of: setting a flag in the entry in response to determining that the memory access counter satisfies the threshold, or omitting setting the flag in the entry in response to determining that the memory access counter does not satisfy the threshold.

18. The method of claim 16, further comprising receiving, by the memory system controller from the host system, configuration information indicating at least one of: an indication that one or more memory access requests are capable of being tracked by the memory system, an aging factor associated with tracking the one or more memory access requests by the memory system, a duration of an epoch associated with tracking the one or more memory access requests by the memory system, a tracking granularity associated with tracking the one or more memory access requests by the memory system, one or more memory access request types to be tracked by the memory system, or a memory access counter threshold value associated with tracking the one or more memory access requests by the memory system.

19. The method of claim 16, wherein storing the identifier in the ring buffer structure includes storing the identifier in a portion of the ring buffer structure by overwriting another identifier stored in the portion of the ring buffer structure.

20. The method of claim 16, further comprising: receiving, by the memory system controller from the host system, a request to read data from the data structure; determining, by the memory system controller, one or more entries in the data structure whose respective flags have been set; and transmitting, by the memory system controller to the host system, an indication of a respective identifier and a respective memory access counter for each entry whose respective flag has been set.

Images