Communication module, communication control method and electronic equipment

Abstract

The invention discloses a communication module, a communication control method and electronic equipment, and relates to the technical field of communication. The communication module comprises a host, a slave, a communication bus, a first switch, a second switch and a resending chip. The first end of the first switch is connected with the first end of the host and the communication bus. The second end of the first switch is connected with the first end of the resending chip. And the first end of the second switch is connected with the slave. The second end of the second switch is connected with the communication bus. And the third end of the second switch is connected with the second end of the resending chip. And when determining that the resending chip is abnormal, the host controls the first end and the second end of the first switch to be switched off, controls the first end and the third end of the second switch to be switched off, and controls the first end and the second end of the second switch to be switched on. Therefore, the resending chip can be skipped, and the first end of the host is connected with the slave through the communication bus, so that normal communication between the host and the slave is ensured.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a communication module, a communication control method, and an electronic device. Background Technology

[0002] Electronic devices such as mobile phones, tablets, and smartwatches typically include a communication module. The communication module consists of a master unit, a slave unit, and a communication bus connecting the master and slave units. The master unit can transmit communication data to the slave unit via the communication bus.

[0003] In related technologies, the communication module also includes a retransmission chip. The retransmission chip is connected to the host and communication bus via a first switch, and to the slave and communication bus via a second switch. When the retransmission chip needs to retransmit data to the slave, it can control the second switch to connect the slave to the retransmission chip.

[0004] However, in the related technologies, when the replacement chip malfunctions, the communication module may malfunction, affecting the normal communication between the host and the slave. Summary of the Invention

[0005] This application provides a communication module, a communication control method, and an electronic device. In this communication module, the host device can control a first switch and a second switch to bypass the re-transmission chip when the re-transmission chip malfunctions, thereby ensuring normal communication between the host and slave devices. The technical solution is as follows:

[0006] Firstly, a communication module is provided. The communication module is used in electronic devices. The communication module includes a master unit, a slave unit, a communication bus, a first switch, a second switch, and a retransmission chip.

[0007] The first switch has a first terminal and a second terminal. The first terminal of the first switch is connected to the first terminal of the host and the communication bus. The second terminal of the first switch is connected to the first terminal of the retransmission chip. When the first terminal and the second terminal of the first switch are connected, the first terminal of the retransmission chip is connected to the communication bus. In this case, the retransmission chip can monitor the communication data between the host and the slave device.

[0008] The second switch has a first terminal, a second terminal, and a third terminal. The first terminal of the second switch is connected to the slave device. The second terminal of the second switch is connected to the communication bus. The third terminal of the second switch is connected to the second terminal of the retransmission chip. When the first and second terminals of the second switch are closed, the slave device is connected to the communication bus. In this case, the master and slave devices can transmit communication data through the communication bus. When both the first and third terminals of the second switch are closed, the slave device is connected to the second terminal of the retransmission chip. In this case, the retransmission chip can retransmit data to the slave device.

[0009] The second terminal of the host is connected to the control terminal of the first switch, enabling the host to control the switching on and off between the first and second terminals of the first switch. The second terminal of the host is also connected to the control terminal of the second switch, enabling the host to control the switching on and off between the first and second terminals of the second switch, and also to control the switching on and off between the first and third terminals of the second switch. The third terminal of the host is connected to the third terminal of the replacement chip to determine if the replacement chip is malfunctioning.

[0010] In this embodiment, when the host determines that the replacement chip has malfunctioned, it can control the first and second terminals of the first switch to turn off, and also control the first and third terminals of the second switch to turn off. In this case, the first terminal of the replacement chip is not connected to the communication bus, and the second terminal of the replacement chip is not connected to the slave device. Thus, the replacement chip can be bypassed. When the host determines that the replacement chip has malfunctioned, it can also control the first and second terminals of the second switch to turn on. In this case, the first terminal of the host is connected to the slave device through the communication bus, thereby ensuring normal communication between the host and the slave device.

[0011] The structure of the communication module will be further explained below.

[0012] In some embodiments, the fourth terminal of the replacement chip is connected to the control terminal of the second switch, so that the replacement chip can control the conduction and cutoff between the first and second terminals of the second switch, and can control the conduction and cutoff between the first and third terminals of the second switch.

[0013] When the data retransmission chip needs to retransmit data to the slave device, it controls the first and third terminals of the second switch to be turned on, and controls the first and second terminals of the second switch to be turned off. In this way, the retransmission chip can simulate the master device retransmitting data to the slave device. Here, the control priority of the retransmission chip over the second switch is lower than the control priority of the master device over the second switch.

[0014] Specifically, the communication module also includes a first resistor. The first end of the first resistor is connected to the fourth end of the supplementary transmission chip, and the second end of the first resistor is connected to the second end of the host and the control end of the second switch.

[0015] In some embodiments, the fifth terminal of the replacement chip is connected to the control terminal of the first switch, so that the replacement chip can control the conduction and cutoff between the first terminal and the second terminal of the first switch.

[0016] When no abnormality occurs, the retransmission chip controls the first and second terminals of the first switch to be turned on. In this way, the retransmission chip can monitor the communication data between the master and slave devices on the communication bus, thereby determining whether data retransmission to the slave device is necessary. Here, the retransmission chip's control priority over the first switch is lower than the master's control priority over the first switch.

[0017] Specifically, the communication module also includes a second resistor. The first end of the second resistor is connected to the fifth end of the supplementary transmission chip, and the second end of the second resistor is connected to the second end of the host and the control end of the first switch.

[0018] In some embodiments, the retransmission chip includes a first register and a second register. The retransmission chip is used to monitor communication data between the master and slave devices on the communication bus. The retransmission chip is also used to simulate the master retransmitting data to the slave device when the monitored communication data contains a preset instruction. The value of the first register is incremented by one each time the retransmission chip monitors a frame of communication data. The value of the second register is incremented by one each time the retransmission chip completes the retransmission of a frame of data. The master device uses the values ​​of the first register and the second register to determine whether the retransmission chip has malfunctioned.

[0019] In some embodiments, the first switch further has a third terminal, which is left floating. When the host determines that the replacement chip has malfunctioned, it controls the first and third terminals of the first switch to be turned on. In this embodiment, at any given time, only one of the second and third terminals of the first switch is connected to the first terminal of the first switch.

[0020] Secondly, a communication control method is also provided, applied to a communication module as described in any embodiment of the first aspect. The communication control method includes: a host determining whether a faulty replacement chip has occurred; if a faulty replacement chip is determined to have occurred, the host controls the first and second terminals of a first switch to turn off, and controls the first and third terminals of a second switch to turn off, and controls the first and second terminals of the second switch to turn on; if a faulty replacement chip is determined not to have occurred, the host controls the first and second terminals of the first switch to turn on, or the host does not control the first switch.

[0021] In some embodiments, the fourth terminal of the retransmission chip is connected to the control terminal of the second switch, and the fifth terminal of the retransmission chip is connected to the control terminal of the first switch. The communication control method further includes: the retransmission chip monitoring the communication data between the master and slave devices on the communication bus; if the communication data contains a preset instruction, the retransmission chip controls the first and third terminals of the second switch to be turned on, and controls the first and second terminals of the second switch to be turned off; the retransmission chip simulates the master device retransmitting data to the slave device, and the retransmission chip simulates the slave device preempting the master device from the bus.

[0022] The following section provides a detailed explanation of the step of "the host determines whether an anomaly has occurred in the resend chip" using two different implementation methods.

[0023] In the first implementation, the retransmission chip includes a first register and a second register. The value of the first register is incremented by one each time the retransmission chip detects a frame of communication data; the value of the second register is incremented by one each time the retransmission chip completes the retransmission of a frame of data.

[0024] The host determines whether the reissue chip is malfunctioning by: the host reading the values ​​of the first register and the second register at first preset time intervals; if the value of the first register is the same for a first preset number of consecutive times, and the value of the second register is the same for a second preset number of consecutive times, then the host determines that the reissue chip is malfunctioning; if the value of the first register is the same for a number of consecutive times but does not reach the first preset number of times, and / or the value of the second register is the same for a number of consecutive times but does not reach the second preset number of times, then the host determines that the reissue chip is not malfunctioning.

[0025] In the second implementation, the communication control method further includes: if the replacement chip fails to self-test, the replacement chip transmits a preset communication signal to the host and resets to the state at power-on.

[0026] The host determines whether the replacement chip is malfunctioning, including: after receiving the preset communication signal, the host determines whether the replacement chip has successfully self-recovered; if the replacement chip fails to self-recover successfully, the host determines that the replacement chip is malfunctioning; if the replacement chip successfully self-recovers, the host reconfigures the replacement chip to make it work normally.

[0027] The "reissue chip self-test abnormality" includes the following five possible situations.

[0028] In the first scenario, if the duration for which the replacement chip simulates the host to resend data to the slave device reaches the second preset duration, the replacement chip will be determined to have a self-test anomaly.

[0029] In the second scenario, if the replacement chip determines that the communication module is in the bus arbitration stage or the frame sequence stage, and the replacement chip detects that the clock signal and data signal in the communication bus are both low for a duration that reaches the third preset duration, then the replacement chip determines that the self-test is abnormal.

[0030] In the third scenario, after the retransmission chip detects a frame of communication data, it calculates the parity check bit of the communication data to obtain the first check bit; the retransmission chip collects the parity check bit of the communication data to obtain the second check bit; if the first check bit and the second check bit are different, the retransmission chip determines that the self-test is abnormal.

[0031] In the fourth case, if the difference between the voltage value indicated in the communication data and the preset voltage value is greater than the preset threshold, the retransmission chip will determine that the self-test is abnormal.

[0032] In the fifth scenario, after each data retransmission, the retransmission chip receives a preset feedback signal from the slave device within a fourth preset time period. If the retransmission chip fails to receive the preset feedback signal within the fourth preset time period after two consecutive data retransmissions, the retransmission chip determines that the self-test is abnormal.

[0033] Thirdly, embodiments of this application also provide an electronic device, including a power-consuming device and a communication module as described in any embodiment of the first aspect, wherein the communication module operates a communication control method as described in any embodiment of the second aspect. A slave device in the communication module is connected to the power-consuming device and is used to supply power to the power-consuming device. A master device is used to control the voltage output from the slave device to the power-consuming device, that is, to control the voltage supplied by the slave device to the power-consuming device.

[0034] The technical effects achieved by the second and third aspects mentioned above are similar to those achieved by the corresponding technical means in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0035] Figure 1 This is a schematic diagram illustrating an application scenario of the first type of communication module provided in this application embodiment;

[0036] Figure 2 This is a schematic diagram illustrating an application scenario of the second type of communication module provided in this application embodiment;

[0037] Figure 3 This is a schematic diagram of the architecture of the first communication module provided in the embodiments of this application;

[0038] Figure 4 This is a schematic diagram of the architecture of the second communication module provided in the embodiments of this application;

[0039] Figure 5 This is a communication timing diagram of the SPMI communication module provided in the embodiments of this application;

[0040] Figure 6 This is a schematic diagram of the architecture of the third communication module provided in the embodiments of this application;

[0041] Figure 7 This is a circuit structure diagram of the first type of communication module provided in the embodiments of this application;

[0042] Figure 8 This is a circuit structure diagram of the second type of communication module provided in the embodiments of this application;

[0043] Figure 9 This is a circuit diagram of a second switch provided in an embodiment of this application;

[0044] Figure 10 This is a circuit diagram of a first switch provided in an embodiment of this application;

[0045] Figure 11 This is a flowchart of the first communication control method provided in the embodiments of this application;

[0046] Figure 12 This is a flowchart of the second communication control method provided in the embodiments of this application;

[0047] Figure 13 This is a flowchart of the third communication control method provided in the embodiments of this application.

[0048] The meanings of the various symbols in the attached icons are as follows:

[0049] 10. Electronic device; 20. Communication module; 201. First chip; 202. Second chip; 210. Master; 220. Slave; 230. Communication bus; 231. Data signal line; 232. Clock signal line; 240. Reissue chip; 250. First switch; 260. Second switch. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0051] It should be understood that "multiple" as mentioned in this application refers to two or more. In the description of this application, unless otherwise stated, " / " indicates "or," for example, A / B can mean A or B; "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist, for example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, to facilitate a clear description of the technical solutions of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0052] Figure 1 and Figure 2 These are schematic diagrams illustrating different application scenarios of the communication module provided in this application embodiment. The communication module can be applied to electronic devices 10, including mobile phones, tablets, wearable devices, etc. Wearable devices can be, for example, smartwatches, wristbands, etc. Figure 1 The electronic device 10 shown is a mobile phone. Figure 2 The electronic device 10 shown is a smartwatch.

[0053] Figure 3 This is a schematic diagram of the architecture of a communication module 20 provided in an embodiment of this application. Figure 3 As shown, the communication module 20 includes a master unit 210, a slave unit 220, and a communication bus 230 connecting the master unit 210 and the slave unit 220. The master unit 210 and the slave unit 220 can transmit communication data via the communication bus 230. The communication module 20 may include multiple master units 210 and multiple slave units 220. For example, in... Figure 3 In the illustrated embodiment, the communication module 20 includes four master units 210, namely 210a, 210b, 210c, and 210d; the communication module 20 also includes four slave units 220, namely 220a, 220b, 220c, and 220d. Here, the communication module 20 can be a system power management interface (SPMI) communication module with a master-slave architecture, which will be described in detail below.

[0054] Figure 4 This is a schematic diagram of another communication module 20 provided in this application embodiment. The communication module 20 shown in the figure is an SPMI communication module. SPMI is a hardware interface standard defined by the Mobile Industry Processor Interface (MIPI) Alliance, generally used as a power management interface. Through SPMI, the system on chip (SOC) can be connected to the power management integrated circuit (PMIC), so that the SOC can accurately monitor and control the output voltage of the PMIC, thereby ensuring the performance of the electrical components in the electronic device 10 that need to be powered by the PMIC. The electrical components in electronic device 10 may include, for example, a display screen, camera, indicator, motor, buttons, internal memory, speaker, receiver, microphone, headphone jack, subscriber identification module (SIM) card interface, external memory interface, sensors (e.g., pressure sensor, gyroscope, barometric pressure sensor, magnetic sensor, accelerometer, distance sensor, proximity sensor, fingerprint sensor, temperature sensor, touch sensor, ambient light sensor, bone conduction sensor), power amplifier (PA), driver amplifier (DA), low noise amplifier (LNA), etc. That is, when communication module 20 is an SPMI communication module, the master unit 210 can be a System-on-a-Chip (SOC), and the slave unit 220 can be a PMIC. The slave unit 220 is connected to the electrical component to supply power to it. The master unit controls the voltage output from the slave unit to the electrical component. The host 210 can also be a module within the SOC; for example, the host 210 could be an advanced operating system protection (AOP) module or a power management key (PMK) module within the SOC. Figure 4In the embodiment shown, host 210a and host 210b can be jointly packaged in the first chip 201; host 210c and host 210d are each packaged in a chip; slave 220a is packaged in a chip; slave 220b and slave 220c are jointly packaged in the second chip 202, and so on.

[0055] Still as Figure 4 As shown, when communication module 20 is an SPMI communication module, the communication bus 230 connecting the master 210 and slave 220 is an SPMI bus. The SPMI bus includes a data signal line 231 and a clock signal line 232. The data signal line 231 is used to transmit the data signal SDATA, and the clock signal line 232 is used to transmit the clock signal SCLK. The SPMI bus is an asynchronous bus that can connect up to four masters 210 and sixteen slaves 220. When multiple masters 210 and multiple slaves 220 communicate through the SPMI bus, they can resolve conflicts by arbitrarily arbitrating the bus access. When the communication bus 230 is idle, multiple masters 210 and multiple slaves 220 can request access to the communication bus 230 through bus arbitration. The master 210a can monitor the bus arbitration request and grant the communication bus 230 to a requester.

[0056] Figure 5 This is a communication timing diagram of the SPMI communication module provided in an embodiment of this application. For example... Figure 5 As shown, when any host 210 communicates with slave 220, the stage in which the communication module 20 is located may include the bus arbitration stage, the sequence start stage, the frame sequence stage, and the bus stop stage.

[0057] Specifically, when multiple devices (including master 210 and slave 220) initiate communication, during the bus arbitration phase, master 210a determines which initiating device has a higher priority, allowing each device to preempt the bus according to its priority and gain bus access. Generally, each device can preempt the bus by pulling the data signal SDATA high. After any device preempts the communication bus 230 and gains bus access, it gains control of the clock signal SCLK on the communication bus 230 and provides the clock signal.

[0058] The sequence start phase is a buffer phase. During the sequence start phase, the device that gains bus access pulls the clock signal SCLK low. During the sequence start phase, the device that gains bus access also first pulls the data signal SDATA high, then pulls it low again to generate a sequence start condition (SSC). The receiving device in communication module 20 (e.g., slave 220) prepares to receive subsequent communication data after detecting the SSC.

[0059] The frame sequence stage is used to execute data transmission instructions, thereby transmitting communication data. The communication data includes transmission commands, transmission addresses, and transmission data. The transmission commands can be, for example, the master 210 reading from the slave 220's register, the master 210 writing to the slave 220's register, or the slave 220 writing to the master 210's register. In some specific embodiments, the communication data can be, for example, the master 210a writing data 01 to the slave 220a's register at address 0110.

[0060] The bus stop phase is the process by which communication module 20 stops communication. During the bus stop phase, the device that has acquired bus access will pull the clock signal SCLK and the data signal SDATA low. After both the clock signal SCLK on clock signal line 232 and the data signal SDATA on data signal line 231 are pulled low, the communication bus 230 is in an idle state.

[0061] For ease of understanding, the clock signal line 232 and the data signal line 231 will still be described as a whole (i.e., the communication bus 230) in the following description. Figure 6 This is a schematic diagram of the architecture of another communication module 20 provided in an embodiment of this application. For example... Figure 6 As shown, the communication module 20 may also include a retransmission chip 240, a first switch 250, and a second switch 260.

[0062] Specifically, the first terminal 1 of the first switch 250 is connected to the host 210 and the communication bus 230. The second terminal 2 of the first switch 250 is connected to the first terminal 1 of the supplementary transmission chip 240. The third terminal 3 of the first switch 250 is left unconnected, meaning it is not connected to any of the supplementary transmission chip 240, the host 210, the slave 220, or the communication bus 230. The first terminal 1 of the second switch 260 is connected to the slave 220. The second terminal 2 of the second switch 260 is connected to the communication bus 230. The third terminal 3 of the second switch 260 is connected to the second terminal of the supplementary transmission chip 240. The fourth terminal 4 of the supplementary transmission chip 240 is connected to the control terminal 4 of the second switch 260 to control the second switch 260. The fifth terminal 5 of the supplementary transmission chip 240 is connected to the control terminal 4 of the first switch 250 to control the first switch 250. In some specific embodiments, the replacement chip 240 is also connected to the host 210 (not shown in the figure) so that the host 210 can configure the replacement chip 240 after it is powered on.

[0063] Generally, the host 210 can configure the supplementary transmission chip 240 after powering it on, and the configured supplementary transmission chip 240 enters the working state. When the supplementary transmission chip 240 is working, it controls the first terminal 1 and the second terminal 2 of the first switch 250 to be turned on, and also controls the first terminal 1 and the second terminal 2 of the second switch 260 to be turned on. In this way, the host 210 and the slave 220 can transmit communication data through the communication bus 230. When the supplementary transmission chip 240 is working, it also listens to the communication data between the host 210 and the slave 220 on the communication bus 230. When the communication data contains a preset instruction, the supplementary transmission chip 240 can control the first terminal 1 and the third terminal 3 of the second switch 260 to be turned on. At this time, the supplementary transmission chip 240 can simulate the host 210 to retransmit data to the slave 220, and simulate the slave 220 to preempt the host 210 on the bus. The preset instruction is configured by the host 210 to configure the supplementary transmission chip 240. The retransmission chip 240 simulates the host 210 to retransmit data to the slave 220. It can modify and retransmit specific communication data without affecting the communication between the host 210 and the slave 220, thereby realizing customized control of the slave 220. The retransmission chip 240 simulates the slave 220 to preempt the host 210 on the bus, which can prevent the host 210 from continuing to transmit communication data during the data retransmission of the slave 220 by the retransmission chip 240.

[0064] When the replacement chip 240 malfunctions, it can control the first terminal 1 and the third terminal 3 of the first switch 250 to be turned on, and also control the first terminal 1 and the second terminal 2 of the second switch 260 to be turned on. In this way, the host 210 and the slave 220 can transmit communication data through the communication bus 230, and bypass the replacement chip 240.

[0065] However, Figure 6 The communication module 20 shown also has the following problems: (1) If the replacement chip 240 malfunctions when connected to the host 210 and the communication bus 230 via the first switch 250, or when the replacement chip 240 malfunctions when connected to the slave 220 or the communication bus 230 via the second switch 260 (i.e., when the replacement chip 240 is connected to the communication bus 230), the entire communication module 20 may malfunction. (2) The first switch 250 and the second switch 260 are completely controlled by the replacement chip 240. When the replacement chip 240 malfunctions, it may be unable to control the first switch 250 and the second switch 260, thus preventing the replacement chip 240 from bypassing, which will cause the communication of the communication module 20 to be uncontrollable. (3) After the replacement chip 240 malfunctions, it needs to be restarted or asynchronously reset to restore normal operation, which may affect the communication between the host 210 and the slave 220.

[0066] Based on this, embodiments of this application also provide a communication module, a communication control method, and an electronic device. In this communication module, the host can control the operation of the first switch and the second switch to skip the replacement chip when the replacement chip malfunctions, thereby ensuring normal communication between the host and the slave.

[0067] The communication module provided in the embodiments of this application will be explained in detail below. The communication module provided in the embodiments of this application can be applied to electronic devices, such as those used in... Figure 1 and Figure 2 The electronic device 10 shown. In the embodiments of this application, the connection between the two electronic devices is always an electrical connection. Here, an electrical connection means that the two electronic devices can transmit electrical signals through the connection. The electrical connection between the two electronic devices can be a direct connection through a wire or an indirect connection through other electronic devices.

[0068] Figure 7 This is a circuit structure diagram of a communication module 20 provided in an embodiment of this application. For example... Figure 7 As shown, the communication module 20 includes a host 210, a slave 220, a communication bus 230, a retransmission chip 240, a first switch 250, and a second switch 260.

[0069] Communication module 20 may include one or more host devices 210. For example, when communication module 20 is an SPMI communication module 20, it may include up to four host devices 210. Each host device 210 may be a System-on-a-Chip (SoC) in an electronic device, or an AOP module or PMK module within the SoC. Figure 7In the illustrated embodiment, the communication module 20 includes four hosts 210, namely 210a, 210b, 210c, and 210d. The following description uses host 210a as an example. Host 210a has a first terminal 1, a second terminal 2, and a third terminal 3.

[0070] The communication module 20 may also include one or more slave devices 220. For example, when the communication module 20 is an SPMI communication module 20, it may include up to 16 slave devices 220. Each slave device 220 may be a power management device in the PMIC, and each power management device may be a buck converter or a boost converter. Figure 7 In the embodiment shown, the communication module 20 includes four slave devices 220, namely 220a, 220b, 220c, and 220d. The following description uses any one of the slave devices 220 as an example.

[0071] The first switch 250 has a first terminal 1 and a second terminal 2. The first terminal 1 of the first switch 250 is connected to the first terminal 1 of the host 210a and the communication bus 230. The second terminal 2 of the first switch 250 is connected to the first terminal 1 of the supplementary transmission chip 240. When the first terminal 1 and the second terminal 2 of the first switch 250 are turned on, the first terminal 1 of the supplementary transmission chip 240 is connected to the communication bus 230, and the supplementary transmission chip 240 can monitor the communication data between the host 210a and the slave 220. When the first terminal 1 and the second terminal 2 of the first switch 250 are turned off, the first terminal 1 of the supplementary transmission chip 240 is not connected to the communication bus 230, and the supplementary transmission chip 240 cannot monitor the communication data between the host 210a and the slave 220.

[0072] The second switch 260 has a first terminal 1, a second terminal 2, and a third terminal 3. The first terminal 1 of the second switch 260 is connected to the slave device 220. The second terminal 2 of the second switch 260 is connected to the communication bus 230. The third terminal 3 of the second switch 260 is connected to the second terminal 2 of the retransmission chip 240. When the first terminal 1 and the second terminal 2 of the second switch 260 are on, the slave device 220 is connected to the communication bus 230, and the master device 210a and the slave device 220 can transmit communication data through the communication bus 230. When the first terminal 1 and the second terminal 2 of the second switch 260 are off, the slave device 220 is not connected to the communication bus 230, and the master device 210a and the slave device 220 cannot transmit communication data through the communication bus 230. When the first terminal 1 and the third terminal 3 of the second switch 260 are on, the slave device 220 is connected to the second terminal 2 of the retransmission chip 240, and the retransmission chip 240 can retransmit data to the slave device 220. When the first terminal 1 and the third terminal 3 of the second switch 260 are turned off, the slave device 220 is not connected to the second terminal 2 of the retransmission chip 240. At this time, the retransmission chip 240 cannot retransmit data to the slave device 220.

[0073] The second terminal 2 of the host 210a is connected to the control terminal 4 of the first switch 250, so that the host 210a can control the switching on and off between the first terminal 1 and the second terminal 2 of the first switch 250. The second terminal 2 of the host 210a is also connected to the control terminal 4 of the second switch 260, so that the host 210a can control the switching on and off between the first terminal 1 and the second terminal 2 of the second switch 260, and can also control the switching on and off between the first terminal 1 and the third terminal 3 of the second switch 260. The third terminal 3 of the host 210a is connected to the third terminal 3 of the replacement chip 240, so that the host 210a can determine whether the replacement chip 240 is malfunctioning.

[0074] In this embodiment, when the host 210a determines that the replacement chip 240 has malfunctioned, it can control the first terminal 1 and the second terminal 2 of the first switch 250 to turn off, and control the first terminal 1 and the third terminal 3 of the second switch 260 to turn off. In this case, the first terminal 1 of the replacement chip 240 is not connected to the communication bus 230, and the second terminal 2 of the replacement chip 240 is not connected to the slave device 220 or the communication bus 230. Thus, the replacement chip 240 can be bypassed. When the host 210a determines that the replacement chip 240 has malfunctioned, it also controls the first terminal 1 and the second terminal 2 of the second switch 260 to turn on. In this case, the first terminal 1 of the host 210a is connected to the slave device 220 through the communication bus 230, the second terminal 2 of the second switch 260, and the first terminal 1, thereby ensuring normal communication between the host 210a and the slave device 220.

[0075] Therefore, the communication module 20 provided in this application embodiment allows the host 210a to skip the supplementary transmission chip 240 when an anomaly is detected, thus ensuring normal communication between the host 210a and the slave 220. In this way, firstly, it avoids the entire communication module 20 from malfunctioning due to an anomaly occurring when the supplementary transmission chip 240 is connected to the communication bus 230. Secondly, it avoids the problem of uncontrollable communication in the communication module 20 caused by the inability to control the first switch 250 and the second switch 260 when the supplementary transmission chip 240 malfunctions.

[0076] In the above embodiments, only host 210a is used as an example to illustrate the connection relationship between host 210a, communication bus 230, first switch 250, second switch 260, and supplementary transmission chip 240. It is understood that when the communication module 20 also includes host 210b, host 210c, and host 210d, as a feasible implementation, each of host 210b, host 210c, and host 210d can be connected only to the communication bus 230. In this case, the structure of the communication module 20 is as follows: Figure 7 As shown. Alternatively, as another feasible implementation, for any one or more of the host 210b, host 210c, and host 210d, the connection method can be: the first end is connected to the communication bus 230, the second end is connected to the control terminal 4 of the first switch 250 and the control terminal 4 of the second switch 260, and the third end is connected to the third terminal 3 of the supplementary transmission chip 240, which will not be described in detail.

[0077] The structure of the communication module 20 provided in this application embodiment will be further explained below in four parts.

[0078] Part 1: The structure of the first switch 250.

[0079] Figure 8 This is a circuit structure diagram of another communication module 20 provided in an embodiment of this application. For example... Figure 8As shown, in some embodiments, the first switch 250 also has a third terminal 3. The third terminal 3 of the first switch 250 is left floating. That is, the third terminal 3 of the first switch 250 is not connected to any one of the supplementary chip 240, the host 210, the slave 220, the communication bus 230, or the second switch 260. When the host 210a determines that the supplementary chip 240 has malfunctioned, it can control the first terminal 1 and the third terminal 3 of the first switch 250 to conduct. In the embodiments of this application, the first switch 250 can be a single pole double throw (SPDT) switch. That is, at any given time, only one of the second terminal 2 and the third terminal 3 of the first switch 250 is conducting with the first terminal 1 of the first switch 250. Similarly, the second switch 260 can also be an SPDT switch. At any given time, only one of the second terminal 2 and the third terminal 3 of the second switch 260 is conducting with the first terminal 1 of the second switch 260.

[0080] Part II. Control logic of the host 210a and the supplementary chip 240 on the second switch 260.

[0081] In some embodiments, it remains the same. Figure 8 As shown, the fourth terminal 4 of the replacement chip 240 is connected to the control terminal 4 of the second switch 260, so that the replacement chip 240 can control the switching on and off between the first terminal 1 and the second terminal 2 of the second switch 260, and can also control the switching on and off between the first terminal 1 and the third terminal 3 of the second switch 260. Here, the control priority of the replacement chip 240 over the second switch 260 is lower than the control priority of the host 210a over the second switch 260.

[0082] When the host 210a determines that the retransmission chip 240 is not malfunctioning, the retransmission chip 240 can control the second switch 260. In this case, when the retransmission chip 240 needs to retransmit data to the slave 220, it can control the first terminal 1 and the third terminal 3 of the second switch 260 to be turned on, and control the first terminal 1 and the second terminal 2 of the second switch 260 to be turned off, thereby retransmitting data to the slave 220. After the retransmission chip 240 completes the retransmission of data to the slave 220, it can control the first terminal 1 and the third terminal 3 of the second switch 260 to be turned off, and control the first terminal 1 and the second terminal 2 of the second switch 260 to be turned on, so that the host 210a and the slave 220 can transmit communication data through the communication bus 230. When the host 210a determines that the replacement chip 240 has malfunctioned, since the host 210a has a higher control priority over the second switch 260 than the replacement chip 240 has a higher control priority over the second switch 260, it can ensure that the first terminal 1 and the third terminal 3 of the second switch 260 are turned off and the first terminal 1 and the second terminal 2 of the second switch 260 are turned on.

[0083] In some specific embodiments, the "control priority of the replacement chip 240 on the second switch 260 is lower than the control priority of the host 210a on the second switch 260" can be achieved through the following scheme.

[0084] Still as Figure 8 As shown, the communication module 20 also includes a first resistor R1. The first end of the first resistor R1 is connected to the fourth terminal 4 of the supplementary transmission chip 240, and the second end of the first resistor R1 is connected to the second terminal 2 of the host 210a and the control terminal 4 of the second switch 260. In this embodiment, the circuit structure of the second switch 260 can be as follows: Figure 9 As shown.

[0085] Specifically, the second switch 260 includes a first transistor M1 and a second transistor M2. The first transistor M1 is an N-type transistor, and its first terminal is the second terminal 2 of the second switch 260. The second transistor M2 is a P-type transistor, and its first terminal is the third terminal 3 of the second switch 260. The second terminals of the first transistor M1 and the second transistor M2 are connected together to form the first terminal 1 of the second switch 260. The control terminals of the first transistor M1 and the second transistor M2 are connected together to form the control terminal 4 of the second switch 260.

[0086] When the host 210a determines that the retransmission chip 240 is not malfunctioning, the second terminal 2 of the host 210a does not need to output a level signal. In this case, if the retransmission chip 240 needs to retransmit data to the slave 220, that is, when it needs to control the first terminal 1 and the third terminal 3 of the second switch 260 to be turned on and the first terminal 1 and the second terminal 2 to be turned off, the fourth terminal 4 of the retransmission chip 240 can output a low-level signal. At this time, the control terminals of the first transistor M1 and the second transistor M2 both input low-level signals, the first transistor M1 is turned off and the second transistor M2 is turned on, that is, the first terminal 1 and the second terminal 2 of the second switch 260 are turned off and the first terminal 1 and the third terminal 3 are turned on. If the retransmission chip 240 completes the data retransmission to the slave 220, that is, when it needs to control the first terminal 1 and the third terminal 3 of the second switch 260 to be turned off and the first terminal 1 and the second terminal 2 to be turned on, the fourth terminal 4 of the retransmission chip 240 can output a high-level signal. At this time, both the control terminals of the first transistor M1 and the second transistor M2 are input with high-level signals. The first transistor M1 is turned on and the second transistor M2 is turned off, which means that the first terminal 1 and the third terminal 3 of the second switch 260 are turned off, and the first terminal 1 and the second terminal 2 are turned on.

[0087] When the host 210a determines that the replacement chip 240 has malfunctioned, that is, when the host 210a needs to control the first terminal 1 and the third terminal 3 of the second switch 260 to be turned off and the first terminal 1 and the second terminal 2 to be turned on, the second terminal 2 of the host 210a can output a high-level signal. In this case, due to the presence of the first resistor R1, regardless of whether the fourth terminal 4 of the replacement chip 240 outputs a low-level signal, a high-level signal, or no signal, the control terminal 4 of the second switch 260 will always input a high-level signal. At this time, the control terminals of the first transistor M1 and the second transistor M2 will both input high-level signals, the first transistor M1 will be turned on and the second transistor M2 will be turned off, thus realizing the turning off of the first terminal 1 and the third terminal 3 of the second switch 260 and the turning on of the first terminal 1 and the second terminal 2.

[0088] In this embodiment, the transistor can be a field-effect transistor (FET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET). The transistor can also be an insulated-gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), etc., which will not be elaborated further.

[0089] Part III. Control logic of the host 210a and the supplementary chip 240 on the first switch 250.

[0090] In some embodiments, it remains the same. Figure 8 As shown, the fifth terminal 5 of the replacement chip 240 is connected to the control terminal 4 of the first switch 250, so that the replacement chip 240 can control the conduction and de-conduction between the first terminal 1 and the second terminal 2 of the first switch 250, and can also control the conduction and de-conduction between the first terminal 1 and the third terminal 3 of the first switch 250. Here, the control priority of the replacement chip 240 over the first switch 250 is lower than the control priority of the host 210a over the first switch 250.

[0091] Based on this, when the host 210a determines that the retransmission chip 240 is not malfunctioning, the retransmission chip 240 can control the first switch 250. In this case, the retransmission chip 240 can control the first terminal 1 and the second terminal 2 of the first switch 250 to be turned on, thereby monitoring the communication data between the host 210a and the slave 220 in the communication bus 230, and determining whether to retransmit data to the slave 220 based on the communication data. When the host 210a determines that the retransmission chip 240 is malfunctioning, since the host 210a's control priority over the first switch 250 is higher than the retransmission chip 240's control priority over the first switch 250, it can ensure that the first terminal 1 and the third terminal 3 of the first switch 250 are turned on, and the first terminal 1 and the second terminal 2 of the first switch 250 are turned off.

[0092] In some specific embodiments, the "control priority of the replacement chip 240 over the first switch 250 is lower than the control priority of the host 210a over the first switch 250" can be achieved through the following scheme.

[0093] Still as Figure 8 As shown, the communication module 20 also includes a second resistor R2. The first end of the second resistor R2 is connected to the fifth terminal 5 of the supplementary transmission chip 240, and the second end of the second resistor R2 is connected to the second terminal 2 of the host 210a and the control terminal 4 of the first switch 250. In this embodiment, the circuit structure of the first switch 250 can be as follows: Figure 10 As shown.

[0094] Specifically, the first switch 250 includes a third transistor M3 and a fourth transistor M4. The third transistor M3 is a P-type transistor, and the fourth transistor M4 is an N-type transistor. The first terminals of the third transistor M3 and the fourth transistor M4 are connected together to form the first terminal 1 of the first switch 250. The second terminal of the third transistor M3 is the second terminal 2 of the first switch 250. The second terminal of the fourth transistor M4 is the third terminal 3 of the first switch 250. The control terminals of the third transistor M3 and the fourth transistor M4 are connected together to form the control terminal 4 of the first switch 250.

[0095] When the host 210a determines that the replacement chip 240 is not malfunctioning, the second terminal 2 of the host 210a may not output a level signal. In this case, the fifth terminal 5 of the replacement chip 240 may output a low-level signal. At this time, both the control terminals of the third transistor M3 and the fourth transistor M4 input low-level signals, the third transistor M3 is turned on and the fourth transistor M4 is turned off, that is, the first terminal 1 and the second terminal 2 of the first switch 250 are turned on, and the first terminal 1 and the third terminal 3 are turned off. At this time, the replacement chip 240 can monitor the communication data between the host 210a and the slave 220 on the communication bus 230.

[0096] When the host 210a determines that the replacement chip 240 has malfunctioned, that is, when the host 210a needs to control the first terminal 1 and the third terminal 3 of the first switch 250 to be on and the first terminal 1 and the second terminal 2 to be off, the third terminal 3 of the host 210a can output a high-level signal. In this case, due to the presence of the second resistor R2, regardless of whether the fifth terminal 5 of the replacement chip 240 outputs a low-level signal, a high-level signal, or no signal, the control terminal 4 of the first switch 250 will always input a high-level signal. At this time, the control terminals of the third transistor M3 and the fourth transistor M4 will both input high-level signals, the third transistor M3 will be off and the fourth transistor M4 will be on, that is, the first terminal 1 and the second terminal 2 of the first switch 250 will be off and the first terminal 1 and the third terminal 3 will be on. At this time, the replacement chip 240 cannot monitor the communication data between the host 210a and the slave 220 on the communication bus 230.

[0097] Understandable, Figure 8 In the illustrated embodiment, since the control terminal 4 of the first switch 250 and the control terminal 4 of the second switch 260 are connected together, and the host 210a needs to control the first terminal 1 and the third terminal 3 of the first switch 250 to be on while simultaneously controlling the first terminal 1 and the second terminal 2 of the second switch 260 to be on, the first transistor M1 and the fourth transistor M4 need to be transistors of the same type (both N-type or both P-type). In some other embodiments, when the second terminal of the host 210a includes two sub-ports, which are used to control the first transistor M1 and the fourth transistor M4 respectively, the first transistor M1 and the fourth transistor M4 can also be transistors of different types. Similarly, when the second terminal of the host 210a includes four sub-ports, which are used to control four transistors (i.e., the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4) respectively, the type of each of the four transistors can be arbitrarily selected.

[0098] Part IV. Working Logic of Reissued Chip 240

[0099] In this embodiment, the retransmission chip 240 is used to: monitor the communication data between the host 210a and the slave 220 in the communication bus 230; if the communication data contains a preset instruction, the retransmission chip 240 controls the first and third terminals of the second switch 260 to be turned on, and controls the first and second terminals of the second switch 260 to be turned off; and simulates the host 210a to retransmit data to the slave 220.

[0100] Based on this, the retransmission chip 240 may include a first register and a second register. The first register is a listening counter register, and its value is incremented by one each time the retransmission chip 240 listens for a frame of communication data. The second register is a retransmission counter register, and its value is incremented by one each time the retransmission chip 240 completes the retransmission of a frame of data.

[0101] In some specific embodiments, the first register and the second register can be 16-bit registers. That is, the values ​​of the first register and the second register range from 0 to 65535. In this case, when the value of the first register (or the second register) accumulates to 65535, the value of the first register (or the second register) needs to be cleared to zero. The host 210a can determine whether the retransmission chip 240 has malfunctioned based on the values ​​of the first register and the second register.

[0102] This application also provides a communication control method, applied to, for example... Figure 7 or Figure 8 The communication module 20 is shown. (Example) Figure 11 As shown, the communication control method includes the following steps S110 and S120.

[0103] S110, the host 210a determines whether the reissue chip 240 is malfunctioning.

[0104] S120, if it is determined that the replacement chip 240 is abnormal, the host 210a controls the first terminal 1 and the second terminal 2 of the first switch 250 to turn off, and controls the first terminal 1 and the third terminal 3 of the second switch 260 to turn off, and controls the first terminal 1 and the second terminal 2 of the second switch 260 to turn on.

[0105] In this configuration, the replacement chip 240 is neither connected to the communication bus 230 via the first switch 250 nor to the communication bus 230 or the slave device 220 via the second switch 260. In other words, the replacement chip 240 is completely bypassed to prevent a malfunctioning replacement chip 240 from affecting normal communication between the host 210a and the slave device 220. Simultaneously, the host 210a is connected to the slave device 220 via the communication bus 230, the second terminal 2 of the second switch 260, and the first terminal 1, thereby ensuring normal communication between the host 210a and the slave device 220.

[0106] In some embodiments, when the host 210a performs step S120, it can also control the retransmission chip 240 to power down.

[0107] The following example demonstrates the application of communication control methods to, for instance... Figure 8 Taking the communication module 20 shown as an example, the communication control method will be further explained.

[0108] In some embodiments, the communication control method further includes the following steps S210 to S230.

[0109] S210, the supplementary chip 240 monitors the communication data between the host 210a and the slave 220 in the communication bus 230.

[0110] The replacement chip 240 may have a configuration port (not shown in the figure), which is connected to the host 210a so that the host 210a can configure the replacement chip 240 after powering it on. After configuration, the replacement chip 240 enters the working state. When the replacement chip 240 is working, it controls the first terminal 1 and the second terminal 2 of the first switch 250 to be turned on, and also controls the first terminal 1 and the second terminal 2 of the second switch 260 to be turned on. At this time, the host 210a and the slave 220 transmit communication data through the communication bus 230, and the replacement chip 240 can monitor the communication data between the host 210a and the slave 220 on the communication bus 230.

[0111] S220, if the communication data contains a preset instruction, the retransmission chip 240 controls the first terminal 1 and the third terminal 3 of the second switch 260 to be turned on, and controls the first terminal 1 and the second terminal 2 of the second switch 260 to be turned off.

[0112] The preset command is configured by the host 210a to the retransmission chip 240. When the retransmission chip 240 is monitoring the communication data between the host 210a and the slave 220 on the communication bus 230, if it detects that the communication data contains the preset command, it indicates that the retransmission chip 240 needs to retransmit data to the slave 220. In this case, the retransmission chip 240 can control the first terminal 1 and the third terminal 3 of the second switch 260 to be turned on, so that the retransmission chip 240 can retransmit data to the slave 220. When the first terminal 1 and the third terminal 3 of the second switch 260 are turned on, the first terminal 1 and the second terminal 2 are turned off.

[0113] S230, the retransmission chip 240 simulates the host 210a to retransmit data to the slave 220, and the retransmission chip 240 simulates the slave 220 to preempt the host 210a on the bus.

[0114] When the first terminal 1 and the third terminal 3 of the second switch 260 are turned on, the retransmission chip 240 can simulate the host 210a to retransmit data to the slave 220. When the retransmission chip 240 retransmits data to the slave 220, it can do so according to a preset program. The preset program can be configured by the host 210a to send data to the retransmission chip 240, or it can be set by someone skilled in the art; no limitation is made here. In this way, specific communication data can be modified and retransmitted without affecting the communication between the host 210a and the slave 220, thereby achieving customized control of the slave 220.

[0115] When the retransmission chip 240 simulates the master 210a retransmitting data to the slave 220, it also simulates the slave 220 preempting the master 210a on the bus. As mentioned earlier, during the bus preemption period, none of the devices (including the master 210a) will output communication data. In other words, the retransmission chip 240 simulating the slave 220 preempting the master 210a on the bus prevents the master 210a from continuing to transmit communication data while the retransmission chip 240 is retransmitting data to the slave 220.

[0116] Based on the above steps S210 to S230, step S110 includes the following two different implementation methods.

[0117] I. The first implementation method.

[0118] In the first implementation, the retransmission chip 240 includes a first register and a second register. Each time the retransmission chip 240 detects a frame of communication data, the value of the first register is incremented by one. Each time the retransmission chip 240 completes the retransmission of a frame of data, the value of the second register is incremented by one. Step S110 includes the following steps S111A to S113A.

[0119] S111A, the host 210a reads the value of the first register and the value of the second register at a first preset time interval.

[0120] S112A, if the value of the first register is the same for a first preset number of times, and the value of the second register is the same for a second preset number of times, then the host 210a determines that the resend chip 240 has malfunctioned.

[0121] S113A, if the number of consecutive identical values ​​in the first register does not reach the first preset number, and / or the number of consecutive identical values ​​in the second register does not reach the second preset number, then the host 210a determines that the resend chip 240 has not malfunctioned.

[0122] The value of the first register indicates the number of frames of communication data between the master 210a and the slave 220 on the communication bus 230 that the retransmission chip 240 detects during operation. The value of the second register indicates the number of frames of data retransmission performed by the retransmission chip 240 to the slave 220 during operation. Therefore, if the master 210a reads the same value from the first register multiple times within a certain period, and the same value from the second register multiple times, it indicates that the retransmission chip 240 neither detected communication data nor retransmitted data to the slave 220 during this period. In this case, the master 210a can determine that the retransmission chip 240 has malfunctioned and cannot properly detect and retransmit communication data. Conversely, if the master 210a reads at least two different values ​​from the first register multiple times within a certain period, it indicates that the retransmission chip 240 detected communication data during this period; and if the master 210a reads at least two different values ​​from the second register multiple times within a certain period, it indicates that the retransmission chip 240 performed data retransmission during this period. If the retransmission chip 240 detects communication data and / or retransmits data to the slave device 220 within a certain period of time, the host device 210a can determine that the retransmission chip 240 has not malfunctioned.

[0123] In this embodiment, the first preset duration, the first preset number of times, and the second preset number of times can all be set by those skilled in the art based on experience and requirements. For example, the first preset duration can be any duration from 100ms (milliseconds) to 1s (seconds), such as 100ms, 200ms, 500ms, 800ms, or 1s. The first preset number of times can be any number from 3 to 10, such as 3, 5, 8, or 10 times. The second preset number of times can also be any number from 3 to 10. The first preset number of times and the second preset number of times can be the same or different.

[0124] II. The second implementation method.

[0125] In the second implementation, the communication control method further includes the following step S310.

[0126] S310, if the replacement chip 240 fails to self-test, the replacement chip 240 transmits a preset communication signal to the host 210a and resets to the state at power-on.

[0127] Specifically, the replacement chip 240 can also perform a self-test during operation. When the replacement chip 240 malfunctions during the self-test, it can transmit a preset communication signal to the host 210a to report the self-test malfunction. When transmitting the preset communication signal to the host 210a, the replacement chip 240 can also reset itself to the power-on state, that is, the replacement chip 240 performs self-recovery.

[0128] In some specific embodiments, the "self-test abnormality of replacement chip 240" in step S310 includes the following five possible situations.

[0129] 1. First possible scenario. In the first possible scenario, the communication control method further includes the following step S3101.

[0130] S3101, if the duration for which the retransmission chip 240 simulates the host 210a to retransmit data to the slave 220 reaches the second preset duration, then the retransmission chip 240 determines that the self-test is abnormal.

[0131] Specifically, when the retransmission chip 240 is not malfunctioning, the duration for which the retransmission chip 240, simulating the host 210a, retransmits data to the slave 220 is generally a fixed duration, referred to as the expected retransmission duration for ease of description. The second preset duration is slightly longer than the expected retransmission duration. For example, the expected retransmission duration is generally 3 μs (microseconds) to 4 μs, in which case the second preset duration can be 5 μs, 6 μs, or 10 μs. In some other embodiments, the expected retransmission duration can also be 6 μs or 8 μs, in which case the second preset duration can be 9 μs or 10 μs. The second preset duration can be set by those skilled in the art based on experience and requirements.

[0132] When the duration for which the retransmission chip 240 simulates the host 210a retransmitting data to the slave 220 reaches the second preset duration, it indicates that the data retransmission duration has exceeded the expected retransmission duration, that is, the continuous conduction duration of the first terminal 1 and the third terminal 3 of the second switch 260 has exceeded the expected retransmission duration. In this case, the retransmission chip 240 determines that there is a self-test abnormality.

[0133] 2. The second possible scenario. In the second possible scenario, the communication control method further includes the following step S3102.

[0134] S3102, if the replacement chip 240 determines that the communication module 20 is in the bus arbitration stage or the frame sequence stage, and the replacement chip 240 detects that the clock signal SCLK and data signal SDATA in the communication bus 230 are both low for a duration of three preset durations, then the replacement chip 240 determines that the self-test is abnormal.

[0135] Specifically, such as Figure 5As described in the illustrated embodiment, when the communication module 20 is in the bus arbitration phase, each device can preempt the bus by pulling the data signal SDATA high. After any device preempts the communication bus 230 and obtains bus occupancy, it can obtain control of the clock signal SCLK in the communication bus 230 and provide the clock signal. That is, during the bus arbitration phase, if the replacement chip 240 does not malfunction, it will inevitably detect the high-level data signal SDATA and the high-level clock signal SCLK. Based on this, the replacement chip 240 can be provided with a third preset duration, which is longer than the duration during which the clock signal SCLK and the data signal SDATA in the communication bus 230 are both low during the bus arbitration phase. The third preset duration can be, for example, 2μs, 3μs, or 5μs. The third preset duration can be set by those skilled in the art based on experience and requirements.

[0136] If the replacement chip 240 determines that the communication module 20 is in the bus arbitration phase, and the replacement chip 240 detects that the clock signal SCLK and data signal SDATA in the communication bus 230 are both low for a duration of the third preset duration, it indicates that the replacement chip 240 has not correctly detected the high-level clock signal SCLK or data signal SDATA. In this case, the replacement chip 240 determines that the self-test is abnormal.

[0137] Similarly, such as Figure 5 As described in the illustrated embodiment, when the communication module 20 is in the frame sequence stage, it needs to transmit communication data. That is, during the frame sequence stage, the communication bus 230 needs to transmit the clock signal SCLK and the data signal SDATA. Therefore, during the frame sequence stage, if the supplementary chip 240 does not malfunction, it will inevitably detect a high-level data signal SDATA and a high-level clock signal SCLK. Based on this, the third preset duration is also greater than the duration during which the clock signal SCLK and the data signal SDATA in the communication bus 230 are both low during the frame sequence stage.

[0138] If the replacement chip 240 determines that the communication module 20 is in the frame sequence stage, and the replacement chip 240 detects that the clock signal SCLK and data signal SDATA in the communication bus 230 are both low for a duration of the third preset duration, it indicates that the replacement chip 240 has not correctly detected the high-level clock signal SCLK or data signal SDATA. In this case, the replacement chip 240 determines that the self-test is abnormal.

[0139] In some other embodiments, step S3102 can also be replaced by: if the replacement chip 240 determines that the communication module 20 is in the bus arbitration stage, and the replacement chip 240 detects that the clock signal SCLK and data signal SDATA in the communication bus 230 are both low for a duration of A preset duration, then the replacement chip 240 determines that a self-test anomaly has occurred; and if the replacement chip 240 determines that the communication module 20 is in the frame sequence stage, and the replacement chip 240 detects that the clock signal SCLK and data signal SDATA in the communication bus 230 are both low for a duration of B preset duration, then the replacement chip 240 determines that a self-test anomaly has occurred. Preset duration A is not equal to preset duration B. That is, thresholds for the duration of the clock signal SCLK and data signal SDATA in the communication bus 230 being low can be set for the bus arbitration stage and the frame sequence stage respectively, which will not be elaborated further.

[0140] 3. The third possible scenario. In the third possible scenario, the communication control method further includes the following steps S31031 to S31033.

[0141] S31031, after the retransmission chip 240 detects a frame of communication data, it calculates the parity check bit of the communication data and obtains the first check bit.

[0142] S31032, the parity check bit of the communication data collected by the supplementary chip 240 is used to obtain the second check bit.

[0143] S31033, if the first check bit and the second check bit are different, the resend chip 240 will determine that the self-test is abnormal.

[0144] Specifically, in SPMI communication, the communication data includes data bits and parity bits. After listening to a frame of communication data, the retransmission chip 240 calculates the parity bit of the communication data based on the data bits, thus obtaining the first parity bit. Simultaneously, when listening to the same frame of communication data, the retransmission chip 240 can also directly obtain the parity bit carried in the communication data, thus obtaining the second parity bit. In other words, the first parity bit is the parity bit calculated by the retransmission chip 240 based on the data bits of the listened communication data; the second parity bit is the parity bit carried in the communication data listened to by the retransmission chip 240.

[0145] Based on this, the retransmission chip 240 can determine whether the first check bit and the second check bit are the same. When the first check bit and the second check bit are different, the retransmission chip 240 determines that the self-test is abnormal.

[0146] 4. The fourth possible scenario. In the fourth possible scenario, the communication control method further includes the following step S3104.

[0147] S3104, if the difference between the voltage value indicated in the communication data and the preset voltage value is greater than the preset threshold, the retransmission chip 240 determines that the self-test is abnormal.

[0148] Specifically, when communication module 20 is an SPMI communication module 20 and slave device 220 is a power management device in a PMIC, the communication data transmitted from master device 210a to slave device 220 can generally be used to indicate a voltage value so that the output voltage of the power management device is equal to the voltage value indicated by master device 210a. Here, after listening to the communication data, the supplementary chip 240 determines whether the difference between the voltage value indicated by master device 210a and a preset voltage value in the communication data is greater than a preset threshold. The preset voltage value and preset threshold can both be set by those skilled in the art based on the rated voltage of the electronic device powered by the power management device. In some embodiments, the preset threshold can be any value from 1V to 3V. For example, the preset threshold can be 1V, 1.5V, 2V, or 3V.

[0149] If the difference between the voltage value indicated in the communication data and the preset voltage value is greater than the preset threshold, it indicates that the voltage value indicated by the host 210a, as detected by the retransmission chip 240, is too high. In this case, the retransmission chip 240 determines that the self-test is abnormal.

[0150] 5. The fifth possible scenario. In the fifth possible scenario, the communication control method further includes the following steps S31051 and S31052.

[0151] S31051, after each data retransmission, the retransmission chip 240 receives a preset feedback signal transmitted by the slave device 220 within a fourth preset time period.

[0152] S31052, if the retransmission chip 240 does not receive the preset feedback signal within the fourth preset time period after two consecutive data retransmissions, the retransmission chip 240 determines that the self-test is abnormal.

[0153] Specifically, after each data retransmission by the retransmission chip 240, the slave device 220 transmits a preset feedback signal to the retransmission chip 240 within a fourth preset duration. Therefore, if the retransmission chip 240 fails to receive the preset feedback signal within the fourth preset duration after two consecutive data retransmissions, it indicates that the retransmission has failed or that the slave device 220 is unable to transmit the preset feedback signal to the retransmission chip 240 normally. In this case, the retransmission chip 240 determines a self-test anomaly. The fourth preset duration can be set by those skilled in the art according to requirements. In some embodiments, the fourth preset duration can be any duration from 50μs to 200μs. For example, the fourth preset duration can be 50μs, 100μs, 150μs, or 200μs.

[0154] Based on the above step S310, step S110 may include the following steps S111B to S113B.

[0155] S111B, after receiving the preset communication signal, the host 210a determines whether the retransmission chip 240 has successfully recovered.

[0156] S112B, if the replacement chip 240 fails to recover successfully, it is determined that the replacement chip 240 has malfunctioned.

[0157] S113B, if the replacement chip 240 successfully recovers, the host 210a reconfigures the replacement chip 240 to make it work properly.

[0158] After receiving a preset communication signal, i.e., after receiving a self-test anomaly reported by the retransmission chip 240, the host 210a determines whether the retransmission chip 240 has successfully recovered, i.e., whether the retransmission chip 240 has been reset to the power-on state. If yes, the host 210a can reconfigure the retransmission chip 240, thereby enabling the retransmission chip 240 to resume normal operation. If no, the host 210a determines that the retransmission chip 240 has malfunctioned, and then executes step S120.

[0159] It is easy to understand that the two different implementations of step S110 described above do not conflict. Therefore, step S110 in the communication control method provided in this application embodiment can include both of these implementations simultaneously.

[0160] In some other embodiments, the communication control method further includes step S130 after step S110.

[0161] S130, if it is determined that the replacement chip 240 is not malfunctioning, the host 210a controls the connection of the first terminal 1 and the second terminal 2 of the first switch 250, or the host 210a does not control the first switch 250.

[0162] When the replacement chip 240 is functioning normally, the host 210a can control the first terminal 1 and the second terminal 2 of the first switch 250 to be turned on. In this case, the first terminal 1 of the replacement chip 240 is connected to the host 210a and the communication bus 230, so that the replacement chip 240 can monitor the communication data between the host 210a and the slave 220 on the communication bus 230. In some embodiments, when the replacement chip 240 is functioning normally, the host 210a may not control the first switch 250 and the second switch 260. In this case, the replacement chip 240 can control the first terminal 1 and the second terminal 2 of the first switch 250 to be turned on, thereby monitoring the communication data between the host 210a and the slave 220 on the communication bus 230. When the first terminal 1 and the second terminal 2 of the first switch 250 are turned on, the first terminal 1 and the third terminal 3 are turned off.

[0163] The communication control method will now be explained in detail with reference to the accompanying drawings, using a specific embodiment. In this embodiment, the communication control method is applied to, for example... Figure 8 The communication module 20 shown is an SOC (System-on-a-Chip) for the host 210a, a PMIC (Personal Microcontroller) for the slave 220, and an SPMI (Simplified Chinese Component Interface) communication module 20.

[0164] When the communication module 20 is working, the possible abnormalities generally include the following three types:

[0165] 1. Abnormal electrical signals in communication bus 230. For example: (1) When communication module 20 is communicating, the electrical signals in communication bus 230 may be interfered with and produce glitches. (2) When the retransmission chip 240 retransmits data, it abnormally occupies communication bus 230, resulting in abnormal electrical signals in communication bus 230. (3) The host 210a or slave 220 abnormally pulls the bus.

[0166] 2. The electronic device 10 used by the communication module 20 malfunctions. For example: (1) A software malfunction in the electronic device 10 causes the electronic device 10 to restart. (2) A hardware malfunction in the electronic device 10 causes a power failure, resulting in a fault restart of the electronic device 10.

[0167] 3. Malfunction of the replacement chip 240. For example: (1) The listening logic of the replacement chip 240 is abnormal, causing the replacement chip 240 to fail to correctly listen to the communication data in the communication bus 230. (2) The listening logic of the replacement chip 240 is abnormal, causing the data identified by the replacement chip 240 to be inconsistent with expectations. (3) The replacement logic of the replacement chip 240 is abnormal, causing it to be unable to perform data replacement normally. (4) The replacement logic of the replacement chip 240 is abnormal, causing the replacement time to exceed the expected replacement time.

[0168] Of the three types of anomalies mentioned above, in addition to the "abnormal operation of the replacement chip 240," an "abnormal electrical signal in the communication bus 230" may also cause the replacement chip 240 to malfunction. Based on this, this application embodiment provides six anomaly detection methods for possible anomalies that may occur when the replacement chip 240 is operating, as shown in Table 1 below.

[0169] Table 1

[0170]

[0171]

[0172] According to Table 1 above, "abnormal electrical signal in communication bus 230" can be detected by three abnormality detection methods numbered 3, 4, and 5, and "abnormal operation of replacement chip 240" can be detected by three abnormality detection methods numbered 1, 2, and 6.

[0173] ① Based on anomaly detection method number 1, such as Figure 12 As shown, the communication control method provided in this application embodiment may include the following steps S1 to S11.

[0174] S1, the host 210a completes the configuration of the retransmission chip 240.

[0175] After the host 210a powers on the retransmission chip 240, it configures the retransmission chip 240, and the configured retransmission chip 240 enters the working state.

[0176] S2, the replacement chip 240 is connected to the communication bus 230 and listens to the communication data.

[0177] The replacement chip 240 controls the first terminal 1 and the second terminal 2 of the first switch 250 to be turned on, so that the first terminal 1 of the replacement chip 240 is connected to the communication bus 230 and listens to the communication data between the host 210 and the slave 220 in the communication bus 230.

[0178] S3, the value of the first register is incremented by one for each frame of communication data detected by the retransmission chip 240.

[0179] S4, the retransmission chip 240 simulates the host 210a to retransmit data to the slave 220.

[0180] When the communication data in the communication bus 230 contains a preset instruction, the retransmission chip 240 controls the first terminal 1 and the third terminal 3 of the second switch 260 to be turned on, thereby simulating the host 210a to retransmit data to the slave 220.

[0181] S5, when the retransmission chip 240 completes the retransmission of each frame of data, the value of the second register is incremented by one.

[0182] S6, host 210a begins polling and detection.

[0183] S7, host 210a reads the values ​​of the first register and the second register.

[0184] S8, interval 500ms.

[0185] S9, whether the values ​​of the first register and the second register have changed.

[0186] After the host reads the values ​​of the first register and the second register, it determines whether the values ​​of the first register and the second register have changed. If yes, it returns to step S7. If no, it proceeds to step S10.

[0187] S10, has it reached 5 times?

[0188] If so, it indicates that the value of the first register is the same for 5 consecutive times and the value of the second register is the same for 5 consecutive times. At this time, the host 210a determines that the reissue chip 240 has malfunctioned and executes step S11.

[0189] If not, it indicates that the number of times the value of the first register is the same consecutively has not reached 5, and / or the number of times the value of the second register is the same consecutively has not reached 5. At this time, the host 210a determines that the resend chip 240 has not malfunctioned and returns to the execution step S7.

[0190] S11, the host 210a controls the skipping of the retransmission chip 240.

[0191] After determining that the replacement chip 240 has malfunctioned, the host 210a controls the first terminal 1 and the second terminal 2 of the first switch 250 to turn off, and controls the first terminal 1 and the third terminal 3 of the first switch 250 to turn on, and controls the first terminal 1 and the third terminal 3 of the second switch 260 to turn off, and controls the first terminal 1 and the second terminal 2 of the second switch 260 to turn on, so as to skip the replacement chip 240. After determining that the replacement chip 240 has malfunctioned, the host 210a also controls the replacement chip 240 to power down.

[0192] In this case, the host 210a will not power on the retransmission chip 240 and configure it until the next system restart of the electronic device 10.

[0193] ② Based on anomaly detection method number 2, such as Figure 13 As shown, the communication control method provided in this application embodiment may include the following steps S12 to S14.

[0194] S12, send a busy signal high.

[0195] When the retransmission chip 240 simulates the host 210a to retransmit data to the slave 220, the retransmission busy signal is pulled high.

[0196] S13 triggers a 5μs timing period. If the busy signal is still high when the 5μs time is reached, the 240 chip will fail its self-test.

[0197] When the busy signal is pulled high during the retransmission, the timing is triggered. If the busy signal is still high when the timing reaches 5μs, it indicates that the data retransmission time exceeds the expected retransmission time. At this time, the retransmission chip 240 determines that the self-test is abnormal and the abnormality type is retransmission abnormality.

[0198] S14, resend abnormal signal and pull high.

[0199] ③ Based on anomaly detection method number 3, such as Figure 13 As shown, the communication control method provided in this application embodiment may include the following steps S15 to S17.

[0200] S15, listen for the arb_busy signal to go high or listen for the rd_busy signal to go high.

[0201] When the retransmission chip 240 determines that the communication module 20 is in the bus arbitration phase, it listens for the arb_busy signal to go high. When the retransmission chip 240 determines that the communication module 20 is in the frame sequence phase, it listens for the rd_busy signal to go high.

[0202] S16 triggers a 2μs timing. If the clock signal SCLK and data signal SDATA are both low for 2μs while the arb_busy signal or the rd_busy signal is high, the 240 reissue chip will fail its self-test.

[0203] Timing can be triggered by listening for either the arb_busy signal or the rd_busy signal to go high. If, while listening for either the arb_busy or rd_busy signal to go high, the clock signal SCLK and the data signal SDATA remain low for 2μs, it indicates that the replacement chip 240 has not correctly detected the high-level clock signal SCLK or data signal SDATA. In this case, the replacement chip 240 determines a self-test anomaly, and the anomaly type is an abnormal listening state of the communication bus 230.

[0204] S17, the communication bus 230 monitoring status abnormal signal is pulled high.

[0205] ④ Based on anomaly detection method number 4, such as Figure 13 As shown, the communication control method provided in this application embodiment may include the following steps S18 to S19.

[0206] S18, judge the parity bit. If the calculated parity bit is not equal to the collected parity bit, the resend chip 240 self-test is abnormal.

[0207] If the parity bit calculated by the retransmission chip 240 is not equal to the parity bit collected, then the retransmission chip 240 will have a self-test error and the error type will be parity error.

[0208] S19, parity check anomaly signal is pulled high.

[0209] ⑤, based on anomaly detection method number 5, such as Figure 13 As shown, the communication control method provided in this application embodiment may include the following steps S20 to S21.

[0210] S20: Judge the voltage value indicated in the communication data. If the difference between the voltage value in the communication data and the preset voltage value is greater than 2V, the retransmission chip 240 determines that the self-test is abnormal.

[0211] After the replacement chip 240 listens to the communication data, it subtracts the preset voltage value from the voltage value indicated in the communication data. If the difference is greater than 2V, the replacement chip 240 determines that the self-test is abnormal and the abnormality type is abnormal listening voltage value.

[0212] S21, abnormal voltage value monitoring signal is pulled high.

[0213] ⑥, Based on anomaly detection method number 6, such as Figure 13 As shown, the communication control method provided in this application embodiment may include the following steps S22 to S23.

[0214] S22, after the retransmission chip 240 completes one data retransmission, it detects the preset feedback signal returned by the slave device 220 within 100μs. If it fails to detect the signal twice in a row, the retransmission chip 240 will fail the self-test.

[0215] After the retransmission chip 240 simulates the host 210a to complete a data retransmission to the slave 220, the slave 220 needs to reply with a preset feedback signal within 100μs. If the retransmission chip 240 fails to receive the preset feedback signal from the slave 220 within 100μs after two consecutive data retransmissions, the retransmission chip 240 will have a self-test error, and the error type will be slave 220 response error.

[0216] S23, slave device 220 responds with an abnormal signal high.

[0217] In the embodiments of this application, such as Figure 13As shown, after any one of steps S14, S17, S19, S21, and S23, the communication control method may further include steps S24 and S25.

[0218] S24, the supplementary chip 240 transmits a preset communication signal to the host 210a.

[0219] S25, reset chip 240 to its power-on state.

[0220] Step S25 involves the replacement chip 240 performing self-recovery.

[0221] Steps S24 and S25 can be performed simultaneously. After steps S24 and S25, the communication control method may further include steps S26 to S28.

[0222] S26, the host 210a determines whether the replacement chip 240 has successfully recovered.

[0223] The host 210a determines whether the replacement chip 240 has been reset to its power-on state. If not, the replacement chip 240 has not successfully self-recovered, and step S27 is executed; if yes, the replacement chip 240 has successfully self-recovered, and step S28 is executed.

[0224] When executing step S26, host 210a can also determine the fault type of the retransmission chip 240 by reading the registers in the retransmission chip 240. The fault types of the retransmission chip 240 include the above-mentioned retransmission fault, communication bus 230 listening status fault, parity bit fault, listening voltage value fault, and slave 220 response fault.

[0225] S27, host 210a determines that the reissue chip 240 has malfunctioned and executes step S11.

[0226] After step S27, step S11 can be executed, that is, the host 210a controls the first switch 250 and the second switch 260 to skip the retransmission chip 240, and the host 210a controls the retransmission chip 240 to power down.

[0227] S28, the host 210a reconfigures the retransmission chip 240 to make the retransmission chip 240 work normally.

[0228] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A communication module applied to an electronic device, characterized in that, The communication module comprises a host, a slave, a communication bus, a first switch, a second switch and a retransmission chip; a first end of the first switch is connected with a first end of the host and the communication bus, and a second end of the first switch is connected with a first end of the retransmission chip; a first end of the second switch is connected with the slave, a second end of the second switch is connected with the communication bus, and a third end of the second switch is connected with a second end of the retransmission chip; a second end of the host is connected with a control end of the first switch and a control end of the second switch, and a third end of the host is connected with a third end of the retransmission chip, for determining whether the retransmission chip is abnormal; when the host determines that the retransmission chip is abnormal, the host controls the first end and the second end of the first switch to be off, controls the first end and the third end of the second switch to be off, and controls the first end and the second end of the second switch to be on.

2. The communication module of claim 1, wherein, a fourth end of the retransmission chip is connected with a control end of the second switch; when the retransmission chip needs to retransmit data to the slave, the retransmission chip controls the first end and the third end of the second switch to be on, and controls the first end and the second end of the second switch to be off; the control priority of the retransmission chip on the second switch is lower than the control priority of the host on the second switch.

3. The communication module of claim 2, wherein, The communication module further comprises a first resistor; a first end of the first resistor is connected with the fourth end of the retransmission chip, and a second end of the first resistor is connected with the second end of the host and a control end of the second switch.

4. The communication module according to any one of claims 1 to 3, wherein a fifth end of the retransmission chip is connected with a control end of the first switch; when the retransmission chip is not abnormal, the retransmission chip controls the first end and the second end of the first switch to be on, and the control priority of the retransmission chip on the first switch is lower than the control priority of the host on the first switch.

5. The communication module of claim 4, wherein, The communication module further comprises a second resistor; a first end of the second resistor is connected with the fifth end of the retransmission chip, and a second end of the second resistor is connected with the second end of the host and a control end of the first switch.

6. The communication module according to any one of claims 1 to 5, wherein The retransmission chip comprises a first register and a second register; the retransmission chip is used for listening to communication data between the host and the slave in the communication bus, and the retransmission chip is further used for simulating the host to retransmit data to the slave when the communication data contains a preset instruction; the value of the first register is increased by one every time the retransmission chip listens to one frame of the communication data; the value of the second register is increased by one every time the retransmission chip completes one frame of data retransmission; the host is used for determining whether the retransmission chip is abnormal according to the value of the first register and the value of the second register.

7. The communication module according to any one of claims 1 to 6, wherein The first switch further has a third end, and the third end of the first switch is suspended; the host controls the first end and the third end of the first switch to be on when the host determines that the retransmission chip is abnormal.

8. A communication control method applied to the communication module according to any one of claims 1 to 7, characterized in that, The method comprises: the host determines whether the retransmission chip is abnormal; If it is determined that the retransmission chip is abnormal, the host controls the first end and the second end of the first switch to be off, controls the first end and the third end of the second switch to be off, and controls the first end and the second end of the second switch to be on.

9. The communication control method of claim 8, wherein, The fourth end of the retransmission chip is connected with the control end of the second switch; and the method further comprises: The retransmission chip listens to the communication data between the host and the slave in the communication bus; If the preset instruction is contained in the communication data, the retransmission chip controls the first end and the third end of the second switch to be on, and controls the first end and the second end of the second switch to be off; The retransmission chip simulates the host to retransmit data to the slave, and simulates the slave to occupy the bus to the host.

10. The communication control method of claim 9, wherein, The retransmission chip comprises a first register and a second register; the value of the first register is increased by one every time the retransmission chip listens to one frame of the communication data; and the value of the second register is increased by one every time the retransmission chip completes one frame of data retransmission. The host determines whether the retransmission chip is abnormal, comprising: The host reads the values of the first register and the second register every first preset time interval; If the value of the first register is the same for a first preset number of times continuously, and the value of the second register is the same for a second preset number of times continuously, the host determines that the retransmission chip is abnormal; If the value of the first register is not the same for the first preset number of times continuously, and / or the value of the second register is not the same for the second preset number of times continuously, the host determines that the retransmission chip is not abnormal.

11. The communication control method of claim 9, wherein The method further comprises: If the retransmission chip is abnormal in self-checking, the retransmission chip transmits a preset communication signal to the host, and resets to a power-on state; The host determines whether the retransmission chip is abnormal, comprising: After receiving the preset communication signal, the host determines whether the retransmission chip is successfully recovered; If the retransmission chip is not successfully recovered, it is determined that the retransmission chip is abnormal.

12. The communication control method of claim 11, wherein, The method further comprises: If the retransmission chip is successfully recovered, the host reconfigures the retransmission chip, so that the retransmission chip works normally.

13. The communication control method according to claim 11 or 12, wherein The method further comprises: If the duration of the retransmission chip simulating the host to retransmit data to the slave reaches a second preset duration, the retransmission chip determines that the self-checking is abnormal.

14. The communication control method according to any one of claims 11 to 13, wherein The method further comprises: If the retransmission chip determines that the communication module is in a bus arbitration stage or a frame sequence stage, and the retransmission chip detects that the duration of the clock signal and the data signal in the communication bus being low reaches a third preset duration, the retransmission chip determines that the self-checking is abnormal.

15. The communication control method according to any one of claims 11 to 14, wherein The method further comprises: After listening to one frame of the communication data, the retransmission chip calculates the parity bit of the communication data to obtain a first check bit; The retransmission chip collects the parity bit of the communication data to obtain a second check bit; If the first check bit is different from the second check bit, the retransmission chip determines that the self-checking is abnormal.

16. The communication control method according to any one of claims 11 to 15, wherein The method further comprises: If a difference between the voltage value indicated in the communication data and a preset voltage value is greater than a preset threshold value, the resend chip determines that a self-checking is abnormal.

17. The communication control method according to any one of claims 11 to 16, wherein The method further comprises: After the resend chip completes data resend once, the resend chip receives a preset feedback signal transmitted by the slave within a fourth preset time length; If the resend chip does not receive the preset feedback signal within the fourth preset time length after data resend twice in succession, the resend chip determines that a self-checking is abnormal.

18. The method of any one of claims 8 to 17, wherein, The fifth end of the resend chip is connected with the control end of the first switch, and the method further comprises: If it is determined that the resend chip is not abnormal, the host controls the first end and the second end of the first switch to be conductive, or the host does not control the first switch.

19. An electronic device, comprising: The communication module comprises an electrical device and the communication module as claimed in any one of claims 1 to 7. The slave is connected with the electrical device and is used to supply power to the electrical device; and the host is used to control a voltage output by the slave to the electrical device.

Images