Chip model and chip model expansion method

Abstract

The invention provides a chip model and an expansion method of the chip model. The chip model comprises an RISC-V function model (a core function module and an expansion control module). The core function module at least comprises an instruction decoder, an instruction executor, a register block and an external interrupt processor; the expansion control module at least comprises an instruction code expansion interface, an instruction execution expansion interface, a register expansion interface, a peripheral interface and an external interrupt interface; the instruction code expansion interface and the instruction execution expansion interface respectively register functions of custom instructions to the instruction decoder and the instruction executor based on respective corresponding preset interface specifications; the register expansion interface is used for registering a self-defined register in the register group based on a corresponding preset interface specification; the peripheral interface interacts with other function models through a transaction-level modeling protocol; and the external interrupt interface transmits interrupt signals sent by other function models and received through the TLM to an external interrupt processor in the core function module.

Description

Technical Field

[0001] This disclosure relates to the field of chips, and more particularly to a chip model and a method for extending the chip model. Background Technology

[0002] In the field of chip design and verification, the open-source instruction set architecture (Reduced Instruction Set Computer V, RISC-V) is widely used in chip development due to its open-source and flexible characteristics. In the early stages of chip model development, due to the limitations of hardware development schedules, the chip's software and compilers need to be developed and debugged based on the RISC-V functional model of the virtual prototyping platform.

[0003] However, when integrating existing RISC-V functional models into a virtual prototyping platform, the source code needs to be modified to adapt to different RISC-V architectures and to interact with other peripheral models within the virtual prototyping platform. This results in a large workload, a long development cycle, and poor scalability and portability of the RISC-V functional models. Summary of the Invention

[0004] This disclosure provides a chip model and a method for extending the chip model. Its main purpose is to solve the problems existing in the RISC-V functional model in terms of custom instruction set extension, peripheral interaction, and platform adaptation.

[0005] According to a first aspect of this disclosure, a chip model is provided, the chip model including a RISC-V functional model, wherein the RISC-V functional model includes: a core functional module and an extended control module; The core functional modules include at least an instruction decoder, an instruction executor, a register set, and an external interrupt handler; The extended control module includes at least an instruction code extension interface, an instruction execution extension interface, a register extension interface, a peripheral interface, and an external interrupt interface; The instruction code extension interface is configured to register custom instructions with the instruction decoder based on a preset instruction registration interface specification; The instruction execution extension interface is configured to register the execution function of the custom instruction with the instruction executor based on a preset instruction execution registration interface specification; The register extension interface is configured to register the custom registers accessed by the custom instructions with the register group based on a preset register interface specification. The peripheral interface is configured to interact with other functional models via a transaction-level modeling protocol; The external interrupt interface is configured to receive interrupt signals sent by other functional models through the transaction-level modeling protocol, and to pass the interrupt signals to the external interrupt processor in the core functional module.

[0006] In some embodiments, the instruction code extension interface is further configured to register the decoding function of the custom instruction with the instruction decoder based on a preset instruction registration interface specification.

[0007] In some embodiments, the instruction code extension interface is configured to call the instruction registration interface function to register the custom instruction and the decoding function to the instruction decoder, and the instruction registration interface specification is used to specify the structure of the custom instruction and the decoding function; The instruction execution extension interface is configured to call the instruction execution registration interface function to register the execution process of the custom instruction to the instruction executor. The instruction execution registration interface specification is used to standardize the structure of the execution process parameters of the custom instruction. The register extension interface is configured to call the register registration interface function to register the custom register to the register group, and the register interface specification is used to standardize the structure of the custom register parameters.

[0008] In some embodiments, the peripheral interface includes a multi-penetration initiator Socket, which is configured to bind at least one of the other functional models. The binding operation is performed by calling the bind method of the multi-penetration initiator Socket.

[0009] In some embodiments, the extended control module further includes: The architecture control unit controls the compilation scope of the core functional module through compilation options, so as to compile the instruction set and functions within the compilation scope of the core functional module.

[0010] In some embodiments, the core functional module further includes a bus; The bus is used for data transmission and address mapping of the other functional models.

[0011] According to a second aspect of this disclosure, a method for extending a chip model is provided, the method being applied to the chip model described in the first aspect above, comprising: Obtain custom instructions, wherein the structure of the custom instructions conforms to the instruction registration interface specification; Call the instruction registration interface function to register the custom instruction to the instruction decoder; Obtain the execution process parameters of the custom instruction, wherein the execution process parameters of the custom instruction conform to the instruction execution registration interface specification; The instruction execution registration interface function is called to register the execution process parameters of the custom instruction to the instruction executor.

[0012] In some embodiments, the method further includes: Obtain the decoding function of the custom instruction, wherein the structure of the decoding function conforms to the instruction registration interface specification; The instruction registration interface function registers the custom instruction to the instruction decoder, including: The custom instruction and the decoding function are registered to the instruction decoder by calling the instruction registration interface function.

[0013] In some embodiments, the method further includes: Obtain the custom register parameters of the custom register accessed by the custom instruction, wherein the structure of the custom register parameters conforms to the register interface specification; The custom register parameter is registered to the register group by calling the register registration interface function.

[0014] According to a third aspect of this disclosure, a method for extending a chip model is provided, the method being applied to the chip model described in the first aspect above, comprising: Bind at least one other functional module through the peripheral interface.

[0015] According to a fourth aspect of this disclosure, a method for extending a chip model is provided, the method being applied to the chip model described in the first aspect above, comprising: At least one other functional module is bound to an external interrupt interface to receive interrupt signals sent by at least one of the other functional modules.

[0016] According to a fifth aspect of this disclosure, an extension device for a chip model is provided, the device being applied to the chip model described in the first aspect above, comprising: The first acquisition unit is used to acquire custom instructions, wherein the structure of the custom instructions conforms to the instruction registration interface specification. The first registration unit is used to call the instruction registration interface function to register the custom instruction to the instruction decoder; The second acquisition unit is used to acquire the execution process parameters of the custom instruction, wherein the execution process parameters of the custom instruction conform to the instruction execution registration interface specification; The second registration unit is used to call the instruction execution registration interface function to register the execution process parameters of the custom instruction to the instruction executor.

[0017] In some embodiments, the apparatus further includes: The third acquisition unit is used to acquire the decoding function of the custom instruction, wherein the structure of the decoding function conforms to the instruction registration interface specification; The first registration unit is further configured to call the instruction registration interface function to register the custom instruction and the decoding function to the instruction decoder.

[0018] In some embodiments, the apparatus further includes: The fourth acquisition unit is used to acquire the custom register parameters of the custom register accessed by the custom instruction, wherein the structure of the custom register parameters conforms to the register interface specification; The third registration unit is used to call the register registration interface function to register the custom register parameters to the register group.

[0019] According to a sixth aspect of this disclosure, an extension device for a chip model is provided, the device being applied to the chip model described in the first aspect above, comprising: The first binding unit is used to bind at least one other functional module through the peripheral interface.

[0020] According to a seventh aspect of this disclosure, an extension device for a chip model is provided, the device being applied to the chip model described in the first aspect above, comprising: The second binding unit is used to bind at least one other functional module through an external interrupt interface to receive an interrupt signal sent by at least one of the other functional modules.

[0021] According to an eighth aspect of this disclosure, an electronic device is provided, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed, enable the at least one processor to perform the method described in any of the second, third, or fourth aspects described above.

[0022] According to a ninth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform the method described in any one of the second, third, or fourth aspects described above.

[0023] In summary, compared with related technologies, the solution disclosed herein enables the expansion of custom instructions and registers through the core functional modules and extended control modules in the RISC-V functional model. Specifically, the instruction code expansion interface, instruction execution expansion interface, and register expansion interface of the extended control module correspond to the instruction decoder, instruction executor, and register set of the core functional module, respectively. Each interface of the extended control module is predefined with preset interface specifications adapted to the corresponding core functional module. When expanding custom instructions and registers, each interface of the extended control module defines the function and register of the custom instruction according to the corresponding preset interface specifications. Then, the function and register of the custom instruction are registered to the instruction decoder, instruction executor, and register set of the corresponding core functional module through the corresponding interface of the extended control module. This expansion of custom instructions and registers can be completed without modifying the source code of the RISC-V functional model, improving the development and debugging efficiency of the chip model. Furthermore, the solution disclosed herein can also achieve interaction between the RISC-V functional model and other functional models by using transaction-level modeling protocols to build peripheral interfaces and external interrupt interfaces, improving the portability of the RISC-V functional model when integrated into different virtual prototyping platforms.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0025] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 A block diagram of a chip model provided in an embodiment of this disclosure; Figure 2 A schematic flowchart illustrating a chip model extension method provided in an embodiment of this disclosure; Figure 3 A flowchart illustrating another method for extending a chip model provided in this embodiment of the present disclosure; Figure 4 A flowchart illustrating another method for extending a chip model provided in this embodiment of the present disclosure; Figure 5 A schematic flowchart illustrating a chip model extension method provided in an embodiment of this disclosure; Figure 6 A schematic flowchart illustrating a chip model extension method provided in an embodiment of this disclosure; Figure 7 A schematic diagram of the structure of an expansion device for a chip model provided in an embodiment of this disclosure; Figure 8A schematic diagram of the structure of an expansion device for another chip model provided in an embodiment of this disclosure; Figure 9 A schematic diagram of the structure of an expansion device for a chip model provided in an embodiment of this disclosure; Figure 10 A schematic diagram of the structure of an expansion device for a chip model provided in an embodiment of this disclosure; Figure 11 This is a schematic block diagram of an example electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0026] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0027] The chip model and its extension method according to embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0028] Figure 1 This is a block diagram of a chip model provided in an embodiment of the present disclosure.

[0029] like Figure 1 As shown, the chip model includes a RISC-V functional model, wherein the RISC-V functional model includes: a core functional module 11 and an extended control module 12, wherein: The core functional module 11 includes at least an instruction decoder 111, an instruction executor 112, a register group 113, and an external interrupt processor PLIC 114.

[0030] In some embodiments, the core functional module 11 is used to implement the standard functions of the RISC-V functional model; the instruction decoder 111 is used to decode the instructions of the RISC-V functional model and call the instruction executor 112 according to the decoded instructions; the instruction executor 112 is used to implement the specific behavior of the instructions of the RISC-V functional model; the register group 113 mainly includes RISC-V standard integer, floating-point, vector registers and control status registers, provides register access interface for the instruction executor 112, and supports the registration of custom registers through the register extension interface; the external interrupt processor 114 is used to receive and process interrupt signals from other functional models.

[0031] Optionally, the core functional module 11 further includes a bus 115 and an interrupt processor CLINT 116; wherein, the bus 115 is used to realize data transmission and address mapping of peripherals; the interrupt processor 116 is used to process software-triggered interrupts and interrupt signals generated by timers.

[0032] The extended control module 12 includes at least an instruction code extension interface 121, an instruction execution extension interface 122, a register extension interface 123, a peripheral interface 124, and an external interrupt interface 125.

[0033] The instruction code extension interface 121 is configured to register custom instructions with the instruction decoder 111 based on a preset instruction registration interface specification.

[0034] In some embodiments, the instruction code extension interface 121 receives the definition of a custom instruction based on a preset instruction registration interface specification and registers the definition to the instruction set of the instruction decoder 111. After registration, the instruction decoder 111 can recognize and parse the custom instruction.

[0035] The instruction execution extension interface 122 is configured to register the execution function of the custom instruction with the instruction executor 112 based on a preset instruction execution registration interface specification.

[0036] In some embodiments, the instruction execution extension interface 122 receives the execution function corresponding to a custom instruction based on a preset instruction execution interface specification, and registers the execution function to the instruction executor 112. After registration, when the instruction decoder 111 recognizes the custom instruction, the instruction executor 112 can call the corresponding execution function to complete the instruction operation.

[0037] The register extension interface 123 is configured to register the custom registers accessed by the custom instructions to the register group based on a preset register interface specification.

[0038] In some embodiments, the register extension interface 123 receives the definition of a custom register based on a preset register interface specification and registers the custom register to the register group 113. After registration, the instruction executor 112 can access the custom register through the standard interface when executing custom instructions.

[0039] The preset interface specification is defined by the extension control module 12 and is used to standardize the user's usage. The preset interface specification may adopt, but is not limited to, a preset interface specification based on function pointers, a preset interface specification based on virtual function interfaces, or a preset interface specification based on configuration files to implement the standardized extension of custom instruction functions and custom registers by the extension control module 12. The specific form of the preset interface specification is not limited in the specific embodiments of this disclosure.

[0040] The peripheral interface 124 is configured to interact with other functional models via a transaction-level modeling protocol.

[0041] Transaction Level Modeling (TLM) is a standardized protocol for data interaction between modules. It achieves data transmission by defining a transaction structure (including address, data, operation type, etc.), without needing to concern itself with the underlying signal timing. It only needs to complete the initiation and reception of transactions through interface functions.

[0042] In some embodiments, peripheral interface 124 is implemented using the multi_passthrough_initiator_socket from the TLM2.0 standard. As a transaction initiator, it supports establishing connections with multiple other functional models simultaneously without limitation. When a connection to another functional model is needed, the peripheral interface 124 is bound to the target_socket of the other functional model using the bind method. After binding, data interaction between the core functional module 11 and other functional models is completed through peripheral interface 124.

[0043] The external interrupt interface 125 is configured to receive interrupt signals sent by the other functional models through the transaction-level modeling protocol, and to pass the interrupt signals to the external interrupt processor in the core functional module.

[0044] In some embodiments, the external interrupt interface 125 is implemented using the multi_passthrough_target_socket in the TLM2.0 standard. As a transaction receiver, it supports receiving interrupt signals from multiple other functional models simultaneously without limiting the number. When other functional models generate an interrupt, the interrupt signal is transmitted to the external interrupt processor 114 for processing through the external interrupt interface 125.

[0045] The chip model provided in this disclosure can expand custom instructions through the core functional modules and extended control modules in the RISC-V functional model. The instruction code expansion interface, instruction execution expansion interface, and register expansion interface of the extended control module correspond to the instruction decoder, instruction executor, and register set of the core functional module, respectively. Each interface of the extended control module is predefined with preset interface specifications adapted to the corresponding core functional module. When expanding custom instructions and registers, each interface of the extended control module defines the function of the custom instruction and the custom register according to the corresponding preset interface specifications. Then, the function of the custom instruction and the custom register are registered to the instruction decoder, instruction executor, and register set of the corresponding core functional module through the corresponding interface of the extended control module. This expansion of custom instructions and registers can be completed without modifying the source code of the RISC-V functional model, improving the development and debugging efficiency of the chip model. Furthermore, the peripheral interface and external interrupt interface built based on the transaction-level modeling protocol support the RISC-V functional model to flexibly access various peripheral models, enabling the RISC-V functional model to adapt to different virtual prototyping platforms and improving the portability and interactivity of the RISC-V functional model.

[0046] Optionally, the instruction code extension interface 121 is further configured to register the decoding function of the custom instruction with the instruction decoder 111 based on a preset instruction registration interface specification.

[0047] In some embodiments, when a custom instruction uses a new decoding function, the instruction code extension interface 121 receives the decoding function corresponding to the custom instruction based on a preset instruction registration interface specification, and registers the decoding function to the instruction decoder 111. After registration, when the instruction decoder 111 encounters the custom instruction, it will call the registered decoding function to parse the instruction.

[0048] In this way, the instruction code extension interface registers the custom instruction and its decoding function with the instruction decoder. When the instruction decoder receives the custom instruction later, it can call the registered decoding function to parse the custom instruction and output the decoding result to trigger the subsequent instruction execution process without modifying the original code logic of the instruction decoder.

[0049] Furthermore, the instruction code extension interface 121 is configured to call the instruction registration interface function to register the custom instruction and the decoding function to the instruction decoder 111, and the instruction registration interface specification is used to standardize the structure of the custom instruction and the decoding function.

[0050] In some embodiments, the instruction registration interface specification defines a data structure for describing custom instructions and their decoding functions. This structure includes, but is not limited to, the following fields: the opcode of the custom instruction and the corresponding decoding function pointer. The instruction code extension interface 121 calls the instruction registration interface function, taking the received structure instance conforming to the instruction registration interface specification as input parameters. By parsing the structure content, it adds the mapping relationship between the opcode of the custom instruction and the decoding function pointer to the instruction decoder 111.

[0051] The instruction execution extension interface 122 is configured to call the instruction execution registration interface function to register the execution process of the custom instruction to the instruction executor 112. The instruction execution registration interface specification is used to standardize the structure of the execution process parameters of the custom instruction.

[0052] In some embodiments, the instruction execution registration interface specification defines a data structure for describing parameters of a custom instruction execution process. This structure includes, but is not limited to, the following fields: the opcode of the custom instruction and the corresponding instruction execution function pointer. The instruction execution extension interface 122 calls the instruction execution registration interface function, taking the received structure instance conforming to the instruction execution registration interface specification as a parameter. By parsing this structure, the mapping relationship between the opcode of the custom instruction and the instruction execution function pointer is added to the instruction executor 112.

[0053] The register extension interface 123 is configured to call the register registration interface function to register the custom register to the register group 113, and the register interface specification is used to standardize the structure of the custom register parameters.

[0054] In some embodiments, the register interface specification defines a data structure for describing custom registers. This structure includes, but is not limited to, the following fields: register name, register type, register address range, and access control bits. The register extension interface 123 calls the register registration interface function, taking the received structure instance conforming to the register interface specification as input parameters. By parsing the structure content, it allocates a storage area of ​​a specified size within the address space of register group 113 and sets the corresponding access control attributes.

[0055] The above methods ensure the compatibility between the extended control module and the core functional module, and achieve standardization of custom instruction extensions.

[0056] To enhance the connectivity between the RISC-V functional model and other functional models, the peripheral interface includes a multi-penetration initiator socket, which is configured to bind to at least one of the other functional models. The binding operation is performed by calling the bind method of the multi-penetration initiator socket.

[0057] In some embodiments, the multi-penetration initiator Socket is a communication endpoint defined according to the TLM2.0 standard, providing multiple independent communication channels as a transaction initiator. When it is necessary to establish a connection between the RISC-V functional model and other functional models, the bind method provided by the multi-penetration initiator Socket is called to bind the Socket to the corresponding target Socket in the other functional model. The binding operation establishes a transaction transmission channel between the two, enabling the core functional module to initiate read and write transactions to the other bound functional models through this peripheral interface.

[0058] In this way, the RISC-V functional model achieves flexible connection with other external functional models through standardized multi-penetration initiator sockets. This connection mechanism supports binding multiple peripheral models simultaneously, and the binding operation is completed through the standard bind method without modifying the internal implementation of the RISC-V functional model, thus improving the scalability of the RISC-V functional model.

[0059] To improve the running speed of RISC-V functional models, such as Figure 1 As shown, the extended control module 12 further includes: The architecture control unit 126 controls the compilation scope of the core functional module 11 through compilation options, so as to compile the instruction set and functions within the compilation scope of the core functional module 11.

[0060] Among them, the compilation options (which can be configured via CMake or Makefile, and the configuration method of the compilation options is not limited in this embodiment) are used to limit the instruction set and functions that the core functional module 11 needs to retain. The architecture control unit 126 generates the corresponding compilation script by parsing these options, and then controls the compiler to compile only the code within the specified range.

[0061] In some embodiments, the architecture control unit 126 pre-sets conditional compilation macros in the code of the core functional module 11, with each macro corresponding to a type of instruction set or function. When the instruction set and functions that the core functional module 11 needs to retain are specified through compilation options, the architecture control unit 126 converts these options into macro definition parameters and passes them to the compiler.

[0062] By limiting the instruction set and functions of the core functional module 11 through the architecture control unit 126, redundant code is reduced and the running speed of the RISC-V functional model is improved.

[0063] Figure 2 This is a flowchart illustrating a chip model extension method provided in an embodiment of the present disclosure.

[0064] like Figure 2 As shown, the method includes the following steps: Step 201: Obtain the custom instruction, wherein the structure of the custom instruction conforms to the instruction registration interface specification.

[0065] In some embodiments, the definition information of custom instructions is read from user configuration or external files. This definition information is organized into a structure that conforms to the instruction registration interface specification, and the structure includes, but is not limited to, the opcode field and instruction format field of the custom instruction.

[0066] Step 202: Call the instruction registration interface function to register the custom instruction to the instruction decoder.

[0067] In some embodiments, a structure containing custom instruction definition information is sent as an input parameter to the instruction registration interface function. The instruction registration interface function parses the structure, extracts the opcode information, and creates a corresponding entry in the instruction decoder to complete the registration of the custom instruction.

[0068] Step 203: Obtain the execution process parameters of the custom instruction, wherein the execution process parameters of the custom instruction conform to the instruction execution registration interface specification.

[0069] In some embodiments, parameters describing the execution process of a custom instruction are obtained. These execution process parameters are organized into a structure conforming to the instruction execution registration interface specification. This structure includes, but is not limited to, the opcode field of the custom instruction and the corresponding execution function pointer field.

[0070] Step 204: Call the instruction execution registration interface function to register the execution process parameters of the custom instruction to the instruction executor.

[0071] In some embodiments, a structure containing execution process parameters is sent as an input parameter to the instruction execution registration interface function. The instruction execution registration interface function parses the structure content and registers the corresponding execution function pointer to the instruction executor according to the opcode, establishing a mapping relationship between opcode and execution function.

[0072] The method provided in this disclosure can register custom instructions with the instruction decoder and instruction executor through standardized interface functions and structured parameter passing. It can complete the expansion of custom instructions without modifying the source code of the RISC-V functional model, thereby improving the development and debugging efficiency of the chip model.

[0073] Figure 3 This is a flowchart illustrating a chip model extension method provided in an embodiment of the present disclosure, as shown below. Figure 3 As shown, the method includes the following steps: Step 301: Obtain the decoding function of the custom instruction, wherein the structure of the decoding function conforms to the instruction registration interface specification.

[0074] In some embodiments, a decoding function for a user-provided custom instruction is obtained. This decoding function is encapsulated in a structure conforming to the instruction registration interface specification. This structure includes, but is not limited to, the following fields: the opcode of the custom instruction and the corresponding decoding function pointer. The decoding function is responsible for parsing the encoding format of the custom instruction and extracting the operands and function code information from the custom instruction.

[0075] Step 302: Call the instruction registration interface function to register the custom instruction and the decoding function to the instruction decoder.

[0076] In some embodiments, a structure containing a custom instruction opcode and its corresponding decoding function is sent as an input parameter to the instruction registration interface function. The instruction registration interface function parses the structure and adds the mapping between the custom instruction opcode and the decoding function pointer to the instruction decoder. After registration is complete, the instruction decoder can call the registered decoding function to parse the instruction when it encounters the custom instruction.

[0077] The above method enables flexible expansion of the decoding logic and ensures compatibility between the custom instruction decoding process and the instruction decoder function.

[0078] Figure 4 This is a flowchart illustrating a chip model extension method provided in an embodiment of the present disclosure, as shown below. Figure 4 As shown, the method includes the following steps: Step 401: Obtain the custom register parameters of the custom register accessed by the custom instruction. The structure of the custom register parameters conforms to the register interface specification.

[0079] In some embodiments, a set of parameters describing custom register attributes is obtained from user configuration or external files. These parameters are organized into a structure conforming to the register interface specification, which includes, but is not limited to, the following fields: register identifier, register address mapping range, register bit width, and access control bits.

[0080] Step 402: Call the register registration interface function to register the custom register parameters to the register group.

[0081] In some embodiments, a structure instance containing custom register parameters is sent as input to the register registration interface function. The register registration interface function parses the parameters in the structure, allocates the corresponding storage area in the address space of the register group, and sets the corresponding access control policy according to the access control bits, thus completing the registration of the custom register in the register group.

[0082] In this way, the registration of custom registers can be completed without modifying the original code logic of the register set, ensuring that custom registers can be accurately accessed by custom instructions, and further supporting the implementation of custom instructions.

[0083] Figure 5 This is a flowchart illustrating a chip model extension method provided in an embodiment of the present disclosure.

[0084] like Figure 5 As shown, the method includes the following steps: Step 501: Bind at least one other functional module through the peripheral interface.

[0085] In some embodiments, the peripheral interface is implemented using the multi_passthrough_initiator_socket from the TLM2.0 standard, allowing connection to other functional models (i.e., other peripheral models) without limiting the number of connections. By calling the TLM2.0 bind method, the peripheral interface is bound to the target_socket of other peripheral models. When other peripheral models send interaction tasks, these tasks are transmitted in the form of TLM transactions, containing information such as operation type, target address, and data length. After receiving the TLM transaction, the peripheral interface, based on the operation type and target address in the TLM transaction, obtains the corresponding access permissions through the core functional module's bus, generates a TLM transaction containing response data or status information, and returns it to the other peripheral models via the peripheral interface, completing bidirectional data interaction.

[0086] Figure 6 This is a flowchart illustrating a chip model extension method provided in an embodiment of the present disclosure.

[0087] like Figure 6 As shown, the method includes the following steps: Step 601: Bind at least one other functional module through an external interrupt interface to receive an interrupt signal sent by at least one of the other functional modules.

[0088] In some embodiments, the external interrupt interface is implemented using the multi_passthrough_target_socket of the TLM2.0 standard. It can receive interrupt information from other functional models (i.e., other peripheral models), and there is no limit to the number of peripheral models. When an interrupt event occurs in another peripheral model, a TLM interrupt transaction containing information such as interrupt identifier and priority is generated and sent to the external interrupt interface via its own initiator_socket. After receiving the TLM interrupt transaction, the external interrupt interface parses the interrupt information in the TLM interrupt transaction into a signal format recognizable by the core functional module, and transmits it to the external interrupt handler (PLIC) of the core functional module through the internal signal link, which triggers the subsequent interrupt response process.

[0089] Using the above methods, the RISC-V functional model can interact with various peripheral models through standardized interfaces to transmit data and interrupt signals. Peripherals can be expanded without modifying the source code of the core functional modules, thus improving the interoperability of the RISC-V functional model.

[0090] Corresponding to the chip model extension method described above, this invention also proposes a chip model extension device. Since the device embodiments of this invention correspond to the method embodiments described above, details not disclosed in the device embodiments can be referred to in the method embodiments described above, and will not be repeated here.

[0091] Figure 7 This is a schematic diagram of the structure of an expansion device for a chip model provided in an embodiment of the present disclosure, as shown below. Figure 7 As shown, it includes: The first acquisition unit 71 is used to acquire custom instructions, wherein the structure of the custom instructions conforms to the instruction registration interface specification. The first registration unit 72 is used to call the instruction registration interface function to register the custom instruction to the instruction decoder; The second acquisition unit 73 is used to acquire the execution process parameters of the custom instruction, wherein the execution process parameters of the custom instruction conform to the instruction execution registration interface specification; The second registration unit 74 is used to call the instruction execution registration interface function to register the execution process parameters of the custom instruction to the instruction executor.

[0092] This device can register custom instructions with the instruction decoder and instruction executor through standardized interface functions and structured parameter passing. It can complete the expansion of custom instructions without modifying the source code of the RISC-V functional model, thus improving the development and debugging efficiency of the chip model.

[0093] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 8As shown, the device further includes: The third acquisition unit 75 is used to acquire the decoding function of the custom instruction, wherein the structure of the decoding function conforms to the instruction registration interface specification; The first registration unit 72 is also used to call the instruction registration interface function to register the custom instruction and the decoding function to the instruction decoder.

[0094] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 8 As shown, the device further includes: The fourth acquisition unit 76 is used to acquire the custom register parameters of the custom register accessed by the custom instruction, wherein the structure of the custom register parameters conforms to the register interface specification; The third registration unit 77 is used to call the register registration interface function to register the custom register parameters to the register group.

[0095] Figure 9 This is a schematic diagram of the structure of an expansion device for a chip model provided in an embodiment of the present disclosure, as shown below. Figure 9 As shown, it includes: The first binding unit 81 is used to bind at least one other functional module through the peripheral interface.

[0096] Figure 10 This is a schematic diagram of the structure of an expansion device for a chip model provided in an embodiment of the present disclosure, as shown below. Figure 10 As shown, it includes: The second binding unit 91 is used to bind at least one other functional module through an external interrupt interface to receive an interrupt signal sent by at least one of the other functional modules.

[0097] It should be noted that the foregoing explanation of the method embodiments also applies to the apparatus of the embodiments of this disclosure, and the principle is the same. Therefore, the embodiments of this disclosure are not limited thereto.

[0098] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0099] Figure 11 A schematic block diagram of an example electronic device 1000 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0100] like Figure 11 As shown, the electronic device 1000 includes a computing unit 1001, which can perform various appropriate actions and processes according to a computer program stored in ROM (Read-Only Memory) 1002 or loaded from storage unit 1008 into RAM (Random Access Memory) 1003. The RAM 1003 may also store various programs and data required for the operation of the electronic device 1000. The computing unit 1001, ROM 1002, and RAM 1003 are interconnected via bus 1004. An I / O (Input / Output) interface 1005 is also connected to bus 1004.

[0101] Multiple components in electronic device 1000 are connected to I / O interface 1005, including: input unit 1006, such as keyboard, mouse, etc.; output unit 1007, such as various types of displays, speakers, etc.; storage unit 1008, such as disk, optical disk, etc.; and communication unit 1009, such as network card, modem, wireless transceiver, etc. Communication unit 1009 allows electronic device 1000 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0102] The computing unit 1001 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), various special-purpose AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, DSPs (Digital Signal Processors), and any suitable processor, controller, microcontroller, etc. The computing unit 1001 performs the various methods and processes described above, such as chip model extension methods. For example, in some embodiments, chip model extension methods may be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 1008. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 1000 via ROM 1002 and / or communication unit 1009. When the computer program is loaded into RAM 1003 and executed by the computing unit 1001, one or more steps of the methods described above may be performed. Alternatively, in other embodiments, the computing unit 1001 may be configured to execute the extended methods of the aforementioned chip model by any other suitable means (e.g., by means of firmware).

[0103] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application-Specific Standard Products), SOCs (System-on-Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0104] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0105] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, EPROM (Electrically Programmable Read-Only Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0106] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (Cathode-Ray Tube) or LCD (Liquid Crystal Display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0107] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include LANs (Local Area Networks), WANs (Wide Area Networks), the Internet, and blockchain networks.

[0108] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service system that addresses the shortcomings of traditional physical hosts and VPS (Virtual Private Server) services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0109] It's important to note that artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0110] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0111] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A chip model, characterized by, The chip model comprises a RISC-V function model, wherein the RISC-V function model comprises a core function module and an extension control module; The core function module at least comprises an instruction decoder, an instruction executor, a register group, and an external interrupt processor; The extension control module at least comprises an instruction code extension interface, an instruction execution extension interface, a register extension interface, a peripheral interface, and an external interrupt interface; The instruction code extension interface is configured to register a custom instruction to the instruction decoder based on a preset instruction registration interface specification; The instruction execution extension interface is configured to register an execution function of the custom instruction to the instruction executor based on a preset instruction execution registration interface specification; The register extension interface is configured to register a custom register accessed by the custom instruction to the register group based on a preset register interface specification; The peripheral interface is configured to interact with other function models through a transaction-level modeling protocol; The external interrupt interface is configured to receive an interrupt signal sent by the other function models through the transaction-level modeling protocol and deliver the interrupt signal to the external interrupt processor in the core function module.

2. The chip model of claim 1, wherein, The instruction code extension interface is further configured to register a decoding function of the custom instruction to the instruction decoder based on the preset instruction registration interface specification.

3. The chip model of claim 2, wherein, The instruction code extension interface is configured to register the custom instruction and the decoding function to the instruction decoder by calling an instruction registration interface function, and the instruction registration interface specification is used to specify a structure of the custom instruction and the decoding function; The instruction execution extension interface is configured to register an execution process of the custom instruction to the instruction executor by calling an instruction execution registration interface function, and the instruction execution registration interface specification is used to specify a structure of an execution process parameter of the custom instruction; The register extension interface is configured to register the custom register to the register group by calling a register registration interface function, and the register interface specification is used to specify a structure of a custom register parameter.

4. The chip model of claim 1, wherein, The peripheral interface comprises a multi-penetration initiator Socket, which is configured to bind at least one of the other function models, and the binding operation is performed by calling a bind method of the multi-penetration initiator Socket.

5. The chip model of claim 1, wherein, The extension control module further comprises: An architecture control unit controls a compilation range of the core function module through a compilation option to compile an instruction set and a function in the compilation range of the core function module.

6. An extension method of a chip model, characterized by, The method is applied to the chip model of any one of claims 1-5, comprising: obtaining a custom instruction, a structure of the custom instruction conforming to an instruction registration interface specification; calling an instruction registration interface function to register the custom instruction to an instruction decoder; obtaining an execution process parameter of the custom instruction, the execution process parameter of the custom instruction conforming to an instruction execution registration interface specification; calling an instruction execution registration interface function to register the execution process parameter of the custom instruction to the instruction executor.

7. The method of claim 6, wherein, The method further comprises: obtaining a decoding function of the custom instruction, a structure of the decoding function conforming to the instruction registration interface specification; the calling instruction registration interface function registers the custom instruction to the instruction decoder, comprising: calling the instruction registration interface function to register the custom instruction and the decoding function to the instruction decoder.

8. The method of claim 7, wherein, The method further comprises: obtaining a custom register parameter of a custom register accessed by the custom instruction, a structure of the custom register parameter conforming to a register interface specification; calling a register registration interface function to register the custom register parameter to a register group.

9. An extension method of a chip model, characterized by, The method is applied to the chip model in any one of claims 1-5, comprising: binding at least one other functional module through a peripheral interface.

10. A method of extending a chip model, the method comprising: The method is applied to the chip model in any one of claims 1-5, comprising: binding at least one other functional module through an external interrupt interface to receive an interrupt signal sent by at least one of the other functional modules.

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