Timing constraint text checking method and device and electronic equipment

Abstract

The invention relates to the technical field of circuits, in particular to a timing constraint text checking method and device and electronic equipment. Obtaining at least one initial time sequence constraint text corresponding to the target circuit; identifying each initial time sequence constraint text, and extracting clock information corresponding to at least one target clock included in the target circuit; generating an initial clock tree structure according to the clock information corresponding to each target clock; checking each target clock according to the initial clock tree structure, and determining an error type corresponding to the initial clock tree structure; and according to the error type, correcting the initial clock tree structure to generate a target clock tree structure. Finally, an accurate and compliant clock tree is obtained, a reliable clock model is provided for subsequent time sequence analysis and chip function verification, and design errors and iteration cost are reduced. Therefore, high efficiency and accuracy of SDC verification are realized.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and more specifically to a method, apparatus, and electronic device for checking timing constraint text. Background Technology

[0002] In the chip design process, timing constraints are the core link to ensure chip functionality and performance. SDC (Synopsys Design Constraints), as an industry-standard description of timing constraints, directly determines the effectiveness of downstream processes such as synthesis, placement and routing, and timing analysis.

[0003] However, traditional SDC (Software Design Control) inspection methods have long relied on engineers manually checking text line by line. With the continuous increase in chip complexity, these methods have gradually revealed insurmountable limitations. Engineers need to trace clock hierarchy relationships and verify constraint logic in massive amounts of text, which not only consumes a lot of manpower and time and is inefficient, but is also very easy to miss potential errors due to human negligence. Especially for complex clock paths that cross modules and multiple levels, the accuracy of manual verification is difficult to guarantee.

[0004] More importantly, manual inspection cannot achieve efficient linkage verification between SDC constraints and the actual circuit structure. Therefore, existing manual inspection methods are no longer sufficient to meet the efficiency and accuracy requirements of complex chip designs for SDC verification, and a technical solution that also incorporates automated verification is urgently needed to overcome this pain point. Summary of the Invention

[0005] This invention provides a method, apparatus, and electronic device for checking time-constrained text, addressing the urgent need for a technical solution that also incorporates automated verification.

[0006] In a first aspect, the present invention provides a timing constraint text inspection method, the method comprising: acquiring at least one initial timing constraint text corresponding to a target circuit; identifying each initial timing constraint text and extracting clock information corresponding to at least one target clock included in the target circuit; generating an initial clock tree structure based on the clock information corresponding to each target clock; verifying each target clock based on the initial clock tree structure and determining the error type corresponding to the initial clock tree structure; and correcting the initial clock tree structure based on the error type to generate a target clock tree structure.

[0007] In one optional implementation, the initial timing constraint texts are identified, and clock information corresponding to at least one target clock included in the target circuit is extracted. This includes: preprocessing each initial timing constraint text to obtain each target timing constraint text; the preprocessing includes at least one of syntax format unification and dynamic parameter completion; generating master clock keywords based on the clock type corresponding to the target clock; the clock type includes a base clock and a derived clock; the derived clock is derived from the corresponding base clock; generating multiple auxiliary clock keywords based on the clock information corresponding to the target clock; the clock information corresponding to the base clock includes the clock name, clock frequency, clock creation point, clock duty cycle, and the stopping point of the base clock in the target circuit; the clock information corresponding to the derived clock includes the clock name, clock division ratio, clock creation point, clock duty cycle, the parent clock of the derived clock, and the stopping point of the derived clock in the target circuit; and extracting clock information corresponding to at least one target clock included in the target circuit from each target timing constraint text based on the master clock keywords and each auxiliary clock keyword.

[0008] In one optional implementation, clock information corresponding to at least one target clock included in the target circuit is extracted from each target timing constraint text based on the master clock keyword and each auxiliary clock keyword. This includes: for each target timing constraint text, identifying each statement in the target timing constraint text and detecting whether each statement contains a master clock keyword; identifying statements containing master clock keywords as candidate statements; determining the clock type corresponding to the candidate clock contained in the candidate statement based on the master clock keyword contained in the candidate statement; determining each auxiliary clock keyword corresponding to the candidate clock based on the clock type corresponding to the candidate clock; detecting whether the candidate statement contains at least one auxiliary clock keyword; if the candidate statement contains at least one auxiliary clock keyword, it is determined to be a valid clock statement; identifying the candidate clock corresponding to the valid clock statement as the target clock and determining the clock type corresponding to the target clock; and identifying the valid clock statement to determine the clock information corresponding to the target clock.

[0009] In one optional implementation, an initial clock tree structure is generated based on the clock information corresponding to each target clock, including: identifying the timing constraint text of each target clock to determine the target module corresponding to each target clock in the target circuit; selecting base clocks from each target clock according to the clock type corresponding to each target clock; determining the base clock corresponding to the top-level module as the main root node according to the target module corresponding to each base clock; determining the base clock corresponding to the non-top-level module as the secondary root node; placing the main root node at the top center of the tree structure; placing the target modules corresponding to each secondary root node on both sides of the main root node according to their distribution in the target circuit; determining the parent clock corresponding to each derived clock according to the derived clocks in each target clock; the parent clock is either a base clock or a derived clock; arranging each derived clock according to its position in the tree structure to generate the initial clock tree structure.

[0010] In one optional implementation, each target clock is verified according to the initial clock tree structure to determine the error type corresponding to the initial clock tree structure. This includes: checking whether each derived clock in the target clock has a corresponding parent clock in the initial clock tree structure; if the derived clock does not have a corresponding parent clock in the initial clock tree structure, the error type is determined to be a missing parent clock, and an alarm message is output; correspondingly, the initial clock tree structure is corrected according to the error type to generate a target clock tree structure, including: modifying the derived clocks without parent clocks to base clocks; or, obtaining the circuit structure reference data corresponding to the target circuit; adding base clocks to the derived clocks without parent clocks according to the circuit structure reference data; or, modifying the parent clock information of the derived clocks corresponding to the derived clocks without parent clocks.

[0011] In one optional implementation, each target clock is verified based on the initial clock tree structure to determine the error type corresponding to the initial clock tree structure, including: acquiring circuit structure reference data corresponding to the target circuit; searching for clock creation point information corresponding to each target clock in the circuit structure reference data; if the clock creation point information corresponding to the target clock cannot be found, the error type is determined to be a clock creation point mismatch in the target circuit, and an alarm message is output; correspondingly, the initial clock tree structure is corrected according to the error type to generate the target clock tree structure, including: Based on the circuit structure corresponding to the target circuit, modify the clock creation point information corresponding to the target clock for which no clock creation point information was found in the initial clock tree structure.

[0012] In one optional implementation, each target clock is verified according to the initial clock tree structure to determine the error type corresponding to the initial clock tree structure, including: filtering stop clocks marked with target stop points from each target clock; the target stop point is used to characterize the stop point of the stop clock in the target circuit; obtaining the global clock list in the circuit structure reference data corresponding to the target circuit; checking whether the first stop point corresponding to each recorded clock in the global clock list is consistent with the target stop point corresponding to each stop clock; if the first stop point corresponding to each recorded clock in the global clock list is inconsistent with the target stop point corresponding to each stop clock, the error type is determined to be no specified clock stop information, and an alarm message is output; correspondingly, the initial clock tree structure is corrected according to the error type to generate the target clock tree structure, including: if the clock name corresponding to the recorded clock in the global clock list is consistent with the clock name corresponding to the stop clock, the target stop point corresponding to the stop clock is corrected according to the first stop point corresponding to the recorded clock; or, if there is no clock name corresponding to the stop clock in the global clock list, the target stop point corresponding to the stop clock is deleted.

[0013] In one optional implementation, each target clock is verified based on the initial clock tree structure to determine the error type corresponding to the initial clock tree structure. This includes: obtaining the circuit structure reference data corresponding to the target circuit; verifying whether there is a physical connection between the derived clock in the target clock and the parent clock corresponding to the derived clock based on the physical node connectivity in the circuit structure reference data; if there is no physical connection between the derived clock and the parent clock corresponding to the derived clock, the error type is determined to be "no path between the generated clock and the parent clock"; and an alarm message is output; correspondingly, the initial clock tree structure is corrected according to the error type to generate the target clock tree structure, including: modifying the derived clock creation point corresponding to the derived clock; or, modifying the parent clock creation point corresponding to the parent clock corresponding to the derived clock.

[0014] In one optional implementation, each target clock is verified based on the initial clock tree structure to determine the error type corresponding to the initial clock tree structure. This includes: obtaining the circuit structure reference data corresponding to the target circuit; detecting whether each target clock is subsequently connected to a driving logic unit based on the clock driving logic table in the circuit structure reference data; if no driving logic unit is subsequently connected to the target clock, the error type is determined to be clock redundancy, and a prompt message is output; correspondingly, the initial clock tree structure is corrected according to the error type to generate the target clock tree structure, including: deleting subsequent target clocks that are not subsequently connected to a driving logic unit; or, modifying the clock creation point corresponding to the subsequent target clocks that are not subsequently connected to a driving logic unit.

[0015] Secondly, the present invention provides a temporal constraint text checking device, the device comprising: The acquisition module is used to acquire at least one initial timing constraint text corresponding to the target circuit; The extraction module is used to identify each initial timing constraint text and extract clock information corresponding to at least one target clock included in the target circuit; The generation module is used to generate an initial clock tree structure based on the clock information corresponding to each target clock. The verification module is used to verify each target clock according to the initial clock tree structure and determine the error type corresponding to the initial clock tree structure. The correction module is used to correct the initial clock tree structure according to the error type and generate the target clock tree structure.

[0016] Thirdly, the present invention provides an electronic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the timing constraint text checking method of the first aspect or any corresponding embodiment described above.

[0017] The timing constraint text checking method, apparatus, and electronic device provided in this application acquire at least one initial timing constraint text corresponding to the target circuit as the original basis for clock information extraction, ensuring that subsequent analysis has a complete source of constraints and laying the foundation for accurate clock model construction. Key clock parameters are accurately extracted from the initial timing constraint text, transforming unstructured text into structured data, providing clear data support for clock tree generation. Based on the clock information corresponding to each target clock, an initial clock tree structure is generated, visually presenting the hierarchical relationship between clocks and intuitively reflecting the clock distribution, facilitating subsequent verification and analysis. Each target clock is verified based on the initial clock tree structure, determining the error type corresponding to the initial clock tree structure, identifying problems in the initial clock tree structure, clarifying the root cause of errors, and providing direction for correction. Targeted corrections are performed for the error types, eliminating deviations between the clock model and the actual circuit, ultimately obtaining an accurate and compliant clock tree, providing a reliable clock model for subsequent timing analysis and chip functional verification, reducing design errors and iteration costs. This achieves high efficiency and accuracy in SDC verification. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating a time-constrained text checking method according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating another time-constrained text checking method according to an embodiment of the present invention; Figure 3 This is a structural block diagram of a timing-constrained text checking device according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0022] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0023] According to an embodiment of the present invention, a method for checking time-constrained text is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0024] This embodiment provides a time-constrained text inspection method, which can be used in electronic devices. Figure 1 This is a flowchart of a timing constraint text checking method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps: Step S101: Obtain at least one initial timing constraint text corresponding to the target circuit.

[0025] Specifically, the timing constraint text for the target circuit is usually an SDC (Synopsys Design Constraints) file, and may also contain constraint fragments in the form of TCL scripts. The file format (.sdc, .tcl) and version must be specified (such as the syntax specifications to be compatible with EDA tools (such as PrimeTime, Innovus).

[0026] Specifically, electronic devices can extract at least one timing constraint text from the constraint library of the chip design project. If the timing constraint text is scattered across multiple files (such as top-level constraints + submodule constraints), it needs to be merged hierarchically (such as importing the top-level constraints first, and then overlaying the submodule constraints) to ensure the integrity of the constraints.

[0027] Specifically, the electronic device can also receive at least one timing constraint text corresponding to the target circuit input by the user, or it can receive at least one timing constraint text corresponding to the target circuit sent by other devices.

[0028] This application does not specifically limit the method by which the electronic device obtains at least one initial timing constraint text corresponding to the target circuit.

[0029] Step S102: Identify each initial timing constraint text and extract clock information corresponding to at least one target clock included in the target circuit.

[0030] Specifically, the electronic device can use a text recognition method to identify each initial timing constraint text and extract clock information corresponding to at least one target clock included in the target circuit.

[0031] This step will be explained in detail below.

[0032] Step S103: Generate an initial clock tree structure based on the clock information corresponding to each target clock.

[0033] Specifically, electronic devices can generate an initial clock tree structure based on the clock information corresponding to each target clock and the position of each target clock in the target circuit.

[0034] This step will be explained in detail below.

[0035] Step S104: Verify each target clock according to the initial clock tree structure to determine the error type corresponding to the initial clock tree structure.

[0036] Specifically, the electronic device can acquire the circuit structure reference data corresponding to the target circuit. Then, based on the circuit structure reference data corresponding to the target circuit, it verifies each target clock in the initial clock tree structure to determine the error type corresponding to the initial clock tree structure.

[0037] This step will be explained in detail below.

[0038] Step S105: Based on the error type, correct the initial clock tree structure to generate the target clock tree structure.

[0039] Specifically, electronic devices can correct the initial clock tree structure based on the error type and a preset correction method to generate a target clock tree structure.

[0040] This step will be explained in detail below.

[0041] The timing constraint text checking method provided in this embodiment obtains at least one initial timing constraint text corresponding to the target circuit as the original basis for clock information extraction, ensuring that subsequent analysis has a complete source of constraints and laying the foundation for accurate clock model construction. Key clock parameters are accurately extracted from the initial timing constraint text, transforming unstructured text into structured data, providing clear data support for clock tree generation. Based on the clock information corresponding to each target clock, an initial clock tree structure is generated, visually presenting the hierarchical relationship between clocks and intuitively reflecting the clock distribution, facilitating subsequent verification and analysis. Each target clock is verified based on the initial clock tree structure, determining the error type corresponding to the initial clock tree structure, identifying problems in the initial clock tree structure, clarifying the root cause of errors, and providing direction for correction. Targeted corrections are performed for the error types, eliminating deviations between the clock model and the actual circuit, ultimately obtaining an accurate and compliant clock tree, providing a reliable clock model for subsequent timing analysis and chip functional verification, reducing design errors and iteration costs. This achieves high efficiency and accuracy in SDC verification.

[0042] This embodiment provides a time-constrained text inspection method, which can be used in electronic devices. Figure 2 This is a flowchart of a timing constraint text checking method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps: Step S201: Obtain at least one initial timing constraint text corresponding to the target circuit.

[0043] For details on this step, please refer to the description of step S101 above, which will not be repeated here.

[0044] Step S202: Identify each initial timing constraint text and extract clock information corresponding to at least one target clock included in the target circuit.

[0045] Specifically, step S202 above may include the following steps: Step S2021: Preprocess each initial time series constraint text to obtain each target time series constraint text.

[0046] Preprocessing includes at least one of the following: syntax format standardization and dynamic parameter completion.

[0047] Specifically, electronic devices can standardize syntax rules to avoid recognition biases when dealing with timing constraint texts from different sources. For example, an electronic device can convert keywords (such as create_clock, create_generated_clock, -name, -source) in all constraint statements in the timing constraint text to lowercase (or uppercase), such as unifying Create_Clock to create_clock and -Name to -name.

[0048] Electronic devices can unify the path representation method (e.g., unify {top / clk_in} and top / clk_in into the format {top / clk_in} with curly braces) and the frequency / period unit (e.g., unify 10ns and 100MHz into the period format, with 100MHz corresponding to a period of 10ns).

[0049] In addition, electronic devices split compound statements (such as splitting create_clock-nameclk1-period10[get_portsclk1_in];create_clock-nameclk2... into two independent statements) and remove redundant separators between statements (such as extra semicolons and spaces).

[0050] Specifically, for key parameters missing in the timing constraint text (such as unspecified duty cycle and default division ratio), electronic devices can complete them based on industry standards and common sense in circuit design.

[0051] For example, if the `create_clock` statement does not specify `-duty_cycle` (duty cycle), it defaults to 50%; if it does not specify `-waveform` (waveform), it defaults to `{0 5}` (a 5ns high level for a 10ns period). If the `create_generated_clock` statement does not specify `-divide_by` (division ratio) or `-multiply_by` (multiplication ratio), it is completed based on the frequency of the parent clock (`-source`) and the actual purpose of the derived clock (e.g., if the parent clock is 100MHz, the derived clock defaults to a division ratio of 2, i.e., 50MHz). If the clock creation point path (e.g., `[get_portsclk_in]`) does not specify the module level, it is completed by combining the top-level module name of the target circuit (e.g., `[get_ports{top / clk_in}]`). After preprocessing, a uniformly formatted and parameter-complete "target timing constraint text" is obtained, ensuring the accuracy of subsequent keyword recognition.

[0052] Step S2022: Generate master clock keywords based on the clock type corresponding to the target clock.

[0053] The clock types include base clocks and derived clocks; derived clocks are derived from the corresponding base clocks.

[0054] Specifically, electronic devices can generate the master clock keyword corresponding to the target clock based on the correspondence between clock type and master clock keyword.

[0055] For example, the base clock is defined by the create_clock statement and is used to describe the original clock source in the circuit (such as crystal oscillator input, PLL output); the derived clock is defined by the create_generated_clock statement and is generated based on the base clock by frequency division, frequency multiplication, or phase shift (such as the frequency division clock in the submodule).

[0056] Electronic devices can determine the primary keywords for two types of clocks based on the above correspondence: primary keyword for the base clock: create_clock (uniquely identifies the base clock definition statement); primary keyword for the derived clock: create_generated_clock (uniquely identifies the derived clock definition statement).

[0057] Finally, the electronic device generates a list of master clock keywords: ["create_clock" "create_generated_clock"], which is used for filtering subsequent statements.

[0058] Step S2023: Generate multiple auxiliary clock keywords based on the clock information corresponding to the target clock.

[0059] The clock information corresponding to the base clock includes the clock name, clock frequency, clock creation point, clock duty cycle, and the stopping point of the base clock in the target circuit; the clock information corresponding to the derived clock includes the clock name, clock division ratio, clock creation point, clock duty cycle, the parent clock of the derived clock, and the stopping point of the derived clock in the target circuit.

[0060] Specifically, the core information of the base clock includes: clock name, clock frequency (period), clock creation point, clock duty cycle, and stop point. The corresponding auxiliary clock keywords are as follows: Clock name: -name (parameter defining the clock name); Clock frequency / period: -period (period parameter, frequency can be calculated from the period); Clock creation point: get_ports, get_pins (path functions specifying the creation point); Clock duty cycle: -duty_cycle (duty cycle parameter); Stop point: stop_propagation (statement associated with stopping clock propagation), -clock (clock name parameter associated with the stop point).

[0061] Then, the electronic device extracts the clock information fields of the derived clock. The derived clock, based on the basic clock information, adds "parent clock" and "division ratio," and the corresponding auxiliary clock keywords are as follows: Auxiliary clock keywords inherited from the base clock: Clock name: -name (parameter defining the clock name); Clock creation point: get_ports, get_pins (path functions specifying the creation point); Clock duty cycle: -duty_cycle (duty cycle parameter); Stop point: stop_propagation (statement associated with stopping clock propagation), -clock (clock name parameter associated with the stop point). Specific auxiliary clock keywords: -source (parameter specifying the parent clock), -divide_by (division ratio parameter), -multiply_by (multiplication ratio parameter).

[0062] Finally, the electronic device generates a list of auxiliary clock keywords (categorized by type): Basic clock auxiliary clock keywords: ["-name", "-period", "get_ports", "get_pins", "-duty_cycle", "stop_propagation", "-clock"]. Derivative clock auxiliary clock keywords: ["-name", "-duty_cycle", "get_ports", "get_pins", "stop_propagation", "-clock", "-source", "-divide_by", "-multiply_by"].

[0063] Step S2024: Based on the master clock keyword and each auxiliary clock keyword, extract the clock information corresponding to at least one target clock included in the target circuit from each target timing constraint text.

[0064] Specifically, step S2024 above may include the following steps: Step a1: For each target timing constraint text, identify each statement in the target timing constraint text and detect whether each statement contains the master clock keyword.

[0065] Specifically, the electronic device iterates through each statement in the target timing constraint text (preprocessed and split into independent statements). For each statement, a string match is performed to check if it contains `create_clock` (the primary keyword for the base clock) or `create_generated_clock` (the primary keyword for the derived clock). Example: The statement `create_clock -name clk_top-period 10 [get_ports {top / clk_in}]` containing `create_clock` is marked as a candidate statement.

[0066] Step a2: Identify statements containing the master clock keyword as candidate statements.

[0067] Specifically, the electronic device identifies statements containing the keyword "master clock" as candidate statements. Then, it collects all statements containing the keyword "master clock" to form a "candidate statement list." The electronic device filters invalid key keyword scenarios: if the key keyword in a statement is only a comment (e.g., # create_clock is used for base clock), the statement is excluded. For example, the candidate statement list includes two types of statements: create_clock ... and create_generated_clock ....

[0068] Step a3: Determine the clock type corresponding to the candidate clock contained in the candidate statement based on the master clock keyword contained in the candidate statement.

[0069] Specifically, the electronic device can determine the type of the primary keyword contained in each statement in the candidate statement list: if it contains `create_clock`, the candidate clock type is "basic clock"; if it contains `create_generated_clock`, the candidate clock type is "derived clock". For example, the statement `create_generated_clock -name clk_sub -source[get_clocks clk_top]...` contains the primary keyword "derived clock", and the candidate clock type is "derived clock".

[0070] Step a4: Determine the auxiliary clock keywords corresponding to each candidate clock based on the clock type of the candidate clock.

[0071] Specifically, if the candidate clock type is "basic clock", the "basic clock auxiliary clock keyword list" is invoked. If the candidate clock type is "derived clock", the "derived clock auxiliary clock keyword list" is invoked. For example, the derived clock candidate statement matches specific auxiliary clock keywords such as -source and -divide_by.

[0072] Step a5: Detect whether the candidate statement contains at least one auxiliary clock keyword.

[0073] Specifically, for each candidate statement, the electronic device iterates through its list of matching auxiliary clock keywords, checking for the presence of at least one keyword by determining string inclusion relationships (e.g., whether the statement contains parameters such as -name or -period). Example: The basic clock candidate statement `create_clock -name clk_top ...` contains `-name`, thus passing the auxiliary clock keyword check; if the statement is simply `create_clock` (without any parameters), it does not contain any auxiliary clock keywords.

[0074] Step a6: If at least one auxiliary clock keyword is among the candidate statements, then it is determined to be a valid clock statement.

[0075] Specifically, if a candidate statement contains at least one auxiliary clock keyword, it is determined to be a "valid clock statement" (meeting the basic conditions for extracting clock information). If a candidate statement does not contain any auxiliary clock keywords, it is determined to be an "invalid clock statement" (such as create_clock;, which has no actual parameters and cannot extract information), and the statement is excluded. Example: create_clock-name clk_top -period 10 [get_ports {top / clk_in}] includes -name and -period.

[0076] Step a7: Determine the candidate clocks corresponding to the valid clock statements as the target clocks, and determine the clock type corresponding to the target clocks.

[0077] Specifically, the electronic device determines the candidate clock corresponding to the valid clock statement as the "target clock" and retains the determined clock type (base clock / derived clock).

[0078] For example, the valid statement create_generated_clock -name clk_sub ... corresponds to the target clock "clk_sub" and the type "derived clock".

[0079] Step a8: Identify valid clock statements and determine the clock information corresponding to the target clock.

[0080] Specifically, if the target clock corresponds to a base clock, the electronic device identifies the valid clock statement corresponding to the target clock and determines the clock information corresponding to the base clock.

[0081] Basic clock information extraction: Clock name: extracted from the -name parameter (e.g., -name clk_top, then the name is "clk_top"); Clock frequency: calculated from the -period parameter (e.g., -period 10, then the period is 10ns, then the frequency is 100MHz); Clock creation point: extracted from the path after get_ports or get_pins (e.g., [get_ports {top / clk_in}], then the creation point is "top / clk_in"); Clock duty cycle: extracted from the -duty_cycle parameter (e.g., -duty_cycle50, then 50%); Stop point: extracted from the associated stop_propagation statement (e.g., stop_propagation -clockclk_top [get_pins {top / reg / clk}], then the stop point is "top / reg / clk").

[0082] If the target clock corresponds to a derived clock, the electronic device identifies the valid clock statement corresponding to the target clock and determines the clock information corresponding to the derived clock.

[0083] Extraction of derived clock information: Inherits the extraction logic of the base clock: extract name, creation point, duty cycle, and stop point; Parent clock of derived clock: extracted from the -source parameter (e.g., -source [get_clocks clk_top], then the parent clock is "clk_top"); Clock division ratio: extracted from the -divide_by parameter (e.g., -divide_by 2, then the division ratio is 2).

[0084] The electronic device generates a target clock information table, which contains all extracted target clocks and their corresponding types and detailed parameters (such as name, frequency, creation point, etc.), providing data support for the subsequent generation of the initial clock tree structure.

[0085] Step S203: Generate an initial clock tree structure based on the clock information corresponding to each target clock.

[0086] Specifically, step S203 above may include the following steps: Step S2031: Identify the timing constraint texts of each target and determine the target module corresponding to each target clock in the target circuit.

[0087] Specifically, the electronic device can obtain the "clock creation point" of each target clock from the target clock information table (e.g., the creation point of the base clock clk_top is "top / clk_in", and the creation point of the derived clock clk_sub1 is "top / sub1 / clk_out").

[0088] The electronic device then splits the creation point path hierarchically (using " / " as the separator). The first segment of the creation point path is the top-level module (usually fixed as "top" or a circuit name, such as "chip_top"). Starting from the second segment, the creation point path becomes a sub-module hierarchy, taking the closest direct sub-module to the creation point as the "target module".

[0089] Example 1: Create a point "top / clk_in" containing only the top-level module, with the target module being "top-level module". Example 2: Create a point "top / sub1 / div / clk_out" with the direct child module "sub1" and the target module being "sub1". Example 3: Create a point "top / sub2 / reg / clk" with the direct child module "sub2" and the target module being "sub2".

[0090] Next, the electronic device establishes a mapping relationship between the "target clock" and the "target module," generating a mapping table that records the target module corresponding to each clock. An example "target clock - target module" mapping table is as follows: Table 1 “Target Clock - Target Module” Mapping Table

[0091] Step S2032: Select the base clock from each target clock according to the clock type corresponding to each target clock.

[0092] Specifically, the electronic device extracts the "Clock Type" field (base clock / derived clock) for each clock from the "Target Clock Information Table". All target clocks with "Clock Type = Base Clock" are retained to form a "Base Clock List", while derived clocks are excluded (to be processed as branch nodes later). For example, the base clock list contains "clk_top" and "clk_sub2_base", serving as a candidate set for the root node of the clock tree.

[0093] Step S2033: Based on the target modules corresponding to each base clock, determine the base clock corresponding to the top-level module as the main root node.

[0094] Specifically, the electronic device uses the "target clock-target module" mapping table to match a target module for each clock in the "base clock list". If the target module of the base clock is the "top-level module" (e.g., the target module of clk_top is the "top-level module"), then it is determined as the "main root node".

[0095] It should be noted that the base clock of the top-level module is usually a global clock source (such as a crystal oscillator input). If there are multiple top-level base clocks (such as a dual clock source design), they are all used as the main root node (and subsequently arranged in order of frequency).

[0096] Finally, the electronic device generates a list of primary root nodes (such as [clk_top]).

[0097] Step S2034: Determine the base clock corresponding to the non-top-level module as the secondary root node.

[0098] Specifically, the electronic device excludes the primary root node from the "base clock list," and the target modules of the remaining base clocks are all "non-top-level modules" (such as sub2), which are then determined as "secondary root nodes." For example, if the target module of clk_sub2_base is sub2 (non-top-level), then it is determined as a secondary root node. The electronic device outputs a list of secondary root nodes (such as [clk_sub2_base]).

[0099] Step S2035: Place the root node at the top center of the tree structure.

[0100] The tree structure uses a preset coordinate system with the X-axis horizontal (negative on the left, positive on the right) and the Y-axis vertical (negative at the top, positive at the bottom, with the top layer having the smallest Y value); the unit is pixels (px), with the default top layer Y coordinate being 50px and the horizontal center X coordinate being 500px.

[0101] Specifically, if there is only one root node, its coordinates are fixed at (500, 50), located at the top center of the tree structure. If there are multiple root nodes (e.g., clk_top1, clk_top2), the electronic devices can be arranged horizontally from high to low frequency, centered (total width = number of nodes × 200px, centered distribution). Example: two root nodes with coordinates (400, 50) and (600, 50). The electronic device outputs a root node layout diagram, including coordinate information (e.g., clk_top: (500, 50)).

[0102] Step S2036: For each secondary root node, place the target modules corresponding to the secondary root nodes on both sides of the main root node according to their distribution in the target circuit.

[0103] Specifically, electronic devices can determine the distribution area of ​​the target module corresponding to each secondary root node from the structural design of the target circuit (e.g., left region: sub1, sub3; right region: sub2, sub4).

[0104] For the secondary root node of the target module in the left area, place it to the left of the main root node, with a horizontal spacing of 200px and vertical alignment with the main root node (Y=50).

[0105] For example, the secondary root node of sub1, clk_sub1_base, has coordinates (300, 50); the secondary root node of sub3, clk_sub3_base, has coordinates (100, 50).

[0106] For the secondary root node of the target module in the right area, place it to the right of the main root node, with a horizontal spacing of 200px and vertical alignment with the main root node.

[0107] For example, the secondary root node of sub2, clk_sub2_base, has coordinates (700, 50); the secondary root node of sub4, clk_sub4_base, has coordinates (900, 50).

[0108] Within the same area, the target modules are arranged alphabetically by name to ensure an orderly layout. Finally, the electronic device generates a secondary root node layout diagram, including coordinate information (e.g., clk_sub2_base: (700, 50)).

[0109] Step S2037: Determine the parent clock corresponding to each derived clock based on the derived clocks in each target clock.

[0110] The parent clock is either the base clock or a derived clock.

[0111] Specifically, the electronic device obtains the parent clock of the derived clock from the target clock information table, such as the parent clock of clk_sub1 being clk_top.

[0112] If the parent clock name is in the "base clock list" (e.g., clk_top is the base clock), then the parent clock is the "base clock" (root node).

[0113] If the parent clock name is a determined derived clock (e.g., the parent clock of clk_sub1_div is clk_sub1), then the parent clock is a "derived clock" (branch node).

[0114] For example, the parent clock of clk_sub1 is clk_top (the base clock); the parent clock of clk_sub1_div2 is clk_sub1 (the derived clock).

[0115] Electronic devices generate a "derived clock - parent clock" association table, specifying the parent node of each derived clock.

[0116] Step S2038: Arrange each derived clock according to the position of its parent clock in the tree structure to generate the initial clock tree structure.

[0117] Specifically, electronic devices can group derived clocks according to the parent clock hierarchy.

[0118] Among them, the first-level derived clock is a derived clock whose parent clock is the root node (basic clock) (e.g., the parent clock of clk_sub1 is clk_top); the second-level derived clock is a derived clock whose parent clock is the first-level derived clock (e.g., the parent clock of clk_sub1_div2 is clk_sub1); and so on, forming a hierarchical sequence of derived clocks.

[0119] The electronic device lays out each derived clock according to the hierarchical sequence of derived clocks. Vertical hierarchy: child node hierarchy = parent node hierarchy + 1, with a fixed vertical spacing of 100px (e.g., parent node Y=50, child node Y=150).

[0120] If the target module of the derived clock is the same as that of the parent clock (e.g., the parent clock target module is sub1, and the derived clock target module is sub1): the horizontal coordinate is the same as that of the parent node (X remains unchanged), and the vertical distribution is as follows.

[0121] If the target module of the derived clock is different from that of the parent clock (across modules, such as the top-level target module of the parent clock and the sub1 target module of the derived clock): it will be horizontally offset to the corresponding module area (such as the parent node X=500, sub1 is on the left, and the derived clock X=300).

[0122] Electronic devices can use straight lines to connect child nodes and parent nodes, with solid lines used within the same module and dashed lines used across modules.

[0123] Next, the electronic device arranges the derived clocks at each level layer by layer. For the first-level derived clock, the root node is used as the parent node, and after being horizontally offset according to the distribution of the target modules, it is placed at level Y=150. For example, the parent node clk_top (X=500, Y=50) of clk_sub1 (target module sub1) is placed at (300, 150), connected by a solid line. For the second-level derived clock, the first-level derived clock is used as the parent node, and the X value remains the same for the same target module, and it is placed at level Y=250. For example, the parent node clk_sub1 (X=300, Y=150) of clk_sub1_div2 (target module sub1) is placed at (300, 250), connected by a solid line; and so on, until all derived clocks are arranged.

[0124] Finally, the electronic device integrates the coordinates, hierarchy, and parent-child relationships of the root node and derived nodes, and labels node attributes (e.g., the base clock is circular, derived clocks are rectangular; the primary root node is dark green, secondary root nodes are light green, and derived clocks are blue). The electronic device generates a visual tree structure (such as SVG or image format), including nodes, paths, and brief parameters (name, frequency). Finally, the electronic device outputs the initial clock tree structure (including node layout, hierarchy, and path connections).

[0125] Step S204: Verify each target clock according to the initial clock tree structure to determine the error type corresponding to the initial clock tree structure.

[0126] Step S205: Based on the error type, correct the initial clock tree structure to generate the target clock tree structure.

[0127] In an optional embodiment of this application, step S204 may include the following steps: Step b1: Check if each derived clock in the target clock has a corresponding parent clock in the initial clock tree structure.

[0128] Specifically, the electronic device filters out all nodes with "clock type = derived clock" from the "target clock information table" and obtains the "derived clock parent clock" name of each derived clock (e.g., the parent clock of clk_sub1 is clk_top, and the parent clock of clk_sub2 is clk_undef).

[0129] The electronic device traverses all nodes (including the root node and branch nodes) of the initial clock tree structure and checks if there is a node with the exact same name as the parent clock of the derived clock. If a node with the same name exists and its level is above the derived clock node (parent node level < child node level), then it is determined that "the parent clock exists"; if no node with the same name exists, or if a node exists but its level does not match (e.g., parent node level ≥ child node level), then it is determined that "the parent clock is missing".

[0130] For example, the parent clock of the derived clock clk_sub2 is clk_undef. If there is no clk_undef node in the initial clock tree structure, it is determined that the parent clock is missing.

[0131] Step b2: If the derived clock does not have a corresponding parent clock in the initial clock tree structure, the error type is determined to be missing parent clock, and an alarm message is output.

[0132] Specifically, if the derived clock does not have a corresponding parent clock in the initial clock tree structure, the electronic device marks the error type as "parent clock missing" (ERROR type error).

[0133] Then, the electronic device generates an alarm message, which must include the following key information: error type: "ERROR - Parent clock missing"; derived clock information: name, module, position (coordinates or level) in the initial clock tree; missing parent clock information: parent clock name, expected level.

[0134] For example, ERROR - Parent clock missing: The parent clock clk_undef of derived clock clk_sub2 (module sub2, level 2) does not exist in the initial clock tree. Please check the timing constraints or clock tree structure.

[0135] The electronic devices output alarm information in the form of text logs and mark the corresponding derived clock nodes with red flashing in the initial clock tree visualization diagram to facilitate quick location.

[0136] Correspondingly, step S205, which corrects the initial clock tree structure according to the error type and generates the target clock tree structure, may include the following steps: Step b3: Modify the derived clock that does not have a parent clock to the base clock.

[0137] Specifically, in the "Target Clock Information Table", the electronic device changes the "Clock Type" of the derived clock from "Derived Clock" to "Base Clock" and deletes derived clock-specific fields such as "Derived Clock Parent Clock" and "Clock Division Ratio".

[0138] Furthermore, in the target timing constraint text, the electronic device replaces the `create_generated_clock` statement corresponding to the derived clock with the `create_clock` statement, supplementing the basic clock parameters (such as `-period`). Original statement: `create_generated_clock -name clk_sub2 -source [get_clocks clk_undef] -divide_by 2[get_pins {sub2 / clk_out}]`. Modified statement: `create_clock -name clk_sub2 -period 20 [get_pins {sub2 / clk_out}]`.

[0139] The electronic device migrates the derived node from the derived clock branch node to the root node level, making it a secondary root node (if its target module is not a top-level module). It is placed in the corresponding module area according to the secondary root node layout rules (e.g., if the sub2 module is on the right, it is placed to the right of the main root node); the original derived clock path connection is deleted, its own child nodes (if any) are retained, and the child node hierarchy is adjusted accordingly (if originally second-level, then first-level).

[0140] or, Step b4: Obtain the circuit structure reference data corresponding to the target circuit.

[0141] Specifically, electronic devices can extract the circuit structure reference data corresponding to the target circuit related to the parent clock from the target circuit design database. The core data includes: the creation point path that the parent clock should have (e.g., the actual creation point of clk_undef is "top / pll / clk_out"); the frequency parameters of the parent clock (e.g., the PLL output frequency is 200MHz); and the target module where the parent clock is located (e.g., "top-level module").

[0142] Step b5: Based on the circuit structure reference data, add a base clock for the derived clock that does not have a parent clock.

[0143] Specifically, electronic devices can add parent clock definitions in the timing constraint text based on circuit structure reference data. That is, a new create_clock statement is added to define the missing parent clock, such as create_clock -name clk_undef -period 5 [get_ports {top / pll / clk_out}] (frequency 200MHz, period 5ns).

[0144] The electronic device adds a parent clock node in the initial clock tree structure. If the parent clock target module is the top-level module, it is placed at the center top level as the main root node according to step S2035 (e.g., coordinates (500, 50). If there is already a main root node, it is offset horizontally).

[0145] If it is not a top-level module, it will be placed in the corresponding module area as a secondary root node according to step S2036.

[0146] In the "Derived Clock - Parent Clock" association table, the electronic device binds the derived clock (e.g., clk_sub2) that originally lacked a parent clock to the newly added parent clock (clk_undef). Following rule S2038, the electronic device is laid out with the newly added parent clock as the reference (e.g., if the parent clock is at the top level, then the derived clock clk_sub2 (sub2 module) is placed at the right-hand Y=150 level), and the connection between the derived clock and the parent clock is drawn (dashed lines are used across modules).

[0147] or, Step b6: Modify the parent clock information of the derived clock that does not have a parent clock.

[0148] Specifically, electronic devices select valid clocks (base clocks or other derived clocks) that have a physical path connection with the derived clock based on circuit structure reference data and design intent.

[0149] For example, the parent clock of the derived clock clk_sub2 is mistakenly written as clk_undef, but should actually point to the main root node clk_top (the two are physically connected).

[0150] In the target timing constraint text, the electronic device modifies the -source parameter of the create_generated_clock statement. For example, the original statement is: create_generated_clock -name clk_sub2 -source [get_clocks clk_undef] ..., and the modified statement is: create_generated_clock -name clk_sub2 -source[get_clocks clk_top]....

[0151] Next, in the "Derived Clock - Parent Clock" association table, the electronic device changes the parent clock of clk_sub2 from clk_undef to clk_top. Using the new parent clock (clk_top) as a reference, it rearranges the layout according to step S2038 (e.g., if clk_top is at the top center, then clk_sub2 (sub2 module) is placed at the right-hand Y=150 level). The electronic device deletes the invalid connections of the original erroneous parent clock and draws the connection to the new parent clock.

[0152] In an optional embodiment of this application, step S204 may include the following steps: Step c1: Obtain the circuit structure reference data corresponding to the target circuit.

[0153] Specifically, electronic devices can extract the circuit structure reference data corresponding to the target circuit related to the parent clock from the target circuit design database. The core data includes: the creation point path that the parent clock should have (e.g., the actual creation point of clk_undef is "top / pll / clk_out"); the frequency parameters of the parent clock (e.g., the PLL output frequency is 200MHz); and the target module where the parent clock is located (e.g., "top-level module").

[0154] Step c2: Locate the clock creation point information corresponding to each target clock in the circuit structure reference data.

[0155] Specifically, the electronic device obtains the "clock creation point" path of all target clocks (base clock and derived clock) from the "target clock information table" (e.g., the creation point of the base clock clk_top is "top / clk_in", and the creation point of the derived clock clk_sub1 is "sub1 / clk_out").

[0156] Then, the electronic device checks whether there is an entry in the "physical node list" of the circuit structure reference data that is exactly the same as the creation point path (e.g., "sub1 / clk_out" must be a complete match, while "sub1 / CLK_OUT" or "top / sub1 / clk_out" are considered to be non-matches). If the path matches, further confirm that the node type is a "clock node" (excluding data nodes to avoid misusing data signals as clocks).

[0157] For example, if the creation point of the target clock clk_sub1 is "sub1 / clk_out", and the query finds that there is only "sub1 / clk_buf_out" in the circuit, then the match fails.

[0158] Step c3: If the clock creation point information corresponding to the target clock cannot be found, the error type is determined to be that the clock creation point failed to match in the target circuit, and an alarm message is output.

[0159] Specifically, for target clocks in the "Clock Creation Point Matching Table" where "Matching Result = Failure" (including "Path Does Not Exist" or "Node Type is Not Clock"), the electronic device marks the error type as "Clock creation point failed to match in the target circuit" (ERROR type error).

[0160] Then, the electronic device generates an alarm message, which must include the following key information: Error type: "ERROR - Clock creation point matching failed"; Target clock information: name, clock type (base clock / derived clock), module; Creation point information: target creation point path, the most similar existing path in the baseline data (for easy correction).

[0161] For example, ERROR - Clock creation point match failed: The creation point "sub1 / clk_out" for the derived clock clk_sub1 (module sub1) does not exist in the circuit structure, and the most similar path is "sub1 / clk_buf_out" (clock node).

[0162] The alarm information is output in the form of a text log, and the corresponding clock node is highlighted in red in the initial clock tree visualization, while the missing creation point path is also marked.

[0163] Correspondingly, in step S205, the initial clock tree structure is corrected according to the error type to generate the target clock tree structure, including: Step c4: Based on the circuit structure corresponding to the target circuit, modify the clock creation point information corresponding to the target clock that failed to find clock creation point information in the initial clock tree structure.

[0164] Specifically, based on the circuit structure reference data, the electronic device can select alternative creation points that meet the following conditions in the initial clock tree structure for the target clock that failed to match, according to the circuit structure corresponding to the target circuit: the path exists in the "physical node list"; the node type is "clock node"; and it belongs to the same target module as the original creation point (e.g., if the original creation point belongs to the sub1 module, the alternative point must also be in the sub1 module).

[0165] Electronic devices can preferentially select nodes with similar names to the original path and on the clock propagation path (such as replacing the original "sub1 / clk_out" with "sub1 / clk_buf_out", both of which belong to the clock path of the sub1 module).

[0166] Then, the electronic device updates the creation point parameters in the target timing constraint text, corrects the constraint statement corresponding to the target clock, and replaces the path after get_ports or get_pins with a valid alternative point.

[0167] For example, the original statement (derived clock clk_sub1): create_generated_clock -name clk_sub1 -source [get_clocks clk_top] [get_pins {sub1 / clk_out}]. Modified: create_generated_clock -name clk_sub1 -source [get_clocks clk_top] [get_pins {sub1 / clk_buf_out}].

[0168] Next, the electronic device updates the "Clock Creation Point" of the target clock in the "Target Clock Information Table" to the alternative path. If the module where the creation point is located remains unchanged: the clock's position (coordinates) in the initial clock tree remains unchanged, and only the "Creation Point Path" attribute label of the node is updated; if the module where the creation point is located changes (in rare cases, such as when it was originally sub1 but was mistakenly written as sub2 and corrected to sub1): the clock node coordinates are adjusted according to the new module position (e.g., moving from the right area to the left area). If the modification of the creation point causes a change in the path, it is necessary to recheck whether there is a physical connection between the two (to avoid introducing new "path missing" errors).

[0169] In an optional embodiment of this application, step S204 may include the following steps: Step d1: Select the stop clock marked with the target stop point from the target clocks.

[0170] The target stopping point is used to characterize the stopping point of the stopping clock in the target circuit.

[0171] Specifically, electronic devices can filter out target clocks (both base clocks and derived clocks) that contain a "stop point" field from the "target clock information table". These clocks are called "stop clocks", and the path recorded in their "stop point" field is the "target stop point" (e.g., the target stop point of clock clk_sub1 is "sub1 / reg / clk").

[0172] The electronic device marks the relationship between the stop clock and the target stop point to generate a "stop clock-target stop point" mapping table, which clarifies the target stop point path and the source of the constraint statement corresponding to each stop clock (such as which timing constraint text the stop_propagation statement comes from).

[0173] Step d2: Obtain the global clock list from the circuit structure reference data corresponding to the target circuit.

[0174] Specifically, electronic devices can extract valid information from circuit structure reference data, including: recorded clock names: all clocks that actually exist in the circuit (such as clk_top, clk_sub1, etc.); first stopping point: the actual stopping node path reached by each recorded clock in the circuit (i.e., the clock stops after propagating to this node, determined by physical connection and logic design); node validity identifier: marking whether the first stopping point is a valid physical node (such as "valid" or "invalid").

[0175] Step d3: Check whether the first stop point corresponding to each recorded clock in the global clock list is consistent with the target stop point corresponding to each stop clock.

[0176] Specifically, the electronic device uses the "clock name" as the key to match the "stop clock - target stop point" mapping table with the "global clock list".

[0177] If the stop clock name has a corresponding recorded clock name in the global clock list (e.g., clk_sub1 exists in both), then path comparison begins. If the stop clock name does not exist in the global clock list (e.g., clk_sub3 is not in the global list), then it is directly marked as "clock does not exist". The consistency of the stop point path is compared. For stop clocks and recorded clocks with matching names, the paths of the target stop point and the first stop point are precisely compared: if they are completely identical (e.g., both are "sub1 / reg / clk"), then the consistency match is successful; if they are partially identical but have differences (e.g., target stop point "sub2 / buf / clk_stop" vs first stop point "sub2 / reg / clk_stop"), then the consistency match fails; if the first stop point of the recorded clock is invalid (e.g., the path does not exist), then the consistency match fails.

[0178] The electronic device records the test results and generates a "Stop Point Consistency Test Table", as shown in Table 2 below: Table 2 Stop Point Consistency Detection Table

[0179] Step d4: If the first stop point corresponding to each recorded clock in the global clock list is inconsistent with the target stop point corresponding to each stop clock, then the error type is determined to be no specified clock stop information, and an alarm signal is output.

[0180] Specifically, for stopped clocks in the "Stop Point Consistency Detection Table" where "Detection Result = Inconsistent" or "Detection Result = Clock Does Not Exist", the electronic device marks the error type as "No Specified Clock Stop Information" (ERROR type error).

[0181] Electronic devices generate alarm information, which must include the following key information: Error type: "ERROR - No specified clock stop information"; Stop clock information: name, target stop point path; Problem details: If the clock exists, it indicates the difference between the target stop point and the first stop point; if the clock does not exist, it indicates that the clock is not in the global clock list.

[0182] Example 1 (Path Inconsistency): ERROR - No Specified Clock Stop Information: The target stop point "sub2 / buf / clk_stop" of the stop clock clk_sub2 is inconsistent with the actual first stop point "sub2 / reg / clk_stop". Example 2 (Clock Does Not Exist): ERROR - No Specified Clock Stop Information: The stop clock clk_sub3 does not exist in the global clock list, and its target stop point "sub3 / clk_stop" is invalid.

[0183] The electronic device outputs alarm information in the form of a text log, and marks the target stop point of the corresponding stop clock in red in the initial clock tree visualization (e.g., mark "invalid stop point" next to the node).

[0184] Correspondingly, in step S205, the initial clock tree structure is corrected according to the error type to generate the target clock tree structure, including: Step d5: If the clock name corresponding to the recorded clock in the global clock list is the same as the clock name corresponding to the stopped clock, then correct the target stop point corresponding to the stopped clock according to the first stop point corresponding to the recorded clock.

[0185] Specifically, the electronic device retrieves the first stop point of the recorded clock that matches the stop clock name from the global clock list and verifies the validity of its node (it must be in a "valid" state, such as "sub2 / reg / clk_stop" being a valid physical node).

[0186] The target stop point path in the `stop_propagation` statement of the electronic device's updated target timing constraints is modified and replaced with the first stop point. For example, the original statement is: `stop_propagation -clock clk_sub2[get_pins {sub2 / buf / clk_stop}]`. The modified statement is: `stop_propagation -clock clk_sub2 [get_pins {sub2 / reg / clk_stop}]`.

[0187] Next, in the initial clock tree structure, the electronic device updates the target stop point marker corresponding to the stopped clock from the original path to the first stop point path, deletes the erroneous markers, and marks the correct stop point position with an orange solid line (the connection with the clock node remains unchanged).

[0188] or, Step d6: If there is no clock name corresponding to the stop clock in the global clock list, then delete the target stop point corresponding to the stop clock.

[0189] Specifically, the electronic device can verify that the stop clock name does not exist in the global clock list (e.g., clk_sub3 does not actually exist in the circuit and is a misdefined clock), and that no actual clock arrives at its target stop point path.

[0190] The electronic device removes the stop_propagation statement corresponding to the stop clock from the target timing constraint text (e.g., delete stop_propagation -clock clk_sub3 [get_pins {sub3 / clk_stop}]).

[0191] In the initial clock tree structure visualization, delete the target stop point marker and related connections (if any) for the stopped clock in the electronic device to ensure that only valid constraint information is retained in the clock tree.

[0192] In an optional embodiment of this application, step S204 may include the following steps: Step e1: Obtain the circuit structure reference data corresponding to the target circuit.

[0193] Specifically, electronic devices can extract the circuit structure reference data corresponding to the target circuit related to the parent clock from the target circuit design database. The core data includes: the creation point path that the parent clock should have (e.g., the actual creation point of clk_undef is "top / pll / clk_out"); the frequency parameters of the parent clock (e.g., the PLL output frequency is 200MHz); and the target module where the parent clock is located (e.g., "top-level module").

[0194] Step e2: Based on the physical node connectivity in the circuit structure reference data, verify whether there is a physical connection between the derived clock in the target clock and the parent clock corresponding to the derived clock.

[0195] Specifically, electronic devices can obtain the creation point path of the derived clock (e.g., the creation point of clk_sub is "sub1 / B2") from the "target clock information table"; and the creation point path of the corresponding parent clock (e.g., the creation point of the parent clock clk_top is "top / A0").

[0196] Then, the electronic device checks the "Node Connection Table" to see if there is a direct connection between the derived clock creation point and the parent clock creation point (e.g., whether "A0→B2" is directly connected). If there is no direct connection, it checks the "Path Connectivity Matrix" to see if there is an indirect path (e.g., "A0→A1→A2→B2"), and all intermediate nodes in the path are devices that allow clock propagation (e.g., buffers, trigger clock terminals). If the two creation points belong to different modules (e.g., top and sub1), it is necessary to confirm that the path passes through a valid module interface node (e.g., "top / sub1_interface") to avoid isolated nodes across modules.

[0197] Then, the electronic device generates a "derived clock-parent clock path verification table", as shown in Table 3 below: Table 3 Derivative Clock-Parent Clock Path Verification Table

[0198] Step e3: If there is no physical connection between the derived clock and its corresponding parent clock, the error type is determined to be "no path between the generated clock and the parent clock"; and an alarm message is output.

[0199] Specifically, for derived clocks in the "Derived Clock-Parent Clock Path Verification Table" where "Verification Result = No Path", the electronic device marks the error type as "No path between the generated clock and the parent clock" (ERROR type error).

[0200] Electronic devices generate alarm information, which must include the following key information: Error type: "ERROR - No path between the generated clock and the parent clock"; Clock pair information: derived clock name and creation point, parent clock name and creation point; Path details: indicating that there is no direct or indirect connection between the two (the nearest intermediate node can be attached, such as "A0's nearest node is A1, B2's nearest node is B1, A1 and B1 are not connected"). For example, ERROR - No path between the generated clock and the parent clock: There is no direct or indirect connection between the derived clock clk_sub2 (creation point sub1 / B2) and the parent clock clk_top (creation point top / A0). The reachable nodes of A0 are A1 / A2, and the reachable node of B2 is B1, and the two have no intersection.

[0201] The electronic device outputs alarm information in the form of a text log, and marks the original path with a red dashed line in the initial clock tree visualization (marked "invalid path"), while highlighting the two creation point nodes.

[0202] Correspondingly, in step S205, the initial clock tree structure is corrected according to the error type to generate the target clock tree structure, including: Step e4: Modify the derivative clock creation point corresponding to the derivative clock.

[0203] Specifically, based on circuit structure reference data, the electronic device selects nodes within the module to which the derived clock belongs that meet the following conditions as new creation points: they have a valid physical path (direct or indirect connection) with the parent clock creation point; they are nodes on the clock propagation path (such as clock buffer output, frequency divider output); and they have similar functions to the original creation point (such as both being clock branch points within a submodule).

[0204] For example, a new creation point "A3" is selected for clk_sub2 (original creation point B2). This node has a path "A0→A1→A3" with the parent clock creation point A0.

[0205] Next, the electronic device corrects the target timing constraint text, changing the creation point path in the `create_generated_clock` statement to a new node, such as: Original statement: `create_generated_clock -name clk_sub2 -source[get_clocks clk_top] [get_pins {sub1 / B2}]`. Modified statement: `create_generated_clock -name clk_sub2 -source [get_clocks clk_top] [get_pins {sub1 / A3}]`.

[0206] In addition, electronic devices update the "Target Clock Information Table" to replace the "Clock Creation Point" field of the derived clock.

[0207] Finally, in the initial clock tree structure, the derived clock nodes are moved from their original positions (corresponding coordinates of B2) to the corresponding coordinates of the newly created point A3 (adjusted according to the module layout rules), invalid path connections are deleted, and connections from the parent clock node to the newly derived clock node are drawn (solid lines represent valid paths). The connection validity between the newly created point and the parent clock creation point is confirmed again through the physical node connectivity.

[0208] or, Step e5: Modify the parent clock creation point corresponding to the parent clock of the derived clock.

[0209] Specifically, based on circuit structure reference data, the electronic device selects nodes on the parent clock propagation path that meet the following conditions as new creation points: there is a valid physical path with the derived clock creation point; it is located upstream of the module to which the derived clock belongs (ensuring that the clock propagation direction is reasonable); and it maintains the ability to drive other child clocks (if the parent clock also drives other derived clocks, it is necessary to ensure that the new creation point also has a path with these clocks).

[0210] For example, the parent clock clk_top originally created point A0 (which has no path to the derived clock clk_sub2's B2), and then a new point "A2" is created. This node has a path "A2→B1→B2" with B2.

[0211] Next, the electronic device corrects the target timing constraint text by changing the creation point path in the `create_clock` statement of the parent clock (base clock) to the new node. For example: Original statement: `create_clock -name clk_top -period 10[get_ports {top / A0}]`. Modified statement: `create_clock -name clk_top -period 10 [get_pins{top / A2}]`.

[0212] In addition, the electronic device updates the "Target Clock Information Table" and replaces the "Clock Creation Point" field of the parent clock.

[0213] In the initial clock tree structure, the parent clock node is moved from its original position (coordinates corresponding to A0) to the corresponding coordinates of the newly created point A2. The connections between the parent clock and all derived clocks (including clk_sub2 and other child clocks) are redrawn to ensure that they are all valid paths; the connections between the newly created point of the parent clock and the creation points of all derived clocks that depend on it are checked to avoid introducing new path missing errors.

[0214] In an optional embodiment of this application, step S204 may include the following steps: Step f1: Obtain the circuit structure reference data corresponding to the target circuit.

[0215] Specifically, electronic devices can extract the circuit structure reference data corresponding to the target circuit related to the parent clock from the target circuit design database. The core data includes: the creation point path that the parent clock should have (e.g., the actual creation point of clk_undef is "top / pll / clk_out"); the frequency parameters of the parent clock (e.g., the PLL output frequency is 200MHz); and the target module where the parent clock is located (e.g., "top-level module").

[0216] Step f2: Based on the clock drive logic table in the circuit structure reference data, detect whether each target clock is subsequently connected to a drive logic unit.

[0217] Specifically, the electronic device obtains the "clock creation point" path of all target clocks (base clocks and derived clocks) from the "target clock information table" (e.g., the creation point of clk_spare is "top / spare / clk").

[0218] The clock-driven logic table is queried, and the following checks are performed for each creation point of the target clock: Existence of driving unit: Check in the "Clock Drive Logic Table" whether there is a corresponding "List of Driving Units" for this creation point.

[0219] Driver validity: If a driver unit exists, determine whether it contains valid sequential logic (such as a clock connection of at least one flip-flop); if only an idle unit is connected (such as an unused buffer) or there is no unit, it is considered "no valid driver".

[0220] For example, the creation point "top / spare / clk" of the target clock clk_spare has no driver unit in the driver logic table → it is determined as "no driver logic unit connected".

[0221] The electronic device records the test results and generates a "clock-driven logic test table".

[0222] In step f3, if no driving logic unit is subsequently connected to the target clock, the error type is determined to be clock redundancy, and a prompt message is output.

[0223] Specifically, when a target clock is detected to be not connected to valid drive logic, it is determined to be redundant and a warning is issued. The specific operation is as follows: For target clocks with "Detection Result = No" in the "Clock Drive Logic Detection Table", the error type is marked as "Clock Redundancy" (WARNING type error, non-fatal but requires optimization).

[0224] The electronic device generates a warning message, which must include the following key information: Error type: "WARNING - Clock Redundancy"; Redundant clock information: name, clock type (basic / derived), creation point path; Reason for redundancy: explanation of no valid drive logic (e.g., "no downstream drive unit" or "only connected to idle buffer").

[0225] For example, WARNING - Clock Redundancy: The base clock clk_spare (creation point top / spare / clk) is not connected to any valid drive logic unit, which may be a misdefined or reserved clock.

[0226] Correspondingly, in step S205, the initial clock tree structure is corrected according to the error type to generate the target clock tree structure, including: Step f4: Delete the target clock that is not connected to the driving logic unit.

[0227] Specifically, the electronic device removes the clock creation statement from the target timing constraint text. If it is a base clock: delete the corresponding create_clock statement (e.g., create_clock -name clk_spare ...); if it is a derived clock: delete the corresponding create_generated_clock statement, and check if there are any dependent child derived clocks (if so, they need to be processed synchronously or their parent clock needs to be adjusted).

[0228] In the initial clock tree structure visualization of the electronic device, delete the redundant clock node and all its child nodes (if they are derived clocks). Clear the path connections and attribute labels associated with the node; or, Step f5: Modify the clock creation point corresponding to the target clock that is not connected to the driving logic unit.

[0229] Specifically, when the redundant clock is a reserved clock (which may be enabled in the future) or when there is no drive due to an incorrect creation point selection, the creation point is adjusted to make it connect to valid logic.

[0230] The selection of valid creation points for electronic devices is based on circuit structure reference data. To select a new creation point path for redundant clocks, the following conditions must be met: the downstream of the creation point must be connected to valid driving logic (such as flip-flops or active buffers); it must belong to the same module as the original creation point (to avoid logic confusion caused by cross-module migration); if it is a reserved clock, the new creation point can be connected to a "to be enabled" logic unit (such as an unwired but designed flip-flop).

[0231] For example, if the original creation point of the redundant clock clk_sub3 is "sub3 / clk_div" (without a driver), then the new creation point is "sub3 / clk_buf" (driven by sub3 / reg2 / clk).

[0232] Next, the creation point parameter of the creation point correction clock definition statement in the timing constraints of the electronic device is updated. For example, the original statement (base clock): create_clock -name clk_sub3 -period 15 [get_pins{sub3 / clk_div}], is modified to: create_clock -name clk_sub3 -period 15 [get_pins{sub3 / clk_buf}].

[0233] Finally, in the initial clock tree structure, the electronic device migrates the clock node from its original creation point to the coordinates corresponding to the new creation point, updates the node's "clock creation point" attribute label, and deletes the "redundant clock" marker.

[0234] The timing constraint text inspection method provided in this application preprocesses the initial timing constraint text, eliminating format differences between constraint texts from different sources, avoiding subsequent recognition deviations, and ensuring the integrity of clock information, laying the foundation for accurate extraction. It generates master clock keywords to quickly locate the definition statements of two types of clocks, improving the efficiency and accuracy of clock recognition. It generates auxiliary clock keywords to refine the extraction dimensions, ensuring complete capture of key clock parameters. It detects whether statements contain master clock keywords, quickly filtering out potentially clock-related statements, excluding irrelevant content, narrowing the processing scope, and improving efficiency. It identifies candidate statements, focusing on statements containing master keywords, initially locking in potential clock definition statements, laying the foundation for subsequent accurate recognition. It determines the type of candidate clock, distinguishing between basic clocks and derived clocks based on master keywords, clarifying the clock's hierarchical attributes, and providing a basis for subsequent classification processing. It calls dedicated auxiliary keywords for different types of clocks to ensure the relevance and completeness of extracted parameters. It verifies whether candidate statements contain valid parameters, filtering out empty statements without actual information to ensure the validity of extracted content. Through auxiliary keyword verification, it confirms that statements contain sufficient clock information, preventing invalid data from entering subsequent processes. Clearly define the clocks that need to be processed and their types to ensure the accuracy of the core objects used in clock tree construction. Extract clock parameters in a structured manner from valid statements to provide accurate and complete data for clock tree generation, ensuring the reliability of subsequent steps.

[0235] Next, identify the target module corresponding to the target clock, clarifying the module affiliation of each clock to provide a basis for the subsequent module-based layout of the clock tree and avoid cross-module confusion. Screen basic clocks to accurately locate candidate root nodes of the clock tree, clarifying the core anchor points of the clock hierarchy to ensure the rationality of the tree structure. Determine the main root node, using the basic clock of the top-level module as the core to ensure the global clock source is centrally located in the tree, conforming to the circuit clock propagation logic. Determine secondary root nodes to distinguish independent basic clocks of non-top-level modules, avoiding root node confusion and adapting to design scenarios with multiple independent clock sources for multiple modules. Place the main root node to fix the position of the core node, providing a benchmark for subsequent node layout and ensuring the clock tree structure is symmetrical and intuitive. Place secondary root nodes, distributing them according to modules to fit the circuit physical structure, reduce cross-regional path intersections, and facilitate visualization and understanding. Establish the relationship between derived clocks and parent clocks, clarifying clock hierarchy dependencies and laying the foundation for the branch node layout of the tree structure. The derived clocks are arranged layer by layer according to the position of the parent node, forming a complete hierarchical tree structure, which intuitively presents the dependencies and distribution between clocks, and provides a clear visual model for subsequent verification and correction.

[0236] Next, the electronic device checks the existence of the parent clock of the derived clock. By verifying the association between the derived clock and the parent clock, it identifies breaks in the clock hierarchy in advance, avoiding the construction of a clock tree with logical errors. It determines if a parent clock is missing and issues an alarm, clearly defining the error type and providing timely feedback to help quickly locate the root cause of the problem and provide a clear direction for correction. Derived clocks without a parent clock are modified to base clocks, suitable for scenarios where the clock is actually an independent source. Adjusting the type eliminates hierarchical contradictions and simplifies the clock tree structure. Based on the circuit structure baseline data, base clocks are added to derived clocks without a parent clock. For cases where the parent clock exists but is not defined, the base clock definition is supplemented to improve the clock hierarchy chain and ensure that derived clocks have a reasonable source. Parent clock information is modified: this resolves issues such as incorrect parent clock names or pointers, rebuilds the correct hierarchical association, and makes the clock tree conform to the actual circuit logic.

[0237] Optionally, acquire circuit structure baseline data to provide a "benchmark standard" for the actual physical nodes of the circuit, providing an objective basis for verifying the authenticity of clock creation points and ensuring the accuracy of verification results. Locate the creation point information of the target clock and verify whether the clock creation point actually exists in the circuit by comparing it with the baseline data, avoiding the construction of clock trees based on fictitious nodes and reducing model errors from the source. Determine creation point matching failures and issue alarms to promptly identify creation point path errors, pinpoint the error location, and provide prompts to help quickly locate the problem. Correct the clock creation point information by adjusting erroneous creation points according to the actual circuit structure, ensuring that clock nodes correspond to physical nodes in the circuit, guaranteeing that the clock tree reflects the actual circuit connections, and providing accurate physical references for subsequent timing analysis and placement / routing.

[0238] Optionally, filter and mark the stopping clocks of the target stopping point: Focus on the clocks that need to be verified for stopping propagation constraints, clarify the verification object, avoid interference from clocks without stopping points, and improve verification efficiency. Obtain a global clock list to provide reference data of the actual clocks and their stopping points in the circuit, providing an objective basis for verifying the validity of the stopping points and ensuring the accuracy of the verification standard. By comparing the target stopping point with the actual first stopping point, path errors in the stopping constraints can be found, avoiding timing analysis based on erroneous constraints. Determine if there is no specified clock stopping information and issue an alarm to promptly identify problems such as stopping point mismatch or clock non-existence, clarify the error location and provide a clear direction for correction. Correct the target stopping point according to the first stopping point: When the current clock exists but the stopping point is incorrect, make the stopping constraints consistent with the actual circuit, ensuring that the clock propagation stopping rules accurately reflect the physical connection. Alternatively, delete invalid target stopping points: When the stopping clock does not exist in the circuit, clear invalid constraints to avoid redundant information interfering with the clock tree and ensure the model is simple and accurate.

[0239] Optionally, obtain circuit structure baseline data: This provides the actual connection relationships of the circuit's physical nodes, offering an objective basis for verifying the authenticity of the clock path and ensuring the accuracy of the verification. Verify the physical connection between the derived clock and the parent clock. By checking their connectivity, identify "broken links" in the clock hierarchy in advance, avoiding the construction of a path model that does not match the actual circuit. Determine missing paths and issue alarms, promptly identifying errors where the derived clock and parent clock have no physical connection, pinpointing the problem location and providing a precise direction for correction. Modify the derived clock creation point: By adjusting the creation point of the derived clock to a node with a physical connection to the parent clock, a valid path is reconstructed, ensuring that the clock hierarchy conforms to the actual circuit connection logic. Alternatively, modify the parent clock creation point: By adjusting the creation point of the parent clock to a node that can connect to the derived clock, broken paths are repaired, ensuring that the clock propagation relationship accurately reflects the physical connections.

[0240] Optionally, obtain circuit structure baseline data to provide actual information on clock driving logic, offering an objective basis for determining clock redundancy and ensuring that verification standards align with actual circuit conditions. Detect the target clock's driving logic: By checking if there are effective driving units downstream of the clock, identify redundant clocks not involved in actual circuit operation, avoiding invalid clocks consuming resources or interfering with analysis. Determine clock redundancy and provide alerts, promptly identifying redundant clocks, clarifying issues, and providing alerts to help optimize the clock tree structure and reduce unnecessary design complexity. Delete redundant clocks: Remove clocks with no practical use, simplify the clock tree, reduce the computational load of subsequent timing analysis and verification, and improve design efficiency. Alternatively, modify the clock creation point, adjusting the creation point to connect redundant clocks to effective driving logic, activating the function of idle clocks, and ensuring that clock resources are used rationally.

[0241] This embodiment also provides a timing-constrained text checking device, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0242] This embodiment provides a time-constrained text checking device, such as... Figure 3 As shown, it includes: The acquisition module 301 is used to acquire at least one initial timing constraint text corresponding to the target circuit; The extraction module 302 is used to identify each initial timing constraint text and extract clock information corresponding to at least one target clock included in the target circuit; The generation module 303 is used to generate an initial clock tree structure based on the clock information corresponding to each target clock. The verification module 304 is used to verify each target clock according to the initial clock tree structure and determine the error type corresponding to the initial clock tree structure. The correction module 305 is used to correct the initial clock tree structure according to the error type and generate the target clock tree structure.

[0243] The timing constraint text checking apparatus provided in this embodiment of the invention can execute the timing constraint text checking method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method. Further functional descriptions of the various modules and units described above are the same as in the corresponding embodiments described above, and will not be repeated here.

[0244] Figure 4 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. See below for details. Figure 4 The diagram illustrates a structural schematic suitable for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 01, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 02 or a program loaded from a memory 08 into a random access memory (RAM) 03. The RAM 03 also stores various programs and data required for the operation of the electronic device. The processor 01, ROM 02, and RAM 03 are interconnected via a bus 04. An input / output (I / O) interface 05 is also connected to the bus 04.

[0245] Typically, the following devices can be connected to I / O interface 05: input devices 06 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 07 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 08 including, for example, magnetic tapes, hard disks, etc.; and communication devices 09. Communication device 09 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although electronic devices with various devices are illustrated, it should be understood that it is not required to implement or possess all the devices shown, and more or fewer devices may be implemented alternatively.

[0246] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium after being downloaded over a network. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the timing-constrained text checking method shown in the above embodiments.

[0247] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method of timing-constrained text checking, characterized by, The method comprises: acquiring at least one initial timing constraint text corresponding to a target circuit; identifying each of the initial timing constraint texts and extracting clock information corresponding to at least one target clock included in the target circuit; generating an initial clock tree structure according to the clock information corresponding to each of the target clocks; verifying each of the target clocks according to the initial clock tree structure, determining an error type corresponding to the initial clock tree structure; modifying the initial clock tree structure according to the error type, and generating a target clock tree structure.

2. The method of claim 1, wherein, The identification of each of the initial timing constraint texts and the extraction of clock information corresponding to at least one target clock included in the target circuit comprise: preprocessing each of the initial timing constraint texts to obtain each target timing constraint text; the preprocessing comprises at least one of syntax format unification and dynamic parameter completion; generating a main clock keyword according to the clock type corresponding to the target clock; the clock type comprises a basic clock and a derived clock; the derived clock is derived based on the corresponding basic clock; generating a plurality of auxiliary clock keywords according to the clock information corresponding to the target clock; the clock information corresponding to the basic clock comprises a clock name, a clock frequency, a clock creation point, a clock duty cycle, and a stop point of the basic clock in the target circuit; the clock information corresponding to the derived clock comprises a clock name, a clock division ratio, a clock creation point, a clock duty cycle, a derived clock parent clock, and a stop point of the derived clock in the target circuit; extracting clock information corresponding to at least one target clock included in the target circuit from each of the target timing constraint texts according to the main clock keyword and each of the auxiliary clock keywords.

3. The method of claim 2, wherein, The extraction of clock information corresponding to at least one target clock included in the target circuit from each of the target timing constraint texts according to the main clock keyword and each of the auxiliary clock keywords comprises: for each of the target timing constraint texts, identifying each sentence in the target timing constraint text and detecting whether the main clock keyword is included in each of the sentences; determining the sentence containing the main clock keyword as a candidate sentence; determining the clock type corresponding to a candidate clock included in the candidate sentence according to the main clock keyword included in the candidate sentence; determining each of the auxiliary clock keywords corresponding to the candidate clock according to the clock type corresponding to the candidate clock; detecting whether at least one auxiliary clock keyword is included in the candidate sentence; if at least one of the auxiliary clock keywords is included in the candidate sentence, it is determined as a valid clock sentence; determining the candidate clock corresponding to the valid clock sentence as the target clock and determining the clock type corresponding to the target clock; identifying the valid clock sentence to determine the clock information corresponding to the target clock.

4. The method of claim 1, wherein, The generation of an initial clock tree structure according to the clock information corresponding to each of the target clocks comprises: Identify each target timing constraint text, determine the corresponding target module of each target clock in the target circuit; According to the clock type corresponding to each target clock, filter out the basic clock from each target clock; According to the target module corresponding to each basic clock, determine the basic clock corresponding to the top-level module as the main root node; Determine the basic clock corresponding to the non-top-level module as the secondary root node; Place the main root node at the center of the tree structure top level; For each secondary root node, place it on both sides of the main root node according to the distribution of the target module corresponding to the secondary root node in the target circuit; According to each derived clock in the target clock, determine the parent clock corresponding to each derived clock; The parent clock is the basic clock or the derived clock; According to the position of the parent clock corresponding to each derived clock in the tree structure, arrange each derived clock to generate the initial clock tree structure.

5. The method of claim 1, wherein, According to the initial clock tree structure, the target clock is checked to determine the error type corresponding to the initial clock tree structure, including: Check if each derived clock in the target clock has a corresponding parent clock in the initial clock tree structure; If the derived clock does not have a corresponding parent clock in the initial clock tree structure, it is determined that the error type is parent clock missing, and an alarm information is outputted; Correspondingly, according to the error type, the initial clock tree structure is modified to generate a target clock tree structure, including: Modify the derived clock without a parent clock to a basic clock; Or, Obtain the circuit structure reference data corresponding to the target circuit; According to the circuit structure reference data, add a basic clock to the derived clock without a parent clock; Or, Modify the derived clock parent clock information corresponding to the derived clock without a parent clock.

6. The method of claim 1, wherein, According to the initial clock tree structure, the target clock is checked to determine the error type corresponding to the initial clock tree structure, including: Obtain the circuit structure reference data corresponding to the target circuit; Find the clock creation point information corresponding to each target clock in the circuit structure reference data; If the clock creation point information corresponding to the target clock cannot be found, it is determined that the error type is that the clock creation point fails to match in the target circuit, and an alarm information is outputted; Correspondingly, according to the error type, the initial clock tree structure is modified to generate a target clock tree structure, including: According to the circuit structure corresponding to the target circuit, modify the clock creation point information corresponding to the target clock that fails to find the clock creation point information in the initial clock tree structure.

7. The method of claim 1, wherein, According to the initial clock tree structure, the target clock is checked to determine the error type corresponding to the initial clock tree structure, including: Filter out the stop clock marked with a target stop point from each target clock; The target stop point is used to represent the stop point of the stop clock in the target circuit; acquire a global clock list in circuit structure reference data corresponding to the target circuit; detect whether the first stop point corresponding to each record clock recorded in the global clock list is consistent with the target stop point corresponding to each stop clock; if the first stop point corresponding to each record clock recorded in the global clock list is inconsistent with the target stop point corresponding to each stop clock, determine that the error type is no specified clock stop information, and output alarm information; correspondingly, according to the error type, correct the initial clock tree structure to generate a target clock tree structure, including: if the clock name corresponding to the record clock in the global clock list is consistent with the clock name corresponding to the stop clock, correct the target stop point corresponding to the stop clock according to the first stop point corresponding to the record clock; or, if the clock name corresponding to the stop clock is not in the global clock list, delete the target stop point corresponding to the stop clock.

8. The method of claim 1, wherein, the error type corresponding to the initial clock tree structure is determined by checking each target clock according to the initial clock tree structure, including: acquiring circuit structure reference data corresponding to the target circuit; verifying whether there is a physical connection between the derived clock in the target clock and the parent clock corresponding to the derived clock according to the physical node connection relationship in the circuit structure reference data: if there is no physical connection between the derived clock and the parent clock corresponding to the derived clock, determine that the error type is that there is no path between the generated clock and the parent clock; and output alarm information; correspondingly, according to the error type, correct the initial clock tree structure to generate a target clock tree structure, including: modify the derived clock creation point corresponding to the derived clock; or, modify the parent clock creation point corresponding to the parent clock corresponding to the derived clock.

9. The method of claim 1, wherein, the error type corresponding to the initial clock tree structure is determined by checking each target clock according to the initial clock tree structure, including: acquiring circuit structure reference data corresponding to the target circuit; detecting whether there is a driving logic unit connected after each target clock according to the clock driving logic table in the circuit structure reference data; if there is no driving logic unit connected after the target clock, determine that the error type is clock redundancy, and output prompt information; correspondingly, according to the error type, correct the initial clock tree structure to generate a target clock tree structure, including: delete the target clock which has no driving logic unit connected after; or, modify the clock creation point corresponding to the target clock which has no driving logic unit connected after.

10. A timing constrained text checking apparatus characterized by comprising: the device includes: an acquisition module for acquiring at least one initial timing constraint text corresponding to a target circuit; an extraction module for identifying each initial timing constraint text and extracting clock information corresponding to at least one target clock included in the target circuit; a generation module for generating an initial clock tree structure according to the clock information corresponding to each target clock; A checking module is configured to check each target clock according to the initial clock tree structure, and determine an error type corresponding to the initial clock tree structure; A correction module is configured to correct the initial clock tree structure according to the error type, and generate a target clock tree structure.

11. An electronic device, comprising: The method comprises the following steps: A memory and a processor are connected in communication with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the timing constraint text checking method according to any one of claims 1 to 9.

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