Storage array and error correction code encoding and decoding method

Abstract

The embodiment of the invention provides a storage array and an error correction code encoding and decoding method. Each column of storage units of the storage array comprises an input unit, an intermediate result unit and an output unit; the input unit comprises a first unit and a second unit and is used for storing input data of encoding and decoding of the error correction code; the intermediate result unit comprises a third unit and a fourth unit, or comprises a third unit, a fourth unit and a fifth unit; the first unit, the second unit and the third unit are respectively connected with different source lines, the fourth unit and the second unit are connected with the same source line, and the fifth unit and the first unit are connected with the same source line; the output unit is used for storing coding and decoding result data, the output unit and the first unit are connected with the same source line, or the output unit and the second unit are connected with the same source line, so that the calculation delay in the memory is reduced, the calculation efficiency is improved, the power consumption is reduced, the occupation of the memory unit is reduced, and the storage density is improved; and the construction of complex operation is simpler and more efficient.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to a memory array and an error correction code encoding / decoding method. Background Technology

[0002] Error-correcting codes are a key technology for ensuring data reliability, especially crucial in advanced manufacturing processes where miniaturization and device stability challenges are significant. Traditional error-correcting code encoding and decoding are performed in the processor, requiring data to be transferred back and forth between memory and the processor, creating the "memory wall" problem. Therefore, moving error-correcting code encoding and decoding to in-memory computation is an inevitable trend.

[0003] In-memory computing utilizes the storage cells within the memory itself to construct logic gates and perform Boolean logic operations. Its core idea is to integrate computing functions into the memory array and directly process the stored data, thereby minimizing the significant latency and power consumption caused by data transmission.

[0004] However, implementing error correction code encoding and decoding through in-memory computation also faces challenges: error correction code encoding and decoding involves many steps. Taking Hamming code as an example, its encoding and decoding process involves multiple XOR operations. In the traditional dual-source poleline (2-SL) in-memory logic architecture, during multi-step logic operations, after the intermediate result data is obtained by processing the input data, the intermediate result data must be copied to the storage unit connected to the same source poleline as the input data before the input data and intermediate result data can continue to be processed. These copying steps increase computational latency and power consumption, reduce computational efficiency, and require more storage units to temporarily store intermediate result data, resulting in reduced storage density. Summary of the Invention

[0005] This application provides a storage array and an error correction code encoding / decoding method to reduce in-memory computation latency, improve computational efficiency, reduce power consumption, reduce storage unit occupancy, and increase storage density.

[0006] In a first aspect, embodiments of this application provide a storage array, including: multiple columns of storage units, each column of storage unit including an input unit, an intermediate result unit and an output unit;

[0007] The input unit is used to store the input data for error correction code encoding and decoding. The error correction code encoding and decoding process includes multiple XOR operations. The input unit includes a first unit and a second unit.

[0008] The intermediate result unit includes a third unit and a fourth unit, or the intermediate result unit includes the third unit, the fourth unit, and a fifth unit; the third unit is used to store first intermediate result data obtained by calculating the first XOR input data, and is used to store second intermediate result data obtained by calculating the second XOR input data; the fourth unit is used to store first XOR result data obtained by calculating the first XOR input data and the first intermediate result data; the fifth unit is used to store second XOR result data obtained by calculating the second XOR input data and the second intermediate result data; the first XOR input data is the input data in the first unit and / or the second XOR result data; the second XOR input data is the input data in the second unit and / or the first XOR result data;

[0009] The first unit, the second unit, and the third unit are respectively connected to different source lines, the fourth unit is connected to the same source line as the second unit, and the fifth unit is connected to the same source line as the first unit;

[0010] The output unit is used to store the first encoding / decoding result data obtained by calculating the second intermediate result data, the first XOR result data, and the input data in the second unit. The output unit is connected to the same source line as the first unit. Alternatively, the output unit is used to store the second encoding / decoding result data obtained by calculating the first intermediate result data and the second XOR result data, or the second encoding / decoding result data obtained by calculating the first intermediate result data, the second XOR result data, and the input data in the first unit. The output unit is connected to the same source line as the second unit.

[0011] In some implementations, the source line includes a first source line, a second source line, and a third source line;

[0012] The first unit is connected to the first source line, the second unit is connected to the second source line, and the third unit is connected to the third source line.

[0013] In some implementations, the first unit includes at least two storage units, the second unit includes at least one storage unit, the third unit includes at least two storage units, the fourth unit includes at least one storage unit, the fifth unit includes at least one storage unit, and the output unit includes at least one storage unit.

[0014] The storage array provided in this application provides a wiring method with fewer operation steps and higher computational efficiency by adding source poles. This eliminates the need to copy the intermediate result data of the XOR operation in the multi-step XOR operation during the error correction code encoding and decoding process. In other words, it completely eliminates the two copy operations required in the traditional dual-source pole 2-SL architecture, fundamentally reducing the number of steps and pulse cycles required for error correction code encoding and decoding. Moreover, the encoding and decoding processes are completed inside the storage array, which greatly reduces the in-memory computation latency, improves computational efficiency, reduces power consumption, reduces storage cell occupancy, and increases storage density.

[0015] Secondly, embodiments of this application provide a storage array, including: multiple columns of storage units, each column of storage unit including an input unit, an intermediate result unit and an output unit;

[0016] The input unit is used to store the input data for error correction code encoding and decoding. The error correction code encoding and decoding process includes multiple XOR operations.

[0017] The intermediate result unit includes a third unit and a fourth unit, or the intermediate result unit includes the third unit, the fourth unit, and a fifth unit; the third unit is used to store first intermediate result data obtained by calculating the first XOR input data, and is used to store second intermediate result data obtained by calculating the second XOR input data; the fourth unit is used to store first XOR result data obtained by calculating the first XOR input data and the first intermediate result data; the fifth unit is used to store second XOR result data obtained by calculating the second XOR input data and the second intermediate result data; the first XOR input data is the input data in the input unit and / or the second XOR result data; the second XOR input data is the first XOR result data;

[0018] The input unit, the third unit, and the fourth unit are each connected to different source lines, while the fifth unit and the input unit are connected to the same source line.

[0019] The output unit is used to store the first encoding / decoding result data obtained by calculating the first XOR result data and the second intermediate result data. The output unit is connected to the same source line as the input unit; or...

[0020] The output unit is used to store the second encoding / decoding result data obtained by calculating the second XOR result data and the first intermediate result data, or the second encoding / decoding result data obtained by calculating the second XOR result data, the input data, and the first intermediate result data. The output unit is connected to the same source line as the fourth unit.

[0021] In some implementations, the source line includes a first source line, a second source line, and a third source line;

[0022] The input unit is connected to the first source line, the third unit is connected to the second source line, and the fourth unit is connected to the third source line.

[0023] In some implementations, the input unit includes at least four storage units, the third unit includes at least two storage units, the fourth unit includes at least two storage units, the fifth unit includes at least one storage unit, and the output unit includes at least one storage unit.

[0024] In some implementations, when the storage array is used for error correction code encoding, the input data is error correction code information bits, and the first or second encoding / decoding result data is error correction code redundancy bits.

[0025] When the storage array is used for error correction code decoding, the input data consists of error correction code information bits and error correction code redundancy bits, and the first or second encoding / decoding result data consists of error correction code correction sub-bits.

[0026] In some implementations, every two adjacent columns of memory cells share the source line;

[0027] And / or, each column of storage cells is connected to multiple bit lines.

[0028] In some implementations, the storage unit includes a magnetic storage device, which is a spin-orbit moment magnetic storage device or a spin-transfer moment magnetic storage device.

[0029] The storage array provided in this application provides a wiring method with fewer operation steps and higher computational efficiency by adding source poles. This eliminates the need to copy the intermediate result data of the XOR operation in the multi-step XOR operation during the error correction code encoding and decoding process. In other words, it completely eliminates the two copy operations required in the traditional dual-source pole 2-SL architecture, fundamentally reducing the number of steps and pulse cycles required for error correction code encoding and decoding. Moreover, the encoding and decoding processes are completed inside the storage array, which greatly reduces the in-memory computation latency, improves computational efficiency, reduces power consumption, reduces storage cell occupancy, and increases storage density.

[0030] Thirdly, embodiments of this application provide an error-correcting code encoding / decoding method, including:

[0031] The read word line of the storage unit corresponding to the first XOR input data is enabled, the write word line of the third unit is enabled, the first source line is connected to the first logic level, and the third source line is grounded, so as to write the first intermediate result data into the third unit.

[0032] The read word line of the storage unit corresponding to the first XOR input data and the first intermediate result data is enabled, the write word line of the fourth unit is enabled, the first source line is connected to the third logic level, the third source line is connected to the fourth logic level, and the second source line is grounded, so as to write the first XOR result data into the fourth unit.

[0033] The read lines of the second unit, the third unit, and the fourth unit are enabled, the write lines of the output unit are enabled, the second source line is connected to the seventh logic level, the third source line is connected to the eighth logic level, and the first source line is grounded, so as to write the first encoding and decoding result data into the output unit.

[0034] The error correction code encoding and decoding method provided in this application, by adding source poles, eliminates the need to copy the intermediate result data of the XOR operation in the multi-step XOR operation during the error correction code encoding and decoding process. This completely eliminates the two copy operations required in the traditional dual-source pole 2-SL architecture, fundamentally reducing the number of steps and pulse cycles required for error correction code encoding and decoding. Furthermore, both the encoding and decoding processes are completed within the memory array, significantly reducing in-memory computation latency, improving computational efficiency, reducing power consumption, reducing memory cell occupancy, and increasing storage density. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0036] Figure 1 This is a schematic diagram of the structure of a dual-source poleline (2-SL) memory array;

[0037] Figure 2 A schematic diagram of the structure of a column of storage cells provided in an embodiment of this application. Figure 1 ;

[0038] Figure 3 A schematic diagram of a storage array provided in this application embodiment. Figure 1 ;

[0039] Figure 4 A schematic diagram of the structure of a column of storage cells provided in an embodiment of this application. Figure 2 ;

[0040] Figure 5 A schematic diagram of the structure of a column of storage cells provided in an embodiment of this application. Figure 3 ;

[0041] Figure 6 A schematic diagram of the structure of a column of storage cells provided in an embodiment of this application. Figure 4 ;

[0042] Figure 7 A schematic diagram of a storage array provided in this application embodiment. Figure 2 ;

[0043] Figure 8 A schematic diagram of the structure of a column of storage cells provided in an embodiment of this application. Figure 5 ;

[0044] Figure 9 A schematic diagram of the structure of a column of storage cells provided in an embodiment of this application. Figure 6 ;

[0045] Figure 10 A schematic diagram of the structure of a column of storage cells provided in an embodiment of this application. Figure 7 ;

[0046] Figure 11 A schematic diagram of a series of storage units for Hamming code encoding provided in an embodiment of this application;

[0047] Figure 12 A schematic diagram of a series of storage units for Hamming code decoding provided in an embodiment of this application;

[0048] Figure 13 This is a schematic diagram of the control unit provided in an embodiment of this application.

[0049] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0050] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0051] First, combine Figure 1 Examples of in-memory computing in related technologies are provided.

[0052] Figure 1The diagram illustrates the structure of a dual-source-line (2-SL) memory array. In this array, each column of memory cells is connected to two source lines (SL00 and SL01). Memory cells A, B, C2, and C3 are connected to source line SL00, while memory cells C1 and R are connected to source line SL01. Figure 1 In the examples and other embodiments following this application, the data stored in storage unit A is represented by A, the data stored in storage unit B is represented by B, the data stored in storage unit C1 is represented by C1, and so on for other storage units. Furthermore, in Figure 1 In the examples and other embodiments of this application, the storage cell is in a high-resistance state, corresponding to stored data "0", and the storage cell is in a low-resistance state, corresponding to stored data "1".

[0053] based on Figure 1 The structure of the storage array shown requires the following four steps to perform an XOR operation on A and B:

[0054] Step 11: C1 = A NOR B; Step 12: C2 = COPY C1; Step 13: C3 = COPY C1; Step 14: R = (A,B,C2,C3).

[0055] In step 11, the read word line RWL0 of memory cell A is enabled, the read word line RWL1 of memory cell B is enabled, and the write word line WWL2 of memory cell C1 is enabled. A logic voltage Vlogic(NOR) is applied to the source line SL00, the source line SL01 is grounded, and the current on the bit line BL0 can cause the resistance state of memory cell C1 to flip or remain unchanged, thereby realizing the writing of the result of A NORB into memory cell C1.

[0056] In step 12, the read word line RWL2 of the control memory cell C1 is enabled, the write word line WWL3 of the control memory cell C2 is enabled, the logic voltage Vlogic(COPY) is applied to the source line SL01, the source line SL00 is grounded, and the current on the bit line BL0 can cause the resistance state of the memory cell C2 to flip or remain unchanged, thereby realizing the copying of C1 to the memory cell C1.

[0057] The implementation process of step 13 is similar to that of step 12, where C1 is copied to storage unit C3.

[0058] In step 14, the read word line RWL0 of memory cell A is enabled, the read word line RWL1 of memory cell B is enabled, the read word line RWL3 of memory cell C2 is enabled, the read word line RWL4 of memory cell C3 is enabled, and the write word line WWL5 of memory cell R is enabled. A logic voltage Vlogic(TH4) is applied to the source line SL00, and the source line SL01 is grounded. The current on the bit line BL0 can cause the resistance state of memory cell R to flip or remain unchanged, thereby realizing the switching of the read word line R. The result of (A, B, C2, C3) is written to storage unit R. Therefore, in Figure 1 In the multi-step logic operation of the illustrated memory array structure, due to the limitation on the number of source lines, if the intermediate result data output from the first step and the input data from the first step are to be used together for the second step calculation, the intermediate result data needs to be copied to another memory cell (i.e., two copy operations are required). This other memory cell is connected to the same source line as the memory cell containing the input data from the first step. However, copying the intermediate result data increases computational latency, power consumption, and computational efficiency, making it very difficult and inefficient to construct complex operations. Furthermore, copying the intermediate result requires more memory cells, reducing storage density.

[0059] Furthermore, error correction code encoding and decoding involve XOR operations between multiple bits. This means that to achieve error correction code encoding and decoding through in-memory computation, the aforementioned XOR operations need to be performed multiple times, requiring two copy operations in each XOR operation. This results in a large number of copy operations during error correction code encoding and decoding, leading to increased computational latency, increased power consumption, reduced computational efficiency, and the need for more storage units, thus reducing storage density.

[0060] To address the aforementioned issues, this application proposes a storage array that avoids copying intermediate result data during multi-step logical operations by adding source lines, thereby preventing the copying of intermediate result data during error correction code encoding and decoding.

[0061] In the storage array provided in this application embodiment, each column of storage cells is connected to at least three source lines, combined with Figure 2 As shown, the example is that each column of memory cells in the memory array is connected to three source lines.

[0062] Figure 2 The example uses a column of memory cells. The source lines connected to the memory cells in this column of memory array include source lines SL00, SL01, and SL02. Memory cells A and B are connected to source line SL00, memory cells C1 and C2 are connected to source line SL01, and memory cell R is connected to source line SL02.

[0063] based on Figure 2 The structure shown requires the following three steps to perform an XOR operation on A and B: Step 21: C1 = A NOR B; Step 22: C2 = A NOR B; Step 23: C3 = (A, B, C1, C2).

[0064] In step 21, the read word line RWL0 of memory cell A, the read word line RWL1 of memory cell B, and the write word line WWL2 of memory cell C1 are enabled. This means the read channels of memory cells A and B are enabled, the write channel of memory cell C1 is enabled, and the read or write channels of other memory cells are disabled. A logic level Vlogic(NOR) is applied to the source line SL00, and the source line SL01 is grounded. The current on the bit line BL0 can cause the resistance state of memory cell C1 to flip or remain unchanged, thereby writing the result of A NOR B into memory cell C1.

[0065] The initial value of memory cell C1 is "1", meaning its initial resistance state is low. When the initial values ​​of memory cells A and B are both "0", the current on bit line BL0 is below the toggle threshold, preventing memory cell C1 from flipping, and C1 remains in the low-resistance state, meaning C1 is still "1". When the initial values ​​of memory cells A and B are "0" and "1" respectively, or "1" and "0" respectively, or when the initial values ​​of memory cells A and B are both "1", the current on bit line BL0 exceeds the toggle threshold, causing memory cell C1 to flip from the low-resistance state to the high-resistance state, meaning C1 flips from "1" to "0". This achieves the operation C1 = A NOR B.

[0066] Step 22 is similar to step 21, except that the write word line WWL3 of the control memory cell C2 is enabled, that is, the write channel of the memory cell C2 is turned on. The current on the bit line BL0 can make the resistance state of the memory cell C2 flip or remain unchanged, thereby realizing the writing of the result of A NOR B into the memory cell C2.

[0067] In step 23, the read word line RWL0 of memory cell A is enabled, the read word line RWL1 of memory cell B is enabled, the read word line RWL2 of memory cell C1 is enabled, the read word line RWL3 of memory cell C2 is enabled, and the write word line WWL4 of memory cell R is enabled. A logic level Vlogic is applied to the source lines SL00 and SL01. With the source line SL02 grounded, the current on the bit line BL0 can cause the resistance state of the memory cell R to flip or remain unchanged, thereby realizing the switching of the source line SL02 to the source line BL0. The result of (A,B,C1,C2) is written into storage unit R.

[0068] The initial value of memory cell R is "0", meaning its initial resistance state is high resistance. When the initial values ​​of memory cells A, B, C1, and C2 are "0", "1", "0", and "0" respectively, or when the initial values ​​of memory cells A, B, C1, and C2 are "1", "0", "0", and "0" respectively, the current on bit line BL0 is below the toggling threshold, preventing the resistance state of memory cell R from flipping. Memory cell R remains in a high resistance state, meaning R is still "0". When the initial values ​​of memory cells A, B, C1, and C2 are "0", "0", "1", and "1" respectively, or when the initial values ​​of memory cells A, B, C1, and C2 are "1", "1", "0", and "0" respectively, the current on bit line BL0 is above the toggling threshold, causing memory cell R to flip from a high resistance state to a low resistance state, meaning R flips from "0" to "1". This achieves the operation R = TH4(A, B, C1, C2).

[0069] based on Figure 2 The truth table for the XOR operation of the structure shown is shown in Table 1.

[0070] Table 1

[0071] A B C1 C2 R 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 1 1 0 0 0

[0072] The XOR operation described above requires only 3 calculation steps, which takes 3 pulse cycles and uses 6 storage units. Since each storage unit is connected to three source lines, after calculating the intermediate result data (C1 or C2) from the input data (A and B), there is no need to copy the intermediate result data (C1 or C2). Simply apply logic levels to source lines SL00 and SL01 and ground source line SL02 to directly perform subsequent calculations on the input data and intermediate result data. In other words, the XOR operation does not require copying the intermediate result data, thereby improving calculation efficiency, reducing storage unit occupation, and increasing storage density.

[0073] Furthermore, since error-correcting code encoding and decoding are implemented through multi-step XOR operations, therefore, based on Figure 2 The XOR operation in the illustrated embodiment is used to implement error correction code encoding and decoding. It also eliminates the need to copy intermediate result data, fundamentally reducing the number of steps and pulse cycles required for error correction code encoding and decoding, improving computational efficiency, reducing power consumption, reducing storage unit occupation, increasing storage density, and completing the entire encoding and decoding process within the storage array, effectively avoiding data transfer between the processor and memory, and significantly reducing in-memory computation latency and power consumption.

[0074] The storage unit in this application embodiment may include a magnetic storage device, which may be a spin-orbit moment magnetic storage device (SOT-MRAM) or a spin-transfer moment magnetic storage device (STT-MRAM). The spin-orbit moment magnetic storage device includes at least a spin-orbit moment layer and a magnetic tunnel junction disposed above the spin-orbit moment layer.

[0075] Furthermore, the spin-orbit moment layer is used to generate corresponding spin polarization currents with different writing currents, thereby generating spin torques in different directions. The spin-orbit moment layer can be a single layer or a stack, and its material includes conductive materials with strong spin-orbit coupling effects. For example, the material of the spin-orbit moment layer includes one or more of Pt, Pd, Hf, Au, AuPt, PtHf, PtCr, PtMn, FeMn, NiMn, Ta, W, Ir, IrMn, WOx, WN, WON, TaN, and TaB, as well as topological insulators. Topological insulators include Bi... x Se 1-x Bi x Sb 1-x , (Bi,Sb)2Te3, where x independently satisfies the value of 0.1-0.9.

[0076] A magnetic tunnel junction (MTJ) is the core structure of a magnetic storage device. MTJs can be cylindrical, elliptical, rectangular, or toroidal. A MTJ consists of a free layer, a barrier layer, and a fixed layer stacked from bottom to top. When the free and fixed layers are magnetized in the same direction (i.e., parallel, P-state), the MTJ is in a low-resistivity state, storing data "1". When the free and fixed layers are magnetized in opposite directions (i.e., antiparallel, AP-state), the MTJ is in a high-resistivity state, storing data "0".

[0077] Based on the above principles, the storage array structure for implementing error-correcting code encoding and decoding is explained.

[0078] In one implementation, refer to Figure 3 As shown, the storage array 60 includes multiple columns of storage cells, each column of storage cells including an input cell 61, an intermediate result cell 62 and an output cell 63.

[0079] The input unit 61 is used to store the input data for error correction code encoding and decoding. The error correction code encoding and decoding process includes multiple XOR operations. The input unit 61 includes a first unit 611 and a second unit 612.

[0080] Intermediate result unit 62 includes a third unit 621 and a fourth unit 622, or intermediate result unit 62 includes a third unit 621, a fourth unit 622 and a fifth unit 623; the third unit 621 is used to store first intermediate result data obtained by calculating the first XOR input data, and is used to store second intermediate result data obtained by calculating the second XOR input data; the fourth unit 622 is used to store first XOR result data obtained by calculating the first XOR input data and the first intermediate result data; the fifth unit 623 is used to store second XOR result data obtained by calculating the second XOR input data and the second intermediate result data; the first XOR input data is the input data in the first unit 611 and / or the second XOR result data; the second XOR input data is the input data in the second unit 612 and / or the first XOR result data. Figure 3 The fifth unit 623 is connected by a dashed line, indicating that the fifth unit 623 is an optional storage unit.

[0081] Units 611, 612, and 621 are connected to different source lines, unit 622 is connected to the same source line as unit 612, and unit 623 is connected to the same source line as unit 611. Figure 3 In the first unit 611 and the fifth unit 623, the source line SL00 is connected; the second unit 612 and the fourth unit 622 are connected to the source line SL01; and the third unit 621 is connected to the source line SL02.

[0082] Output unit 63 is used to store the first encoding / decoding result data obtained by calculating the second intermediate result data, the first XOR result data, and the input data in the second unit 612. Output unit 63 is connected to the same source line as the first unit 611, such as... Figure 3 In the first unit 611, output unit 63 is connected to source line SL00; or, output unit 63 is used to store the second encoding / decoding result data obtained by calculating the first intermediate result data and the second XOR result data, or the second encoding / decoding result data obtained by calculating the first intermediate result data, the second XOR result data, and the input data in the first unit 611. Output unit 63 and the second unit 612 are connected to the same source line, such as... Figure 3 In the middle, the output unit 63 is connected to the source line SL01. Figure 3 The output unit 63 is connected to the source line by a dashed line, indicating that the output unit 63 is connected to the source line SL00 or the source line SL01.

[0083] It should be noted that in this embodiment, only the first unit 611, the second unit 612 and the third unit 621 need to be connected to different source lines, the fourth unit 622 needs to be connected to the same source line as the second unit 612, the fifth unit 623 needs to be connected to the same source line as the first unit 611, and the output unit 63 needs to be connected to the same source line as the first unit 611, or the output unit 63 needs to be connected to the same source line as the second unit 612. That is, the number of source lines is at least three, but there is no limitation on the specific number of source lines.

[0084] The first unit 611 includes at least two storage units, the second unit 612 includes at least one storage unit, the third unit 621 includes at least two storage units, the fourth unit 622 includes at least one storage unit, the fifth unit 623 includes at least one storage unit, and the output unit 63 includes at least one storage unit.

[0085] Under the above premise, the source lines connected to different memory cells in the first unit 611 can be different. When the second unit 612 includes multiple memory cells, the source lines connected to different memory cells in the second unit 612 can be different. When the third unit 621 includes multiple memory cells, the source lines connected to different memory cells in the fourth unit 622 can be different. When the fifth unit 623 includes multiple memory cells, the source lines connected to different memory cells in the fifth unit 623 can be different. When the output unit 63 includes multiple memory cells, the source lines connected to different memory cells in the output unit 63 can be different.

[0086] Taking a storage cell column with source lines including a first source line, a second source line, and a third source line as an example, the first cell 611 is connected to the first source line, the second cell 612 is connected to the second source line, and the third cell 621 is connected to the third source line. The fourth cell 622 is connected to the second source line, the fifth cell 623 is connected to the first source line, and the output cell 63 is connected to the first source line, or the output cell 63 is connected to the second source line.

[0087] Input unit 61, intermediate result unit 62, and output unit 63 are connected to bit line BL. Figure 3 The write and read lines connected to the storage unit are not shown in the diagram. When the write line connected to the storage unit is active, the write channel of the storage unit is enabled; when the read line connected to the storage unit is active, the read channel of the storage unit is enabled.

[0088] During the process of calculating the first intermediate result data by the first XOR input data, the read word line of the storage unit corresponding to the first XOR input data is valid, the write word line of the third unit 621 is valid, the first source line is connected to the first logic level, and the third source line is grounded, so as to write the first intermediate result data into the third unit 621.

[0089] During the process of calculating the second intermediate result data by the second XOR input data, the read word line of the storage unit corresponding to the second XOR input data is valid, the write word line of the third unit 621 is valid, the second source line is connected to the second logic level, and the third source line is grounded, so as to write the second intermediate result data into the third unit 621.

[0090] During the process of calculating the first XOR result data by the first XOR input data and the first intermediate result data, the read word line of the storage unit corresponding to the first XOR input data and the first intermediate result data is valid, the write word line of the fourth unit 622 is valid, the first source line and the third source line are connected to the third logic level, and the second source line is grounded, so as to write the first XOR result data into the fourth unit 622.

[0091] During the process of calculating the second XOR result data by the second XOR input data and the second intermediate result data, the read word line of the storage unit corresponding to the second XOR input data and the second intermediate result data is valid, the write word line of the fifth unit 623 is valid, the second source line and the third source line are connected to the fourth logic level, and the first source line is grounded, so as to write the second XOR result data into the fifth unit 623.

[0092] During the process of calculating the first encoding and decoding result data by processing the second intermediate result data, the first XOR result data, and the input data in the second unit 612, the read word lines of the second unit 612, the third unit 621, and the fourth unit 622 are valid, the write word line of the output unit 63 is valid, the second source line and the third source line are connected to the fifth logic level, and the first source line is grounded, so as to write the first encoding and decoding result data into the output unit 63.

[0093] During the process of calculating the second encoding and decoding result data by calculating the first intermediate result data and the second XOR result data, the read word lines of the third unit 621 and the fifth unit 623 are valid, the write word line of the output unit 63 is valid, the second source line and the third source line are connected to the sixth logic level, and the first source line is grounded, so as to write the second encoding and decoding result data into the output unit 63.

[0094] During the process of calculating the second encoding / decoding result data by combining the first intermediate result data, the second XOR result data, and the input data in the first unit 611, the read word lines of the first unit 611, the third unit 621, and the fifth unit 623 are valid, the write word line of the output unit 63 is valid, the first source line and the third source line are connected to the seventh logic level, and the second source line is grounded, so as to write the second encoding / decoding result data into the output unit 63.

[0095] exist Figure 3 In the architecture shown, in some embodiments, the intermediate result unit 62 includes a third unit 621 and a fourth unit 622. The first XOR input data is the input data in the first unit 611, the second XOR input data is the input data in the second unit 612 and the first XOR result data, and the output unit 63 is used to store the first encoding / decoding result data obtained by calculating the second intermediate result data, the first XOR result data and the input data in the second unit 612. The output unit 63 is connected to the same source line as the first unit 611.

[0096] Reference Figure 4 As shown, an example is given using a single column of storage cells. Figure 4 The image illustrates the effect of transposing a column of storage units. To facilitate demonstrating the calculation process, [the image is shown here]. Figure 4 The rows and columns are transposed in all subsequent illustrations.

[0097] Figure 4 In this structure, the first unit includes storage units d1 and d2, the second unit includes storage unit d3, the third unit includes storage units R1 and R2, and the fourth unit includes storage unit R3. The output unit includes storage unit P. Storage units d1, d2, and P are connected to the first source line SL00, storage units d3 and R3 are connected to the second source line SL01, and storage units R1 and R2 are connected to the third source line SL02.

[0098] Error-correcting encoding or decoding of data d1, d2, and d3 yields data P. The process of error-correcting encoding or decoding involves an XOR operation on data d1, d2, and d3, i.e., P = d1 XOR d2 XOR d3. This process can be broken down into the following steps:

[0099] Step 31: R1 = d1 NOR d2; Step 32: R2 = d1 NOR d2; Step 33: R3 = (d1, d2, R1,R2);

[0100] Step 34: R1 = d³ NOR R3; Step 35: R2 = d³ NOR R3; Step 36: P = (d3, R3, R1, R2).

[0101] Steps 31-33 and 34-36 all involve XOR operations. For detailed calculations of the XOR operation, please refer to [link to relevant documentation]. Figure 2 The explanation of the XOR operation in the illustrated embodiment is similar in subsequent embodiments.

[0102] In step 31, the read word line RWL1 of memory cell d1, the read word line RWL2 of memory cell d2, and the write word line WWL5 of memory cell R1 are enabled. A first logic level Vlogic(NOR) is applied to the first source line SL00, and the third source line SL02 is grounded. Step 32 is similar to step 31, except that the write word line WWL6 of memory cell R2 is enabled. In step 33, the read word line RWL1 of memory cell d1, the read word line RWL2 of memory cell d2, the read word line RWL5 of memory cell R1, the read word line RWL6 of memory cell R2, and the write word line WWL4 of memory cell R3 are enabled. A third logic level Vlogic(NOR) is applied to the first source line SL00 and the third source line SL02. The second source line SL01 is grounded.

[0103] In step 34, the read word line RWL3 of memory cell d3, the read word line RWL4 of memory cell R3, and the write word line WWL5 of memory cell R1 are enabled. A second logic level, Vlogic(NOR), is applied to the second source line SL01, and the third source line SL02 is grounded. Step 35 is similar to step 34, except that the write word line WWL6 of memory cell R2 is enabled. In step 36, the read word line RWL3 of memory cell d3, the read word line RWL4 of memory cell R3, the read word line RWL5 of memory cell R1, the read word line RWL6 of memory cell R2, and the write word line WWL4 of memory cell R3 are enabled. A fifth logic level, Vlogic(NOR), is applied to the second source line SL01 and the third source line SL02. The first source line SL00 is grounded.

[0104] exist Figure 3In the architecture shown, in some embodiments, the intermediate result unit 62 includes a third unit 621, a fourth unit 622, and a fifth unit 623. The first XOR input data is the input data in the first unit 611, or the first XOR input data is the input data in the first unit 611 and the second XOR result data, and the second XOR input data is the input data in the second unit 612 and the first XOR result data. The output unit 63 is used to store the second encoding / decoding result data obtained by calculating the first intermediate result data, the second XOR result data, and the input data in the first unit 611. The output unit 63 and the second unit 612 are connected to the same source line.

[0105] Reference Figure 5 As shown, Figure 5 The diagram uses a single column of storage cells as an example for clarity. Figure 5 The memory cells are divided into three units. The first unit includes memory cells d1, d2, and d4; the second unit includes memory cell d3; the third unit includes memory cells R1 and R2; the fourth unit includes memory cell R3; and the fifth unit includes memory cell R4. The output unit includes memory cell P. Memory cells d1, d2, d4, and R4 are connected to the first source line SL00; memory cells d3, R3, and P are connected to the second source line SL01; and memory cells R1 and R2 are connected to the third source line SL02.

[0106] Error-correcting encoding or decoding of data d1, d2, d3, and d4 yields data P. The process of error-correcting encoding or decoding involves an XOR operation of data d1, d2, d3, and d4, i.e., P = d1 XOR d2 XOR d3 XOR d4. This process can be broken down into the following steps:

[0107] Step 41: R1 = d1 NOR d2; Step 42: R2 = d1 NOR d2; Step 43: R3 = (d1, d2, R1,R2);

[0108] Step 44: R1 = d3 NOR R3; Step 45: R2 = d3 NOR R3; Step 46: R4 = (d3, R3, R1, R2);

[0109] Step 47: R1 = d⁴ NOR R⁴; Step 48: R2 = d⁴ NOR R⁴; Step 49: P = (d4, R4, R1, R2).

[0110] Steps 41-43, 44-46, and 47-49 all involve XOR operations.

[0111] Steps 41-42 can be referred to the description of steps 31-32 in the aforementioned embodiments. In step 43, the read word line RWL1 of the control memory cell d1 is enabled, the read word line RWL2 of the control memory cell d2 is enabled, the read word line RWL5 of the control memory cell R1 is enabled, the read word line RWL6 of the control memory cell R2 is enabled, and the write word line WWL7 of the control memory cell R3 is enabled. A third logic level Vlogic is applied to the first source line SL00 and the third source line SL02. The second source line SL01 is grounded.

[0112] In step 44, the read word line RWL3 of memory cell d3, the read word line RWL7 of memory cell R3, and the write word line WWL5 of memory cell R1 are enabled. A second logic level, Vlogic(NOR), is applied to the second source line SL01, and the third source line SL02 is grounded. Step 45 is similar to step 44, except that the write word line WWL6 of memory cell R2 is enabled. In step 46, the read word line RWL3 of memory cell d3, the read word line RWL7 of memory cell R3, the read word line RWL5 of memory cell R1, the read word line RWL6 of memory cell R2, and the write word line WWL8 of memory cell R4 are enabled. A fourth logic level, Vlogic(NOR), is applied to the second source line SL01 and the third source line SL02. The first source line SL00 is grounded.

[0113] In step 47, the read word line RWL4 of memory cell d4, the read word line RWL8 of memory cell R4, and the write word line WWL5 of memory cell R1 are enabled. A first logic level Vlogic(NOR) is applied to the second source line SL01, and the third source line SL02 is grounded. Step 48 is similar to step 47, except that the write word line WWL6 of memory cell R2 is enabled. In step 49, the read word line RWL4 of memory cell d4, the read word line RWL8 of memory cell R4, the read word line RWL5 of memory cell R1, the read word line RWL6 of memory cell R2, and the write word line WWL0 of memory cell P are enabled. A seventh logic level Vlogic(NOR) is applied to the first source line SL00 and the third source line SL02. The second source line SL01 is grounded.

[0114] exist Figure 3In the architecture shown, in some embodiments, the intermediate result unit 62 includes a third unit 621, a fourth unit 622, and a fifth unit 623. The first XOR input data is the input data in the first unit 611, or the first XOR input data is the second XOR result data. The second XOR input data is the input data in the second unit 612, or the second XOR input data is the first XOR result data. The output unit 63 is used to store the second encoding / decoding result data obtained by calculating the second XOR result data and the first intermediate result data. The output unit 63 and the second unit 612 are connected to the same source line.

[0115] Reference Figure 6 As shown, Figure 6 The storage units shown in the diagram are in the same column for clarity. Figure 6 The memory cells are divided into three units. The first unit includes memory cells d1, d2, d3, and d4; the second unit includes memory cells d5 and d6; the third unit includes memory cells R1 and R2; the fourth unit includes memory cells R3 and R4; and the fifth unit includes memory cells R5 and R6. The output unit includes memory cell P. Memory cells d1, d2, d3, d4, R5, and R6 are connected to the first source line SL00; memory cells d5, d6, R3, R4, and P are connected to the second source line SL01; and memory cells R1 and R2 are connected to the third source line SL02.

[0116] Error-correcting encoding or decoding of data d1, d2, d3, d4, d5, and d6 yields data P. The error-correcting encoding or decoding process involves an XOR operation on the data d1, d2, d3, d4, d5, and d6, i.e., P = d1 XOR d2 XOR d3 XOR d4 XOR d5 XOR d6. This process can be broken down into the following steps:

[0117] Step 51: R1 = d1 NOR d2; Step 52: R2 = d1 NOR d2; Step 53: R3 = (d1, d2, R1,R2);

[0118] Step 54: R1 = d3 NOR d4; Step 55: R2 = d3 NOR d4; Step 56: R4 = (d3, d4, R1,R2);

[0119] Step 57: R1 = d5 NOR d6; Step 58: R2 = d5 NOR d6; Step 59: R5 = (d5, d6, R1,R2);

[0120] Step 510: R1 = R3 NOR R4; Step 511: R2 = R3 NOR R4; Step 512: R6 = (R3, R4, R1, R2);

[0121] Step 513: R1 = R5 NOR R6; Step 514: R2 = R5 NOR R6; Step 515: P = (R5, R6, R1, R2).

[0122] Steps 51-53, 54-56, 57-59, 510-512, and 513-515 all involve XOR operations.

[0123] In step 51, the read word line RWL1 of memory cell d1, the read word line RWL2 of memory cell d2, and the write word line WWL7 of memory cell R1 are enabled. A first logic level Vlogic(NOR) is applied to the first source line SL00, and the third source line SL02 is grounded. Step 52 is similar to step 51, except that the write word line WWL8 of memory cell R2 is enabled. In step 53, the read word line RWL1 of memory cell d1, the read word line RWL2 of memory cell d2, the read word line RWL7 of memory cell R1, the read word line RWL8 of memory cell R2, and the write word line WWL9 of memory cell R3 are enabled. A third logic level Vlogic(NOR) is applied to the first source line SL00 and the third source line SL02. The second source line SL01 is grounded.

[0124] Step 54 is similar to step 51, except that the read word line RWL3 of storage unit d3 and the read word line RWL4 of storage unit d4 are enabled. Step 55 is similar to step 54, except that the write word line WWL8 of storage unit R2 is enabled. Step 56 is similar to step 53, except that the read word line RWL3 of storage unit d3 and the read word line RWL4 of storage unit d4 are enabled, and the write word line WWL10 of storage unit R4 is enabled.

[0125] In step 57, the read word line RWL5 of memory cell d5, the read word line RWL6 of memory cell d6, and the write word line WWL7 of memory cell R1 are enabled. A second logic level Vlogic(NOR) is applied to the second source line SL01, and the third source line SL02 is grounded. Step 58 is similar to step 57, except that the write word line WWL8 of memory cell R2 is enabled. In step 59, the read word line RWL5 of memory cell d5, the read word line RWL6 of memory cell d6, the read word line RWL7 of memory cell R1, the read word line RWL8 of memory cell R2, and the write word line WWL11 of memory cell R5 are enabled. A fourth logic level Vlogic(NOR) is applied to the second source line SL01 and the third source line SL02. The first source line SL00 is grounded.

[0126] Step 510 is similar to step 57, except that the read word line RWL9 of storage unit R3 and the read word line RWL10 of storage unit R4 are enabled. Step 511 is similar to step 510, except that the write word line WWL8 of storage unit R2 is enabled. Step 512 is similar to step 59, except that the read word line RWL9 of storage unit R3, the read word line RWL10 of storage unit R4, and the write word line WWL12 of storage unit R6 are enabled.

[0127] In step 513, the read word line RWL11 of memory cell R5, the read word line RWL12 of memory cell R6, and the write word line WWL7 of memory cell R1 are enabled. A first logic level Vlogic(NOR) is applied to the second source line SL01, and the third source line SL02 is grounded. Step 514 is similar to step 513, except that the write word line WWL8 of memory cell R2 is enabled. In step 515, the read word line RWL11 of memory cell R5, the read word line RWL12 of memory cell R6, the read word line RWL7 of memory cell R1, the read word line RWL8 of memory cell R2, and the write word line WWL0 of memory cell P are enabled. A sixth logic level Vlogic(NOR) is applied to the first source line SL00 and the third source line SL02. The second source line SL01 is grounded.

[0128] In another implementation, refer to Figure 7 As shown, the storage array 100 includes multiple columns of storage cells, each column of storage cell including an input cell 101, an intermediate result cell 102 and an output cell 103.

[0129] The input unit 101 is used to store the input data for error correction code encoding and decoding. The error correction code encoding and decoding process includes multi-step XOR operations.

[0130] Intermediate result unit 102 includes a third unit 1021 and a fourth unit 1022, or intermediate result unit 102 includes a third unit 1021, a fourth unit 1022 and a fifth unit 1023; the third unit 1021 is used to store first intermediate result data obtained by calculating the first XOR input data, and is used to store second intermediate result data obtained by calculating the second XOR input data; the fourth unit 1022 is used to store first XOR result data obtained by calculating the first XOR input data and the first intermediate result data; the fifth unit 1023 is used to store second XOR result data obtained by calculating the second XOR input data and the second intermediate result data; the first XOR input data is the input data in input unit 101 and / or the second XOR result data; the second XOR input data is the first XOR result data. Figure 7 The fifth unit 1023 is connected by a dashed line, indicating that the fifth unit 1023 is an optional storage unit.

[0131] Input unit 101, third unit 1021, and fourth unit 1022 are connected to different source lines, while fifth unit 1023 and input unit 101 are connected to the same source line. For example... Figure 7 In the middle, input unit 101 and fifth unit 1023 are connected to source line SL00, third unit 621 is connected to source line SL01, and fourth unit 622 is connected to source line SL02.

[0132] Output unit 103 is used to store the first encoding / decoding result data obtained by calculating the first XOR result data and the second intermediate result data. Output unit 103 is connected to the same source line as input unit 101, such as... Figure 7 In this context, output unit 103 is connected to source line SL00; or, output unit 103 is used to store the second encoding / decoding result data obtained by calculating the second XOR result data and the first intermediate result data, or the second encoding / decoding result data obtained by calculating the second XOR result data, the input data in input unit 101, and the first intermediate result data. Output unit 103 and fourth unit 1022 are connected to the same source line, such as... Figure 7 In the middle, the output unit 103 is connected to the source line SL02. Figure 7 The output unit 103 is connected to the source line by a dashed line, indicating that the output unit 103 is connected to the source line SL00 or the source line SL02.

[0133] It should be noted that in this embodiment, only the input unit 101, the third unit 1021 and the fourth unit 1022 need to be connected to different source lines, the fifth unit 1023 and the input unit 101 need to be connected to the same source line, and the output unit 103 needs to be connected to the same source line as the input unit 101, or the output unit 103 needs to be connected to the same source line as the fourth unit 1022. That is, the number of source lines is at least three, but there is no limitation on the specific number of source lines.

[0134] The input unit 101 includes at least four storage units, the third unit 1021 includes at least two storage units, the fourth unit 1022 includes at least two storage units, the fifth unit 1023 includes at least one storage unit, and the output unit 103 includes at least one storage unit.

[0135] Under the above conditions, the source lines connected to different memory cells in input unit 101 can be different, the source lines connected to different memory cells in third unit 1021 can be different, the source lines connected to different memory cells in fourth unit 1022 can be different, when fifth unit 1023 includes multiple memory cells, the source lines connected to different memory cells in fifth unit 1023 can be different, and when output unit 103 includes multiple memory cells, the source lines connected to different memory cells in output unit 103 can be different.

[0136] Taking the source lines of each column of storage cells as including the first source line, the second source line and the third source line as an example, the input unit 101 and the fifth unit 1023 are connected to the first source line, the third unit 1021 is connected to the second source line, the fourth unit 1022 is connected to the third source line, and the output unit 103 is connected to either the first source line or the third source line.

[0137] Input unit 101, intermediate result unit 102, and output unit 103 are connected to bit line BL. Figure 7 The write and read lines connected to the storage unit are not shown in the diagram. When the write line connected to the storage unit is active, the write channel of the storage unit is enabled; when the read line connected to the storage unit is active, the read channel of the storage unit is enabled.

[0138] During the process of calculating the first intermediate result data by the first XOR input data, the read word line of the storage unit corresponding to the first XOR input data is valid, the write word line of the third unit 1021 is valid, the first source line is connected to the first logic level, and the second source line is grounded, so as to write the first intermediate result data into the third unit 1021.

[0139] During the process of calculating the second intermediate result data by the second XOR input data, the read word line of the storage unit corresponding to the second XOR input data is valid, the write word line of the third unit 1021 is valid, the third source line is connected to the second logic level, and the second source line is grounded, so as to write the second intermediate result data into the third unit 1021.

[0140] During the process of calculating the first XOR result data by the first XOR input data and the first intermediate result data, the read word line of the storage unit corresponding to the first XOR input data and the first intermediate result data is valid, the write word line of the fourth unit 1022 is valid, the first source line and the second source line are connected to the third logic level, and the third source line is grounded, so as to write the first XOR result data into the fourth unit 1022.

[0141] During the process of calculating the second XOR result data by the second XOR input data and the second intermediate result data, the read word lines of the storage units corresponding to the second XOR input data and the second intermediate result data are valid, the write word lines of the fifth unit 1023 are valid, the second source line and the third source line are connected to the fourth logic level, and the first source line is grounded, so as to write the second XOR result data into the fifth unit 1023.

[0142] During the process of calculating the first encoded / decoded result data by processing the first XOR result data and the second intermediate result data, the read word lines of the third unit 1021 and the fourth unit 1022 are valid, the write word line of the output unit 103 is valid, the second source line and the third source line are connected to the fifth logic level, and the first source line is grounded, so as to write the first encoded / decoded result data into the output unit 103.

[0143] During the process of calculating the second XOR result data and the first intermediate result data to obtain the second encoding and decoding result data, the read word lines of the third unit 1021 and the fifth unit 1023 are valid, the write word line of the output unit 103 is valid, the first source line and the second source line are connected to the sixth logic level, and the third source line is grounded, so as to write the second encoding and decoding result data into the output unit 103.

[0144] During the process of calculating the second XOR result data, input data, and first intermediate result data to obtain the second encoding / decoding result data, the read word lines of input unit 101, third unit 1021, and fifth unit 1023 are valid, the write word line of output unit 103 is valid, the first source line and the second source line are connected to the seventh logic level, and the third source line is grounded, so as to write the second encoding / decoding result data into output unit 103.

[0145] exist Figure 7In the architecture shown, in some embodiments, the intermediate result unit 102 includes a third unit 1021 and a fourth unit 1022. The first XOR input data is the input data in the input unit 101. The output unit 103 is used to store the first encoding / decoding result data obtained by calculating the first XOR result data and the second intermediate result data. The output unit 103 is connected to the same source line as the input unit 101.

[0146] Reference Figure 8 As shown, Figure 8 The diagram uses a single column of storage cells as an example for clarity. Figure 8 The memory cells are divided into three parts. The input unit includes memory cells d1, d2, d3, and d4. The third unit includes memory cells R1 and R2, and the fourth unit includes memory cells R3 and R4. The output unit includes memory cell P. Memory cells d1, d2, d3, d4, and P are connected to the first source line SL00, memory cells R1 and R2 are connected to the second source line SL01, and memory cells R3 and R4 are connected to the third source line SL02.

[0147] Error-correcting encoding or decoding of data d1, d2, d3, and d4 yields data P. The process of error-correcting encoding or decoding involves an XOR operation on data d1, d2, d3, and d4, i.e., P = d1 XOR d2 XOR d3 XOR d4. This process can be broken down into the following steps:

[0148] Step 61: R1 = d1 NOR d2; Step 62: R2 = d1 NOR d2; Step 63: R3 = (d1, d2, R1,R2);

[0149] Step 64: R1 = d3 NOR d4; Step 65: R2 = d3 NOR d4; Step 66: R4 = (d3, d4, R1,R2);

[0150] Step 67: R1 = R3 NOR R4; Step 68: R2 = R3 NOR R4; Step 69: P = (R3, R4, R1, R2).

[0151] Steps 61-63, 64-66, and 67-69 are all XOR operations.

[0152] In step 61, the read word line RWL1 of memory cell d1, the read word line RWL2 of memory cell d2, and the write word line WWL5 of memory cell R1 are enabled. A first logic level Vlogic(NOR) is applied to the first source line SL00, and the second source line SL01 is grounded. Step 62 is similar to step 61, except that the write word line WWL6 of memory cell R2 is enabled. In step 63, the read word line RWL1 of memory cell d1, the read word line RWL2 of memory cell d2, the read word line RWL5 of memory cell R1, the read word line RWL6 of memory cell R2, and the write word line WWL7 of memory cell R3 are enabled. A third logic level Vlogic(NOR) is applied to the first source line SL00 and the second source line SL01. The third source line SL02 is grounded.

[0153] Step 64 is similar to step 61, except that read word line RWL3 of storage unit d3 and read word line RWL4 of storage unit d4 are enabled. Step 65 is similar to step 64, except that write word line WWL6 of storage unit R2 is enabled. Step 66 is similar to step 63, except that read word line RWL3 of storage unit d3 and read word line RWL4 of storage unit d4 are enabled, and write word line WWL8 of storage unit R4 is enabled.

[0154] In step 67, the read word line RWL7 of memory cell R3, the read word line RWL8 of memory cell R4, and the write word line WWL7 of memory cell R1 are enabled. A second logic level Vlogic(NOR) is applied to the third source line SL02, and the second source line SL01 is grounded. Step 68 is similar to step 67, except that the write word line WWL8 of memory cell R2 is enabled. In step 69, the read word line RWL7 of memory cell R3, the read word line RWL8 of memory cell R4, the read word line RWL5 of memory cell R1, the read word line RWL6 of memory cell R2, and the write word line WWL0 of memory cell P are enabled. A fifth logic level Vlogic(NOR) is applied to the second source line SL01 and the third source line SL02. The first source line SL00 is grounded.

[0155] exist Figure 7In the architecture shown, in some embodiments, the intermediate result unit 102 includes a third unit 1021, a fourth unit 1022, and a fifth unit 1023; the first XOR input data is the input data in the input unit 101, or the first XOR input data is the input data in the input unit 101 and the second XOR result data; the output unit 103 is used to store the second encoding / decoding result data obtained by calculating the second XOR result data, the input data in the input unit 101, and the first intermediate result data, and the output unit 103 is connected to the same source line as the fourth unit 1022.

[0156] Reference Figure 9 As shown, Figure 9 The diagram uses a single column of storage cells as an example for clarity. Figure 9 The memory cells are divided into several units. The input units include memory cells d1, d2, d3, d4, and d5. The third unit includes memory cells R1 and R2, the fourth unit includes memory cells R3 and R4, and the fifth unit includes memory cell R5. The output unit includes memory cell P. Memory cells d1, d2, d3, d4, d5, and R5 are connected to the first source line SL00, memory cells R1 and R2 are connected to the second source line SL01, and memory cells R3, R4, and P are connected to the third source line SL02.

[0157] Error-correcting encoding or decoding of data d1, d2, d3, d4, and d5 yields data P. The process of error-correcting encoding or decoding involves an XOR operation on the data d1, d2, d3, d4, and d5, i.e., P = d1 XOR d2 XOR d3 XOR d4 XOR d5. This process can be broken down into the following steps:

[0158] Step 71: R1 = d1 NOR d2; Step 72: R2 = d1 NOR d2; Step 73: R3 = (d1, d2, R1,R2);

[0159] Step 74: R1 = d3 NOR d4; Step 75: R2 = d3 NOR d4; Step 76: R4 = (d3, d4, R1,R2);

[0160] Step 77: R1 = R3 NOR R4; Step 78: R2 = R3 NOR R4; Step 79: R5 = (R3, R4, R1, R2);

[0161] Step 710: R1 = d5 NOR R5; Step 711: R2 = d5 NOR R5; Step 712: P = (d5, R5, R1, R2).

[0162] Steps 71-73, 74-76, 77-79, and 710-712 are all XOR operations.

[0163] In step 71, the read word line RWL1 of memory cell d1, the read word line RWL2 of memory cell d2, and the write word line WWL6 of memory cell R1 are enabled. A first logic level Vlogic(NOR) is applied to the first source line SL00, and the second source line SL01 is grounded. Step 72 is similar to step 71, except that the write word line WWL7 of memory cell R2 is enabled. In step 73, the read word line RWL1 of memory cell d1, the read word line RWL2 of memory cell d2, the read word line RWL6 of memory cell R1, the read word line RWL7 of memory cell R2, and the write word line WWL8 of memory cell R3 are enabled. A third logic level Vlogic(NOR) is applied to the first source line SL00 and the second source line SL01. The third source line SL02 is grounded.

[0164] Step 74 is similar to step 71, except that read word line RWL3 of storage unit d3 and read word line RWL4 of storage unit d4 are enabled. Step 75 is similar to step 74, except that write word line WWL7 of storage unit R2 is enabled. Step 76 is similar to step 73, except that read word line RWL3 of storage unit d3 and read word line RWL4 of storage unit d4 are enabled, and write word line WWL9 of storage unit R4 is enabled.

[0165] In step 77, the read word line RWL8 of memory cell R3, the read word line RWL9 of memory cell R4, and the write word line WWL6 of memory cell R1 are enabled. A second logic level, Vlogic(NOR), is applied to the third source line SL02, and the second source line SL01 is grounded. Step 78 is similar to step 77, except that the write word line WWL7 of memory cell R2 is enabled. In step 79, the read word line RWL8 of memory cell R3, the read word line RWL9 of memory cell R4, the read word line RWL6 of memory cell R1, the read word line RWL7 of memory cell R2, and the write word line WWL10 of memory cell R5 are enabled. A fourth logic level, Vlogic(NOR), is applied to the second source line SL01 and the third source line SL02. The first source line SL00 is grounded.

[0166] In step 710, the read word line RWL5 of memory cell d5, the read word line RWL10 of memory cell R5, and the write word line WWL6 of memory cell R1 are enabled. A first logic level Vlogic(NOR) is applied to the second source line SL01, and the third source line SL02 is grounded. Step 711 is similar to step 710, except that the write word line WWL7 of memory cell R2 is enabled. In step 712, the read word line RWL5 of memory cell d5, the read word line RWL10 of memory cell R5, the read word line RWL6 of memory cell R1, the read word line RWL7 of memory cell R2, and the write word line WWL0 of memory cell P are enabled. A seventh logic level Vlogic(NOR) is applied to the first source line SL00 and the second source line SL01. The third source line SL02 is grounded.

[0167] exist Figure 7 In the architecture shown, in some embodiments, the intermediate result unit 102 includes a third unit 1021, a fourth unit 1022, and a fifth unit 1023; the first XOR input data is the input data in the input unit 101, or the first XOR input data is the second XOR result data; the output unit 103 is used to store the second encoding / decoding result data obtained by calculating the second XOR result data and the first intermediate result data, and the output unit 103 and the fourth unit 1022 are connected to the same source line.

[0168] Reference Figure 10 As shown, Figure 10 The storage units shown in the diagram are in the same column for clarity. Figure 10 The memory cells are divided into several units. The input units include memory cells d1, d2, d3, d4, d5, d6, d7, and d8. The third unit includes memory cells R1 and R2, the fourth unit includes R3 and R4, and the fifth unit includes R5 and R6. The output unit includes memory cell P. Memory cells d1, d2, d3, d4, d5, d6, d7, d8, R5, and R6 are connected to the first source line SL00. Memory cells R1 and R2 are connected to the second source line SL01, and memory cells R3, R4, and P are connected to the third source line SL02.

[0169] Error-correcting code encoding or decoding of data d1, d2, d3, d4, d5, d6, d7, and d8 yields data P. The error-correcting code encoding or decoding process involves an XOR operation on the data d1, d2, d3, d4, d5, d6, d7, and d8, i.e., P = d1 XOR d2 XOR d3 XOR d4 XOR d5 XOR d6 XOR d7 XOR d8. This process can be broken down into the following steps:

[0170] Step 81: R1 = d1 NOR d2; Step 82: R2 = d1 NOR d2; Step 83: R3 = (d1, d2, R1,R2);

[0171] Step 84: R1 = d3 NOR d4; Step 85: R2 = d3 NOR d4; Step 86: R4 = (d3, d4, R1,R2);

[0172] Step 87: R1 = R3 NOR R4; Step 88: R2 = R3 NOR R4; Step 89: R5 = (R3, R4, R1, R2);

[0173] Step 810: R1 = d5 NOR d6; Step 811: R2 = d5 NOR d6; Step 812: R3 = (d1, d2, R1, R2);

[0174] Step 813: R1 = d7 NOR d8; Step 814: R2 = d7 NOR d8; Step 815: R4 = (d3, d4, R1, R2);

[0175] Step 816: R1 = R3 NOR R4; Step 817: R2 = R3 NOR R4; Step 818: R6 = (R3, R4, R1, R2);

[0176] Step 819: R1 = R5 NOR R6; Step 820: R2 = R5 NOR R6; Step 821: P = (R5, R6, R1, R2).

[0177] Steps 81-83, 84-86, 87-89, 810-812, 813-815, 816-818, and 819-821 are all XOR operations.

[0178] In step 81, the read word line RWL1 of memory cell d1, the read word line RWL2 of memory cell d2, and the write word line WWL9 of memory cell R1 are enabled. A first logic level Vlogic(NOR) is applied to the first source line SL00, and the second source line SL01 is grounded. Step 82 is similar to step 81, except that the write word line WWL10 of memory cell R2 is enabled. In step 83, the read word line RWL1 of memory cell d1, the read word line RWL2 of memory cell d2, the read word line RWL9 of memory cell R1, the read word line RWL10 of memory cell R2, and the write word line WWL11 of memory cell R3 are enabled. A third logic level Vlogic(NOR) is applied to the first source line SL00 and the second source line SL01. The third source line SL02 is grounded.

[0179] Step 84 is similar to step 81, except that the read word line RWL3 of storage unit d3 and the read word line RWL4 of storage unit d4 are enabled. Step 85 is similar to step 84, except that the write word line WWL10 of storage unit R2 is enabled. Step 86 is similar to step 83, except that the read word line RWL3 of storage unit d3 and the read word line RWL4 of storage unit d4 are enabled, and the write word line WWL12 of storage unit R4 is enabled.

[0180] In step 87, the read word line RWL11 of memory cell R3, the read word line RWL12 of memory cell R4, and the write word line WWL9 of memory cell R1 are enabled. A second logic level, Vlogic(NOR), is applied to the third source line SL02, and the second source line SL01 is grounded. Step 88 is similar to step 87, except that the write word line WWL10 of memory cell R2 is enabled. In step 89, the read word line RWL11 of memory cell R3, the read word line RWL12 of memory cell R4, the read word line RWL9 of memory cell R1, the read word line RWL10 of memory cell R2, and the write word line WWL13 of memory cell R5 are enabled. A fourth logic level, Vlogic(NOR), is applied to the second source line SL01 and the third source line SL02. The first source line SL00 is grounded.

[0181] Step 810 is similar to step 81, except that the read word line RWL5 of storage unit d5 and the read word line RWL6 of storage unit d6 are enabled. Step 811 is similar to step 810, except that the write word line WWL10 of storage unit R2 is enabled. Step 812 is similar to step 83, except that the read word line RWL5 of storage unit d5 and the read word line RWL6 of storage unit d6 are enabled.

[0182] Step 813 is similar to step 81, except that the read word line RWL7 of storage unit d7 and the read word line RWL8 of storage unit d8 are enabled. Step 814 is similar to step 813, except that the write word line WWL10 of storage unit R2 is enabled. Step 815 is similar to step 86, except that the read word line RWL7 of storage unit d7 and the read word line RWL8 of storage unit d8 are enabled.

[0183] Steps 816-817 are similar to steps 87-88. Step 818 is similar to step 89, except that the write line WWL14 of memory cell R6 is enabled.

[0184] Step 819 is similar to step 87, except that the read word line RWL13 of memory cell R5 and the read word line RWL14 of memory cell R6 are enabled. Step 820 is similar to step 819, except that the write word line WWL10 of memory cell R2 is enabled. In step 821, the read word line RWL13 of memory cell R5, the read word line RWL14 of memory cell R6, the read word line RWL9 of memory cell R1, the read word line RWL10 of memory cell R2, and the write word line WWL14 of memory cell P are enabled. A sixth logic level Vlogic is applied to the first source line SL00 and the second source line SL01. The third source line SL02 is grounded.

[0185] In the above embodiments, when the storage array is used for error correction code encoding, the input data is the error correction code information bits, and the first or second encoding / decoding result data is the error correction code redundancy bits.

[0186] When the storage array in the above embodiments is used for error correction code decoding, the input data consists of error correction code information bits and error correction code redundancy bits, and the first or second encoding / decoding result data consists of error correction code correction sub-bits.

[0187] The following example illustrates the process of error correction code encoding and error correction code coding of the storage array based on the embodiment of this application, using (7,4) Hamming code as an example.

[0188] For example, the (7,4) Hamming code encoding is based on Figure 3 When the structure shown is implemented, as follows: Figure 11 As shown, Figure 11 The diagram uses a single column of storage cells as an example for clarity. Figure 11The storage units are divided into three parts. Storage units d1, d2, d3, and d4 in this column are used to store information bits d1, d2, d3, and d4, respectively. Storage units P1, P2, and P3 are used to store redundant bits P1, P2, and P3, respectively. Storage units R1, R2, R3, and R4 are used to store intermediate result data during the encoding process.

[0189] Storage cells d1, d2, R3, and P1 are connected to source line SL00; storage cells d3, d4, R4, P2, and P3 are connected to source line SL01; and storage cells R1 and R2 are connected to source line SL02.

[0190] Based on the encoding principle of (7,4) Hamming code, the redundant bit P1 is calculated from the information bits d1, d2, and d4; the redundant bit P2 is calculated from the information bits d1, d3, and d4; and the redundant bit P3 is calculated from the information bits d2, d3, and d4. The calculation method is as follows:

[0191] P1=d1 XOR d2 XOR d4; P2=d1 XOR d3 XOR d4; P3=d2 XOR d3 XOR d4.

[0192] In other words, P1 is the encoding result obtained by XORing d1, d2, and d4; P2 is the encoding result obtained by XORing d1, d3, and d4; and P3 is the encoding result obtained by XORing d2, d3, and d4.

[0193] Reference Figure 3 The structure shown, for the calculation process of P1, includes input units d1, d2, and d4; intermediate result units R1, R2, and R4; and output unit P1. The first unit includes d1 and d2, the second unit includes d4, the third unit includes R1 and R2, and the fourth unit includes R4. Storage units d1, d2, and P1 are connected to the first source line SL00; storage units d4 and R4 are connected to the second source line SL01; and storage units R1 and R2 are connected to the third source line SL02.

[0194] For the calculation process of P2, the input units include storage units d1, d3, and d4; the intermediate result units include storage units R1, R2, and R3; and the output unit includes storage unit P2. The first unit includes storage units d3 and d4; the second unit includes storage unit d1; the third unit includes storage units R1 and R2; and the fourth unit includes storage unit R3. Storage units d3, d4, and P2 are connected to the first source line SL01; storage units d1 and R3 are connected to the second source line SL00; and storage units R1 and R2 are connected to the third source line SL02.

[0195] For the calculation process of P3, the input units include storage units d2, d3, and d4; the intermediate result units include storage units R1, R2, and R3; and the output unit includes storage unit P3. The first unit includes storage units d3 and d4; the second unit includes storage unit d2; the third unit includes storage units R1 and R2; and the fourth unit includes storage unit R3. Storage units d3, d4, and P3 are connected to the first source line SL01; storage units d1 and R3 are connected to the second source line SL00; and storage units R1 and R2 are connected to the third source line SL02.

[0196] For detailed calculations of P1, P2, and P3, please refer to [the provided text]. Figure 4 The illustrations in the examples are as follows.

[0197] For example, the (7,4) Hamming code decoding is based on Figure 7 When the structure shown is implemented, as follows: Figure 12 As shown, Figure 12 The diagram uses a single column of storage cells as an example for clarity. Figure 12 The storage units are divided into three parts. Storage units d1, d2, d3, and d4 in this column are used to store information bits d1, d2, d3, and d4, respectively. Storage units P1, P2, and P3 are used to store redundant bits P1, P2, and P3, respectively. Storage units S1, S2, and S3 are used to store correction bits S1, S2, and S3, respectively. Storage units R1, R2, R3, and R4 are used to store intermediate result data during the decoding process.

[0198] Storage cells d1, d2, d3, d4, P1, P2, P3, S1, S2, and S3 are connected to source line SL00. Storage cells R1 and R2 are connected to source line SL01. Storage cells R3 and R4 are connected to source line SL02.

[0199] Based on the decoding principle of (7,4) Hamming code, the correction bit S1 is calculated from information bits P1, d1, d2, and d4; the correction bit S2 is calculated from information bits P2, d1, d3, and d4; and the correction bit S3 is calculated from information bits P3, d2, d3, and d4. The calculation method is as follows:

[0200] S1 = P1 XOR d1 XOR d2 XOR d4; S2 = P2 XOR d1 XOR d3 XOR d4; S3 = P3

[0201] In other words, S1 is the decoding result obtained by XORing P1, d1, d2, and d4; S2 is the decoding result obtained by XORing P2, d1, d3, and d4; and S3 is the decoding result obtained by XORing P3, d2, d3, and d4.

[0202] Reference Figure 7 The structure shown, for the calculation process of S1, includes input units P1, d1, d2, and d4; intermediate result units R1, R2, R3, and R4; and output unit S1. The third unit includes R1 and R2, and the fourth unit includes R3 and R4. Storage units P1, d1, d2, d4, and S1 are connected to the first source line SL00; storage units R1 and R2 are connected to the second source line SL01; and storage units R3 and R4 are connected to the third source line SL02.

[0203] For the calculation process of S2, the input units include storage units P2, d1, d3, and d4; the intermediate result units include storage units R1, R2, R3, and R4; and the output unit includes storage unit S2. The third unit includes storage units R1 and R2, and the fourth unit includes storage units R3 and R4. Storage units P2, d1, d3, d4, and S2 are connected to the first source line SL00; storage units R1 and R2 are connected to the second source line SL01; and storage units R3 and R4 are connected to the third source line SL02.

[0204] For the calculation process of S3, the input units include storage units P3, d2, d3, and d4; the intermediate result units include storage units R1, R2, R3, and R4; and the output unit includes storage unit S3. The third unit includes storage units R1 and R2, and the fourth unit includes storage units R3 and R4. Storage units P3, d2, d3, d4, and S3 are connected to the first source line SL00; storage units R1 and R2 are connected to the second source line SL01; and storage units R3 and R4 are connected to the third source line SL02.

[0205] For detailed calculations of S1, S2, and S3, please refer to [the provided text]. Figure 8 The illustrations in the examples are as follows.

[0206] In the storage array provided in this application embodiment, every two adjacent columns of storage cells can share source lines, which can reduce the number of source lines corresponding to a single column of storage cells, effectively alleviate the wiring congestion and area overhead problems that may be caused by the increase in the number of source lines, and achieve a balance between high performance and manufacturing cost.

[0207] For example, the columns of storage cells in the storage array are named sequentially as column 0, column 1, column 2, and column 3, and so on. Column 0 and column 1 share a source line, as do column 2 and column 3, and so on.

[0208] In the storage array provided in this application embodiment, each column of storage cells can be connected to multiple bit lines. Taking two bit lines as an example, in the same column of storage cells, some storage cells are connected to one bit line, and other storage cells are connected to another bit line. When multiple bit lines are connected to each column of storage cells, multiple calculations can be performed simultaneously in one column of storage cells through multiple bit lines, which can further improve the calculation efficiency.

[0209] This application provides an error correction code encoding and decoding method, applied to a method based on... Figure 3 The method includes the following for a storage array with the architecture shown:

[0210] The read word line of the storage unit corresponding to the first XOR input data is enabled, the write word line of the third unit is enabled, the first source line is connected to the first logic level, and the third source line is grounded, so as to write the first intermediate result data into the third unit.

[0211] The read word line of the storage unit corresponding to the first XOR input data and the first intermediate result data is enabled, the write word line of the fourth unit is enabled, the first source line and the third source line are connected to the third logic level, and the second source line is grounded, so as to write the first XOR result data into the fourth unit.

[0212] The read lines of the second, third, and fourth control units are enabled, the write lines of the output unit are enabled, the second and third source lines are connected to the fifth logic level, and the first source line is grounded, so as to write the first encoding and decoding result data into the output unit.

[0213] This application provides an error correction code encoding and decoding method, applied to a method based on... Figure 3 The method includes the following for a storage array with the architecture shown:

[0214] The read word line of the storage unit corresponding to the first XOR input data is enabled, the write word line of the third unit is enabled, the first source line is connected to the first logic level, and the third source line is grounded, so as to write the first intermediate result data into the third unit.

[0215] The read word line of the storage unit corresponding to the first XOR input data and the first intermediate result data is enabled, the write word line of the fourth unit is enabled, the first source line and the third source line are connected to the third logic level, and the second source line is grounded, so as to write the first XOR result data into the fourth unit.

[0216] The read word line of the storage cell corresponding to the second XOR input data is enabled, the write word line of the third cell is enabled, the second source line is connected to the second logic level, and the third source line is grounded, so as to write the second intermediate result data into the third cell.

[0217] The read word line of the storage unit corresponding to the second XOR input data and the second intermediate result data is enabled, the write word line of the fifth unit is enabled, the second source line and the third source line are connected to the fourth logic level, and the first source line is grounded, so as to write the second XOR result data into the fifth unit.

[0218] The read word lines of the second, third, and fourth control units are enabled, the write word lines of the output unit are enabled, the second and third source lines are connected to the fifth logic level, and the first source line is grounded, so as to write the first encoded / decoded result data into the output unit; or,

[0219] The read lines of the third and fifth control units are enabled, the write lines of the output unit are enabled, the second and third source lines are connected to the sixth logic level, and the first source line is grounded, so as to write the second encoding / decoding result data into the output unit; or,

[0220] The read lines of the first, third, and fifth units are enabled, the write lines of the output unit are enabled, the first and third source lines are connected to the seventh logic level, and the second source line is grounded, so as to write the second encoding and decoding result data into the output unit.

[0221] This application provides an error correction code encoding and decoding method, applied to a method based on... Figure 7 The method includes the following for a storage array with the architecture shown:

[0222] The read word line of the storage unit corresponding to the first XOR input data is enabled, the write word line of the third unit is enabled, the first source line is connected to the first logic level, and the second source line is grounded, so as to write the first intermediate result data into the third unit.

[0223] The read word line of the storage unit corresponding to the first XOR input data and the first intermediate result data is enabled, the write word line of the fourth unit is enabled, the first source line and the second source line are connected to the third logic level, and the third source line is grounded, so as to write the first XOR result data into the fourth unit.

[0224] The read lines of the third and fourth control units are enabled, the write lines of the output unit are enabled, the second and third source lines are connected to the fifth logic level, and the first source line is grounded, so as to write the first encoding and decoding result data into the output unit.

[0225] This application provides an error correction code encoding and decoding method, applied to a method based on... Figure 7 The method includes the following for a storage array with the architecture shown:

[0226] The read word line of the storage unit corresponding to the first XOR input data is enabled, the write word line of the third unit is enabled, the first source line is connected to the first logic level, and the second source line is grounded, so as to write the first intermediate result data into the third unit.

[0227] The read word line of the storage unit corresponding to the first XOR input data and the first intermediate result data is enabled, the write word line of the fourth unit is enabled, the first source line and the second source line are connected to the third logic level, and the third source line is grounded, so as to write the first XOR result data into the fourth unit.

[0228] The read word line of the storage unit corresponding to the second XOR input data is enabled, the write word line of the third unit is enabled, the third source line is connected to the second logic level, and the second source line is grounded, so as to write the second intermediate result data into the third unit.

[0229] The read word line of the storage unit corresponding to the second XOR input data and the second intermediate result data is enabled, the write word line of the fifth unit is enabled, the second source line and the third source line are connected to the fourth logic level, and the first source line is grounded, so as to write the second XOR result data into the fifth unit.

[0230] The read lines of the third and fourth control units are enabled, the write lines of the output unit are enabled, the second and third source lines are connected to the fifth logic level, and the first source line is grounded, so as to write the first encoding and decoding result data into the output unit.

[0231] Alternatively, the read lines of the third and fifth units are enabled, the write lines of the output unit are enabled, the first and second source lines are connected to the sixth logic level, and the third source line is grounded, so as to write the second encoding and decoding result data into the output unit.

[0232] Alternatively, the read lines of the control input unit, the third unit, and the fifth unit are enabled, the write lines of the output unit are enabled, the first source line and the second source line are connected to the seventh logic level, and the third source line is grounded, so as to write the second encoding / decoding result data into the output unit.

[0233] The implementation principle and technical effects of the error correction code encoding and decoding method provided in this application can be found in the description of the foregoing embodiments, and will not be repeated here.

[0234] The methods described in this application embodiment can be executed by a control unit electrically connected to the storage array.

[0235] Figure 13 This is a schematic diagram of the control unit provided in this application. Figure 13 As shown, the control unit 130 provided in this embodiment includes at least one processor 1301 and a memory 1302. Optionally, the control unit 130 further includes a communication component 1303. The processor 1301, memory 1302, and communication component 1303 are connected via a bus.

[0236] In a specific implementation, at least one processor 1301 executes computer execution instructions stored in memory 1302, causing at least one processor 1301 to perform the above-described method.

[0237] The specific implementation process of processor 1301 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0238] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microcontroller (MCU) or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0239] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0240] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0241] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0242] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0243] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0244] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an application-specific integrated circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0245] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0246] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0247] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0248] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0249] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0250] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A memory array comprising: The application relates to a memory device, comprising: a plurality of memory cells, each memory cell comprising an input unit, an intermediate result unit and an output unit; the input unit is used for storing input data of error correction code encoding and decoding, the error correction code encoding and decoding process comprises a plurality of steps of exclusive OR operation, and the input unit comprises a first unit and a second unit; the intermediate result unit comprises a third unit and a fourth unit, or the intermediate result unit comprises the third unit, the fourth unit and a fifth unit; the third unit is used for storing first intermediate result data obtained by calculating first exclusive OR input data and is used for storing second intermediate result data obtained by calculating second exclusive OR input data; the fourth unit is used for storing first exclusive OR result data obtained by calculating the first exclusive OR input data and the first intermediate result data; the fifth unit is used for storing second exclusive OR result data obtained by calculating the second exclusive OR input data and the second intermediate result data; the first exclusive OR input data is input data in the first unit and / or the second exclusive OR result data; the second exclusive OR input data is input data in the second unit and / or the first exclusive OR result data; the first unit, the second unit and the third unit are respectively connected with different source lines, the fourth unit is connected with the same source line as the second unit, and the fifth unit is connected with the same source line as the first unit; the output unit is used for storing first encoding and decoding result data obtained by calculating the second intermediate result data, the first exclusive OR result data and input data in the second unit, and the output unit is connected with the same source line as the first unit; or the output unit is used for storing second encoding and decoding result data obtained by calculating the first intermediate result data and the second exclusive OR result data or second encoding and decoding result data obtained by calculating the first intermediate result data, the second exclusive OR result data and input data in the first unit, and the output unit is connected with the same source line as the second unit.

2. The storage array of claim 1, wherein, the source lines comprise a first source line, a second source line and a third source line; the first unit is connected with the first source line, the second unit is connected with the second source line, and the third unit is connected with the third source line.

3. The storage array of claim 1, wherein, the first unit comprises at least two memory cells, the second unit comprises at least one memory cell, the third unit comprises at least two memory cells, the fourth unit comprises at least one memory cell, the fifth unit comprises at least one memory cell, and the output unit comprises at least one memory cell.

4. A memory array comprising: The application relates to a memory device, comprising: a plurality of memory cells, each memory cell comprising an input unit, an intermediate result unit and an output unit; the input unit is used for storing input data of error correction code encoding and decoding, the error correction code encoding and decoding process comprises a plurality of steps of exclusive OR operation; The intermediate result unit comprises a third unit and a fourth unit, or the intermediate result unit comprises the third unit, the fourth unit and a fifth unit; the third unit is configured to store first intermediate result data obtained by calculating first exclusive or input data, and is configured to store second intermediate result data obtained by calculating second exclusive or input data; The fourth unit is configured to store first exclusive or result data obtained by calculating the first exclusive or input data and the first intermediate result data; The fifth unit is configured to store second exclusive or result data obtained by calculating the second exclusive or input data and the second intermediate result data; The first exclusive or input data is input data in the input unit and / or the second exclusive or result data; The second exclusive or input data is the first exclusive or result data; The input unit, the third unit and the fourth unit are respectively connected to different source lines, and the fifth unit and the input unit are connected to the same source line; The output unit is configured to store first encoding result data obtained by calculating the first exclusive or result data and the second intermediate result data, and the output unit and the input unit are connected to the same source line; Or, The output unit is configured to store second encoding result data obtained by calculating the second exclusive or result data and the first intermediate result data, or second encoding result data obtained by calculating the second exclusive or result data, the input data and the first intermediate result data, and the output unit and the fourth unit are connected to the same source line.

5. The storage array of claim 4, wherein, The source lines comprise a first source line, a second source line and a third source line; The input unit is connected to the first source line, the third unit is connected to the second source line, and the fourth unit is connected to the third source line.

6. The storage array of claim 4, wherein, The input unit comprises at least four storage units, the third unit comprises at least two storage units, the fourth unit comprises at least two storage units, the fifth unit comprises at least one storage unit, and the output unit comprises at least one storage unit.

7. The storage array of any of claims 1-6, wherein, In the case of error correction code encoding, the input data is error correction code information bits, and the first encoding result data or the second encoding result data is error correction code redundant bits; In the case of error correction code decoding, the input data is error correction code information bits and error correction code redundant bits, and the first encoding result data or the second encoding result data is error correction code syndrome bits.

8. The storage array of any of claims 1-6, wherein, Every two adjacent storage units in each column share the source line; And / or, each column of storage units is connected to a plurality of bit lines.

9. The storage array of any of claims 1-6, wherein, The storage unit comprises a magnetic storage device, and the magnetic storage device is a spin orbit torque magnetic storage device or a spin transfer torque magnetic storage device.

10. An error-correcting code encoding method characterized by comprising: The method is applied to the storage array of any one of claims 1-3, and the method comprises: controlling the read word line of the storage unit corresponding to the first exclusive or input data to be effective, the write word line of the third unit to be effective, the first source line to be connected to a first logic level, and the third source line to be grounded, so as to write the first intermediate result data into the third unit; controlling the read word line of the storage unit corresponding to the first exclusive or input data and the first intermediate result data to be effective, the write word line of the fourth unit to be effective, the first source line to be connected to the third logic level, the third source line to be connected to the fourth logic level, and the second source line to be grounded, so as to write the first exclusive or result data into the fourth unit; controlling the read word line of the second unit, the third unit and the fourth unit to be effective, the write word line of the output unit to be effective, the second source line to be connected to the seventh logic level, the third source line to be connected to the eighth logic level, and the first source line to be grounded, so as to write the first encoding result data into the output unit.

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