A high-side current limiting protection circuit based on output voltage difference dynamic switching

Abstract

The application discloses a kind of high edge current limiting protection circuit based on output voltage differential dynamic switching in the technical field of semiconductor integrated circuit, including current detection circuit, first NMOS tube, output voltage detection circuit, data selector and current limiting circuit.The application is by two first current detection circuit and second current detection circuit with different sampling ratio, multiplexing current limiting circuit, the segmented current limiting protection of first NMOS tube linear region and saturation region is realized, the problem that single current limiting point cannot adapt to multiple working conditions is solved, through the linkage of voltage differential detection and two-way data selector, the automatic switching of current limiting threshold is realized, ensure that first NMOS tube is in safe current range under different working conditions, improve the reliability of high side switch system, adaptive optimal protection under all conditions is realized, adapt to different safety current demand of first NMOS tube linear region and saturation region, significantly improve the reliability of high side switch.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, specifically a high-side current limiting protection circuit based on dynamic switching of output voltage difference. Background Technology

[0002] High-side switches are widely used in automotive and industrial applications to replace fuses and mechanical switches. By integrating NMOS transistors, logic circuits, and driver circuits, high-side switches provide power and control for devices such as motors, headlights, and electronic control units (ECUs). High-side switches offer overcurrent protection, overtemperature protection, short-circuit protection, and load current detection, effectively improving the reliability and safety of power supply systems compared to conventional fuses and mechanical switches. NMOS transistor current detection is a key technology. Existing methods for high-side switch current detection include:

[0003] Series sampling resistor detection method: This method obtains the current signal by connecting a sampling resistor in series in the main circuit. However, the sampling resistor will generate a large power consumption, especially in the case of long-term operation with high current. The resistor will heat up severely, which will not only reduce the system energy efficiency, but also cause device reliability risks.

[0004] SenseFET sampling method: Current sampling is performed by integrating a SenseFET with the main NMOS transistor. No additional series resistor is required, which avoids the heat generation problem of the sampling circuit and is easier to integrate. The sampling accuracy depends on the matching degree between the SenseFET and the main NMOS transistor.

[0005] Existing current limiting protection schemes for high-side switches typically employ a single current limiting point design, which cannot adapt to the different safety current requirements of the linear and saturation regions of the power transistor: if the current limiting point is set according to the maximum current in the linear region, the current exceeding the safety threshold during operation in the saturation region will cause device damage; if the current limiting point is set according to the safety current in the saturation region, the normal operating current in the linear region will be limited, reducing system efficiency. Summary of the Invention

[0006] The purpose of this invention is to provide a high-side current limiting protection circuit based on dynamic switching of output voltage difference, so as to solve the problem that the above-mentioned single fixed current limiting protection scheme for high-side switch cannot adapt to different operating states of power transistors.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] In a first aspect, the present invention provides a high-side current limiting protection circuit based on dynamic switching of output voltage difference, comprising:

[0009] A current detection circuit, wherein the first input terminal of the current detection circuit is connected to the drain of the first NMOS transistor, and the second input terminal of the current detection circuit is connected to the source of the first NMOS transistor, and the current detection circuit is used to detect the load current flowing through the first NMOS transistor and generate a first sampling current and a second sampling current.

[0010] The drain of the first NMOS transistor is connected to the voltage input terminal V. IN The gate of the first NMOS transistor is connected to a charge pump, and the source of the first NMOS transistor is connected to the voltage output terminal V. OUT ;

[0011] An output voltage detection circuit is provided, wherein the non-inverting input terminal of the output voltage detection circuit is connected to the source of the first NMOS transistor, and the inverting input terminal of the output voltage detection circuit is connected to the voltage input terminal V. IN The output voltage detection circuit is used to detect the voltage input terminal V. IN With voltage output terminal V OUT The pressure difference ΔV between them is used to determine the control signal output.

[0012] A data selector, wherein the data input terminal of the data selector is connected to the output terminal of a current detection circuit, the selection input terminal of the data selector is connected to an output voltage detection circuit, and the output terminal of the data selector outputs a detected voltage V. IMON The output of the data selector is connected to a current-sensing resistor R. SENSE The first terminal, the current sensing resistor R SENSE The second terminal is grounded. The data selector receives a control signal and selects either the first sampling current or the second sampling current as the detection current I based on the control signal. SENSE ;

[0013] A current limiting circuit is provided, wherein the input terminal of the current limiting circuit is connected to the output terminal of the data selector and the gate of the first NMOS transistor, and the output terminal of the current limiting circuit is grounded. The current limiting circuit is used to limit the current flowing through the first NMOS transistor to a current limiting threshold corresponding to the currently selected first sampling current or second sampling current.

[0014] As a further aspect of the present invention: the output voltage detection circuit includes a comparator, the non-inverting input terminal of the comparator being connected to the source of a first NMOS transistor, and the inverting input terminal of the comparator being connected to the voltage input terminal V. IN The output of the comparator is connected to the selection input of the data selector;

[0015] The comparator outputs a pressure difference ΔV, and when the pressure difference (ΔV) is greater than a preset threshold (V0), the comparator will continue to operate. Delta When the pressure difference (ΔV) is less than or equal to the preset threshold (V), a first control signal is output.Delta When the first control signal and the second control signal are combined, a second control signal is output.

[0016] As a further aspect of the present invention: the current detection circuit includes a first current detection circuit and a second current detection circuit. The first input terminal of the first current detection circuit is connected to the drain of the first NMOS transistor, and the second input terminal of the first current detection circuit is connected to the source of the first NMOS transistor. The first current detection circuit detects the load current flowing through the first NMOS transistor and generates a first sampling current.

[0017] The first input terminal of the second current detection circuit is connected to the drain of the first NMOS transistor, and the second input terminal of the second current detection circuit is connected to the source of the first NMOS transistor. The first current detection circuit detects the load current flowing through the first NMOS transistor and generates a second sampling current.

[0018] As a further aspect of the present invention: the data selector is a multiplexer, the data input terminal of the multiplexer is connected to the output terminal of the current detection circuit, the selection input terminal of the multiplexer is connected to the output voltage detection circuit, and the output terminal of the multiplexer outputs the detection voltage V. IMON The output terminal of the multiplexer is connected to a current-sensing resistor R. SENSE The first terminal, the current sensing resistor R SENSE The second terminal is grounded.

[0019] As a further aspect of the present invention: the current limiting circuit includes a first operational amplifier and a second NMOS transistor, the non-inverting input of the first operational amplifier is connected to the output of the multiplexer, and the inverting input of the first operational amplifier is connected to a reference voltage V. REF The output terminal of the first operational amplifier is connected to the gate of the second NMOS transistor, the drain of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is grounded.

[0020] As a further aspect of the present invention: both the first current detection circuit and the second current detection circuit are SenseFET current detection circuits, each SenseFET current detection circuit including a third NMOS transistor and a fourth PMOS transistor, wherein the gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, and the drain of the third NMOS transistor is connected to the voltage input terminal V. IN The source of the third NMOS transistor is connected to the inverting input of the second operational amplifier and the source of the fourth PMOS transistor. The non-inverting input of the second operational amplifier is connected to the source of the first NMOS transistor. The output of the second operational amplifier is connected to the gate of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the data input of the multiplexer.

[0021] As a further aspect of the present invention: the ratio of the first sampling current to the load current is a first proportional coefficient K1, and the ratio of the second sampling current to the load current is a second proportional coefficient K2, wherein the second proportional coefficient K2 < the first proportional coefficient K1.

[0022] As a further aspect of the present invention: when the first current detection circuit is activated to generate the first sampling current, the corresponding first current limiting threshold is I. LIMIT1 =V REF / R SENSE ×K1;

[0023] When the second current detection circuit is activated and generates the second sampling current, the corresponding second current limiting threshold is I. LIMIT2 =V REF / R SENSE ×K2, where I LIMIT2 LIMIT1 .

[0024] Secondly, the present invention provides a high-side switching chip that integrates the aforementioned high-side current limiting protection circuit based on dynamic switching of output voltage difference.

[0025] Thirdly, the present invention provides an electronic system including a power supply, a load, and a power supply path connected between the power supply and the load, wherein a high-side switch chip is disposed in the power supply path.

[0026] Compared with the prior art, the beneficial effects of the present invention are:

[0027] 1. This invention utilizes two current detection circuits with differentiated sampling ratios (first and second) and a current limiting circuit to achieve segmented current limiting protection for the linear and saturation regions of the first NMOS transistor. This solves the problem that a single current limiting point cannot adapt to multiple operating states. By linking voltage difference detection with a two-to-one data selector, the current limiting threshold is automatically switched, ensuring that the first NMOS transistor remains within a safe current range under different operating states. This improves the reliability of the high-side switching system and achieves adaptive optimal protection under all operating conditions. It fundamentally resolves the contradiction of a fixed current limiting point, adapts to the different safe current requirements of the linear and saturation regions of the first NMOS transistor, and significantly improves the reliability, safety, and efficiency of the high-side switch.

[0028] 2. In this invention, both the first and second current detection circuits in the current detection circuit are SenseFET current detection circuits, and their corresponding sampling ratios satisfy k2 < k1. The first current detection circuit mirrors the sensing current by ratio K1, and the second current detection circuit mirrors the sensing current by ratio K2. The mirrored current I output by the second current detection circuit...​SENSE2 I greater than the output of the first current detection circuit SENSE1 Achieve the first current limiting threshold I LIMIT2 The differentiated design of the second current limiting threshold LIMIT1 precisely matches the safety current requirements of the first NMOS transistor 3 under different operating states.

[0029] 3. This invention uses a negative feedback closed loop composed of a first operational amplifier and a second NMOS transistor in the current limiting circuit to ensure current limiting accuracy. At the same time, the circuit structure is simple, easy to integrate, and adaptable to the miniaturization requirements of high-side switching chips, resulting in good performance. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the circuit structure of the present invention;

[0031] Figure 2 This is a schematic diagram of the high-side current sensing principle of SenseFET.

[0032] In the diagram: 1. Current detection circuit; 2. Data selector; 3. First NMOS transistor; 4. Current limiting circuit; 5. Output voltage detection circuit. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example:

[0034] Please see Figure 1 and Figure 2 This embodiment provides a high-side current limiting protection circuit based on dynamic switching of output voltage difference, including current detection circuit 1, first NMOS transistor 3 (NM0), output voltage detection circuit 5, data selector 2 and current limiting circuit 4;

[0035] The current detection circuit 1 has a first input terminal connected to the drain of the first NMOS transistor 3 and a second input terminal connected to the source of the first NMOS transistor 3. The current detection circuit 1 is used to detect the load current flowing through the first NMOS transistor 3 and generate a first sampling current and a second sampling current.

[0036] The drain of the first NMOS transistor 3 is connected to the voltage input terminal V. IN The gate of the first NMOS transistor 3 is connected to the charge pump, and the source of the first NMOS transistor 3 is connected to the voltage output terminal V. OUT ;

[0037] Output voltage detection circuit 5, the non-inverting input terminal of output voltage detection circuit 5 is connected to the source of the first NMOS transistor 3, and the inverting input terminal of output voltage detection circuit 5 is connected to the voltage input terminal V. IN The output voltage detection circuit 5 is used to detect the voltage input terminal V. IN The voltage difference ΔV between the voltage output terminal VOUT and the voltage output terminal is used to generate a control signal.

[0038] Data selector 2 has its data input terminal connected to the output terminal of current detection circuit 1, and its selection input terminal connected to output voltage detection circuit 5. The output terminal of data selector 2 outputs the detected voltage V. IMON The output of data selector 2 is connected to a current sensing resistor R. SENSE The first terminal, current sensing resistor R SENSE The second terminal is grounded, and data selector 2 receives the control signal and selects either the first sampling current or the second sampling current as the detection current I according to the control signal. SENSE ;

[0039] The input terminal of the current limiting circuit 4 is connected to the output terminal of the data selector 2 and the gate of the first NMOS transistor 3, and the output terminal of the current limiting circuit 4 is grounded. The current limiting circuit 4 is used to limit the current flowing through the first NMOS transistor 3 to a current limiting threshold corresponding to the currently selected first sampling current or second sampling current.

[0040] The current detection circuit 1 includes a first current detection circuit and a second current detection circuit. The first input terminal of the first current detection circuit is connected to the drain of the first NMOS transistor 3, and the second input terminal of the first current detection circuit is connected to the source of the first NMOS transistor 3. The first current detection circuit detects the load current flowing through the first NMOS transistor 3 and generates a first sampling current.

[0041] The first input terminal of the second current detection circuit is connected to the drain of the first NMOS transistor 3, and the second input terminal of the second current detection circuit is connected to the source of the first NMOS transistor 3. The first current detection circuit detects the load current flowing through the first NMOS transistor 3 and generates a second sampling current.

[0042] Both the first and second current detection circuits are SenseFET current detection circuits. The SenseFET current detection circuit includes a third NMOS transistor (NM2) and a fourth PMOS transistor (PM3). The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, and the drain of the third NMOS transistor is connected to the voltage input terminal V. INThe source of the third NMOS transistor is connected to the inverting input of the second operational amplifier (OP2) and the source of the fourth PMOS transistor. The non-inverting input of the second operational amplifier is connected to the source of the first NMOS transistor 3. The output of the second operational amplifier is connected to the gate of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the data input of the multiplexer. The ratio of the first sampling current to the load current is the first proportional coefficient K1, and the ratio of the second sampling current to the load current is the second proportional coefficient K2, where the second proportional coefficient K2 < the first proportional coefficient K1. When the first current detection circuit is activated to generate the first sampling current, the corresponding first current limiting threshold is I. LIMIT1 =V REF / R SENSE ×K1;

[0043] When the second current detection circuit is activated and generates the second sampling current, the corresponding second current limiting threshold is I. LIMIT2 =V REF / R SENSE ×K2, where I LIMIT2 LIMIT1 ;

[0044] The charge pump generates a drive voltage to turn on the gate (GATE) of the first NMOS transistor 3. Normally, the GATE voltage will cause the first NMOS transistor 3 to be fully turned on and operate in the linear region. The output voltage detection circuit 5 detects the difference between the input and output voltages. When the output voltage V... OUT With input voltage V IN Pressure difference greater than V Delta Select the second current detection circuit for current sampling. When the voltage difference between the output voltage VOUT and the input voltage VIN is less than V... Delta Once the output voltage is established, the first current detection circuit is selected for current sampling. The sampled current flows through the sampling resistor R. SENSE Generate sampling voltage V IMON Sampling voltage V IMON The input to the non-inverting input of the operational amplifier in current limiting circuit 4 is the reference voltage V. REF As the current of the first NMOS transistor 3 increases, the sampling voltage also rises. When the sampling voltage reaches the reference voltage VREF, the output voltage of the current-limiting operational amplifier begins to rise, turning on NM1, pulling down the GATE voltage, and increasing the on-resistance of the first NMOS transistor 3, thereby limiting the current flowing through the first NMOS transistor 3. Through negative feedback, the current-limiting operational amplifier will increase the detected voltage V. IMON The value remains at V REF This limits the maximum flow rate.

[0045] The detection current I output by the second current detection circuit SENSE2 ​is greater than the detected current I of the first current detection circuit under the same load current condition SENSE1 , in order to ensure that the sampling voltage V IMON can reach the reference voltage V at a smaller power transistor current REF , so that the current limit point before the output voltage is fully established is less than the current limit point after the output voltage is established. The power transistor operates in the saturation region, and a relatively high voltage needs to be borne across its source and drain terminals. At the same time, a large current will flow through, causing serious heating, thus reaching the safe operating area of the power transistor and resulting in damage to the power transistor. At this time, the current needs to be reduced to protect the power transistor. When the output voltage is established, the power transistor operates in the linear region, and because the on-resistance is small, a relatively large current can flow through;

[0046] Set the current sampled by the first current detection circuit to be I OUT / k1, and the current sampled by the second current detection circuit to be I OUT / k2, where k2 < k1. When the first current detection circuit samples the current, the output limit current I LIMIT1 is V REF / R SENSE *k1. When the second current detection circuit samples the current, the output limit current I LIMIT2 is V REF / R SENSE *k2. Because k2 < k1, therefore, I LIMIT2 < I LIMIT1 .

[0047] Specifically, by setting the output voltage detection circuit 5 to continuously detect the voltage input terminal V IN and the voltage output terminal V OUTThe voltage difference ΔV between the two current sensors is used to generate a control signal. This control signal controls the data selector 2 to select either the first sampling current of the first current detection circuit or the second sampling current of the second current detection circuit from the current detection circuit 1. This signal is then fed into the current limiting circuit 4. Because the proportional coefficients of the first and second current detection circuits are different, the current limiting thresholds achieved under the same reference voltage and current sensing resistor are also different. When a large voltage difference is detected, i.e., the risk of saturation is high, a larger proportion of the detection signal is selected, causing the current limiting circuit 4 to trigger protection action under a smaller load current. This results in a lower current limiting threshold, ensuring that the first NMOS transistor 3 operates in the safe region under high voltage difference. When a small voltage difference is detected, i.e., it operates in the linear region, a smaller proportion of the detection signal is selected, causing the current limiting circuit 4 to trigger protection action under a higher load current. Triggering protection, a higher current limiting threshold is adopted to fully utilize the load-carrying capacity of the first NMOS transistor 3. This invention employs two current detection circuits with differentiated sampling ratios, a first current detection circuit and a second current detection circuit, and reuses the current limiting circuit 4 to achieve segmented current limiting protection between the linear region and the saturation region of the first NMOS transistor 3. This solves the problem that a single current limiting point cannot adapt to multiple operating states. Through the linkage of voltage difference detection and the two-to-one data selector 2, the current limiting threshold is automatically switched to ensure that the first NMOS transistor 3 is within the safe current range under different operating states, thereby improving the reliability of the high-side switching system. It achieves adaptive optimal protection under all operating conditions, fundamentally solving the contradiction of a fixed current limiting point, adapting to the different safe current requirements of the linear region and the saturation region of the first NMOS transistor 3, and significantly improving the reliability, safety and working efficiency of the high-side switch.

[0048] Furthermore, in the current detection circuit 1 of the present invention, both the first current detection circuit and the second current detection circuit are SenseFET current detection circuits, and the corresponding sampling ratio coefficients satisfy k2 < k1. The first current detection circuit mirrors the sensing current according to ratio K1, and the second current detection circuit mirrors the sensing current according to ratio K2. The mirrored current I output by the second current detection circuit is... SENSE2 I greater than the output of the first current detection circuit SENSE1 Achieve the first current limiting threshold I LIMIT2 <Second current limiting threshold I LIMIT1 The differentiated design precisely matches the safety current requirements of the first NMOS transistor 3 under different operating states;

[0049] The current limiting circuit 4 uses a negative feedback closed loop composed of the first operational amplifier and the second NMOS transistor to ensure current limiting accuracy. At the same time, the circuit structure is simple, easy to integrate and implement, and adapts to the miniaturization requirements of high-side switching chips, resulting in good performance.

[0050] In this embodiment, the output voltage detection circuit 5 includes a comparator (CMP1). The non-inverting input of the comparator is connected to the source of the first NMOS transistor 3, and the inverting input of the comparator is connected to the voltage input terminal V. IN The output of the comparator is connected to the selection input of the data selector 2;

[0051] The comparator outputs a pressure difference ΔV, and when the pressure difference (ΔV) is greater than a preset threshold (V0), it will trigger a test. Delta When the pressure difference (ΔV) is less than or equal to a preset threshold (V), the first control signal is output. Delta When the first control signal is output, the second control signal is output, and the first control signal and the second control signal form a control signal.

[0052] Specifically, the output voltage detection circuit 5 is used to determine the voltage difference between the input and output voltages. When V OUT Less than V IN -V DELT When A is low, the comparator (CMP1) outputs a low level, and the output current of the 2-to-1 selector is the current detected by the second current detection circuit. When V... OUT Greater than V IN -V DELTA When the comparator CMP1 outputs a high level, the output current of the 2-to-1 selector is the current detected by the first current detection circuit. This allows for the output of different proportions of the detection current when the output voltage and input voltage difference are different.

[0053] In this embodiment, the data selector 2 is a multiplexer (MUX). The data input terminal of the multiplexer is connected to the output terminal of the current detection circuit 1, the selection input terminal of the multiplexer is connected to the output voltage detection circuit 5, and the output terminal of the multiplexer outputs the detected voltage V. IMON The output of the multiplexer is connected to a current-sensing resistor R. SENSE The first terminal, current sensing resistor R SENSE The second terminal is grounded.

[0054] Specifically, the multiplexer selects the corresponding output current from the current detection circuit 1 based on the signal from the output voltage detection circuit 5, thereby achieving precise monitoring of different load currents. The current sensing resistor R... SENSE This circuit is used to convert current signals into voltage signals for subsequent processing and analysis. In this way, the circuit can dynamically adjust the output voltage and ensure a stable detection voltage V under various operating conditions. IMON .

[0055] In this embodiment, the current limiting circuit 4 includes a first operational amplifier (OP1) and a second NMOS transistor (NM1). The non-inverting input of the first operational amplifier is connected to the output of the multiplexer, and the inverting input of the first operational amplifier is connected to the reference voltage V.REF The output of the first operational amplifier is connected to the gate of the second NMOS transistor, the drain of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is grounded.

[0056] Specifically, when the current of the first NMOS transistor 3 (NM0) increases, the detection voltage V generated across the current sensing resistor by the detection current increases. IMON Greater than V REF When the output voltage of the first operational amplifier (OP1) increases, it turns on the second NMOS transistor (NM1). NM1 pulls the gate voltage low, increasing the on-resistance of NM0, thereby reducing the current limit flowing through NM0. Due to the negative feedback of the op-amp, this will cause V... IMO The voltage of N and V REF When the currents are essentially equal, the maximum current of the first NMOS transistor 3 will be limited to V. REF / R SENSE *k1 or V REF / R SENSE *k2, thus limiting the current to different maximum currents under different output voltages, protecting the first NMOS transistor 3; when the output current is small, V IMON Less than V REF When the first operational amplifier (OP1) outputs a low level, NM1 is turned off, which has no effect on the operation of GATE.

[0057] The workflow of this invention is as follows:

[0058] The charge pump generates a driving voltage to provide sufficient driving voltage to the gate of the first NMOS transistor 3, ensuring that the device is turned on normally.

[0059] Output voltage detection circuit 5 calculates the input voltage (V) in real time. IN ) and output voltage (V OUT The pressure difference (ΔV=V) IN -V OUT ), and with a preset threshold (V) Delta ) for comparison;

[0060] When ΔV>V Delta When the first NMOS transistor 3 is operating in the saturation region, the first control signal is output, namely the low-level control signal, and the two-to-one data selector 2 selects the sampling current output of the second current detection circuit.

[0061] When ΔV≤V Delta When the first NMOS transistor 3 is operating in the linear region, the second control signal, i.e., the high-level control signal, is output, and the two-to-one data selector 2 switches to the sampling current output of the first current detection circuit.

[0062] The sampling current flows through the current sensing resistor (R) SENSE ) generates detection voltage (V IMON The input is then fed to the non-inverting input of the first operational amplifier (OP1) in the current limiting circuit 4, and the inverting input of the first operational amplifier is connected to the reference voltage (V). REF );

[0063] When the load current increases, the sampling current increases synchronously, and the detection voltage (V) IMON (Then it rises:)

[0064] If V IMON <V REF When the first operational amplifier (OP1) outputs a low level, the second NMOS transistor (NM1) is turned off, which does not affect the gate drive of the first NMOS transistor 3 (NM0), and the device works normally.

[0065] If V IMON ≥V RE F, the output voltage of the first operational amplifier (OP1) increases, the second NMOS transistor (NM1) turns on, pulling down the gate voltage (GATE) of the first NMOS transistor 3 (NM0), increasing the on-resistance of the device, thereby reducing the current flowing through the first NMOS transistor 3;

[0066] The voltage (V) is detected through the negative feedback of the first operational amplifier. IMON It is stabilized at the reference voltage (V) REF The current is limited to the corresponding threshold near the first NMOS transistor 3 (NM0), thus achieving precise current limiting under different operating conditions.

[0067] Secondly, the present invention provides a high-side switching chip that integrates a high-side current limiting protection circuit based on dynamic switching of output voltage difference.

[0068] Thirdly, the present invention provides an electronic system including a power supply, a load, and a power supply path connected between the power supply and the load, wherein a high-side switch chip is provided in the power supply path.

[0069] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A high-side current limiting protection circuit based on dynamic switching of output voltage difference, characterized in that, include: A current detection circuit, wherein the first input terminal of the current detection circuit is connected to the drain of the first NMOS transistor, and the second input terminal of the current detection circuit is connected to the source of the first NMOS transistor, and the current detection circuit is used to detect the load current flowing through the first NMOS transistor and generate a first sampling current and a second sampling current. The drain of the first NMOS transistor is connected to the voltage input terminal V. IN The gate of the first NMOS transistor is connected to a charge pump, and the source of the first NMOS transistor is connected to the voltage output terminal V. OUT ; An output voltage detection circuit is provided, wherein the non-inverting input terminal of the output voltage detection circuit is connected to the source of the first NMOS transistor, and the inverting input terminal of the output voltage detection circuit is connected to the voltage input terminal V. IN The output voltage detection circuit is used to detect the voltage input terminal V. IN With voltage output terminal V OUT The pressure difference ΔV between them is used to determine the control signal output. A data selector, wherein the data input terminal of the data selector is connected to the output terminal of a current detection circuit, the selection input terminal of the data selector is connected to an output voltage detection circuit, and the output terminal of the data selector outputs a detected voltage V. IMON The output of the data selector is connected to a current-sensing resistor R. SENSE The first terminal, the current sensing resistor R SENSE The second terminal is grounded. The data selector receives a control signal and selects either the first sampling current or the second sampling current as the detection current I based on the control signal. SENSE ; A current limiting circuit is provided, wherein the input terminal of the current limiting circuit is connected to the output terminal of the data selector and the gate of the first NMOS transistor, and the output terminal of the current limiting circuit is grounded. The current limiting circuit is used to limit the current flowing through the first NMOS transistor to a current limiting threshold corresponding to the currently selected first sampling current or second sampling current.

2. The high-side current limiting protection circuit based on dynamic switching of output voltage difference according to claim 1, characterized in that, The output voltage detection circuit includes a comparator, the non-inverting input of which is connected to the source of a first NMOS transistor, and the inverting input of which is connected to the voltage input V. IN The output of the comparator is connected to the selection input of the data selector; The comparator outputs a pressure difference ΔV, and the pressure difference ΔV is greater than a preset threshold V. Delta The first control signal is output when the pressure difference ΔV is less than or equal to the preset threshold V. Delta The second control signal is output at the same time, and the first control signal and the second control signal form a control signal.

3. The high-side current limiting protection circuit based on dynamic switching of output voltage difference according to claim 2, characterized in that, The current detection circuit includes a first current detection circuit and a second current detection circuit. The first input terminal of the first current detection circuit is connected to the drain of the first NMOS transistor, and the second input terminal of the first current detection circuit is connected to the source of the first NMOS transistor. The first current detection circuit detects the load current flowing through the first NMOS transistor and generates a first sampling current. The first input terminal of the second current detection circuit is connected to the drain of the first NMOS transistor, and the second input terminal of the second current detection circuit is connected to the source of the first NMOS transistor. The first current detection circuit detects the load current flowing through the first NMOS transistor and generates a second sampling current.

4. The high-side current limiting protection circuit based on dynamic switching of output voltage difference according to claim 3, characterized in that, The data selector is a multiplexer. The data input terminal of the multiplexer is connected to the output terminal of the current detection circuit, and the selection input terminal of the multiplexer is connected to the output voltage detection circuit. The output terminal of the multiplexer outputs the detection voltage V. IMON The output terminal of the multiplexer is connected to a current-sensing resistor R. SENSE The first terminal, the current sensing resistor R SENSE The second end is grounded.

5. The high-side current limiting protection circuit based on dynamic switching of output voltage difference according to claim 4, characterized in that, The current limiting circuit includes a first operational amplifier and a second NMOS transistor. The non-inverting input of the first operational amplifier is connected to the output of the multiplexer, and the inverting input of the first operational amplifier is connected to a reference voltage V. REF The output terminal of the first operational amplifier is connected to the gate of the second NMOS transistor, the drain of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is grounded.

6. The high-side current limiting protection circuit based on dynamic switching of output voltage difference according to claim 5, characterized in that, Both the first and second current detection circuits are SenseFET current detection circuits. Each SenseFET current detection circuit includes a third NMOS transistor and a fourth PMOS transistor. The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, and the drain of the third NMOS transistor is connected to the voltage input terminal V. IN The source of the third NMOS transistor is connected to the inverting input of the second operational amplifier and the source of the fourth PMOS transistor. The non-inverting input of the second operational amplifier is connected to the source of the first NMOS transistor. The output of the second operational amplifier is connected to the gate of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the data input of the multiplexer.

7. The high-side current limiting protection circuit based on dynamic switching of output voltage difference according to claim 6, characterized in that, The ratio of the first sampled current to the load current is a first proportional coefficient K1, and the ratio of the second sampled current to the load current is a second proportional coefficient K2, wherein the second proportional coefficient K2 < the first proportional coefficient K1.

8. The high-side current limiting protection circuit based on dynamic switching of output voltage difference according to claim 7, characterized in that, When the first current detection circuit is activated and generates the first sampling current, the corresponding first current limiting threshold is I. LIMIT1 =V REF / R SENSE ×K1; When the second current detection circuit is activated and generates the second sampling current, the corresponding second current limiting threshold is I. LIMIT2 =V REF / R SENSE ×K2, where I LIMIT2 LIMIT1 .​ 9. A high-side switch chip, characterized in that, It integrates a high-side current limiting protection circuit based on dynamic switching of output voltage difference as described in any one of claims 1 to 8.

10. An electronic system comprising a power source, a load, and a power supply path connected between the power source and the load, characterized in that, The power supply path is provided with a high-side switch chip as described in claim 9.

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