Chip receiver monitoring and diagnosis method and device, and storage medium

Abstract

The invention provides a chip receiver monitoring and diagnosis method and device, and a storage medium. The method comprises the following steps: determining a plurality of target hardware modules from a signal link of a chip receiver; embedding a plurality of monitoring nodes in the signal link for the plurality of target hardware modules; acquiring parameters obtained when each monitoring node monitors the corresponding target hardware module; judging whether the chip receiver is abnormal in a preset dimension or not; and when abnormity occurs, analyzing the parameters through a processor of the chip and outputting an abnormity analysis result. On the basis, the chip receiver can be automatically monitored, diagnosed and analyzed in real time, high-probability fault information can be quickly analyzed and positioned when abnormity is detected, and problem reproduction is not needed.

Description

Technical Field

[0001] This application relates to the field of LTE (Long-Term Evolution) chip testing technology, specifically to a monitoring and diagnostic method and device for a chip receiver, and a storage medium. Background Technology

[0002] During the research and testing phase of LTE chips, receiver performance debugging is one of the key challenges. Engineers often need to resolve receiver link issues such as cell search failures, low downlink throughput, and frequent disconnections in connected mode. These problems may stem from various factors, including misconfiguration of the chip's RF front-end, power or clock integrity issues in the analog baseband, implementation defects in the digital baseband algorithm, or complex external electromagnetic interference. Traditional methods for locating the root cause of these problems heavily rely on engineers' experience and are cumbersome and inefficient.

[0003] Currently, the industry generally adopts a passive response and step-by-step troubleshooting approach. Specifically, when a problem is discovered during testing, engineers first make an initial judgment based on limited basic logs to identify suspicious modules, such as front-end modules, automatic gain control loops, and RX PLL modules. Then, they further investigate through the following steps: Step 1: Instrument-assisted measurement, using external testing equipment such as oscilloscopes and spectrum analyzers to probe analog signals at key peripheral nodes of the chip; Step 2: Software log analysis, modifying the chip firmware or driver code to add detailed debug print information before and after the suspicious functional modules, then recompiling, flashing, and reproducing the problem; Step 3: Data capture and post-processing, capturing downlink baseband IQ samples or internal intermediate data, exporting them, and then using professional tools such as MATLAB on a PC for offline, non-real-time in-depth analysis. However, this method has several drawbacks. For example, it is time-consuming: the localization process involves multiple iterations of "initial guess, adding logs, reproducing the problem, analyzing, and guessing again," resulting in a lengthy process. It is also difficult to reproduce the problem: for probabilistic faults related to specific wireless environments and terminal states (such as battery level and temperature), the triggering conditions are stringent, making stable reproduction difficult and leading to a stalemate in debugging. Furthermore, it has poor real-time performance: relying on external instruments and offline analysis, it cannot capture instantaneous or cross-module related faults, making it difficult to diagnose complex problems caused by the interaction between subsystems. Summary of the Invention

[0004] In view of this, this application provides a method and device for monitoring and diagnosing a chip receiver, as well as a storage medium, which can at least improve the problems of long cycle, difficulty in reproducing problems and poor real-time performance in monitoring and diagnosing chip receivers.

[0005] This application provides a monitoring and diagnostic method for a chip receiver, including: Several target hardware modules are identified from the signal link of the chip receiver; For the aforementioned target hardware modules, multiple monitoring nodes are embedded in the signal link; Obtain the parameters obtained by each monitoring node when monitoring the corresponding target hardware module; Determine whether the chip receiver exhibits any abnormality in a preset dimension; When an anomaly occurs, the chip's processor analyzes the parameters and outputs the anomaly analysis results.

[0006] Optionally, the plurality of target hardware modules include at least one of the following: radio frequency front-end module, radio frequency analog module, analog-to-digital converter, radio frequency digital module, baseband digital module, clock system, temperature sensor, and power monitoring module.

[0007] Optionally, for the aforementioned target hardware modules, multiple monitoring nodes may be embedded in the signal link, including at least one of the following: A first monitoring node is embedded in the signal link to monitor the parameters of each target hardware module when the chip receiver executes the control signaling path; A second monitoring node is embedded in the signal link to monitor the parameters of each target hardware module when the chip receiver executes the data transmission and reception path; A third monitoring node is embedded in the signal link to monitor the external environment and basic condition parameters of each target hardware module when the chip receiver keeps the system working normally.

[0008] Optionally, the first monitoring node includes: A front-end register readback unit is used to monitor the radio frequency front-end module; An analog register readback unit is used to monitor the radio frequency analog module; A bus monitoring unit is used to monitor the MIPI bus connecting the RF analog module and the processor, as well as the SPI bus connecting the RF analog module and the processor. The PLL status monitoring unit is used to read the parameters of the phase-locked loop in the clock system; In addition, a digital register readback unit is provided for monitoring the radio frequency digital module and the baseband digital module.

[0009] Optionally, the second monitoring node includes: An analog IQ level monitoring unit is used to monitor the radio frequency analog module; A simulated DC offset monitoring unit is used to monitor the radio frequency simulation module; An ADC saturation counting unit is used to monitor the analog-to-digital converter; A digital RSSI monitoring unit is used to monitor the radio frequency digital module; A digital DC monitoring unit is used to monitor the radio frequency digital module; In addition, a real-time signal quality monitoring unit is provided for monitoring the baseband digital module.

[0010] Optionally, the third monitoring node includes: A reference clock monitoring unit is used to monitor the phase-locked loop of the clock system; VCO voltage monitoring unit, used to monitor the phase-locked loop of the clock system; A temperature monitoring unit is used to monitor the temperature sensor; And a power monitoring unit for monitoring the power monitoring module.

[0011] Optionally, the preset dimension includes RSSI. If the chip receiver is abnormal in the preset dimension, it includes at least one of the following: the RSSI is greater than a first threshold, the RSSI is less than a second threshold, or the change value of the RSSI is greater than a third threshold, wherein the second threshold is less than the first threshold.

[0012] Optionally, the preset dimension includes signal quality. If the chip receiver malfunctions in the preset dimension, it includes at least one of the following: RSRQ exceeds the corresponding threshold, EVM exceeds the corresponding threshold, DC component is abnormal, IQ is unbalanced, phase noise is abnormal, frequency offset is abnormal, or inter-symbol interference is abnormal.

[0013] Optionally, the preset dimensions include frequency and time synchronization. If the chip receiver malfunctions in the preset dimensions, it may be due to: frequency synchronization error or time synchronization error exceeding the corresponding threshold.

[0014] Optionally, the preset dimension includes the CRC check result, and the chip receiver may experience an anomaly in the preset dimension, including: the CRC check result is a CRC check failure.

[0015] Optionally, the preset dimension includes downlink throughput. An anomaly in the chip receiver in the preset dimension includes: the downlink throughput being lower than the corresponding threshold for a preset duration.

[0016] Optionally, when an anomaly occurs in a preset dimension, including when the RSSI is greater than a first threshold, the step of analyzing the parameters and outputting the anomaly analysis result through the chip's processor includes: Analyze the parameters of the analog IQ level monitoring unit. If the analog IQ level is found to be abnormal, analyze the parameters of the analog register readback unit. If the parameters are found to be inconsistent with the corresponding configuration parameters, the analog configuration error is diagnosed. If the parameters are found to be consistent with the corresponding configuration parameters, the external strong signal interference is diagnosed. If the simulated IQ level is determined to be normal, the parameters of the simulated DC offset monitoring unit are analyzed. If the DC component is determined to be abnormal, the simulated DC offset calibration error is diagnosed. If the DC component is determined to be normal, the parameters of the ADC saturation counting unit are analyzed. If the ADC is determined to be saturated, it is diagnosed that the analog gain setting is greater than the corresponding threshold, resulting in signal clipping distortion. If the ADC is determined to be unsaturated, the parameters of the digital register readback unit are analyzed. If the digital gain is determined to be abnormal, the digital gain configuration is diagnosed as incorrect. Furthermore, if the digital gain is determined to be normal, the parameters of the digital DC monitoring unit are analyzed. If the residual DC is determined to be greater than the corresponding threshold, the digital domain DC compensation algorithm is diagnosed as malfunctioning or improperly calibrated.

[0017] Optionally, when an anomaly occurs in a preset dimension, including when the RSSI is less than a second threshold, the step of analyzing the parameters and outputting the anomaly analysis result through the chip's processor includes: Analyzing the parameters of the PLL status monitoring unit, if it is determined that the phase-locked loop (PLL) has lost lock, then the downconversion failure is diagnosed as a result of the PLL losing lock. If the phase-locked loop is determined to be locked, the parameters of the front-end register readback unit and the analog register readback unit are analyzed. If the radio frequency configuration is determined to be incorrect, the receiving path is diagnosed as not being fully established. If the RF configuration is determined to be correct, the parameters of the analog IQ level monitoring unit are analyzed. If the analog IQ level is determined to be less than the corresponding threshold, the input signal is diagnosed as weak. Furthermore, if the analog IQ level is determined to reach the corresponding threshold, the parameters of the digital RSSI monitoring unit are analyzed. If the digital RSSI is determined to be less than the corresponding threshold, a digital register configuration error is diagnosed.

[0018] Optionally, when an anomaly occurs in a preset dimension, including a change in RSSI value exceeding a third threshold, the step of analyzing the parameters and outputting anomaly analysis results through the chip's processor includes: If the parameters of the power monitoring unit are analyzed and fluctuations in the power supply voltage are detected, then the problem is diagnosed as power supply noise interference. If it is determined that there is no fluctuation in the power supply voltage, then analyze whether there is periodic fluctuation in RSSI. If it is determined that there is periodic fluctuation, then it is diagnosed as the presence of switching noise interference. If it is determined that there is no periodic fluctuation, then analyze whether there is pulse fluctuation in RSSI. If pulse fluctuation is determined to exist, then it is diagnosed as clock harmonic interference. Furthermore, if it is determined that there is no pulse fluctuation, the parameters of the temperature monitoring unit are analyzed. If it is determined that the RSSI fluctuates abnormally in sync with the temperature, it is diagnosed as temperature change causing gain drift of the analog device. If it is determined that the RSSI fluctuates normally in sync with the temperature, it is diagnosed as input signal fluctuation.

[0019] Optionally, when an anomaly occurs in a preset dimension, including when the RSRQ exceeds the corresponding threshold, the step of analyzing the parameters and outputting the anomaly analysis result through the chip's processor includes: Analyze the parameters of the real-time signal quality monitoring unit. If it is determined that the change in RSRQ does not match the configuration change of the signal bandwidth, then based on RSSI as a preset dimension, determine whether there is an anomaly in the preset dimension. If an anomaly occurs, execute the aforementioned corresponding steps. If no anomaly occurs, analyze whether RSRP is abnormal. If the RSRP is determined to be abnormal, diagnose it as an input signal anomaly.

[0020] Optionally, when an anomaly occurs in a preset dimension, including when the EVM exceeds a corresponding threshold, the step of analyzing the parameters and outputting the anomaly analysis result through the chip's processor includes: The diagnosis was abnormal EVM indicators.

[0021] Optionally, when an anomaly occurs in a preset dimension, including an anomaly in the DC component, the step of analyzing the parameters and outputting the anomaly analysis results through the chip's processor includes: If the parameters of the simulated register readback unit are analyzed and determined to be inconsistent with the corresponding configuration parameters, then a simulated configuration error is diagnosed. If it is determined that it matches the corresponding configuration parameters, the parameters of the simulated DC offset monitoring unit are analyzed. If it is determined that the DC offset compensation is incorrect, it is diagnosed as a DC calibration error. If the DC offset compensation is determined to be correct, the parameters of the ADC saturation counting unit are analyzed. If the ADC is determined to be saturated, the analog gain setting is diagnosed as being greater than the corresponding threshold. If the ADC is determined not to be saturated, the input signal is diagnosed as abnormal.

[0022] Optionally, when an anomaly occurs in a preset dimension, including IQ imbalance, the step of analyzing the parameters and outputting the anomaly analysis results through the chip's processor includes: Analyze the parameters of the analog register readback unit and the digital register readback unit. If they are found to be inconsistent with the corresponding configuration parameters, then the problem is diagnosed as an analog configuration error or a digital configuration error. If the parameters are found to match the corresponding configuration parameters, the parameters of the analog IQ level monitoring unit are analyzed. If the amplitude and phase of the IQ channel are not corrected, the IQ imbalance compensation is diagnosed as a failure. If the amplitude and phase of the IQ channel are successfully corrected, the input signal is diagnosed as abnormal.

[0023] Optionally, when an anomaly, including a phase noise anomaly, occurs in a preset dimension, the step of analyzing the parameters and outputting the anomaly analysis result through the chip's processor includes: If the parameters of the PLL status monitoring unit are analyzed, and it is determined that the phase-locked loop is out of lock, then the diagnosis is a hardware configuration error or stability failure of the phase-locked loop; if it is determined that the phase-locked loop is locked, then the parameters of the reference clock monitoring unit are analyzed, and if it is determined that the reference clock is unstable, then the diagnosis is an abnormal reference clock. If the reference clock is determined to be stable, the parameters of the power monitoring unit are analyzed. If the power supply voltage is found to be fluctuating, it is diagnosed as power supply noise interference; if the power supply voltage is not found to be fluctuating, it is diagnosed as an abnormal input signal.

[0024] Optionally, when an anomaly, including a frequency offset anomaly, occurs in a preset dimension, the step of analyzing the parameters and outputting the anomaly analysis results through the chip's processor includes: If the parameters of the PLL status monitoring unit are analyzed, and it is determined that the phase-locked loop is out of lock, then the diagnosis is a hardware configuration error or stability failure of the phase-locked loop; if it is determined that the phase-locked loop is locked, then the parameters of the VCO voltage monitoring unit are analyzed, and if it is determined that the tuning voltage is unstable, then the diagnosis is a VCO configuration error. If the tuning voltage is determined to be stable, the parameters of the reference clock monitoring unit are analyzed. If the reference clock is determined to be unstable, it is diagnosed as a reference clock abnormality; if the reference clock is determined to be stable, it is diagnosed as an input signal abnormality.

[0025] Optionally, when an anomaly, including inter-symbol interference (ISI) anomaly, occurs in a preset dimension, the step of analyzing the parameters and outputting the anomaly analysis result through the chip's processor includes: Analyze the parameters of the analog register readback unit and the digital register readback unit. If they are found to be inconsistent with the corresponding configuration parameters, then the problem is diagnosed as an analog configuration error or a digital configuration error. If the parameters are found to match the corresponding configuration parameters, the parameters of the reference clock monitoring unit are analyzed. If the time synchronization error is found to be greater than the corresponding threshold, a preset operation is performed. If the time synchronization error is found to be less than the corresponding threshold, the problem is diagnosed as a wireless channel issue causing distortion of the input signal waveform.

[0026] Optionally, the following conditions are determined in sequence: RSRQ exceeds the corresponding threshold, EVM exceeds the corresponding threshold, DC component is abnormal, IQ is unbalanced, phase noise is abnormal, frequency offset is abnormal, and inter-symbol interference is abnormal. Only when an abnormality occurs in the previous preset dimension is the next preset dimension determined. If the EVM does not exceed the corresponding threshold, the determination of whether there is DC component abnormality, IQ imbalance, phase noise abnormality, frequency offset abnormality, or inter-symbol interference abnormality will not be performed. If the change in RSRQ is determined to match the change in signal bandwidth configuration, then stop analyzing whether RSSI and RSRP are abnormal, and directly determine whether EVM exceeds the corresponding threshold.

[0027] Optionally, the preset operation, or when an anomaly occurs in a preset dimension, including a frequency synchronization error or a time synchronization error exceeding a corresponding threshold, the step of analyzing the parameters and outputting the anomaly analysis result through the chip's processor includes: If the parameters of the PLL status monitoring unit are analyzed, and it is determined that the phase-locked loop is out of lock, then the diagnosis is a hardware configuration error or stability failure of the phase-locked loop; if it is determined that the phase-locked loop is locked, then the parameters of the reference clock monitoring unit are analyzed, and if it is determined that the reference clock is unstable, then the diagnosis is an abnormal reference clock. If the reference clock is determined to be stable, then analyze whether the signal quality is normal; If the signal quality is determined to be abnormal, then the aforementioned corresponding steps shall be performed; If the signal quality is determined to be normal, the diagnosis is a baseband algorithm configuration defect.

[0028] Optionally, when an anomaly occurs in a preset dimension, including a CRC check failure, the chip's processor analyzes the parameters and outputs an anomaly analysis result, including: Analyze the parameters of the real-time signal quality monitoring unit. If the SNR is determined to be less than the corresponding threshold, then execute the aforementioned corresponding steps. If the SNR is determined to have reached the corresponding threshold, then analyze whether the EVA has reached the corresponding threshold; if the EVA is determined to have reached the corresponding threshold, then perform the aforementioned corresponding steps. If the EVA is determined to be less than the corresponding threshold, it is diagnosed as a baseband algorithm configuration defect.

[0029] Optionally, when an anomaly occurs in a preset dimension, including when the downlink throughput is lower than the corresponding threshold and persists for a preset duration, the chip's processor analyzes the parameters and outputs the anomaly analysis results, including: Analyze the parameters of the real-time signal quality monitoring unit. If the proportion of CRC check failures is determined to have reached the corresponding threshold, then execute the aforementioned corresponding steps. If the proportion of CRC check failures is determined to be below the corresponding threshold, then the MCS level is analyzed; if the MCS level is below the corresponding threshold, then the corresponding steps described above are performed. If the MCS level reaches the corresponding threshold, analyze whether the number of resource blocks allocated for downlink resources is lower than the corresponding threshold; if so, diagnose it as a network scheduling problem. If not, analyze whether there is a scheduling delay; if so, diagnose it as low protocol stack efficiency.

[0030] This application provides a monitoring and diagnostic device for a chip receiver. The signal link of the chip receiver is provided with several target hardware modules. The device includes multiple monitoring nodes, each of which is embedded in the signal link. These monitoring nodes are used to monitor the corresponding target hardware modules to obtain corresponding parameters and to perform the steps of any of the above-mentioned monitoring and diagnostic methods for chip receivers.

[0031] Another monitoring and diagnostic device for a chip receiver provided in this application includes a processor and a memory. The memory stores a monitoring and diagnostic program. When the monitoring and diagnostic program is executed by the processor, it implements the steps of any of the above-described monitoring and diagnostic methods for a chip receiver.

[0032] This application provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above-described chip receiver monitoring and diagnostic methods.

[0033] As described above, this application embeds multiple monitoring nodes in the signal link of the chip receiver. Each monitoring node is specifically designed for multiple target hardware modules, acquiring parameters obtained by each monitoring node when monitoring its corresponding target hardware module. When an anomaly occurs in the chip receiver, the chip's processor analyzes the relevant parameters and outputs anomaly analysis results. Therefore, this application can determine in real time whether the receiver's reception is abnormal, and output anomaly analysis results upon detection, thereby locating fault information with a high probability. This transforms the traditional step-by-step, iterative diagnostic process into real-time automated fault diagnosis, significantly shortening the entire chip receiver debugging cycle and improving development and testing efficiency. Attached Figure Description

[0034] Figure 1 This is a schematic flowchart of a monitoring and diagnostic method for a chip receiver according to an embodiment of this application; Figure 2 This is a schematic diagram of the monitoring node embedded in the signal link of the chip receiver in this application; Figure 3 This is a flowchart illustrating the problem analysis of the chip receiver from multiple dimensions in this application; Figure 4 This is a flowchart illustrating the RSSI anomaly analysis process in this application; Figure 5 This is a flowchart illustrating the signal quality anomaly analysis process of this application; Figure 6 This is a flowchart illustrating the frequency and time synchronization anomaly analysis performed in this application. Figure 7 This is a flowchart illustrating the CRC check failure analysis process in this application; Figure 8This is a flowchart illustrating the downlink throughput anomaly analysis process in this application; Figure 9 This is a schematic diagram of the structure of a monitoring and diagnostic device provided in an embodiment of this application. Detailed Implementation

[0035] To address the aforementioned problems in the prior art, this application provides a monitoring and diagnostic method and device for a chip receiver, as well as a storage medium. These protection subjects are based on the same concept, and the principles for solving the problems are basically the same or similar. The implementation methods of each protection subject can be referred to mutually, and repeated details will not be elaborated.

[0036] In this application, multiple monitoring nodes are embedded in the signal link of the chip receiver. Each monitoring node is specifically designed for multiple target hardware modules, acquiring parameters obtained by each node when monitoring its corresponding target hardware module. When an anomaly occurs in the chip receiver, the chip's processor analyzes the relevant parameters and outputs anomaly analysis results. Thus, the receiver's reception is judged in real time for anomalies, and anomaly analysis results are output when an anomaly is detected, enabling high-probability fault location.

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only a part of the embodiments of this application, and not all of them. Unless otherwise specified, the following embodiments and their technical features can be combined with each other, and also belong to the technical solutions of this application.

[0038] Figure 1 This is a schematic flowchart of a chip receiver monitoring and diagnostic method according to an embodiment of this application. The chip receiver monitoring and diagnostic method may also be referred to as a "method" or "monitoring and diagnostic method". The applicable chip may include, but is not limited to, LTE UE (User Equipment) chips. The execution subject of each step in the method may be a suitable monitoring and diagnostic device, or a storage medium, processor, controller, etc. with chip receiver monitoring and diagnostic functions.

[0039] See Figure 1 As shown, the method includes at least the following steps S1 to S7.

[0040] S1. Identify several target hardware modules from the signal link of the chip receiver.

[0041] Figure 2 The hardware architecture of the basic signal link of the chip receiver is shown, combined with Figure 2As shown, the signal link includes, in sequence: receiving antenna, radio frequency front-end module, radio frequency analog module, analog-to-digital converter, radio frequency digital module, baseband digital module, and clock system.

[0042] The receiving antenna is used to receive wireless radio frequency signals in space. The RF front-end module is used to transmit the received wireless signals to the chip, including but not limited to filtering and switching functions. Its operating status, such as the receiving frequency band, needs to be configured via the MIPI bus. The RF analog module, as a circuit within the chip receiver (also known as the RF chip), is used to filter, amplify, and down-convert the RF signal to a baseband signal. This RF analog module has sub-modules such as gain amplifiers and mixers, and its operating status, such as the receiving frequency band, needs to be configured via the SPI bus. The analog-to-digital converter (ADC) is used to sample the analog signal from the RF analog module into a digital signal. The ADC configuration needs to ensure that the input signal is within its dynamic range to avoid saturation distortion due to signal overload. The RF digital module is used to further process the received digital signal, such as downsampling, filtering, DC (Direct Current) compensation, and IQ (Quiescent Current) compensation. The baseband digital module is used to demodulate, channel compensate, decode, and perform CRC (Cyclic Redundancy Check) verification on the digital signals processed by the RF digital module. Data that passes the CRC check is the final received user data. The clock system mainly includes a PLL (Phase-Locked Loop) module and a reference clock. The PLL module contains an RX PLL (i.e., a receive PLL) and a baseband PLL. The RX PLL is used to generate the high-frequency local oscillation signal required for down-conversion, and the baseband PLL is used to provide the clock required for baseband digital signal processing. The reference clock is provided by an external crystal oscillator and is used to provide a reference source for the high-frequency clock generated by the PLL.

[0043] In practical scenarios, the signal link also includes a temperature sensor and a power monitoring module. The temperature sensor is used to monitor the relevant temperature of the chip receiver, and the power monitoring module is used to monitor the relevant voltage of the chip receiver. The functions of the aforementioned hardware modules can be found in existing technologies.

[0044] For Figure 2 As shown in the signal link, this application can determine that the target hardware modules to be monitored include at least one of the following: RF front-end module, RF analog module, analog-to-digital converter, RF digital module, baseband digital module, clock system, temperature sensor, and power monitoring module.

[0045] S2. Multiple monitoring nodes are embedded in the signal link for several target hardware modules.

[0046] In scenarios where the chip receiver performs reception, the basic signal link mainly performs control signaling transmission and data transmission and reception. Of course, to ensure its normal reception function, it is also necessary to ensure the necessary external environment and basic conditions. Based on this, this application can embed monitoring nodes separately.

[0047] Continue reading Figure 2 As shown, the multiple monitoring nodes embedded in the signal link include at least one of a first monitoring node, a second monitoring node, and a third monitoring node. The first monitoring node is used to monitor the parameters of the relevant target hardware module when the chip receiver executes the control signaling path, and therefore can also be called a "control path monitoring node." The second monitoring node is used to monitor the parameters of the relevant target hardware module when the chip receiver executes the data transmission and reception path, and therefore can also be called a "data path monitoring node." The third monitoring node is used to monitor the external environment and basic condition parameters of the relevant target hardware module (e.g., a temperature sensor and a power monitoring module) when the chip receiver maintains normal system operation, and therefore can also be called a "system status monitoring node."

[0048] In one example, see [link / reference] Figure 2 As shown, the first monitoring node includes, but is not limited to, at least one of the following: front-end register readback unit, analog register readback unit, bus monitoring unit, PLL status monitoring unit, and digital register readback unit.

[0049] The front-end register readback unit is used to monitor the RF front-end module to obtain relevant parameters of the RF front-end module. For example, it reads back the configuration register of the RF front-end module through the RFFE bus so that its actual value can be compared with the expected configuration value to diagnose whether the configuration command was successfully executed.

[0050] The analog register readback unit is used to monitor the RF simulation module to obtain relevant parameters of the RF simulation module, such as reading back the internal configuration register of the RF simulation module so as to verify whether its working status (such as gain setting, filter bandwidth) meets expectations.

[0051] The bus monitoring unit is used to monitor the MIPI bus connecting the RF analog module and the processor, as well as the SPI bus connecting the RF analog module and the processor. For example, it monitors the communication protocols and data integrity on the MIPI bus and the SPI bus so that the configuration failure caused by the transmission error of the MIPI bus or the SPI bus can be determined in the subsequent step S4.

[0052] The PLL status monitoring unit is used to read the parameters of the phase-locked loop in the clock system. For example, it monitors the locking status of the RXPLL and the baseband PLL in real time. In the subsequent step S4, once the PLL is detected to be out of lock, it can be immediately associated with the resulting reception synchronization failure or signal quality degradation problem.

[0053] The digital register readback unit is used to monitor the radio frequency digital module and the baseband digital module to obtain their relevant parameters. For example, it reads back the configuration registers of the radio frequency digital module and the baseband digital module to ensure that the relevant digital signal processing algorithm parameters are set correctly.

[0054] In one example, see [link / reference] Figure 2 As shown, the second monitoring node includes at least one of an analog IQ level monitoring unit, an analog DC offset monitoring unit, an ADC saturation counting unit, a digital RSSI monitoring unit, a digital DC monitoring unit, and a real-time signal quality monitoring unit.

[0055] The analog IQ level monitoring unit is used to monitor the RF analog module to obtain relevant parameters. For example, before analog-to-digital conversion, it monitors the amplitude of the analog baseband signal so that it can be used to assist in the performance analysis of the automatic gain control loop and the detection of external strong interference.

[0056] The analog DC offset monitoring unit is used to monitor the radio frequency analog module to obtain relevant parameters. For example, it measures and monitors the DC offset introduced by the radio frequency analog module. Since an excessive DC offset will encroach on the dynamic range of the analog-to-digital conversion and degrade the signal quality, it is convenient for subsequent analysis of signal quality issues.

[0057] The ADC saturation counting unit is used to monitor the analog-to-digital converter to obtain relevant parameters. For example, by monitoring the obtained parameters, the number of output samples of the analog-to-digital converter that are in or close to the saturation range can be counted, so as to be used for subsequent quantitative evaluation of nonlinear distortion caused by signal overload.

[0058] The digital RSSI monitoring unit is used to monitor the radio frequency digital module to obtain relevant parameters, such as monitoring the strength indication of the received signal calculated in the digital domain, so that the total power including useful signals, noise and interference signals within the receiving bandwidth can be reflected by the value.

[0059] The digital DC monitoring unit is used to monitor the radio frequency digital module to obtain relevant parameters, such as monitoring the DC component remaining after digital domain compensation, so as to facilitate subsequent evaluation of the effectiveness of the compensation algorithm and its potential impact on signal quality.

[0060] The real-time signal quality monitoring unit is used to monitor the baseband digital module to obtain relevant parameters. For example, for the baseband digital module, a set of signal quality indicators are calculated in parallel through monitoring, including but not limited to signal-to-noise ratio, error vector amplitude, carrier frequency offset, sampling timing deviation, IQ imbalance and DC power, so as to provide core data basis for subsequent comprehensive diagnosis.

[0061] In one example, see [link / reference] Figure 2 As shown, the third monitoring node includes at least one of a reference clock monitoring unit, a VCO (Voltage-Controlled Oscillator) voltage monitoring unit, a temperature monitoring unit, and a power supply monitoring unit.

[0062] The reference clock monitoring unit is used to monitor the phase-locked loop of the clock system to obtain relevant parameters, such as monitoring the frequency accuracy and stability of the reference clock input to the PLL, so as to subsequently eliminate systemic faults caused by clock source abnormalities.

[0063] The VCO voltage monitoring unit is used to monitor the phase-locked loop of the clock system to obtain relevant parameters. For example, it monitors the tuning control voltage of the voltage-controlled oscillator inside the PLL. Abnormal fluctuations in the tuning control voltage can directly reflect the stability of the PLL and are related to the phase noise performance.

[0064] The temperature monitoring unit is used to monitor the temperature sensor to obtain relevant parameters, such as the temperature of the receiver chip or its critical areas. Temperature changes affect the bias point and gain of analog devices and are an important factor leading to performance drift.

[0065] The power monitoring unit is used to monitor the power monitoring module to obtain relevant parameters, such as monitoring the operating voltage supplied to each target hardware module of the receiver. Power supply ripple, voltage drops, or noise can be modulated into the received signal, directly affecting the receiving sensitivity and signal quality.

[0066] Through the first to third monitoring nodes mentioned above, this application can monitor the main hardware modules in the signal link of the receiver. The monitoring range is relatively comprehensive, which is conducive to the comprehensive diagnosis and analysis of the problem.

[0067] S3. Obtain the parameters obtained by each monitoring node when monitoring the corresponding target hardware module.

[0068] S4. Determine if the chip receiver is abnormal in the preset dimension.

[0069] In each subframe during receiver operation, the aforementioned monitoring nodes run automatically, reading key indicators from each hardware module. Each key indicator represents a dimension, and the preset dimensions in this application include, but are not limited to, RSSI, signal quality, frequency and time synchronization, CRC check results, and downlink throughput. Then, for each dimension, the corresponding indicator analysis process is initiated, and by comparing it with predetermined indicators, historical indicators, or ideal indicators, it is determined whether a particular indicator is abnormal.

[0070] If an anomaly occurs, proceed to step S5, whereby the chip's processor analyzes the parameters and outputs the anomaly analysis result; if no anomaly occurs, proceed to steps S3 to S4, which means continuing to monitor whether the chip receiver is transmitting and receiving normally.

[0071] In one example, combining Figure 3 As shown, this application can perform diagnostics and anomaly analysis on five dimensions in sequence: RSSI, signal quality, synchronization (i.e., frequency and time synchronization), CRC check result, and downlink throughput, i.e., analyze reception problems (RX problems). This analysis method essentially prioritizes investigating internal receiver faults related to these five dimensions before considering external signal issues. Signal quality analysis can be performed by checking for anomalies in the EVM (Error Vector Magnitude).

[0072] For the RSSI dimension, an abnormal situation includes at least one of the following: the RSSI is greater than a first threshold (i.e., the current RSSI is too high), the RSSI is less than a second threshold (i.e., the current RSSI is too low), or the change in RSSI is greater than a third threshold (i.e., the current RSSI has a significant change relative to the historical average), wherein the second threshold is less than the first threshold.

[0073] Regarding the signal quality dimension, an abnormal situation includes at least one of the following: RSRQ (Reference Signal Received Quality) exceeding the corresponding threshold, EVM exceeding the corresponding threshold, abnormal DC component, IQ imbalance, abnormal phase noise, abnormal frequency offset, and abnormal inter-symbol interference.

[0074] Regarding the dimension of frequency and time synchronization, the so-called abnormal situation includes: frequency synchronization error or time synchronization error exceeding the corresponding threshold.

[0075] Regarding the CRC check result, the so-called abnormal situation includes: the CRC check result is a CRC check failure.

[0076] Regarding the downlink throughput dimension, the so-called abnormal situation includes: the downlink throughput being lower than the corresponding threshold and lasting for a preset duration.

[0077] Based on the aforementioned dimensions, and when anomalies occur in each dimension, the principle and detailed process of analyzing and outputting anomaly analysis results in step S5 of this application are described below.

[0078] Figure 4 A schematic diagram of the RSSI analysis process of this application is shown.

[0079] When an anomaly occurs in a preset dimension, including when the RSSI is greater than the first threshold (i.e., the RSSI is too high), combined with... Figure 4 As shown, step S5 can be implemented as follows: First, perform an analog path check: analyze the parameters of the analog IQ level monitoring unit to determine whether the analog IQ level is abnormal. If the analog IQ level is found to be abnormal, analyze the parameters of the analog register readback unit to determine whether the analog register is abnormal. If it is found to be inconsistent with the corresponding configuration parameters, it is diagnosed as an analog register abnormality, i.e., an analog configuration error. If it is found to be consistent with the corresponding configuration parameters, the analog register is normal, and it is diagnosed as external strong signal interference. If the analog IQ level is found to be normal, then perform a DC offset influence check: analyze the parameters of the analog DC offset monitoring unit to determine whether the analog DC is too large. If the analog DC is too large, it is determined that the DC component is abnormal, and it is diagnosed as an analog DC offset calibration error. If the analog DC is not too large, it is determined that the DC component is abnormal. If the current component is normal, the next step is to perform an ADC saturation check to determine if the ADC is saturated: Analyze the parameters of the ADC saturation counting unit. If the ADC is determined to be saturated, it is diagnosed that the analog gain setting is greater than the corresponding threshold, i.e., the analog gain is too large, causing signal clipping distortion. If the ADC is determined not to be saturated, the next step is to perform a digital gain check: Analyze the parameters of the digital register readback unit to determine if the digital gain is abnormal. If the digital gain is determined to be abnormal, it is diagnosed as a digital gain configuration error. And, if the digital gain is determined to be normal, the next step is to perform a digital domain DC check: Analyze the parameters of the digital DC monitoring unit to determine if the digital DC is too large. If the residual DC is determined to be greater than the corresponding threshold, i.e., the digital DC is too large, it is diagnosed as a DC calibration problem, such as a failure of the digital domain DC compensation algorithm or improper calibration.

[0080] Based on the combined results of all the above checks, a final analysis report on the excessively high RSSI is generated.

[0081] When an anomaly occurs in the preset dimension, including when the RSSI is less than the second threshold (i.e., the RSSI is too low), the process continues to be combined. Figure 4As shown, step S5 can be implemented as follows: First, perform a clock system check: analyze the parameters of the PLL status monitoring unit to determine whether the PLL status is abnormal. If it is determined that the phase-locked loop is out of lock, i.e., the PLL status is abnormal, then a phase-locked loop fault is diagnosed, such as the phase-locked loop being out of lock causing down-conversion failure, and the PLL register configuration and reference clock frequency are checked in conjunction. If it is determined that the phase-locked loop is locked, i.e., the PLL status is normal, then a front-end configuration check is performed: analyze the parameters of the front-end register readback unit and the analog register readback unit to determine whether the RF configuration is abnormal. If it is determined that the RF configuration is incorrect, then the receiving path is diagnosed as not being fully established, such as the receiving path switch not being turned on. If it is determined that the RF configuration is correct, then proceed to... Analog input signal check: Analyze the parameters of the analog IQ level monitoring unit to determine if the analog IQ level is too low. If the analog IQ level is found to be less than the corresponding threshold, it is determined that the analog IQ level is too low, and the input signal is diagnosed as weak, for example, inferred to be a weak external input signal or an antenna connection problem. If the analog IQ level is found to reach the corresponding threshold, it is determined that the analog IQ level is normal, and then the digital path check is performed: Analyze the parameters of the digital RSSI monitoring unit to determine if the digital RSSI is too low. If the digital RSSI is found to be less than the corresponding threshold, it is determined that the digital register configuration is incorrect, for example, incorrect downsampling or filtering settings causing the signal power to be underestimated.

[0082] Based on the combined results of all the above checks, a final analysis report on the low RSSI is generated.

[0083] When an anomaly occurs in the preset dimension, including when the change in RSSI value exceeds the third threshold (i.e., when RSSI fluctuation is abnormal), the following steps are taken: Figure 4As shown, step S5 can be implemented as follows: First, perform a power stability check: analyze the parameters of the power monitoring unit to determine whether the power supply voltage is abnormal. If the power supply voltage is found to fluctuate, i.e., the power supply voltage is abnormal, it is diagnosed as power supply noise interference. For example, it is directly inferred that power supply ripple or drops cause RSSI fluctuations through analog circuit modulation. If the power supply voltage is found not to fluctuate, i.e., the power supply voltage is normal, then perform a periodic analysis: analyze whether there are periodic fluctuations in RSSI. If there are periodic fluctuations, it is diagnosed as switching noise interference. For example, combine historical RSSI data to analyze whether the fluctuations are periodic. If there is a fixed period, it is inferred that it is related to periodic switching actions in the system (such as CPU power consumption cycle). If there are no periodic fluctuations, then perform pulse interference analysis. The RSSI is analyzed to determine if pulse fluctuations exist. If pulse fluctuations are found, it is diagnosed as clock harmonic interference, for example, inferred to be harmonic interference from other clock domains coupled to the receiving link. If no pulse fluctuations are found, random fluctuations are then correlated with temperature: the fluctuation characteristics of the received signal are used to determine if it is random fluctuation. If it is, it is diagnosed as RSSI fluctuation abnormality caused by random fluctuation. If not, the parameters of the temperature monitoring unit are analyzed to determine if RSSI and temperature fluctuate abnormally synchronously. If RSSI and temperature fluctuate abnormally synchronously, it is diagnosed as a temperature abnormality problem, for example, temperature changes causing gain drift of analog devices. If RSSI and temperature fluctuate normally synchronously, it is diagnosed as input signal fluctuation, for example, it is ultimately inferred that the input signal itself fluctuates because there is a time-varying interference signal in the same frequency band.

[0084] Based on the combined results of all the above examinations, a final analysis report on the abnormal fluctuations in RSSI is generated.

[0085] It should be noted that, in Figure 4 In the analysis process shown, if it is determined that the RSSI is not too large, or that the RSSI is not too small, or that the RSSI does not fluctuate abnormally, this application can continue to perform RSSI analysis to monitor whether the RSSI of the next subframe is abnormal. Alternatively, if it is determined that one of the items is not abnormal, it can monitor whether the remaining two items are abnormal. For example, if it is determined that the RSSI is not too large, it can monitor whether the RSSI is too small and whether the RSSI fluctuates abnormally.

[0086] Figure 5 A schematic diagram of the signal quality anomaly analysis process of this application is shown.

[0087] When an anomaly occurs in a preset dimension, including when the RSRQ exceeds the corresponding threshold (i.e., when the RSRQ is abnormal), combined with... Figure 5As shown, step S5 can be implemented as follows: First, perform a system bandwidth check: analyze the parameters of the real-time signal quality monitoring unit to determine whether the signal bandwidth has changed, thereby determining whether the change in RSRQ matches the change in signal bandwidth configuration, that is, whether the change in system bandwidth configuration can explain the change in RSRQ; if it is determined that the signal bandwidth has not changed, that is, the change in RSRQ does not match the change in signal bandwidth configuration, then based on RSSI as a preset dimension, determine whether there is an anomaly in the preset dimension; if an anomaly occurs, then perform the aforementioned steps. Figure 4 The steps of the RSSI analysis procedure are shown below: If no abnormality is found, analyze whether RSRP is abnormal; if RSRP is determined to be abnormal, diagnose an input signal abnormality, such as a cell coverage problem or in-band interference, indicating a problem with the input signal itself. If RSRP is not abnormal, other checks in the signal quality anomaly analysis procedure can be performed.

[0088] When anomalies occur in the preset dimensions, including EVM exceeding the corresponding threshold, combined with Figure 5 As shown, step S5 can be implemented as follows: diagnosing an abnormal EVM index. That is, monitoring whether the EVM is abnormal; if the EVM is within the normal range, it is determined that there is no significant problem with the signal quality of this subframe, the process is terminated, and a report is output; if the EVM is abnormal, the analysis results of the abnormal EVM index are output, and it is necessary to further locate the cause of the EVM abnormality.

[0089] After diagnosing an abnormal EVM metric, check for abnormalities in the DC component. If the DC component is normal, perform the IQ imbalance check described below. If abnormalities are found in the preset dimensions, including DC component abnormalities, continue with... Figure 5 As shown, step S5 can be implemented as follows: Analyze the parameters of the analog register readback unit to determine whether the analog configuration is abnormal. If it is determined that the configuration does not match the corresponding configuration parameters, i.e., the analog configuration is abnormal, then it is diagnosed as an analog configuration error. If it is determined that the configuration matches the corresponding configuration parameters, i.e., the analog configuration is not abnormal, then analyze the parameters of the analog DC offset monitoring unit to determine whether the DC compensation is incorrect. If it is determined that the DC offset compensation is incorrect, then it is diagnosed as a DC calibration error. If it is determined that the DC offset compensation is correct, then analyze the parameters of the ADC saturation counting unit to determine whether the ADC is saturated. If it is determined that the ADC is saturated, then it is diagnosed that the analog gain setting is greater than the corresponding threshold, i.e., the gain configuration is incorrect. If it is determined that the ADC is not saturated, then it is diagnosed as an input signal abnormality.

[0090] When the DC component is normal, this application continues to determine whether the IQ is unbalanced. If an anomaly, including IQ imbalance, occurs in a preset dimension, it continues to combine... Figure 5As shown, step S5 can be implemented as follows: Analyze the parameters of the analog register readback unit and the digital register readback unit to determine whether the analog-digital configuration is abnormal. If it is determined that the parameters do not match the corresponding configuration parameters, it indicates that the analog-digital configuration is abnormal, and the diagnosis is an analog configuration error or a digital configuration error. If it is determined that the parameters match the corresponding configuration parameters, it indicates that the analog-digital configuration is normal. Then, analyze the parameters of the analog IQ level monitoring unit to determine whether the IQ correction is incorrect. If it is determined that the amplitude and phase of the IQ channel cannot be corrected, the diagnosis is IQ imbalance compensation failure. If it is determined that the amplitude and phase of the IQ channel are successfully corrected, the diagnosis is an input signal abnormality.

[0091] Once IQ balance is determined, it is necessary to further assess whether phase noise is abnormal. If anomalies, including phase noise anomalies, are detected in a preset dimension, further analysis is required. Figure 5 As shown, step S5 can be implemented as follows: Analyze the parameters of the PLL status monitoring unit to determine whether the PLL status is abnormal. If the phase-locked loop is found to be out of lock, i.e., the PLL status is abnormal, then the PLL configuration is diagnosed as incorrect, such as a hardware configuration error or stability failure of the phase-locked loop. If the phase-locked loop is found to be locked, i.e., the PLL status is not abnormal, then the parameters of the reference clock monitoring unit are analyzed to determine whether the reference clock is abnormal. If the reference clock is found to be unstable, then the reference clock is diagnosed as abnormal. If the reference clock is found to be stable, then the parameters of the power supply monitoring unit are analyzed to determine whether the power supply voltage fluctuates. If the power supply voltage fluctuates, then the power supply noise interference is diagnosed. If the power supply voltage does not fluctuate, then the input signal is diagnosed as abnormal.

[0092] If the phase noise is determined to be normal, it is necessary to further determine whether the frequency offset is abnormal. If anomalies, including frequency offset anomalies, are found in the preset dimensions, further analysis is required. Figure 5 As shown, step S5 can be implemented as follows: Analyze the parameters of the PLL status monitoring unit to determine whether the PLL status is abnormal. If the phase-locked loop is found to be unlocked, it is diagnosed as a PLL configuration error, such as a hardware configuration error or stability failure of the phase-locked loop. If the phase-locked loop is found to be locked, analyze the parameters of the VCO voltage monitoring unit to determine whether the VCO voltage is abnormal. If the tuning voltage is found to be unstable, it is diagnosed as a VCO configuration error. If the tuning voltage is found to be stable, analyze the parameters of the reference clock monitoring unit to determine whether the reference clock is abnormal. If the reference clock is found to be unstable, it is diagnosed as a reference clock abnormality. If the reference clock is found to be stable, it is diagnosed as an input signal abnormality, such as an input signal abnormality caused by the Doppler effect due to high-speed movement.

[0093] Once it's determined that the frequency offset is not abnormal, it's necessary to further assess whether the inter-symbol interference (ISI) is abnormal, specifically whether the ISI is excessive. If anomalies, including ISI, are detected in the preset dimensions, further analysis is required. Figure 5As shown, step S5 can be implemented as follows: Analyze the parameters of the analog register readback unit and the digital register readback unit to determine whether the analog or digital configuration is abnormal. If it is determined that the configuration does not match the corresponding configuration parameters, it indicates that the analog or digital configuration is abnormal, and it is diagnosed as an analog configuration error or a digital configuration error, such as bandwidth or coefficient configuration errors. If it is determined that the configuration matches the corresponding configuration parameters, it indicates that the analog or digital configuration is not abnormal. Then, analyze the parameters of the reference clock monitoring unit to determine whether the time synchronization is abnormal. If it is determined that the time synchronization error is greater than the corresponding threshold, it indicates that the time synchronization is abnormal, and a preset operation is performed, such as the following... Figure 7 The analysis process for frequency and time synchronization problems is shown below. If the time synchronization error is determined to be less than the corresponding threshold, it indicates that the time synchronization is not abnormal. The diagnosis is that the problem is caused by a wireless channel transmission problem (such as multipath fading) that leads to distortion of the input signal waveform.

[0094] Continue reading Figure 5 As shown, in the signal quality diagnosis and analysis process, the system sequentially checks for the following: RSRQ exceeding the corresponding threshold, EVM exceeding the corresponding threshold, DC component abnormality, IQ imbalance, phase noise abnormality, frequency offset abnormality, and inter-symbol interference abnormality. Only if an abnormality occurs in the previous preset dimension is the system checked for an abnormality in the next preset dimension. If EVM does not exceed the corresponding threshold, the checks for DC component abnormality, IQ imbalance, phase noise abnormality, frequency offset abnormality, and inter-symbol interference abnormality are not performed. If the change in RSRQ is determined to match the change in signal bandwidth configuration, the analysis of RSSI and RSRP abnormalities is stopped, and the system directly checks whether EVM exceeds the corresponding threshold.

[0095] Based on the combined results of all the above checks, a final analysis report on signal quality anomalies is generated.

[0096] Figure 6 This paper illustrates the analysis flow for frequency and time synchronization problems in this application. This flow aims to quickly distinguish synchronization failures caused by internal receiver clock system malfunctions, external input signal quality issues, and baseband algorithm defects. For example... Figure 6As shown, when an anomaly occurs in a preset dimension, including frequency synchronization error or time synchronization error exceeding the corresponding threshold, step S5 can be implemented as follows: First, a clock system integrity check is performed: the parameters of the PLL status monitoring unit are analyzed to analyze whether the phase-locked loop (PLL) is abnormal. If the PLL is found to be unlocked (i.e., abnormal), that is, if either the RX PLL or the baseband PLL is found to be unlocked, a configuration problem of the PLL is diagnosed, such as a hardware configuration error or stability failure. If the PLL is found to be locked (i.e., no anomaly occurs), the parameters of the reference clock monitoring unit are analyzed to analyze its frequency accuracy and phase jitter to analyze whether the reference clock is abnormal. If the reference clock is found to be unstable, a reference clock anomaly is diagnosed, indicating a reference clock problem that causes excessive phase noise in the PLL output, thereby causing degradation of synchronization performance. If the reference clock is found to be stable, that is, no anomaly occurs in the reference clock, then an external signal quality correlation analysis is performed: the signal quality is analyzed to determine whether it is abnormal. If the signal quality is found to be abnormal, the aforementioned steps are executed. Figure 5 The steps of the signal quality-based analysis process are shown below; if the signal quality is determined to be normal, the problem is diagnosed as an algorithm parameter issue, such as a baseband algorithm configuration defect, which is highly likely to be a baseband synchronization algorithm implementation defect or improper parameter configuration leading to synchronization failure.

[0097] Based on the results of all the above checks, a final analysis report on the frequency and time synchronization anomalies is generated.

[0098] Figure 7 This paper illustrates the analysis process for CRC check failures in this application. This process, by correlating physical layer indicators, aims to accurately distinguish CRC check errors caused by poor wireless channels, internal receiver damage, and baseband algorithm configuration. For example... Figure 6 As shown, when an anomaly occurs in the preset dimension, including a CRC check failure, step S5 can be implemented as follows: First, perform signal strength and noise analysis: analyze the parameters of the real-time signal quality monitoring unit. If it is determined that the SNR is less than the corresponding threshold, that is, the SNR is significantly lower than the normal reception threshold, it indicates that the bit error is mainly caused by poor channel conditions (such as weak signal and strong interference). At this time, the RSSI analysis process is invoked, that is, the following steps are executed: Figure 4 The steps of the RSSI anomaly analysis process shown are as follows: First, determine the cause of the SNR degradation. If the SNR is determined to have reached the corresponding threshold, indicating a good SNR level, the focus shifts to the receiver's signal processing fidelity. At this point, a deeper signal quality analysis is performed: whether the EVA has reached the corresponding threshold. If the EVA is determined to have reached the corresponding threshold, then proceed as follows... Figure 5The steps of the signal quality anomaly analysis process are shown below. If the EVA is determined to be less than the corresponding threshold, it is diagnosed as an algorithm parameter problem, such as a baseband algorithm configuration defect. The combination of good SNR but poor EVM is the key to diagnosing internal damage to the receiver. This combination clearly indicates that although the potential quality of the input signal is acceptable, the receiver's signal link has introduced additional distortion. At this time, the signal quality analysis process is invoked to thoroughly investigate the root causes of hardware damage such as abnormal phase noise, IQ imbalance, and abnormal DC component.

[0099] When EVA is determined to be less than the corresponding threshold, this application continues to diagnose the baseband algorithm and configuration. In other words, if the physical layer indicators are all performing well, the root cause of the data error is locked in the digital domain itself. Specifically, when SNR and EVM are both at excellent levels but CRC check still fails, it indicates a defect in the baseband algorithm implementation or an error in parameter configuration, such as a mismatch in channel estimation parameters.

[0100] Based on the results of all the above checks, a final analysis report on CRC check failures is generated.

[0101] Figure 8 This application illustrates the analysis process for downlink throughput anomalies. When downlink throughput is consistently below a corresponding threshold, the analysis process is triggered, sequentially evaluating the impact of data retransmission, signal quality, network scheduling, and terminal protocol stack status on downlink throughput. Combined with... Figure 8 As shown, when an anomaly occurs in a preset dimension, including when the downlink throughput is lower than the corresponding threshold and remains so for a preset duration (i.e., the downlink throughput is low), step S5 can be implemented as follows: First, perform physical layer data reliability analysis to verify the basic correctness of data transmission: analyze the parameters of the real-time signal quality monitoring unit; if the proportion of CRC check failures reaches the corresponding threshold, then execute... Figure 7 The steps of the CRC check failure analysis process are shown below. In other words, if the CRC error rate increases significantly, it indicates poor physical layer data reliability, and frequent retransmissions directly lead to a decrease in throughput. At this point, the CRC check problem analysis process is invoked to locate the root cause of the errors. If the proportion of CRC check failures is determined not to have reached the corresponding threshold, then link layer spectral efficiency analysis is performed to analyze the amount of data that a unit of resource can carry: the downlink MCS level assigned to the base station is monitored to analyze the MCS level; if the MCS level is lower than the corresponding threshold, then the following steps are executed: Figure 5The steps of the signal quality anomaly analysis process are shown below. For example, if the MCS level remains low for an extended period, it indicates poor channel quality. The base station has chosen a low-spectrum-efficiency transmission scheme to ensure reliability. In this case, the signal quality anomaly analysis process is invoked to deeply diagnose the physical layer causes leading to the low CQI reported by the UE. If the MCS level reaches the corresponding threshold, network-side resource scheduling analysis is then performed to shift the focus to the total amount of time-frequency resources allocated by the network to the UE. This involves analyzing whether the number of downlink resource blocks allocated is lower than the corresponding threshold, i.e., counting the number of resource blocks scheduled by the base station for the UE per unit time to determine if it is lower than the corresponding threshold, or analyzing whether the resource allocation is insufficient. If the number of resource blocks is lower than the corresponding threshold, a network scheduling problem is diagnosed. For example, if the number of allocated resource blocks is consistently low, the bottleneck lies in the network-side scheduler, which may be related to inaccurate cache status reports submitted by the UE, unsuccessful scheduling requests, or base station load balancing strategies. If the number of resource blocks is not lower than the corresponding threshold, scheduling delay analysis is performed, or terminal protocol stack processing efficiency analysis is performed to pinpoint the problem to the terminal's internal protocol stack processing. Figure 8 As shown, the analysis examines whether scheduling delays exist, specifically analyzing the timing of data transmission and reception to check for any abnormal processing gaps. If such gaps exist, the diagnosis is inefficiency of the protocol stack. For example, if a significant delay is found between data reception and uploading to the application layer, or if data transmission exhibits a discontinuous burst pattern, the diagnosis is inefficiency of the protocol stack. Possible root causes include: a defect in the UE uplink scheduling request mechanism; or, poor data buffer management strategy within the terminal or data overflow.

[0102] Based on the combined results of all the above checks, a final analysis report on the abnormal downlink throughput is generated.

[0103] As described above, this application embeds multiple monitoring nodes in the signal link of the chip receiver. Each monitoring node is specifically designed for multiple target hardware modules, acquiring parameters obtained by each monitoring node when monitoring its corresponding target hardware module. When an anomaly occurs in the chip receiver, the chip's processor analyzes the relevant parameters and outputs anomaly analysis results. Therefore, this application can determine in real time whether the receiver's reception is abnormal, and output anomaly analysis results upon detection, thereby locating fault information with a high probability. This transforms the traditional step-by-step, iterative diagnostic process into real-time automated fault diagnosis, significantly shortening the entire chip receiver debugging cycle and improving development and testing efficiency.

[0104] In scenarios involving LTE UE chips, this application can analyze receiver-related problems in real time, automatically locate the cause, and output a report. This avoids the need to troubleshoot receiver modules one by one after a problem occurs and to repeatedly reproduce the same problem during debugging, thereby effectively increasing the debugging efficiency of receiver problems during the research and development and testing of LTE UE chips.

[0105] For example, in a specific scenario, the digital RSSI of an LTE UE chip rises by about 20dB in multiple consecutive subframes and recovers after a period of time. Regarding the RSSI anomaly caused by this, the debugging process of the prior art and this application is compared below.

[0106] The current debugging process is as follows: multiple suspected directions have been identified, such as incorrect DC configuration or incorrect gain configuration. Therefore, detailed debugging logs related to gain and compensation need to be added, and attempts are made to reproduce the problem in the same environment. Since the sudden increase in RSSI is caused by random co-frequency interference, the probability of reproducing the problem is extremely low, resulting in multiple failures to reproduce the problem in the field test, and the debugging process has thus reached a stalemate.

[0107] The debugging process of this application is as follows: after the RSSI surge occurs, if Figure 4 The RSSI anomaly analysis process shown is triggered, initiating real-time automatic cause localization. The process first reads the analog IQ level monitoring node and finds its signal amplitude abnormally high in sync with the digital RSSI, indicating the anomaly originates before the analog domain. The process then checks the analog register readback unit and the front-end register readback unit, confirming that all gain, switching, and other configuration parameters are consistent with expected values, ruling out the possibility of internal configuration errors. Since the analog signal is abnormal and the internal configuration is correct, according to the preset analysis logic, the RSSI anomaly is highly likely caused by strong in-band interference. This analysis report and the RSSI anomaly phenomenon are output simultaneously. Based on this, this application significantly saves debugging time, identifying the cause while discovering the problem, providing crucial clues for subsequent accurate reproduction and verification of the problem in the laboratory using an interference simulator, thereby improving development efficiency.

[0108] For example, in certain scenarios, LTE UE chips may experience probabilistic failures in CRC verification due to high-frequency power supply noise. The following compares the debugging process of existing technologies with that of this application.

[0109] The current debugging process is as follows: Given that the CRC check failure involves multiple modules of the receiver, the initial debugging process checks RSSI, RSRQ, PLL frequency locking status, frequency offset, and DC parameters. All parameters are within the normal range. The next step is to attempt to reproduce the phenomenon again, adding additional debugging information, including checking key analog and digital registers, gain, and front-end status. Since all parameters are normal, the next step is to continue debugging, attempting to reproduce the phenomenon again and capturing received IQ data for offline data analysis. Because this CRC check error is caused by high-frequency power supply noise, and CRC check errors can usually be caused by many reasons, such as poor signal quality or large frequency offset, the reproduced CRC check error may not be due to the same cause as the initial problem. This misleads the debugging direction and masks the original problem.

[0110] The debugging process for this application is as follows: after a CRC check error occurs, such as... Figure 7 The CRC checksum problem analysis process shown is triggered, and automatic real-time cause location begins. The initial check reveals that the SNR is greater than the threshold by 20dB and the EVM is less than the threshold by 10%, meaning the SNR is good but the signal quality is poor. Therefore, the process proceeds to... Figure 5 The signal quality analysis flow is shown. Since the average power change is small under high-frequency noise, the RSRQ change is also small. Further analysis of the EVM anomaly revealed an abnormal phase noise exceeding historical subframes and preset thresholds. The phase noise analysis path was triggered as follows: the PLL status monitoring node showed the PLL was locked, ruling out a loss of lock; the reference clock monitoring node showed a stable clock, ruling out clock source issues; data from the power supply monitoring node revealed high-frequency ripple noise on the power supply to the RF module at the moment the CRC error occurred. It was concluded that the power supply ripple modulated the VCO in the PLL, generating additional phase noise, degrading the EVM, and ultimately causing the CRC check to fail. This analysis report and the CRC failure phenomenon were output synchronously. Based on this, this application can locate the cause of the received signal anomaly in real time, avoiding multiple iterative debugging and improving debugging efficiency.

[0111] This application embodiment also provides a storage medium storing a monitoring and diagnostic program, which is essentially a computer program, and when executed by a processor, implements the steps of a monitoring and diagnostic method for a chip receiver as in any example.

[0112] The storage medium includes, but is not limited to, any one of read-only memory (ROM), random access memory (RAM), magnetic disk, and optical disk.

[0113] Since the monitoring and diagnostic program stored in the storage medium can execute the steps in the monitoring and diagnostic method of the chip receiver of any embodiment of this application, the beneficial effects that the monitoring and diagnostic method of any of the foregoing embodiments can achieve can be realized. For details, please refer to the foregoing embodiments, which will not be repeated here.

[0114] This application also provides a monitoring and diagnostic device for a chip receiver. The signal link of the chip receiver is provided with a plurality of target hardware modules. The device includes multiple monitoring nodes, each of which is embedded in the signal link. These monitoring nodes are used to monitor the corresponding target hardware modules to obtain corresponding parameters and to execute the steps of the monitoring and diagnostic method for the chip receiver in any of the foregoing embodiments.

[0115] This application embodiment also provides another monitoring and diagnostic device or chip, including a memory and a processor. The memory stores a monitoring and diagnostic program. When the monitoring and diagnostic program is executed by the processor, it implements the steps of the monitoring and diagnostic method of the chip receiver in any of the foregoing embodiments. And / or, the monitoring and diagnostic device or chip is provided with a storage medium as shown in the above example, and the corresponding processor loads the storage medium to execute the steps of the monitoring and diagnostic method of the chip receiver, thereby achieving the beneficial effects that the monitoring and diagnostic method of the chip receiver in the corresponding embodiment can achieve.

[0116] Figure 9 This is a schematic diagram of the structure of a monitoring and diagnostic device provided in an embodiment of this application. This monitoring and diagnostic device 90 can also be referred to as a chip receiver monitoring and diagnostic device 90, such as... Figure 9 As shown, it includes: The determination module 91 is used to determine several target hardware modules from the signal link of the chip receiver; The node embedding module 92 is used to embed multiple monitoring nodes in a signal link for several target hardware modules; Monitoring module 93 is used to acquire parameters obtained by each monitoring node when monitoring the corresponding target hardware module; The processing module 94 is used to determine whether the chip receiver has an anomaly in a preset dimension; and when an anomaly occurs, to analyze the parameters and output the anomaly analysis result.

[0117] It should be understood that the above modules can be represented as physical devices or virtual modules (i.e., commonly referred to as logical modules) in actual scenarios. A single physical device can implement a module, or two or more physical devices can work together to implement it. Similarly, the function performed by a single physical device can be implemented by a single physical device, or two or more physical devices can work together to implement it. Furthermore, the functions corresponding to each module can be implemented by the corresponding steps of the monitoring and diagnostic method of the chip receiver in any of the foregoing embodiments.

[0118] The above are only some embodiments of this application and do not limit the patent scope of this application. For those skilled in the art, any equivalent structural transformations made using the content of this specification and drawings are similarly included within the patent protection scope of this application.

[0119] The use of step designations such as S1 and S2 in this document is intended to more clearly and concisely describe the corresponding content and does not constitute a substantial restriction on the order. In specific implementation, those skilled in the art may execute S2 first and then S1, etc., but these should all be within the protection scope of this application.

[0120] Although this document uses terms such as "first," "second," etc., to describe various types of information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. Furthermore, the singular forms "a," "an," and "the" are intended to also include the plural forms. The terms "or" and "and / or" are interpreted as inclusive, or meaning either one or any combination thereof. Exceptions to this definition only arise when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

Claims

1. A method for monitoring and diagnosing a chip receiver, characterized in that, include: Several target hardware modules are identified from the signal link of the chip receiver; For the aforementioned target hardware modules, multiple monitoring nodes are embedded in the signal link; Obtain the parameters obtained by each monitoring node when monitoring the corresponding target hardware module; Determine whether the chip receiver exhibits any abnormality in a preset dimension; When an anomaly occurs, the chip's processor analyzes the parameters and outputs the anomaly analysis results.

2. The method according to claim 1, characterized in that, The plurality of target hardware modules include at least one of the following: radio frequency front-end module, radio frequency analog module, analog-to-digital converter, radio frequency digital module, baseband digital module, clock system, temperature sensor, and power monitoring module.

3. The method according to claim 2, characterized in that, For the aforementioned target hardware modules to embed multiple monitoring nodes in the signal link, at least one of the following is included: A first monitoring node is embedded in the signal link to monitor the parameters of each target hardware module when the chip receiver executes the control signaling path; A second monitoring node is embedded in the signal link to monitor the parameters of each target hardware module when the chip receiver executes the data transmission and reception path; A third monitoring node is embedded in the signal link to monitor the external environment and basic condition parameters of each target hardware module when the chip receiver keeps the system working normally.

4. The method according to claim 3, characterized in that, The first monitoring node includes: A front-end register readback unit is used to monitor the radio frequency front-end module; An analog register readback unit is used to monitor the radio frequency analog module; A bus monitoring unit is used to monitor the MIPI bus connecting the RF analog module and the processor, as well as the SPI bus connecting the RF analog module and the processor. The PLL status monitoring unit is used to read the parameters of the phase-locked loop in the clock system; In addition, a digital register readback unit is provided for monitoring the radio frequency digital module and the baseband digital module; The second monitoring node includes: An analog IQ level monitoring unit is used to monitor the radio frequency analog module; A simulated DC offset monitoring unit is used to monitor the radio frequency simulation module; An ADC saturation counting unit is used to monitor the analog-to-digital converter; A digital RSSI monitoring unit is used to monitor the radio frequency digital module; A digital DC monitoring unit is used to monitor the radio frequency digital module; And, a real-time signal quality monitoring unit, used to monitor the baseband digital module; The third monitoring node includes: A reference clock monitoring unit is used to monitor the phase-locked loop of the clock system; VCO voltage monitoring unit, used to monitor the phase-locked loop of the clock system; A temperature monitoring unit is used to monitor the temperature sensor; And a power monitoring unit for monitoring the power monitoring module.

5. The method according to claim 4, characterized in that, The preset dimension includes RSSI. When the chip receiver is abnormal in the preset dimension, it includes at least one of the following: the RSSI is greater than a first threshold, the RSSI is less than a second threshold, or the change value of the RSSI is greater than a third threshold, wherein the second threshold is less than the first threshold. The preset dimension includes signal quality. If the chip receiver malfunctions in the preset dimension, it includes at least one of the following: RSRQ exceeds the corresponding threshold, EVM exceeds the corresponding threshold, DC component is abnormal, IQ imbalance is abnormal, phase noise is abnormal, frequency offset is abnormal, or inter-symbol interference is abnormal. The preset dimensions include frequency and time synchronization. When the chip receiver malfunctions in the preset dimensions, it includes: frequency synchronization error or time synchronization error exceeding the corresponding threshold. The preset dimension includes the CRC check result. An anomaly occurs in the chip receiver in the preset dimension, including: the CRC check result is a CRC check failure. The preset dimension includes downlink throughput. When the chip receiver malfunctions in the preset dimension, it includes: the downlink throughput being lower than the corresponding threshold for a preset duration.

6. The method according to claim 5, characterized in that, When an anomaly occurs in a preset dimension, including when the RSSI exceeds a first threshold, the process of analyzing the parameters and outputting the anomaly analysis result through the chip's processor includes: Analyze the parameters of the analog IQ level monitoring unit. If the analog IQ level is found to be abnormal, analyze the parameters of the analog register readback unit. If the parameters are found to be inconsistent with the corresponding configuration parameters, the analog configuration error is diagnosed. If the parameters are found to be consistent with the corresponding configuration parameters, the external strong signal interference is diagnosed. If the simulated IQ level is determined to be normal, the parameters of the simulated DC offset monitoring unit are analyzed. If the DC component is determined to be abnormal, the simulated DC offset calibration error is diagnosed. If the DC component is determined to be normal, the parameters of the ADC saturation counting unit are analyzed. If the ADC is determined to be saturated, it is diagnosed that the analog gain setting is greater than the corresponding threshold, resulting in signal clipping distortion. If the ADC is determined to be unsaturated, the parameters of the digital register readback unit are analyzed. If the digital gain is determined to be abnormal, the digital gain configuration is diagnosed as incorrect. Furthermore, if the digital gain is determined to be normal, the parameters of the digital DC monitoring unit are analyzed. If the residual DC is determined to be greater than the corresponding threshold, the digital domain DC compensation algorithm is diagnosed as malfunctioning or improperly calibrated. When an anomaly occurs in a preset dimension, including when the RSSI is less than a second threshold, the process of analyzing the parameters and outputting the anomaly analysis results through the chip's processor includes: Analyzing the parameters of the PLL status monitoring unit, if it is determined that the phase-locked loop (PLL) has lost lock, then the downconversion failure is diagnosed as a result of the PLL losing lock. If the phase-locked loop is determined to be locked, the parameters of the front-end register readback unit and the analog register readback unit are analyzed. If the radio frequency configuration is determined to be incorrect, the receiving path is diagnosed as not being fully established. If the RF configuration is determined to be correct, the parameters of the analog IQ level monitoring unit are analyzed. If the analog IQ level is determined to be less than the corresponding threshold, the input signal is diagnosed as weak. Furthermore, if the analog IQ level is determined to reach the corresponding threshold, the parameters of the digital RSSI monitoring unit are analyzed; if the digital RSSI is determined to be less than the corresponding threshold, it is diagnosed as a digital register configuration error. When an anomaly occurs in a preset dimension, including a change in RSSI value exceeding a third threshold, the process of analyzing the parameters and outputting anomaly analysis results via the chip's processor includes: If the parameters of the power monitoring unit are analyzed and fluctuations in the power supply voltage are detected, then the problem is diagnosed as power supply noise interference. If it is determined that there is no fluctuation in the power supply voltage, then analyze whether there is periodic fluctuation in RSSI. If it is determined that there is periodic fluctuation, then it is diagnosed as the presence of switching noise interference. If it is determined that there is no periodic fluctuation, then analyze whether there is pulse fluctuation in RSSI. If pulse fluctuation is determined to exist, then it is diagnosed as clock harmonic interference. Furthermore, if it is determined that there is no pulse fluctuation, the parameters of the temperature monitoring unit are analyzed. If it is determined that the RSSI fluctuates abnormally in sync with the temperature, it is diagnosed as temperature change causing gain drift of the analog device. If it is determined that the RSSI fluctuates normally in sync with the temperature, it is diagnosed as input signal fluctuation.

7. The method according to claim 6, characterized in that, When an anomaly occurs in a preset dimension, including when the RSRQ exceeds the corresponding threshold, the process of analyzing the parameters through the chip's processor and outputting the anomaly analysis result includes: Analyze the parameters of the real-time signal quality monitoring unit. If it is determined that the change in RSRQ does not match the configuration change of the signal bandwidth, then based on RSSI as a preset dimension, determine whether there is an anomaly in the preset dimension. If an anomaly occurs, execute the steps described in claim 6. If no anomaly occurs, analyze whether RSRP is abnormal. If the RSRP is determined to be abnormal, diagnose it as an input signal anomaly. When an anomaly occurs in a preset dimension, including when the EVM exceeds the corresponding threshold, the process of analyzing the parameters through the chip's processor and outputting the anomaly analysis result includes: The diagnosis was abnormal EVM indicators; When an anomaly occurs in a preset dimension, including an anomaly in the DC component, the process of analyzing the parameters through the chip's processor and outputting the anomaly analysis results includes: If the parameters of the simulated register readback unit are analyzed and determined to be inconsistent with the corresponding configuration parameters, then a simulated configuration error is diagnosed. If it is determined that it matches the corresponding configuration parameters, the parameters of the simulated DC offset monitoring unit are analyzed. If it is determined that the DC offset compensation is incorrect, it is diagnosed as a DC calibration error. If the DC offset compensation is determined to be correct, the parameters of the ADC saturation counting unit are analyzed. If the ADC is determined to be saturated, the analog gain setting is diagnosed as being greater than the corresponding threshold. If the ADC is determined not to be saturated, the input signal is diagnosed as abnormal. When an anomaly occurs in a preset dimension, including IQ imbalance, the process of analyzing the parameters through the chip's processor and outputting the anomaly analysis results includes: Analyze the parameters of the analog register readback unit and the digital register readback unit. If they are found to be inconsistent with the corresponding configuration parameters, then the problem is diagnosed as an analog configuration error or a digital configuration error. If it is determined that it matches the corresponding configuration parameters, the parameters of the analog IQ level monitoring unit are analyzed. If it is determined that the amplitude and phase of the IQ channel cannot be corrected, it is diagnosed as IQ imbalance compensation failure; if it is determined that the amplitude and phase of the IQ channel are successfully corrected, it is diagnosed as input signal abnormality. When an anomaly, including phase noise anomaly, occurs in a preset dimension, the process of analyzing the parameters and outputting the anomaly analysis results through the chip's processor includes: If the parameters of the PLL status monitoring unit are analyzed, and it is determined that the phase-locked loop is out of lock, then the diagnosis is a hardware configuration error or stability failure of the phase-locked loop; if it is determined that the phase-locked loop is locked, then the parameters of the reference clock monitoring unit are analyzed, and if it is determined that the reference clock is unstable, then the diagnosis is a reference clock abnormality. If the reference clock is determined to be stable, the parameters of the power monitoring unit are analyzed. If the power supply voltage is found to be fluctuating, it is diagnosed as power supply noise interference; if the power supply voltage is not found to be fluctuating, it is diagnosed as an abnormal input signal. When an anomaly, including a frequency offset anomaly, occurs in a preset dimension, the process of analyzing the parameters through the chip's processor and outputting the anomaly analysis results includes: If the parameters of the PLL status monitoring unit are analyzed, and it is determined that the phase-locked loop is out of lock, then the diagnosis is a hardware configuration error or stability failure of the phase-locked loop; if it is determined that the phase-locked loop is locked, then the parameters of the VCO voltage monitoring unit are analyzed, and if it is determined that the tuning voltage is unstable, then the diagnosis is a VCO configuration error. If the tuning voltage is determined to be stable, the parameters of the reference clock monitoring unit are analyzed. If the reference clock is determined to be unstable, the reference clock is diagnosed as abnormal. If the reference clock is determined to be stable, the input signal is diagnosed as abnormal. When an anomaly, including inter-symbol interference (ISI) anomaly, occurs in a preset dimension, the step of analyzing the parameters and outputting the anomaly analysis result through the chip's processor includes: Analyze the parameters of the analog register readback unit and the digital register readback unit. If they are found to be inconsistent with the corresponding configuration parameters, then the problem is diagnosed as an analog configuration error or a digital configuration error. If the parameters are found to match the corresponding configuration parameters, the parameters of the reference clock monitoring unit are analyzed. If the time synchronization error is found to be greater than the corresponding threshold, a preset operation is performed. If the time synchronization error is found to be less than the corresponding threshold, the problem is diagnosed as a wireless channel issue causing distortion of the input signal waveform.

8. The method according to claim 7, characterized in that, The system sequentially determines whether the following conditions are met: RSRQ exceeds the corresponding threshold, EVM exceeds the corresponding threshold, DC component is abnormal, IQ is unbalanced, phase noise is abnormal, frequency offset is abnormal, and inter-symbol interference is abnormal. Only when an abnormality occurs in the previous preset dimension is the system determined whether an abnormality occurs in the next preset dimension. If the EVM does not exceed the corresponding threshold, the determination of whether there is DC component abnormality, IQ imbalance, phase noise abnormality, frequency offset abnormality, or inter-symbol interference abnormality will not be performed. If the change in RSRQ is determined to match the change in signal bandwidth configuration, then stop analyzing whether RSSI and RSRP are abnormal, and directly determine whether EVM exceeds the corresponding threshold.

9. The method according to claim 7, characterized in that, The preset operation, or when an anomaly occurs in a preset dimension, including a frequency synchronization error or a time synchronization error exceeding a corresponding threshold, involves the chip's processor analyzing the parameters and outputting the anomaly analysis result, including: If the parameters of the PLL status monitoring unit are analyzed, and it is determined that the phase-locked loop is out of lock, then the diagnosis is a hardware configuration error or stability failure of the phase-locked loop; if it is determined that the phase-locked loop is locked, then the parameters of the reference clock monitoring unit are analyzed, and if it is determined that the reference clock is unstable, then the diagnosis is a reference clock abnormality. If the reference clock is determined to be stable, then analyze whether the signal quality is normal; If the signal quality is determined to be abnormal, then the steps described in claim 7 shall be performed; If the signal quality is determined to be normal, the diagnosis is a baseband algorithm configuration defect.

10. The method according to claim 7, characterized in that, When an anomaly occurs in the preset dimension, including a CRC check failure, The chip's processor analyzes the parameters and outputs anomaly analysis results, including: Analyze the parameters of the real-time signal quality monitoring unit. If the SNR is determined to be less than the corresponding threshold, then execute the steps described in claim 6. If the SNR is determined to have reached the corresponding threshold, then analyze whether the EVA has reached the corresponding threshold; if the EVA is determined to have reached the corresponding threshold, then perform the steps described in claim 7. If the EVA is determined to be less than the corresponding threshold, it is diagnosed as a baseband algorithm configuration defect.

11. The method according to claim 10, characterized in that, When an anomaly occurs in a preset dimension, including when the downlink throughput is lower than the corresponding threshold and remains below a preset duration, The chip's processor analyzes the parameters and outputs anomaly analysis results, including: Analyze the parameters of the real-time signal quality monitoring unit. If the proportion of CRC check failures is determined to reach the corresponding threshold, then execute the steps described in claim 9. If the proportion of CRC check failures is determined to be below the corresponding threshold, the MCS level is analyzed; if the MCS level is below the corresponding threshold, the steps described in claim 7 are executed. If the MCS level reaches the corresponding threshold, analyze whether the number of resource blocks allocated for downlink resources is lower than the corresponding threshold; if so, diagnose it as a network scheduling problem. If not, analyze whether there is a scheduling delay; if so, diagnose it as low protocol stack efficiency.

12. A monitoring and diagnostic device for a chip receiver, characterized in that, The signal link of the chip receiver is provided with a plurality of target hardware modules. The device includes multiple monitoring nodes, each of which is embedded in the signal link and is used to monitor the corresponding target hardware module to obtain the corresponding parameters and to perform the steps of the method as described in any one of claims 1 to 11.

13. A monitoring and diagnostic device for a chip receiver, characterized in that, It includes a processor and a memory, the memory storing a monitoring and diagnostic program, which, when executed by the processor, implements the steps of the method as described in any one of claims 1 to 11.

14. A storage medium, characterized in that, The device contains a computer program that, when executed by a processor, implements the steps of the method as described in any one of claims 1 to 11.

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