Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device having improved reliability and a method for manufacturing the semiconductor device are disclosed. The semiconductor device includes: a first impurity region disposed in a substrate; a second impurity region disposed in the substrate and spaced apart from the first impurity region; a bit line contact plug disposed over the first impurity region and having a multi-tapered sidewall; and a memory contact plug disposed over the second impurity region, in which a multi-tapered sidewall of the bit line contact plug includes at least one inflection point at which a slope varies, and in which the at least one inflection point is disposed higher than a bottom surface of the memory contact plug.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0132447, filed on September 30, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure generally relate to a semiconductor device, and more specifically, to a semiconductor device including a contact plug and a method of manufacturing the semiconductor device. Background Technology

[0004] As semiconductor technology advances, the size of individual fine patterns in semiconductor devices is decreasing. Furthermore, as integrated circuits become more densely integrated, the linewidth of these fine patterns is becoming smaller, increasing the complexity of forming fine patterns between adjacent patterns. Summary of the Invention

[0005] The embodiments of this disclosure pertain to semiconductor devices with improved reliability and methods for manufacturing the same.

[0006] According to one embodiment of the present disclosure, a semiconductor device includes: a first contact structure disposed on a substrate, the first contact structure having multiple tapered sidewalls; a line structure including a wire disposed on the first contact structure; and a plurality of second contact structures disposed between the line structures.

[0007] According to another embodiment of this disclosure, a semiconductor device includes: a first impurity region disposed in a substrate; a second impurity region disposed in the substrate and spaced apart from the first impurity region; a bit line contact plug disposed above the first impurity region and having multi-tapered sidewalls; and a storage contact plug disposed above the second impurity region, wherein the multi-tapered sidewalls of the bit line contact plug include at least one inflection point at which the slope changes, and wherein the at least one inflection point is configured to be higher than the bottom surface of the storage contact plug.

[0008] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device includes: forming a first impurity region and a second impurity region in a substrate; forming a bit line contact hole that exposes the first impurity region and has multi-tapered sidewalls; forming a bit line contact plug that fills the bit line contact hole and includes a lower buried portion and an upper buried portion, the lower buried portion contacting the first impurity region and the upper buried portion being located above the lower buried portion; forming a gap filling layer in a peripheral region of the lower buried portion of the bit line contact plug; recessing the sidewalls of the upper buried portion of the bit line contact plug; and forming a storage contact plug that contacts the second impurity region.

[0009] These and other features and advantages of the embodiments of this disclosure will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0010] Figure 1A This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 1B It is along Figure 1A The cross-sectional view taken by line A-A' shown in the figure.

[0012] Figure 1C It is along Figure 1A The cross-sectional view shown is taken by line B-B'.

[0013] Figure 1D This is a cross-sectional view showing the contact plug of the positioning line.

[0014] Figures 2A to 2C This is a cross-sectional view illustrating a bit line contact plug according to other embodiments of the present disclosure.

[0015] Figures 3 to 15 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figures 16 to 19 This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0017] Figures 20 to 23 This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure. Detailed Implementation

[0018] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Throughout this disclosure, the same reference numerals denote the same parts in various figures and embodiments. Various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When reference is made that a first layer is “on” a second layer or a substrate, it refers not only to the case where the first layer is formed directly on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0019] The following embodiments of this disclosure provide a method for ensuring the spacing between bit line contact plugs and storage contact plugs to suppress current leakage.

[0020] To ensure the spacing between the tips (or inflection points) of specific portions of the storage contact plug and the bit line contact plug, a two-step etching process can be performed during a series of processes that form the bit line contact hole and the bit line contact plug.

[0021] Figure 1A This is a plan view illustrating a semiconductor device 100 according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A The cross-sectional view taken by line A-A' shown in the figure. Figure 1C It is along Figure 1A The cross-sectional view shown is taken by line B-B'. Figure 1D This is a cross-sectional view showing the contact plug of the positioning line.

[0022] refer to Figures 1A to 1D The semiconductor device 100 may include: a line structure BL including a plurality of first conductive patterns 113 located on a substrate 101; a plurality of second conductive patterns 116 formed between the line structures BL; and a plug isolation structure 117 formed between the line structures BL and the second conductive patterns 116. The first conductive patterns 113 may include bit lines 113, and the line structure BL may include a bit line structure BL. The second conductive patterns 116 may include storage contact plugs 116.

[0023] According to another embodiment of this disclosure, the semiconductor device 100 may include: a first contact structure 112 formed on a substrate 101 and having multi-tapered sidewalls; a line structure BL located on the first contact structure 112 and including conductive wires; and a plurality of second contact structures 116 formed between the line structures BL. The first contact structure 112 may include bit line contact plugs 112, and the second contact structures 116 may include storage contact plugs 116. The multi-tapered sidewalls may be referred to as stepped tapered sidewalls.

[0024] Semiconductor device 100 may include a plurality of memory cells. Each memory cell may include a cell transistor, the cell transistor including a buried word line structure (BWL) and a bit line 113.

[0025] An isolation layer 102 and active regions 103 can be formed in substrate 101. Multiple active regions 103 can be defined by the isolation layer 102. Substrate 101 can be a material suitable for semiconductor processes. Substrate 101 can include a semiconductor substrate. Substrate 101 can be formed of a silicon-containing material. Substrate 101 can include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multiples thereof. Substrate 101 can also include other semiconductor materials, such as germanium. Substrate 101 can also include a group III / V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). Substrate 101 can also include an SOI (silicon-on-insulator) substrate. The isolation layer 102 can be formed using a shallow trench isolation (STI) process.

[0026] A gate trench 105 may be formed in a substrate 101. A buried word line structure (BWL) may be formed in the gate trench 105. The buried word line structure (BWL) may include a gate dielectric layer 106, a buried word line 107, and a gate capping layer 108. The gate dielectric layer 106 may be formed on the surface of the gate trench 105. The buried word line 107 may be formed above the gate dielectric layer 106 to partially fill the gate trench 105. The gate capping layer 108 may be formed above the buried word line 107. The upper surface of the buried word line 107 may be disposed at a level below the surface of the substrate 101. The buried word line 107 may be a low-resistance metal material. The buried word line 107 may be formed by sequentially stacking titanium nitride and tungsten. According to another embodiment of this disclosure, the buried word line 107 may be formed solely of titanium nitride (TiN only). The buried word line 107 may be referred to as a "buried gate electrode". The buried character line 107 can extend along the first direction D1.

[0027] A first impurity region 109 and a second impurity region 110 can be formed in the substrate 101. The first impurity region 109 and the second impurity region 110 can be spaced apart from each other by a gate trench 105. The first impurity region 109 and the second impurity region 110 can be referred to as source / drain regions. The first impurity region 109 and the second impurity region 110 can include N-type impurities, such as arsenic (As) or phosphorus (P). The buried word line 107 and the first impurity region 109 and the second impurity region 110 can be a single-cell transistor. Due to the buried word line 107, the single-cell transistor can improve the short-channel effect.

[0028] Bit line contact plug 112 may be formed on substrate 101. Bit line contact plug 112 may be coupled to first impurity region 109. Bit line contact plug 112 may be disposed in bit line contact hole 111. Bit line contact hole 111 may extend through hard mask layer 104 to substrate 101. Hard mask layer 104 may be formed on substrate 101. Hard mask layer 104 may include dielectric material. Bit line contact hole 111 may expose first impurity region 109. Lower surface of bit line contact plug 112 may be lower than upper surface of isolation layer 102 and upper surface of active region 103. Bit line contact plug 112 may be formed of polysilicon or metal. A portion of bit line contact plug 112 may have a linewidth smaller than the diameter of bit line contact hole 111. A stack of bitline barrier 113A and bitline 113 can be formed on bitline contact plug 112, and a bitline hard mask 114 can be formed on bitline 113. The stacked structure of bitline contact plug 112, bitline barrier 113A, bitline 113, and bitline hard mask 114 can be referred to as a bitline structure BL. Bitline 113 can have a line shape extending along a second direction D2 intersecting with buried word line 107. A portion of bitline barrier 113A can be coupled to bitline contact plug 112. Bitline 113 and bitline contact plug 112 can have the same linewidth in a first direction D1. Therefore, bitline 113 and bitline barrier 113A can extend along the second direction D2 and cover bitline contact plug 112. Bitline 113 can include a metallic material, such as tungsten. Bitline hard mask 114 can include a dielectric material, such as silicon nitride.

[0029] Spacer structures 115 can be formed on the sidewalls of the bit line structure BL. Spacer structures 115 can extend to be disposed on the sidewalls of the bit line contact plug 112. Spacer structures 115 may include silicon nitride, silicon oxide, low-k materials, or combinations thereof. Low-k materials may include SiBN, SiCO, SiCN, SiBCN, or combinations thereof. According to another embodiment of this disclosure, spacer structures 115 may include multiple layers of spacers. For example, they may include KK, KO, KN, NK, OK, KA, NKON, NKNAN, NKOK, NKOKN, NKAKN, KOK, or KAK, where N refers to silicon nitride; K refers to a low-k material; O refers to silicon oxide; and A refers to an air gap. According to another embodiment of this disclosure, the outermost spacer of spacer structure 115 may include a low-k material. According to one embodiment of this disclosure, spacer structure 115 may include an inner spacer 115A and an outer spacer 115B. The inner spacer 115A may include silicon nitride, while the outer spacer 115B may include a low-k material.

[0030] Storage contact plugs 116 may be formed between adjacent bit line structures BL. Storage contact plugs 116 may be coupled to a second impurity region 110. Storage contact plugs 116 may include polysilicon, metal nitride, metallic material, metal silicide, or a combination thereof. According to some embodiments of this disclosure, storage contact plugs 116 may include polysilicon, cobalt silicide, and tungsten stacked in the aforementioned order.

[0031] Viewed from a direction parallel to the bit line structure BL, a plug isolation structure 117 can be formed between adjacent memory contact plugs 116. The plug isolation structure 117 can be formed between adjacent bit line structures BL. Adjacent memory contact plugs 116 can be separated by the plug isolation structure 117 in the second direction D2. Multiple plug isolation structures 117 and multiple memory contact plugs 116 can be alternately arranged in the second direction D2 between adjacent bit line structures BL. The memory contact plugs 116 can directly contact the spacer structure 115.

[0032] Storage element 130 may be formed on storage contact plug 116. Storage element 130 may include a capacitor, which includes a storage node. The storage node may include a cylindrical shape. Although not shown, a dielectric layer and plate-like nodes may be further formed on the storage node. In addition to a cylindrical shape, the storage node may also have a cylindrical shape.

[0033] The plug isolation structure 117 may be referred to as an isolation layer or a patterned isolation layer. The plug isolation structure 117 may include an air gap, silicon nitride, a low-k material, or a combination thereof. When the plug isolation structure 117 includes a low-k material, the parasitic capacitance between adjacent storage contact plugs 116 having the plug isolation structure 117 therebetween can be reduced. The plug isolation structure 117 may include an air gap, SiCO, SiCN, SiOCN, SiBN, SiBCN, or a combination thereof.

[0034] refer to Figures 1A to 1D The semiconductor device 100 may include a bit line contact plug 112. The sidewalls of the bit line contact plug 112 may include a multi-tapered profile. The sidewalls of the bit line contact plug 112 may include a first tapered sidewall TS1, a second tapered sidewall TS2, and a vertical sidewall VS.

[0035] The bit line contact plug 112 may include a bottom 112L, a middle 112M, and a top 112U. The sidewall of the bottom 112L may include a first conical sidewall TS1. The sidewall of the middle 112M may include a second conical sidewall TS2. The sidewall of the top 112U may include a vertical sidewall VS. The slope of the vertical sidewall VS may be approximately 90°. The first conical sidewall TS1 may have a first slope θ1 relative to the bottom surface LV1 of the bottom 112L. The second conical sidewall TS2 may have a second slope θ2 relative to the bottom surface LV1 of the bottom 112L. The first slope θ1 of the first conical sidewall TS1 and the second slope θ2 of the second conical sidewall TS2 may be different from each other. The second slope θ2 of the second conical sidewall TS2 may be closer to approximately 90° than the first slope θ1 of the first conical sidewall TS1. Gap filling layers G1 and G2 may be disposed in the peripheral region of the bottom 112L.

[0036] According to another embodiment of this disclosure, the bit line contact plug 112 may include: a lower buried portion coupled to a first impurity region 109 of the active region 13; and an upper buried portion having a width smaller than that of the lower buried portion. For example, the lower buried portion refers to the bottom 112L, while the upper buried portion refers to the middle portion 112M and the top 112U. According to another embodiment of this disclosure, the lower buried portion refers to the bottom 112L and the middle 112M, while the upper buried portion refers to the top 112U.

[0037] The sidewalls of the bit-line contact plug 112 may include multiple inflection points, such as AG1 and AG2, where the slope changes. For example, inflection points AG1 and AG2 may include a first inflection point AG1 located between the first conical sidewall TS1 and the second conical sidewall TS2, and a second inflection point AG2 located between the second conical sidewall TS2 and the vertical sidewall VS. The first inflection point AG1 and the second inflection point AG2 may be positioned at a level higher than the bottom surface LV2 of the storage contact plug 116. Furthermore, the first inflection point AG1 and the second inflection point AG2 may be positioned at a level higher than the upper surfaces of the gap filling layers G1 and G2.

[0038] The first conical sidewall TS1 and the second conical sidewall TS2 can have a conical shape, while the vertical sidewall VS can have a vertical shape. The first conical sidewall TS1 and the second conical sidewall TS2 can provide a stepped conical shape. Gap filling layers G1 and G2 can be disposed in the peripheral region of the bottom 112L. Due to the multi-conical profile, the space S1 between the middle portion 112M and the storage contact plug 116 can be ensured to be sufficiently wide. The multi-conical profile ensures a wider space compared to the space S2 obtainable due to a single conical profile (see reference numeral 'TS').

[0039] According to the above embodiments of the present disclosure, since the space S1 between the bit line contact plug 112 and the storage contact plug 116 is sufficient, current leakage can be prevented.

[0040] As the linewidth of the middle portion 112M of the bit line contact plug 112 decreases, the contact resistance increases. However, the increase in contact resistance is compensated by increasing the linewidth of the bottom portion 112L to ensure sufficient volume.

[0041] Figures 2A to 2C This is a cross-sectional view illustrating a bit line contact plug according to other embodiments of the present disclosure.

[0042] refer to Figure 2A The bit line contact plug 112 may include a bottom 112L, a middle 112M, and a top 112U. The sidewall TS1 of the bottom 112L may have a tapered shape, while the sidewall RS2 of the middle 112M and the sidewall RS3 of the top 112U may have a circular shape. The sidewall TS1 of the bottom 112L and the sidewall RS2 of the middle 112M may have a stepped tapered shape. Gap filling layers G1 and G2 may be disposed in the peripheral region of the bottom 112L.

[0043] refer to Figure 2B The bit line contact plug 112 may include a bottom 112L, a middle 112M, and a top 112U. The sidewall TS1 of the bottom 112L may have a tapered shape, while the sidewall VS2 of the middle 112M and the sidewall VS3 of the top 112U may have a vertical shape. The sidewall TS1 of the bottom 112L and the sidewall VS2 of the middle 112M may have a stepped tapered shape. Gap filling layers G1 and G2 may be disposed in the peripheral region of the bottom 112L.

[0044] refer to Figure 2C The bit line contact plug 112 may include a bottom 112L, a middle 112M, and a top 112U. The sidewall TS1 of the bottom 112L may have a tapered shape, while the sidewall TS2 of the middle 112M and the sidewall TS3 of the top 112U may also have tapered shapes. The sidewall TS1 of the bottom 112L and the sidewall TS2 of the middle 112M may have a stepped tapered shape. Gap filling layers G1 and G2 may be disposed in the peripheral region of the bottom 112L. The sidewalls TS2 and TS3 of the middle and top portions may form smooth, continuous inclined surfaces.

[0045] Figures 3 to 15 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 3 to 15 It shows the basis Figure 1A Cross-sectional view of the manufacturing method of lines A-A' and B-B' shown.

[0046] refer to Figure 3 An isolation layer 12 can be formed on a substrate 11. The isolation layer 12 can define multiple active regions 13 within the substrate 11. The isolation layer 12 can be formed using a shallow trench isolation (STI) process. The STI process can be performed as follows: The substrate 11 can be etched to form isolation trenches (the reference numerals are omitted). The isolation trenches can be filled with a dielectric material to form the isolation layer 12. The isolation layer 12 can include silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes can be used to fill the isolation trenches with a dielectric material. Planarization processes, such as chemical mechanical polishing (CMP), can also be used.

[0047] refer to Figure 4 A gate trench 15 can be formed in the substrate 11. The gate trench 15 can have a line shape intersecting the active region 13 and the isolation layer 12. The gate trench 15 can be formed by forming a mask pattern (not shown) on the substrate 11 and performing an etching process using the mask pattern as an etching mask. To form the gate trench 15, a hard mask layer 14 can be used as an etching barrier. The hard mask layer 14 can have a shape patterned by the mask pattern. The hard mask layer 14 can include silicon oxide. The hard mask layer 14 can include TEOS (tetraethyl orthosilicate). The bottom surface of the gate trench 15 can be disposed at a higher level than the bottom surface of the isolation layer 12.

[0048] Although not shown, a portion of the isolation layer 12 can be recessed, allowing the active region 13 below the gate trench 15 to protrude. For example, the isolation layer 12 below the gate trench 15 can be selectively recessed along the longitudinal direction of the gate trench 15. Therefore, a fin region (its reference numerals are omitted) can be formed below the gate trench 15. The fin region can be part of the channel region.

[0049] refer to Figure 5 A buried word line structure (BWL) can be formed in the gate trench 15. The buried word line structure (BWL) may include: a gate dielectric layer 16 that conformally covers the bottom surface and sidewalls of the gate trench 15; a buried word line 17 that partially fills the lower portion of the gate trench 15 above the gate dielectric layer 16; and a gate capping layer 18 formed above the buried word line 17 to fill the remaining upper portion of the gate trench 15.

[0050] The method for forming a buried word line (BWL) structure can be as follows. First, a gate dielectric layer 16 can be formed on the bottom surface and sidewalls of a gate trench 15. Before forming the gate dielectric layer 16, etching damage to the surface of the gate trench 15 can be repaired by curing. The curing process can, for example, include forming a sacrificial oxide by a thermal oxidation process, and then removing the sacrificial oxide. Forming the sacrificial oxide can include exposing the silicon surface to an oxidizing environment (typically at high temperatures) to grow a thin layer of silicon dioxide (SiO2) on the trench surface. This sacrificial oxide layer helps repair the surface by consuming and passivating defects. Once the sacrificial oxide layer has been formed and the surface damage has been repaired, the sacrificial oxide layer itself can be removed. This can be done using a chemical etching process, which selectively removes the oxide without damaging the underlying silicon. A smoother, defect-free silicon surface is finally obtained, ready for the next step. The gate dielectric layer 16 can be formed by a thermal oxidation process, for example, by oxidizing the bottom and sidewalls of the gate trench 15.

[0051] According to another embodiment of this disclosure, the gate dielectric layer 16 can be formed by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate dielectric layer 16 may include a high-k material, an oxide, a nitride, an oxide oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium oxynitride, or a combination thereof. According to another embodiment of this disclosure, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium oxynitride, aluminum oxide, or a combination thereof.

[0052] According to another embodiment of this disclosure, the gate dielectric layer 16 can be formed by depositing a pad polysilicon layer and then subjecting the pad polysilicon layer to free radical oxidation.

[0053] According to another embodiment of this disclosure, the gate dielectric layer 16 can be formed by forming a pad silicon nitride layer and then subjecting the pad silicon nitride layer to free radical oxidation.

[0054] Subsequently, a buried word line 17 can be formed over the gate dielectric layer 16. The buried word line 17 can be formed by forming a conductive layer (not shown) to fill the gate trench 15 and then performing a recess process. Any suitable deposition process can be used to deposit conductive material to fill the gate trench 15, including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The recess process can be performed by an etch-back process or by sequentially performing a chemical mechanical polishing (CMP) process and an etch-back process. The buried word line 17 can have a recessed shape that partially fills the gate trench 15. The upper surface of the buried word line 17 can be disposed at a lower level than the upper surface of the active region 13. The buried word line 17 can include a semiconductor material, a metal, a metal nitride, or a combination thereof. For example, the buried word line 17 can be composed of titanium nitride (TiN), tungsten (W), or a titanium nitride / tungsten (TiN / W) stack. The titanium nitride / tungsten (TiN / W) stack can have a structure formed by conformally forming titanium nitride and then partially filling the gate trench 15 with tungsten. Titanium nitride can be used alone as a buried word line 17, which can be referred to as a "TiN-only" structure buried word line 17. A dual-gate structure of a titanium nitride / tungsten (TiN / W) stack and a polysilicon layer can also be used as a buried word line 17.

[0055] Subsequently, a gate capping layer 18 can be formed over the buried word line 17. The gate capping layer 18 may include a dielectric material. The remaining portion of the gate trench 15 above the buried word line 17 can be filled with the gate capping layer 18 by depositing the dielectric material using a suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). In one embodiment, the gate capping layer 18 may include silicon nitride. According to another embodiment of this disclosure, the gate capping layer 18 may include silicon oxide. According to yet another embodiment of this disclosure, the gate capping layer 18 may have a NON (nitride-oxide-nitride) structure. The upper surface of the gate capping layer 18 may be disposed at the same level as the upper surface of the hard mask layer 14. For this purpose, a chemical mechanical polishing (CMP) process can be performed when forming the gate capping layer 18.

[0056] After forming the gate capping layer 18, impurity regions 19 and 20 can be formed. Impurity regions 19 and 20 can be formed by a doping process (such as an implantation process). Impurity regions 19 and 20 can include a first impurity region 19 and a second impurity region 20. The first impurity region 19 and the second impurity region 20 can be doped with impurities of the same conductivity type. The first impurity region 19 and the second impurity region 20 can have the same depth. According to another embodiment of this disclosure, the first impurity region 19 can be deeper than the second impurity region 20. The first impurity region 19 and the second impurity region 20 can be referred to as source / drain regions. The first impurity region 19 can be a region to be coupled to a bit line contact plug, while the second impurity region 20 can be a region to be coupled to a memory contact plug. The first impurity region 19 and the second impurity region 20 can be disposed in different active regions 13. Furthermore, the first impurity region 19 and the second impurity region 20 can be spaced apart from each other by gate trenches 15 disposed in their respective active regions 13.

[0057] The cell transistor of the memory cell can be formed by buried word line 17 and first impurity region 19 and second impurity region 20.

[0058] refer to Figure 6 The sacrificial hard mask layer 21 can be formed, for example, over the buried word line structure (BWL) and the hard mask layer 14 by a deposition method. The sacrificial hard mask layer 21 may include silicon oxide, silicon nitride, or a combination thereof.

[0059] Mask pattern 22 may be formed on sacrificial hard mask layer 21. Mask pattern 22 may include a material with etching selectivity relative to sacrificial hard mask layer 21. Mask pattern 22 may include amorphous carbon, photoresist, silicon oxide, silicon nitride, or combinations thereof. Mask pattern 22 may include a plurality of mask level openings 22H. From a top view, mask level openings 22H may have a hole shape. The sidewalls 22S' of mask level openings 22H may have a tapered or ramp shape.

[0060] Subsequently, multiple etching processes can be performed to form bit line contact holes.

[0061] First, a first etching process can be performed. This first etching process can etch a portion of the sacrificial hard mask layer 21 by using mask pattern 22 as an etching barrier. The first etching process can be performed on the sacrificial hard mask layer 21, and can be a partial etching process that etches a portion of the sacrificial hard mask layer 21. An initial recessed opening 21H can be formed in a portion of the sacrificial hard mask layer 21 by the first etching process. The initial recessed opening 21H may not penetrate the sacrificial hard mask layer 21. From a top view, the initial recessed opening 21H can have a hole shape. The initial recessed opening 21H can be formed along the contour of the mask layer opening 22H. Therefore, the sidewall 21S' of the initial recessed opening 21H can have a conical or ramp shape.

[0062] refer to Figure 7 A second etching process involving isotropic etching can be performed. The second etching process can be performed on the sacrificial hard mask layer 21, and the second etching process can be a partial etching process that etches a portion of the sacrificial hard mask layer 21. Through the second etching process, a recessed opening 21V can be formed in a portion of the sacrificial hard mask layer 21. The recessed opening 21V may not penetrate the sacrificial hard mask layer 21. From a top view, the recessed opening 21V may have a hole shape. The recessed opening 21V may have a circular or elliptical cross-section. The recessed opening 21V may open along the mask layer level (…). Figure 6 The outline of the 22H in the middle is formed. Therefore, the sidewalls 21S of the recessed opening 21V can have a conical shape or a ramp shape. During the second etching process or before performing the second etching process, a portion of the mask pattern 22 can be etched. Therefore, the height of the mask pattern 22 can be reduced, but the sidewalls 22S of the mask layer opening 22H can have a conical shape or a ramp shape.

[0063] The recessed opening 21V may include a lower opening LH and an upper opening UH. The sidewalls of the lower opening LH may have a vertical shape, while the sidewalls of the upper opening UH may have a tapered or sloping shape. The lower opening LH and the upper opening UH may have the same height or different heights. The average diameter of the lower opening LH may be smaller than the average diameter of the upper opening UH. The shape of the recessed opening 21V may be described as a disk shape. The initial volume RH of the sacrificial hard mask layer 21 may be retained below the recessed opening 21V.

[0064] refer to Figure 8A third etching process can be performed. This third etching process forms bit line contact holes 23 in the active region 13. The third etching process for forming the bit line contact holes 23 may include: sequentially etching the initial volume RH of the sacrificial hard mask layer 21, the hard mask layer 14, and the isolation layer 12 using a mask pattern 22 as an etching barrier, and etching a portion of the active region 13. After the process of etching a portion of the active region 13, the mask pattern 22 and the sacrificial hard mask layer 21 can be consumed and are not retained.

[0065] A portion of the initial volume RH of the sacrificial hard mask layer 21, the hard mask layer 14, the isolation layer 12, and the active region 13 can be etched along the contours of the mask pattern 22 and the recessed opening 21V. Specifically, the contour of the recessed opening 21V can be transferred vertically downward to form the bit line contact hole 23.

[0066] The first to third etching processes described above can form a disk-shaped bit line contact hole 23. From a top view, the bit line contact hole 23 can be in the shape of a hole.

[0067] Bit line contact hole 23 may include a lower opening H1 and an upper opening H2. The sidewall of the lower opening H1 may have a vertical shape, while the sidewall 23 of the upper opening H2 may have a tapered or sloping shape. The height of the lower opening H1 may be less than the height of the upper opening H2. The average diameter of the lower opening H1 may be less than the average diameter of the upper opening H2. The diameter of the upper opening H2 may increase with increasing distance from the first impurity region. The shape of the bit line contact hole 23 may be described as a disk shape. The first impurity region 19 may be disposed below the bit line contact hole 23. During the formation of the bit line contact hole 23, a portion of the first impurity region 19 may be recessed. The upper portion of the upper opening H2 of the bit line contact hole 23 may be provided by a hard mask layer 14. The sidewall of the hard mask layer 14 may have a tapered or sloping shape.

[0068] refer to Figure 9 A plug layer 24A can be formed in the bit line contact hole 23. The plug layer 24A can be formed on the hard mask layer 14 and the buried word line structure BWL, and fill the bit line contact hole 23. The plug layer 24A may include a conductive material, such as polysilicon or doped polysilicon.

[0069] A bitline barrier layer 25A, a bitline conductive layer 26A, and a bitline hard mask layer 27A may be sequentially formed on the plug layer 24A. The bitline barrier layer 25A and the bitline conductive layer 26A may include a metallic material. The bitline barrier layer 25A and the bitline conductive layer 26A may include a metal, a metal nitride, a metal silicide, or a combination thereof. According to one embodiment of this disclosure, the bitline barrier layer 25A may include titanium nitride, while the bitline conductive layer 26A may include tungsten (W). The bitline hard mask layer 27A may include silicon oxide or silicon nitride. According to one embodiment of this disclosure, the bitline hard mask layer 27A may be formed of silicon nitride.

[0070] refer to Figure 10 A line structure, namely a bit line structure BL, can be formed, including a first conductive pattern. The bit line structure BL may include a stack of bit line contact plugs 24', bit line barriers 25, bit lines 26, and bit line hard masks 27. The bit line contact plugs 24', bit line barriers 25, bit lines 26, and bit line hard masks 27 can be formed by an etching process using a bit line mask layer (not shown). In the bit line structure BL, the first conductive pattern may include the bit line 26.

[0071] Bit line hard mask layer 27A, bit line conductive layer 26A, and bit line barrier layer 25A can be etched using the bit line mask layer (not shown) as an etching barrier. Thus, bit line barrier 25, bit line 26, and bit line hard mask 27 can be formed. Bit line hard mask 27 can be formed by etching bit line hard mask layer 27A. Bit line 26 can be formed by etching bit line conductive layer 26A. Bit line barrier 25 can be formed by etching bit line barrier layer 25A.

[0072] Subsequently, the plug layer 24A located below the bit line barrier 25 can be etched to form a bit line contact plug 24'. The bit line contact plug 24' can be formed on the first impurity region 19. The bit line contact plug 24' can interconnect the first impurity region 19 and the bit line barrier 25. The bit line contact plug 24' can be formed in the bit line contact hole 23. The average diameter of the bit line contact plug 24' can be smaller than the average diameter of the bit line contact hole 23. Therefore, a gap 24G can be defined in the peripheral region of the bit line contact plug 24'.

[0073] Bit line contact plug 24' may include an extension portion 24E, and the extension portion 24E of bit line contact plug 24' may be disposed in the upper part of hard mask layer 14. Therefore, bit line contact plug 24' may extend in the direction of bit line 26 extension and fill bit line contact hole 23.

[0074] The sidewall 24S of the bit line contact plug 24' can have a non-vertical shape. For example, the sidewall 24S of the bit line contact plug 24' can have a tapered or sloping shape. The bit line contact plug 24' can have different diameters depending on the height direction. For example, the diameter of the bottom 24B of the bit line contact plug 24' can be the largest, and this diameter can gradually decrease according to the height. The lower part of the gap 24G can be disposed in the peripheral region of the bottom 24B of the bit line contact plug 24'. The lower part of the gap 24G can extend to be disposed in the isolation layer 12.

[0075] refer to Figures 8 to 10 A gap 24G can be formed in the bit line contact hole 23 by forming a bit line contact plug 24'. This is because the bit line contact plug 24' is formed by etching to a diameter smaller than that of the bit line contact hole 23. The gap 24G may not form a surrounding shape around the bit line contact plug 24', but can be formed independently on the two sidewalls of the bit line contact plug 24'. Therefore, a bit line contact plug 24' and a pair of gaps 24G can be provided in the bit line contact hole 23, and the pair of gaps 24G can be separated by the bit line contact plug 24'. The bottom surface of the gap 24G can extend into the interior of the isolation layer 12. The bottom surface of the gap 24G can be positioned at a level lower than the recessed upper surface of the first impurity region 19. According to another embodiment of the present disclosure, from a top view, the gap 24G can have a surrounding shape around the bit line contact plug 24'.

[0076] The structure comprising the bitline contact plug 24', bitline barrier 25, bitline 26, and bitline hard mask 27 stacked in the aforementioned order can be referred to as the bitline structure BL. From a top view, the bitline structure BL can be a linear pattern structure extending along the second direction D2.

[0077] A linear opening SBL can be defined between adjacent bitline structures BL. The linear opening SBL can be parallel to the bitline structure BL. The upper surface of the hard mask layer 14 and the upper surface of the buried word line structure BWL can be exposed through the linear opening SBL.

[0078] refer to Figure 11A preliminary gap-filling layer 28A can be formed on both sidewalls of the bit line structure BL. The preliminary gap-filling layer 28A can be formed on the bit line structure BL and fill the gap 24G. The preliminary gap-filling layer 28A may include a dielectric material. The preliminary gap-filling layer 28A may include silicon nitride, silicon oxide, a low-k material, or a combination thereof. The low-k material may include SiBN, SiCO, SiCN, SiBCN, or a combination thereof. According to another embodiment of this disclosure, the preliminary gap-filling layer 28A may include a multilayer structure. For example, the preliminary gap-filling layer 28A may include: NKON, NKNAN, NKOK, NKOKN, NKAKN, KOK, or KAK multilayer structures, where N refers to silicon nitride; K refers to a low-k material; O refers to silicon oxide; and A refers to an air gap. According to another embodiment of this disclosure, the outermost material of the preliminary gap-filling layer 28A may include a low-k material.

[0079] A portion of the initial gap filler layer 28A can fill the bottom of the gap 24G, i.e., the peripheral area of ​​the bottom 24B of the bit line contact plug 24'. A portion of the initial gap filler layer 28A can cover the upper surface of the hard mask layer 14 and the upper surface of the buried word line structure BWL.

[0080] refer to Figure 12 The initial gap-filling layer 28A can be selectively recessed to form the gap-filling layer 28.

[0081] The side recessing process of the bit line contact plug 24' can be performed during or after the recessing process used to form the gap filler layer 28. As a result, the bit line contact plug 24 can be formed, and the sidewalls of the bit line contact plug 24 can have a stepped conical shape.

[0082] Bit line contact plug 24 may include an extension 24E, a bottom 24B, a middle portion 24M, and a top 24U. The extension 24E is a portion of the top 24U. The bottom 24B and middle portion 24M of the bit line contact plug 24 may include tapered sidewalls, while the top 24U of the bit line contact plug 24 may include vertical sidewalls. The stepped tapered shape may be defined by the sidewall profiles of the bottom 24B, middle portion 24M, and top 24U. In the bit line contact plug 24, the height of the bottom 24B may be greater than the height of the middle portion 24M, and the height of the top 24U may be greater than the height of the bottom 24B.

[0083] As described above, during the recessing process used to form the gap filling layer 28, the sidewalls of the bit line contact plug 24 can be recessed to ensure sufficient contact burial spaces W1 and W2.

[0084] As the linewidth of the middle portion 24M of the bit line contact plug 24 decreases, the contact resistance may increase. However, the increase in contact resistance is compensated for by increasing the linewidth of the bottom portion 24B to ensure sufficient volume. Specifically, as the necking linewidth of the middle portion 24M decreases during the side recess process, the contact resistance may increase. However, the increase in contact resistance is compensated for by increasing the linewidth of the bottom portion 24B to ensure sufficient volume.

[0085] refer to Figure 13 The spacer structure can be conformally formed on the gap filling layer 28 and the bit line structure BL. This spacer structure can be a two-layer structure of a first spacer layer 29A and a second spacer layer 29B. The first spacer layer 29A can be formed on the gap filling layer 28 and the bit line structure BL, while the second spacer layer 29B can be formed on the first spacer layer 29A. The first spacer layer 29A can be thinner than the second spacer layer 29B. The first spacer layer 29A and the second spacer layer 29B can include dielectric materials. The first spacer layer 29A and the second spacer layer 29B can include silicon nitride, silicon oxide, low-k materials, or combinations thereof. The low-k materials of the first spacer layer 29A and the second spacer layer 29B can include SiBN, SiCO, SiCN, SiBCN, or combinations thereof. The second spacer layer 29B can have a lower dielectric constant than the first spacer layer 29A. According to another embodiment of this disclosure, in addition to the double-layer structure of the first spacer layer 29A and the second spacer layer 29B, a multi-layer spacer structure consisting of three or more layers can also be formed. For example, the multi-layer spacer structure may include: NKN, KNN, KON, NOK, NKON, NKNAN, NKOK, NKOKN, NKAKN, KOK, or KAK, where N refers to silicon nitride; K refers to a low-k material; O refers to silicon oxide; and A refers to an air gap. According to another embodiment of this disclosure, the outermost layer material in the multi-layer spacer structure may include a low-k material.

[0086] refer to Figure 14 The plug isolation layer 30 can be formed on the first spacer layer 29A and the second spacer layer 29B between the bit line structure BL. Forming the plug isolation layer 30 may include depositing and etching a plug isolation material to form a plurality of pore-shaped openings 31 between the plug isolation layers 30.

[0087] The plug isolation layer 30 may include silicon nitride, silicon oxide, low-k materials, or combinations thereof. The low-k material of the plug isolation layer 30 may include SiBN, SiCO, SiCN, SiBCN, or combinations thereof.

[0088] After etching the first spacer layer 29A and the second spacer layer 29B below the aperture 31, the underlying material can be etched to self-align it with the spacer layers 29A and 29B. This creates a plurality of recessed regions 31' that expose portions of the active regions 13 located between the bit line structures BL. Anisotropic etching or a combination of anisotropic and isotropic etching can be used to form the recessed regions 31'. For example, anisotropic etching can be performed first to form the first spacer layer 29A and the second spacer layer 29B between the bit line structures BL, and then isotropic etching can be performed on a portion of the exposed active regions 13. According to another embodiment of this disclosure, isotropic etching can also be performed on the hard mask layer 14. A portion of the active regions 13, such as the second impurity region 20, can be partially exposed through the recessed regions 31'.

[0089] The recessed region 31' can extend into the interior of the substrate 11. When forming the recessed region 31', the isolation layer 12, the gate capping layer 18, and the second impurity region 20 can be recessed to a predetermined depth. The bottom surface of the recessed region 31' can be positioned at a level lower than the upper surface of the bit line contact plug 24. Alternatively, the bottom surface of the recessed region 31' can be positioned at a level higher than the bottom surface of the bit line contact plug 24. The aperture 31 and the recessed region 31' can be interconnected. The vertical structure of the aperture 31 and the recessed region 31' can be referred to as a "memory contact hole".

[0090] refer to Figure 15 A storage contact plug 32 can be formed to fill the orifice opening 31 and the recessed region 31'. The storage contact plug 32 may include a semiconductor material, such as doped polysilicon. The storage contact plug 32 can be formed by depositing a semiconductor material to fill the orifice opening 31 and the recessed region 31'.

[0091] According to the above embodiments of the present disclosure, a sufficient space S1 is formed between the bit line contact plug 24 and the storage contact plug 32, and thus current leakage can be prevented.

[0092] As the linewidth of the middle portion 24M of the bit line contact plug 24 decreases, the contact resistance may increase. However, the increase in contact resistance can be compensated for by increasing the linewidth of the bottom portion 24B to ensure sufficient volume.

[0093] Due to bit line contact plug ( Figure 10 The 24' section has a partial ramp profile during the etching process used to form the bit line contact plug, thus ensuring sufficient bottom space during subsequent side recessing processes (see [reference]). Figure 12 ).

[0094] Because the vertical height of the active region 13 where the memory contact plug 32 will land is protected during the etching process, the vertical spacing between the memory contact plug 32 and the bit line contact plug 24 can be adequately ensured.

[0095] The narrowing of the line width of the bit line contact plug 24 may be accompanied by an increase in contact resistance, which can be compensated for by increasing the volume by increasing the line width at the bottom.

[0096] Figures 16 to 19 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0097] First, by executing Figures 3 to 13 The series of processes shown can form a first spacer layer 29A and a second spacer layer 29B on the bit line structure BL.

[0098] refer to Figure 16 After etching the first spacer layer 29A and the second spacer layer 29B located below the linear opening SBL, the underlying material can be etched to self-align it with the first spacer layer 29A and the second spacer layer 29B. As a result, a plurality of recessed regions 31' can be formed, exposing a portion of the active region 13 located between the bit line structures BL. The recessed regions 31' can be formed using anisotropic etching or a combination of anisotropic and isotropic etching. For example, anisotropic etching can be performed to form the first spacer layer 29A and the second spacer layer 29B between the bit line structures BL, and then a portion of the exposed active region 13 can be isotropically etched. According to another embodiment of this disclosure, isotropic etching can also be performed on the hard mask layer 14. A portion of the active region 13 can be exposed through the recessed regions 31'.

[0099] refer to Figure 17 Line pattern 32A can be formed over the first spacer layer 29A and the second spacer layer 29B to fill each linear opening SBL between the bit line structures BL. Line pattern 32A can fill the linear opening SBL and the recessed region 31'. Line pattern 32A can contact the second impurity region 20. Line pattern 32A can be adjacent to the bit line structure BL. From a top view, multiple line patterns 32A can be disposed between the bit line structures BL. Line pattern 32A can include a semiconductor material, such as doped polysilicon.

[0100] refer to Figure 18The line pattern 32A can be etched using a mask layer extending in a direction intersecting with the line pattern 32A. Therefore, a plurality of memory contact plugs 32 and a plurality of isolation vias 31A can be formed. From a top view, the plurality of memory contact plugs 32 can be disposed between adjacent bit line structures BL, and the isolation vias 31A can be disposed between the memory contact plugs 32. The memory contact plugs 32 can be referred to as a second conductive pattern structure.

[0101] refer to Figure 19 A plug isolation layer 30A can be formed to fill the isolation orifice 31A. Forming the plug isolation layer 30A may include depositing and etching a plug isolation material. A plurality of storage contact plugs 32 may be formed between the plug isolation layers 30A.

[0102] The plug isolation layer 30A may include silicon nitride, silicon oxide, low-k materials, or combinations thereof. The low-k material of the plug isolation layer 30A may include SiBN, SiCO, SiCN, SiBCN, or combinations thereof.

[0103] Figures 20 to 23 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. Figures 20 to 23 It shows the basis Figure 1A A cross-sectional view of the manufacturing method of line A-A' shown.

[0104] First, it is possible to execute as follows: Figures 3 to 7 The illustrated series of processes includes a first etching process and a second etching process. According to this embodiment of the present disclosure, a low-k barrier layer LK, such as SiOC, can be formed on the isolation layer 12. The low-k barrier layer LK can prevent leakage current in the peripheral area of ​​the bit line contact plug.

[0105] Subsequently, reference Figure 20 Buffer spacers BF can be formed on the sacrificial hard mask layer 21 and mask pattern 22. Buffer spacers BF can be formed by depositing and etching silicon nitride.

[0106] refer to Figure 21 A third etching process can be performed. This third etching process forms bit line contact holes 23 in the active region 13. The third etching process for forming the bit line contact holes 23 may include: sequentially etching the sacrificial hard mask layer 21, the hard mask layer 14, and the isolation layer 12 using a mask pattern 22 and a buffer spacer BF as etching barriers; and etching a portion of the active region 13. After the etching of a portion of the active region 13, the mask pattern 22 and the sacrificial hard mask layer 21 can be consumed and are not retained.

[0107] The sacrificial hard mask layer 21, hard mask layer 14, isolation layer 12, and a portion of the active region 13 can be etched along the contour of the buffer spacer BF. Because the etching process is performed along the contour of the buffer spacer BF, a narrower bit line contact hole 23 can be formed.

[0108] The disk-shaped bit line contact hole 23 can be formed through the first to third etching processes described above. From a top view, the bit line contact hole 23 can be in the shape of a hole.

[0109] Let's refer to each other. Figure 8 and Figure 21 The bitline contact hole 23 may include a lower opening H1 and an upper opening H2. The sidewall of the lower opening H1 may have a vertical shape, while the sidewall 23S of the upper opening H2 may have a tapered or sloping shape. The height of the lower opening H1 may be less than the height of the upper opening H2. The average diameter of the lower opening H1 may be less than the average diameter of the upper opening H2. The shape of the bitline contact hole 23 may be described as a disk shape. A first impurity region 19 may be provided below the bitline contact hole 23. When forming the bitline contact hole 23, a portion of the first impurity region 19 may be recessed. The upper part of the upper opening H2 of the bitline contact hole 23 may be provided by a hard mask layer 14. The sidewall of the hard mask layer 14 may have a tapered or sloping shape.

[0110] refer to Figure 22 The plug layer 24A can be formed on the hard mask layer 14 and the buried word line structure BWL, and fill the bit line contact via 23. For example, the plug layer 24A can include polysilicon.

[0111] Bit line barrier layer 25A, bit line conductive layer 26A, and bit line hard mask layer 27A may be sequentially formed on plug layer 24A. Bit line barrier layer 25A and bit line conductive layer 26A may include a metal-containing material. Bit line barrier layer 25A and bit line conductive layer 26A may include a metal, a metal nitride, a metal silicide, or a combination thereof. According to one embodiment of this disclosure, bit line barrier layer 25A may include titanium nitride, while bit line conductive layer 26A may include tungsten (W). Bit line hard mask layer 27A may include silicon oxide or silicon nitride. According to one embodiment of this disclosure, bit line hard mask layer 27A may be formed of silicon nitride.

[0112] refer to Figure 23 A line structure, namely a bit line structure BL, can be formed, including a first conductive pattern. Linear openings SBL can be defined between adjacent bit line structures BL. Linear openings SBL can be parallel to the bit line structures BL. The upper surface of the hard mask layer 14 and the upper surface of the buried word line structure BWL can be exposed through the linear openings SBL.

[0113] The bitline structure BL may include a stack of bitline contact plugs 24, bitline barriers 25, bitlines 26, and bitline hard masks 27. The bitline contact plugs 24, bitline barriers 25, bitlines 26, and bitline hard masks 27 may be formed using an etching process employing a bitline mask layer (not shown). In the bitline structure BL, a first conductive pattern may include the bitline 26.

[0114] The bitline hard mask layer 27A, the bitline conductive layer 26A, and the bitline barrier layer 25A can be etched using a bitline mask layer (not shown) as an etch barrier. Therefore, bitline barrier 25, bitline 26, and bitline hard mask 27 can be formed. The bitline hard mask 27 can be formed by etching the bitline hard mask layer 27A. The bitline 26 can be formed by etching the bitline conductive layer 26A. The bitline barrier 25 can be formed by etching the bitline barrier layer 25A.

[0115] Subsequently, the plug layer 24A located below the bit line barrier 25 can be etched. Thus, a bit line contact plug 24' can be formed. The bit line contact plug 24' can be formed on the first impurity region 19. The bit line contact plug 24' can interconnect the first impurity region 19 and the bit line barrier 25. The bit line contact plug 24' can be formed in the bit line contact hole 23. The average diameter of the bit line contact plug 24' can be smaller than the average diameter of the bit line contact hole 23. Therefore, a gap 24G can be defined in the peripheral region of the bit line contact plug 24'.

[0116] Bit line contact plug 24' may include an extension 24E, and the extension 24E may be disposed in the upper part of the hard mask layer 14. Therefore, the bit line contact plug 24' may extend in the direction of the bit line 26 and fill the bit line contact hole 23.

[0117] The sidewall 24S of the bit line contact plug 24' can have a non-perpendicular shape. For example, the sidewall 24S of the bit line contact plug 24' can have a tapered or sloping shape. The bit line contact plug 24' can have different diameters depending on the height direction. For example, the diameter of the bottom 24B of the bit line contact plug 24' can be the largest, and the diameter can gradually decrease according to the height. The lower part of the gap 24G can be located in the peripheral region of the bottom 24B of the bit line contact plug 24'.

[0118] A landing portion 24R can also be formed above the bottom 24B of the bit line contact plug 24'. The bottom 24B and the landing portion 24R can each have a disk shape and can be perpendicular to each other. The combination of the bottom 24B and the landing portion 24R can define six inflection points.

[0119] As described above, a gap 24G can be formed in the bit line contact hole 21 by forming a bit line contact plug 24'. This is because the bit line contact plug 24' is formed by etching to have a diameter smaller than the diameter of the bit line contact hole 23. The gap 24G may not have a surrounding shape around the bit line contact plug 24', but may be formed independently on the two sidewalls of the bit line contact plug 24'. After all, a bit line contact plug 24' and a pair of gaps 24G can be disposed in the bit line contact hole 23, and the pair of gaps 24G can be separated by the bit line contact plug 24'. The bottom surface of the gap 24G may extend into the interior of the isolation layer 12. The bottom surface of the gap 24G may be disposed at a level lower than the recessed ground surface of the first impurity region 19. According to another embodiment of the present disclosure, from a top view, the gap 24G may have a surrounding shape around the bit line contact plug 24'.

[0120] The structure comprising bitline contact plugs 24', bitline barriers 25, bitlines 26, and bitline hard masks 27 stacked in the aforementioned order can be referred to as a bitline structure BL. From a top view, the bitline structure BL can be a linear pattern structure extending along the second direction D2.

[0121] A linear opening SBL can be defined between adjacent bitline structures BL. The linear opening SBL can be parallel to the bitline structure BL. The upper surface of the hard mask layer 14 and the upper surface of the buried word line structure BWL can be exposed through the linear opening SBL.

[0122] Then, it can be executed. Figures 11 to 19 The series of processes shown.

[0123] According to one embodiment of this disclosure, current leakage can be prevented because the gap between the bit line contact plug and the storage contact plug is sufficient.

[0124] According to one embodiment of this disclosure, the increase in contact resistance can be compensated by increasing the line width at the bottom of the bit line contact plug.

[0125] Although this disclosure has been described in conjunction with specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of this disclosure as defined in the claims. Furthermore, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A first contact structure is disposed on a substrate, and the first contact structure has multi-conical sidewalls; A wire structure, which includes a conductor disposed on the first contact structure; as well as Multiple second contact structures are disposed between the line structures.

2. The semiconductor device according to claim 1, in, The first contact structure has a multi-conical sidewall with at least one inflection point, at which the slope of the multi-conical sidewall changes. The at least one inflection point is located at a level higher than the bottom surface of the second contact structure.

3. The semiconductor device according to claim 1, in, The first contact structure contacts the substrate. The first contact structure includes a lower buried portion and an upper buried portion, and The width of the upper burial portion is smaller than the width of the lower burial portion.

4. The semiconductor device according to claim 1, wherein, The first contact structure includes: The bottom surface contacts the upper surface of the substrate and has a first tapered sidewall; The middle section, which is situated above the bottom and has a second conical sidewall; and The top is positioned above the middle section and has vertical sidewalls.

5. The semiconductor device according to claim 4, wherein, The slope of the first conical sidewall is different from the slope of the second conical sidewall.

6. The semiconductor device according to claim 4, wherein, The slope of the second conical sidewall is closer to 90° than the slope of the first conical sidewall.

7. The semiconductor device according to claim 4, wherein, The first inflection point between the first conical sidewall and the second conical sidewall is located at a level higher than the bottom surface of the second contact structure.

8. The semiconductor device according to claim 7, wherein, The second inflection point between the second conical sidewall and the vertical sidewall is located at a level higher than the bottom surface of the second contact structure and the first inflection point.

9. A semiconductor device, comprising: The first impurity region is disposed in the substrate; A second impurity region is disposed in the substrate and spaced apart from the first impurity region; The bit line contact plug is disposed above the first impurity region and has multi-conical sidewalls; as well as A storage contact plug is disposed above the second impurity region. The multi-conical sidewall of the bit-line contact plug includes at least one inflection point, at which the slope changes. The at least one inflection point is configured to be higher than the bottom surface of the storage contact plug.

10. The semiconductor device according to claim 9, in, The first contact structure contacts the substrate. The first contact structure includes a lower buried portion and an upper buried portion, and The width of the upper burial portion is smaller than the width of the lower burial portion.

11. The semiconductor device according to claim 9, wherein, The bit line contact plug includes: The bottom surface contacts the upper surface of the substrate and has a first tapered sidewall; The middle section, which is formed above the bottom and has a second conical sidewall; and The top is formed above the middle and has vertical sidewalls.

12. The semiconductor device according to claim 11, wherein, The slope of the first conical sidewall is different from the slope of the second conical sidewall.

13. The semiconductor device according to claim 11, wherein, The slope of the second conical sidewall is closer to 90° than the slope of the first conical sidewall.

14. The semiconductor device according to claim 11, wherein, The first inflection point between the first tapered sidewall and the second tapered sidewall is located at a level higher than the bottom surface of the storage contact plug.

15. The semiconductor device according to claim 14, wherein, The second inflection point between the second conical sidewall and the vertical sidewall is located at a level higher than the bottom surface of the second contact structure and the first inflection point.

16. A method for manufacturing a semiconductor device, the method comprising: A first impurity region and a second impurity region are formed in the substrate; A bit line contact hole is formed that exposes the first impurity region and has multi-conical sidewalls; A bit line contact plug is formed, the bit line contact plug fills the bit line contact hole, and includes a lower buried portion and an upper buried portion, the lower buried portion contacting the first impurity region, and the upper buried portion being located above the lower buried portion; A gap-filling layer is formed in the peripheral region of the lower buried portion of the bit line contact plug; The sidewall of the upper buried portion of the bit line contacting the plug is recessed; as well as A storage contact plug is formed that contacts the second impurity region.

17. The method according to claim 16, wherein, The bit line contact hole, which exposes the first impurity region and has the multi-conical sidewalls, comprises: A sacrificial hard mask layer is formed on the substrate; A mask pattern with mask layer openings is formed on the sacrificial hard mask layer; Perform a first etching process, wherein the first etching process is to form a recessed opening with tapered sidewalls in a portion of the sacrificial hard mask layer; Perform a second etching process, wherein the second etching process transforms the recessed opening into a disc-shaped recessed opening; and A third etching process is performed, wherein the disk-shaped recessed opening is transferred to the substrate.

18. The method according to claim 17, wherein, The second etching process includes isotropic etching.

19. The method of claim 16, wherein, The bit line contact plug includes: The bottom surface contacts the upper surface of the substrate and has a first tapered sidewall; The middle section, which is formed above the bottom and has a second conical sidewall; and The top, which is formed above the middle section and has vertical sidewalls, The slope of the second conical sidewall is closer to 90° than the slope of the first conical sidewall.

20. The method according to claim 19, wherein, The first inflection point between the first conical sidewall and the second conical sidewall is located at a level higher than the bottom surface of the storage contact plug, and The second inflection point between the second tapered sidewall and the vertical sidewall is located at a level higher than the bottom surface of the storage contact plug and the first inflection point.

21. The method of claim 17, further comprising: After performing the second etching process A buffer spacer is formed above the disc-shaped recessed opening.

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