HEMT device manufacturing method and HEMT device thereof
By using photolithography to mark the gate region and fill it with gate metal B, which has lower resistivity, the problem of increased gate resistance was solved, resulting in a smaller gate window and lower resistivity, simplifying the process and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-12
- Publication Date
- 2026-03-31
AI Technical Summary
In the prior art, as the gate length of the device decreases, the gate metal resistance becomes increasingly higher, and it becomes difficult to define a window of the same width for the gate metal by photolithography, making it impossible to effectively reduce the gate resistance.
By marking the gate region on the gate layer structure using photolithography, removing the gate layer structure outside the gate region to form the gate structure, and filling the gate structure with gate metal B with lower resistivity, the problem of being unable to etch a smaller gate window due to limitations in photolithography is solved.
This effectively reduces the gate resistance of GaN devices, simplifies the manufacturing process, and lowers costs.
Smart Images
Figure CN121772252A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a method for manufacturing a HEMT device and the HEMT device thereof. Background Technology
[0002] As market demands for smaller size and higher energy efficiency in power devices increase, wide-bandgap GaN devices, due to their lower power loss and faster switching capabilities, have been widely used in high-frequency power conversion systems. Compared to silicon metal-oxide-semiconductor field-effect transistors (MOSFETs), GaN high electron mobility transistors (HEMTs) offer better quality factors and more promising performance in high-power and high-frequency applications.
[0003] As device resistance decreases and area increases, reducing the resistance of the gate metal to reduce the delay in electrical signal transmission becomes crucial.
[0004] Forming a metal gate typically involves depositing a gate metal layer, etching to define the gate region, and then photolithographically creating a window of the same width as the gate metal, within which a dock or other interconnect metal is deposited. However, as the gate length of a device decreases, the resistance of the gate metal increases significantly, and defining a window of the same width as the gate metal via photolithography becomes extremely difficult, making it impossible to directly thicken the metal on top of the gate metal.
[0005] Therefore, we propose a method for manufacturing HEMT devices and the HEMT device thereof. Summary of the Invention
[0006] The purpose of this invention is to provide a method for manufacturing HEMT devices and a HEMT device thereof, so as to solve the above-mentioned problems.
[0007] To achieve the above objectives, the present invention provides the following solution: A method for manufacturing an HEMT device, comprising: Set the underlying structure; A grid structure is laid on the underlying structure; The gate region is marked on the gate layer structure using a photolithography process; the gate layer structure outside the gate region is removed using an etching process to form a gate structure, and a portion of the upper surface of the underlying structure is exposed. The gate structure contains a gate metal A; A material layer is provided such that the material layer covers the exposed upper surface of the underlying structure and the upper surface of the gate structure; Removing part of the material layer exposes the upper surface of the gate structure; The etching rate at the top of the gate structure is greater than the etching rate of the material layer. Remove the top of the gate structure to form an opening and expose the gate metal A; Gate metal B is filled into the opening so that gate metal B is in contact with gate metal A; gate metal A and gate metal B reduce the resistivity of the gate structure; the resistivity of gate metal B is less than the resistivity of gate metal A. Cover with a passivation layer and set source / drain interconnect metals and gate interconnect metals; Connect the gate interconnect metal to the gate metal B.
[0008] Optionally, the underlying structure includes a source / drain metal for connection with the source / drain interconnect metal, one end of the source / drain metal is connected to the source / drain interconnect metal, and the other end of the source / drain metal is connected to a barrier layer, which is disposed within the underlying structure.
[0009] Optionally, the underlying structure includes a substrate layer group, which includes a substrate portion located at the bottom layer and a channel layer located at the top layer, with the barrier layer laid on top of the channel layer.
[0010] Optionally, the band gap layer of the channel layer is smaller than the band gap layer of the barrier layer.
[0011] Optionally, the substrate portion includes a substrate at the bottom and a buffer layer at the top, the buffer layer being connected to the channel layer and located between the substrate and the channel layer.
[0012] Optionally, the substrate is one of a silicon substrate, a sapphire substrate, a silicon carbide substrate, an aluminum nitride substrate, or silicon on an insulating substrate.
[0013] Optionally, a first dielectric layer is disposed above the gate metal A, and the etching rate of the first dielectric layer is greater than the etching rate of the material layer; The opening is formed after the first dielectric layer is removed.
[0014] Optionally, the gate metal A is TiN.
[0015] Optionally, the gate metal B is either tungsten or aluminum.
[0016] A HEMT device is prepared by the above-described HEMT device manufacturing method.
[0017] Compared with the prior art, the present invention has the following advantages and technical effects: This invention marks the gate region on the gate layer structure using photolithography, removes the gate layer structure outside the gate region to form the gate structure, thereby defining the window of the gate metal B, and then directly deposits the gate metal B. This solves the problem in the prior art that the photolithography process cannot etch a smaller gate window; moreover, the process is simple and reduces the process cost; at the same time, the gate metal B deposited in the second step has a lower resistivity than the gate metal A, thereby effectively reducing the gate resistance of the GaN device. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Figure 1 This is a process flow diagram of the present invention; Figures 2 to 11 This is a structural diagram of each step in Embodiment 1 of the present invention; Figures 12 to 21 This is a structural diagram of each step in Embodiment 1 of the present invention; Among them, 101, substrate one; 102, buffer layer one; 103, channel layer one; 104, barrier layer one; 105, gate layer; 106, gate metal A one; 107, first dielectric layer A; 108, second material layer; 109, source / drain metal one; 110, first material layer; 111, second dielectric layer; 112, gate metal B one; 113, source / drain interconnect metal one; 114, gate interconnect metal one; 118, passivation layer one; 2001, first metal material; 2002, first dielectric material; 5001, doped nitride 201, Substrate II; 202, Buffer Layer II; 203, Channel Layer II; 204, Barrier Layer II; 205, Fourth Dielectric Material; 206, Source / Drain Metal II; 207, Sixth Dielectric Material; 208, Gate Dielectric Layer; 209, Third Metal Material; 210, First Dielectric Layer B; 211, Gate Metal A II; 212, Gate Metal B II; 213, Source / Drain Interconnect Metal II; 214, Gate Interconnect Metal II; 215, Passivation Layer II; 218, Third Dielectric Layer; 4001, Capping Layer; 300, Seventh Dielectric Material. Detailed Implementation
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0021] Example 1: refer to Figure 1 This invention discloses a method for manufacturing a HEMT device, comprising: Set the underlying structure; Lay a grid structure on the underlying structure; The gate region is marked on the gate layer structure using photolithography; the gate layer structure outside the gate region is removed using etching to form the gate structure, and the upper surface of part of the underlying structure is exposed. The gate structure contains a gate metal A; A material layer is provided to cover the upper surface of the exposed underlying structure and the upper surface of the gate structure; Removing part of the material layer exposes the upper surface of the gate structure; Among them, the etching rate at the top of the gate structure is greater than the etching rate of the material layer; Remove the top of the gate structure to form an opening and expose the gate metal A; Gate metal B is filled into the opening so that gate metal B is in contact with gate metal A; gate metal A and gate metal B reduce the resistivity of the gate structure; the resistivity of gate metal B is less than that of gate metal A. Cover with a passivation layer and set source / drain interconnect metals and gate interconnect metals; Connect the gate interconnect metal to the gate metal B.
[0022] This invention marks the gate region on the gate layer structure using photolithography, removes the gate layer structure outside the gate region to form the gate structure, thereby defining the window of the gate metal B, and then directly deposits the gate metal B. This solves the problem in the prior art that the photolithography process cannot etch a smaller gate window; moreover, the process is simple and reduces the process cost; at the same time, the gate metal B deposited in the second step has a lower resistivity than the gate metal A, thereby effectively reducing the gate resistance of the GaN device.
[0023] As an optional implementation, the underlying structure includes a source / drain electrode metal for connection with the source / drain interconnect metal. One end of the source / drain electrode metal is connected to the source / drain interconnect metal, and the other end of the source / drain electrode metal is connected to a barrier layer, which is disposed within the underlying structure.
[0024] As an optional implementation, the underlying structure includes a substrate layer group, which includes a substrate portion located at the bottom layer and a channel layer located at the top layer, with a barrier layer laid on top of the channel layer.
[0025] As an alternative implementation, the band gap of the channel layer is smaller than that of the barrier layer.
[0026] As an alternative implementation, the substrate includes a substrate at the bottom and a buffer layer at the top, the buffer layer being connected to the channel layer and located between the substrate and the channel layer.
[0027] As an alternative implementation, the substrate is one of a silicon substrate, a sapphire substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a silicon SOI on an insulating substrate.
[0028] As an optional implementation, a first dielectric layer is disposed above the gate metal A, and the etching rate of the first dielectric layer is greater than the etching rate of the material layer; An opening is formed after the first dielectric layer is removed.
[0029] As an optional implementation, the gate metal A is TiN.
[0030] As an alternative implementation, the gate metal B is either tungsten or aluminum.
[0031] A HEMT device is prepared by the above-described HEMT device manufacturing method.
[0032] Example 2: refer to Figures 2 to 11 This embodiment describes the fabrication of one type of HEMT device using the above method. The specific manufacturing process includes the following steps: The basal layer, the channel layer 103 located on the basal layer, and the barrier layer 104 located on the channel layer 103 are grown sequentially.
[0033] The channel layer 103 has a (relatively) small band gap (e.g., a GaN semiconductor layer), and the barrier layer 104 has a (relatively) large band gap (e.g., an AlGaN semiconductor layer). A two-dimensional electron gas is formed at the interface between the channel layer 103 and the first barrier layer 104, specifically at the top of the channel layer 103.
[0034] The substrate layer includes a substrate 101. In an optional embodiment, the substrate layer includes a substrate 101 and a buffer layer 102. The buffer layer 102 is disposed between the substrate 101 and the channel layer 103 to reduce the problem of lattice mismatch between the substrate 101 and the channel layer 103.
[0035] Substrate 101 can be a silicon substrate, a sapphire substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or silicon on an insulating substrate (SOI), etc.
[0036] Furthermore, a doped nitride layer 5001 is formed on the barrier layer 104.
[0037] In subsequent processes, the doped nitride layer 5001 is partially etched, and the portion remaining in the barrier layer 104 is the gate layer 105.
[0038] Among them, the doped nitride layer 5001 includes P-type GaN material.
[0039] A first metal material 2001 is covered on the upper surface of the doped nitride layer 5001, and a first dielectric material 2002 is covered on the upper surface of the first metal material 2001.
[0040] Partial etching of the first dielectric material 2002, the first metal material 2001, and the doped nitride layer 5001, and etching of the remaining portion to form the first dielectric layer A107, the gate metal A-106, and the gate layer 105 from top to bottom.
[0041] In this embodiment, the first dielectric layer A107, the gate metal A-106, and the gate layer 105 constitute a gate structure.
[0042] Specifically, the gate region is defined using photolithography. First, the first dielectric material 2002 is partially etched to form the first dielectric layer A107. Then, using the first dielectric layer A107 as a mask, the first metal material 2001 and the doped nitride layer 5001 are etched sequentially to form the gate metal A-106 and the gate layer 105.
[0043] Further, a second material layer 108 is covered on the upper surface of the barrier layer 104 and the upper surface of the first dielectric layer A107. Then, a second opening is formed in the second material layer 108 to partially expose the upper surface of the barrier layer 104, and a source / drain metal 109 is formed in the second opening. The source / drain metal 109 is preferably Ti metal or its alloy. Then, a third material layer is covered on the source / drain metal 109 and the second material layer 108. The second material layer 108 and the third material layer together form the first material layer 110. Finally, the first material layer 110 on the first dielectric layer A107 is removed by etching, and the upper surface of the first material layer 110 is planarized by chemical mechanical polishing, so that the remaining first material layer 110 exposes the upper surface of the first dielectric layer A107. The remaining first material layer 110 is set as the second dielectric layer 111. The upper surface of the source / drain metal 109 is lower than the upper surface of the first dielectric layer A107.
[0044] In this embodiment, the underlying structure is composed of a substrate 101, a buffer layer 102, a channel layer 103, a barrier layer 104, and source / drain metals 109.
[0045] The first dielectric layer A107 is removed using a wet or dry etching process, while the second dielectric layer 111 is preserved. The etching rates of the first dielectric layer A107 and the second dielectric layer 111 are different, with the etching rate of the first dielectric layer A107 being greater than that of the second dielectric layer 111.
[0046] In this embodiment, the top and bottom widths of the opening are basically the same.
[0047] Furthermore, a gate metal B-112 is formed using a deposition process. The gate metal B-112 fills the opening.
[0048] Among them, the resistivity of gate metal B-112 is less than that of gate metal A-106.
[0049] An exemplary material for gate metal A-106 is TiN, and an exemplary material for gate metal B-112 is tungsten or aluminum.
[0050] Furthermore, a passivation layer 118 is covered on the upper surface of the second dielectric layer 111 and the gate metal B-112, which further includes an opening on the passivation layer 118 that exposes the upper surface of the gate metal B-112, and an opening through the passivation layer 118 and part of the second dielectric layer 111 that exposes the upper surface of the source-drain metal-109; a gate interconnect metal-114 and a source-drain interconnect metal-113 are formed in the openings, respectively.
[0051] Gate interconnect metal B-114 is connected to gate metal B-112; The source-drain interconnect metal 113 is connected to the source-drain electrode metal 109.
[0052] Example 3: refer to Figures 12 to 21 This embodiment describes another type of HEMT device prepared according to the above method. Its manufacturing process specifically includes the following steps: First, a substrate layer, a second channel layer 203 on the substrate layer, and a second barrier layer 204 on the channel layer 203 are grown sequentially. The second channel layer 203 has a (relatively) small band gap (e.g., a GaN semiconductor layer), and the second barrier layer 204 has a (relatively) large band gap (e.g., an AlGaN semiconductor layer). A two-dimensional electron gas is formed at the interface between the second channel layer 203 and the second barrier layer 204, specifically at the top of the second channel layer 203. The substrate layer includes a second substrate 201. In an optional embodiment, the substrate layer includes a second substrate 201 and a second buffer layer 202, which is disposed between the second substrate 201 and the second channel layer 203 to reduce the problem of lattice mismatch between the second substrate 201 and the second channel layer 203. Substrate 201 can be a silicon substrate, a sapphire substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or silicon (SOI) on an insulating substrate, etc.
[0053] In this embodiment, a capping layer 4001 may also be included on the second barrier layer 204. The capping layer 4001 is used to protect the surface of the second barrier layer 204 to prevent the second barrier layer 204 from oxidizing.
[0054] Further, a fourth dielectric material 205 is formed on the capping layer 4001, and then a portion of the fourth dielectric material 205 is etched to expose a portion of the upper surface of the capping layer 4001. Then, using the fourth dielectric material 205 as a mask layer, the capping layer is etched again to form an opening that exposes the upper surface of the second barrier layer 204.
[0055] Furthermore, a source / drain metal 206 is formed in the opening. Preferably, a deposition process is used to deposit the metal in the opening. The metal is preferably Ti metal and its alloys.
[0056] Then, a fifth dielectric material is formed covering the upper surface of the source / drain metal 206 and the fourth dielectric material 205. Preferably, the fourth dielectric material 205 is made of the same material as the fifth dielectric material. The fifth dielectric material and the fourth dielectric material 205 together form a sixth dielectric material 207.
[0057] The sixth dielectric material 207 is etched to form an opening on the upper surface of the capping layer 4001, wherein the opening is disposed between the two source and drain metals 206 and is separated from the two source and drain metals 206.
[0058] First, a gate dielectric layer 208 is formed on the inner surface of the opening and the upper surface of the sixth dielectric material 207. Then, a third metal material 209 is deposited on the gate dielectric layer 208, completely filling the opening and extending above it, and located on the sixth dielectric material 207. Finally, a seventh dielectric material 300 is formed on the third metal material 209. The gate dielectric layer 208 and the sixth dielectric material 207 are made of different materials.
[0059] In this embodiment, the underlying structure is composed of substrate 201, buffer layer 202, channel layer 203, barrier layer 204, source / drain metal 206, and gate dielectric layer 208.
[0060] Specifically, the seventh dielectric material 300 and the third metal material 209 are partially etched to form the first dielectric layer B210 and the gate metal A211. The gate metal A211 and the first dielectric layer B210 expose the upper surfaces of the gate dielectric layer 208 on both sides of the opening. Specifically, the third metal material 209 is etched using the first dielectric layer B210 as a mask to form the gate metal A211.
[0061] In this embodiment, a gate structure is formed by a first dielectric layer B210 and a gate metal A211.
[0062] A third dielectric layer 218 is formed covering the side surfaces of the gate metal A211 and the first dielectric layer B210. The third dielectric layer 218 covers the exposed upper surface of the gate dielectric layer 208 and the side surfaces of the gate metal A211 and the first dielectric layer B210, and exposes the upper surface of the first dielectric layer B210. The second dielectric layer comprises a sixth dielectric material 207 and the third dielectric layer 218.
[0063] The first dielectric layer B210 is removed to form an opening on the upper surface of the gate metal A211. Specifically, the first dielectric layer B210 is removed by wet or dry etching while the third dielectric layer 218 is retained. The etching rates of the first dielectric layer B210 and the third dielectric layer 218 are different, with the etching rate of the first dielectric layer B210 being greater than that of the third dielectric layer 218.
[0064] Gate metal B212 is formed in the opening. Specifically, metal is deposited on the opening and the third dielectric layer 218, and then the metal on the upper surface of the third dielectric layer 218 is removed to form gate metal B212, such that the upper surface of gate metal B212 is flush with the upper surface of the third dielectric layer 218.
[0065] Furthermore, it also includes a passivation layer 215 forming an upper surface covering the third dielectric layer 218 and the gate metal B 212, wherein it also includes a first opening that passes through the passivation layer 215, the third dielectric layer 218 and a portion of the sixth dielectric material 207 and exposes a portion of the upper surface of the source and drain metals, and a second opening that passes through the passivation layer 215 and exposes a portion of the upper surface of the gate metal B 212; a source and drain interconnect metal 213 and a gate interconnect metal 214 are formed in the first opening and the second opening, respectively.
[0066] In the description of this invention, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this invention, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.
[0067] The above embodiments are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.
Claims
1. A method for manufacturing a HEMT device, characterized in that, include: Set the underlying structure; A grid structure is laid on the underlying structure; The gate region is marked on the gate layer structure using photolithography. The gate layer structure outside the gate region is removed using an etching process to form a gate structure, and a portion of the upper surface of the underlying structure is exposed. The gate structure contains a gate metal A; A material layer is provided such that the material layer covers the exposed upper surface of the underlying structure and the upper surface of the gate structure; Removing part of the material layer exposes the upper surface of the gate structure; The etching rate at the top of the gate structure is greater than the etching rate of the material layer. Remove the top of the gate structure to form an opening and expose the gate metal A; Gate metal B is filled into the opening so that gate metal B is in contact with gate metal A; gate metal A and gate metal B reduce the resistivity of the gate structure; the resistivity of gate metal B is less than the resistivity of gate metal A. Cover with a passivation layer and set source / drain interconnect metals and gate interconnect metals; Connect the gate interconnect metal to the gate metal B.
2. The method for manufacturing a HEMT device according to claim 1, characterized in that, The underlying structure includes a source / drain metal for connection with the source / drain interconnect metal. One end of the source / drain metal is connected to the source / drain interconnect metal, and the other end of the source / drain metal is connected to a barrier layer. The barrier layer is disposed within the underlying structure.
3. The method for manufacturing a HEMT device according to claim 2, characterized in that: The underlying structure includes a substrate layer group, which includes a substrate portion at the bottom layer and a channel layer at the top layer, with the barrier layer laid on top of the channel layer.
4. The HEMT device manufacturing method according to claim 3, characterized in that: The band gap of the channel layer is smaller than that of the barrier layer.
5. A method for manufacturing a HEMT device according to claim 3, characterized in that: The substrate includes a substrate at the bottom and a buffer layer at the top, the buffer layer being connected to the channel layer and located between the substrate and the channel layer.
6. A method for manufacturing a HEMT device according to claim 5, characterized in that: The substrate is one of silicon substrate, sapphire substrate, silicon carbide substrate, aluminum nitride substrate or silicon on an insulating substrate.
7. The method for manufacturing a HEMT device according to claim 1, characterized in that, A first dielectric layer is disposed above the gate metal A, and the etching rate of the first dielectric layer is greater than the etching rate of the material layer. The opening is formed after the first dielectric layer is removed.
8. A method for manufacturing a HEMT device according to claim 1, characterized in that, The gate metal A is TiN.
9. A method for manufacturing a HEMT device according to claim 1, characterized in that, The gate metal B is either tungsten or aluminum.
10. A HEMT device, manufactured by any one of the HEMT device manufacturing methods according to claims 1-9.