An anti-radiation high-performance enhanced gallium nitride-based power device and a manufacturing method thereof

Abstract

The application provides an anti-radiation high-performance enhanced gallium nitride-based power device and a manufacturing method thereof, and belongs to the technical field of semiconductors. a Ga 1‑a N back barrier layer, In b Ga 1‑b N / GaN superlattice layer, a composite gate structure composed of a dielectric layer and a gate Schottky metal layer, and a gradient change island-shaped P-GaN layer, which cooperatively solve the compound problem of dynamic resistance instability and radiation sensitivity. The device not only maintains the normally-off characteristics and high threshold voltage of the enhanced device, but also significantly improves the anti-radiation capability, breakdown voltage and dynamic resistance stability, and is particularly suitable for power electronic applications in strong radiation environments such as aerospace and nuclear energy detection.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a radiation-resistant, high-performance enhanced gallium nitride-based power device and its fabrication method. Background Technology

[0002] Enhancement gallium nitride (GaN) high electron mobility transistors (HEMTs) have become highly promising devices for next-generation aerospace and nuclear energy exploration environments due to their excellent characteristics such as high breakdown electric field, high electron saturation velocity, high reliability and high two-dimensional electron gas density.

[0003] However, traditional enhancement-mode GaNHEMT devices face two critical technical bottlenecks when exposed to the aforementioned radiation environments: First, the dynamic resistance instability problem. Under high-voltage bias, hot electrons in the channel of commercial GaN power devices are trapped. These traps originate from deep-level defects in the GaN buffer layer, interface states in the AlGaN barrier layer and passivation layer, and bulk traps. The trapped charges form a "virtual gate," depleting the two-dimensional electron gas in the channel, leading to a sharp increase in dynamic on-resistance and severely limiting the reliability of the device in high-efficiency power conversion systems. Second, the inherent radiation sensitivity problem. When GaNHEMTs are applied in space radiation or nuclear radiation environments, they are severely affected by the total ionization dose effect and single-event effects. The most critical is the single-event effect, especially single-event burn-out. When high-energy heavy ions are incident on the high electric field region of the device, they ionize to generate dense electron-hole pairs, triggering a fatal discharge current that leads to instantaneous and permanent device failure.

[0004] Currently, industry optimizations for dynamic resistance stability primarily focus on surface passivation processes and field plate structure design, while improvements in radiation resistance emphasize material quality enhancement. Existing technologies lack a comprehensive device structure design and fabrication method that can synergistically address the combined challenges of dynamic resistance instability and radiation sensitivity. Therefore, there is an urgent need for an innovative device structure and fabrication process that can achieve robust normally-off operation while effectively suppressing dynamic resistance degradation during high-voltage switching and significantly enhancing the device's tolerance to strong radiation environments. This will meet the pressing demands of future aerospace, defense, and other fields for highly reliable power electronic devices. Summary of the Invention

[0005] This invention provides a radiation-resistant, high-performance enhanced gallium nitride (GaN)-based power device and its fabrication method. It can improve the dynamic resistance instability and radiation sensitivity problems of existing enhanced gallium nitride high electron mobility transistors. The technical solution is as follows:

[0006] In a first aspect, embodiments of the present invention provide a radiation-resistant, high-performance, enhanced gallium nitride-based power device, comprising, from bottom to top, a substrate layer, a nucleation layer, a high-resistivity buffer layer, and a P-type In... a Ga 1-a N-back barrier layer, In b Ga 1-b N / GaN superlattice layer, low-temperature GaN layer, channel layer, barrier layer and strip P-GaN gate layer;

[0007] A dielectric layer and a gate Schottky metal layer are sequentially disposed above the P-GaN gate layer. A source metal layer and a drain metal layer connected to the channel layer are disposed on both sides of the P-GaN gate layer. A source metal field plate is disposed above the source metal layer, and a drain metal field plate is disposed above the drain metal layer. Multiple island-shaped P-GaN layers are disposed on the barrier layer on the side of the drain metal layer closest to the P-GaN gate layer, and a Schottky metal layer is disposed above the island-shaped P-GaN layers.

[0008] Optionally, the P-type In a Ga 1-a The N-back barrier thickness ranges from 10 to 50 nm, where a ranges from 0.1 to 0.35 nm. The P-type In... a Ga 1-a The Mg doping concentration in the N-back barrier layer ranges from 1×10⁻⁶. 17 cm -3 ~5×10 19 cm -3 ;

[0009] In the width direction of the P-GaN gate layer, the P-type In a Ga 1-a The length of the N-back barrier layer is greater than the length of the P-GaN gate layer and less than or equal to the length of the high-resistivity buffer layer, wherein the P-type In a Ga 1-a The distance between the edge of the N-back barrier layer near the drain metal layer and the drain metal layer is less than the distance between the P-GaN gate layer and the drain metal layer.

[0010] Optionally, the In b Ga 1-b The N / GaN superlattice layer consists of multiple GaN layers and In layers arranged in a periodic cycle from bottom to top. b Ga 1-b N layers, the In b Ga 1-b The thickness ratio of the N layer to the GaN layer ranges from 1:1 to 3:1, and b ranges from 0.05 to 0.25, with b being less than a.

[0011] The Inb Ga 1-b The N / GaN superlattice layer has 3 to 50 cycle numbers, and the In is arranged in a cycle-like manner. b Ga 1-b In layer N, b in the In component remains constant; or b satisfies the following formula for change: In x =In b +[(In a -In b )×Z x / (Z-1)] c Where Z is the number of cycles, Z x For the xth period, c>0.

[0012] Optionally, the dielectric layer is a single dielectric layer formed from any one of SiN, Al2O3, SiO2 and HfO2, or a composite dielectric layer of any combination thereof; the thickness of the single dielectric layer ranges from 10 to 50 nm, the thickness of each layer of the composite dielectric layer ranges from 5 to 15 nm, and the total thickness is ≤60 nm.

[0013] Optionally, the thickness of the island-shaped P-GaN layer is the same as that of the P-GaN gate layer, ranging from 80 to 150 nm; the shape of the island-shaped P-GaN layer is one of square, circular, and elliptical; the length of the island-shaped P-GaN layer in the width direction of the P-GaN gate layer is 1 to 3 micrometers, and the width W in the length direction of the P-GaN gate layer is... i Gradient change, satisfying W i =W1×[1+α×(i-1) / (N-1)] β Among them, W i W1 is the width of the i-th island, and W1 is the width of the first island, ranging from 2 to 5 μm. α is the size expansion factor, ranging from 0.2 to 0.5. β is the nonlinearity factor, ranging from 1.0 to 1.5. i is the island index, and N is the total number of islands. The spacing S between the multiple island-shaped P-GaN layers is... i =S1×exp[γ×(i-1) / (N-1)], where S i S1 is the spacing between the i-th island P-GaN layer (13) and the (i+1)-th island P-GaN layer (13), where S1 is the minimum spacing ranging from 1 to 2 μm, γ is the spacing expansion coefficient ranging from 0.4 to 0.8, and i is the spacing index; the spacing between the island P-GaN layer and the P-GaN gate layer is greater than 3 μm;

[0014] Optionally, the Schottky metal layer above the island-shaped P-GaN layer is interconnected with the drain metal layer; the Schottky metal layer is made of Ni, Pt, or Au; the Schottky metal layer is not in contact with the barrier layer; the shape of the Schottky metal layer is one of square, circular, and elliptical; and the spacing between the Schottky metal layer and the P-GaN gate layer is greater than 2.5 μm.

[0015] Optionally, the source metal field plate is interconnected with the source metal layer, the distance between the source metal field plate and the drain metal field plate is in the range of 2.5 to 5 μm, and the source metal field plate is not in contact with the gate Schottky metal layer; the drain metal field plate is interconnected with the Schottky metal layer, and the distance between the drain metal field plate and the P-GaN gate layer is smaller than the distance between the Schottky metal layer and the P-GaN gate layer.

[0016] Optionally, the P-type In a Ga 1-a The growth temperature of the N-back barrier layer is 800-850°C, which is lower than the growth temperature of the high-resistivity buffer layer and higher than the growth temperature of the In layer. b Ga 1-b Growth temperature of N / GaN superlattice layer.

[0017] Optionally, the P-type In a Ga 1-a The precursor ratio of the N-back barrier layer (4), NH3 / TMIn+TMGa, is 2000-5000, which is higher than that of the In. b Ga 1-b The N / GaN superlattice layer has a lower precursor ratio than the high-resistivity buffer layer.

[0018] In a second aspect, embodiments of the present invention provide a manufacturing method for fabricating the radiation-resistant, high-performance enhanced gallium nitride-based power device described in the first aspect, comprising:

[0019] Step 1: The substrate layer, the nucleation layer, the high-resistivity buffer layer, and the P-type In are grown sequentially from bottom to top on the epitaxial wafer. a Ga 1-a N-back barrier layer, the In b Ga 1-b The N / GaN superlattice layer, the low-temperature GaN layer, the channel layer, the barrier layer, and the P-GaN gate layer;

[0020] Step 2: Grow a dielectric layer on the entire epitaxial wafer, etch and deposit the source metal layer and the drain metal layer in the source and drain regions, and form active region isolation by ion implantation or mesa etching.

[0021] Step 3: Etch the P-GaN gate layer and the island-shaped P-GaN layer in the patterned area to form the gate Schottky metal layer and the Schottky metal layer etching holes and deposit Schottky metal respectively;

[0022] Step 4: Grow or deposit a passivation layer over the entire surface to protect the device surface, etch the source metal field plate and the drain metal field plate in the patterned area and deposit the interconnect metal of the source, drain and gate.

[0023] Step 5: Annealing is performed in an N2 atmosphere to optimize ohmic contacts and stabilize device performance.

[0024] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0025] By innovatively introducing P-type In based on the traditional enhancement-mode P-GaNHEMT device structure. a Ga 1-a N-back barrier layer, In b Ga 1-b The N / GaN superlattice layer, the composite gate structure consisting of a dielectric layer and a Schottky metal gate layer, and the gradient-varying island-like P-GaN layer synergistically solve the combined challenges of dynamic resistance instability and radiation sensitivity. This device not only maintains the normally-off characteristics and high threshold voltage of enhancement-mode devices but also significantly improves radiation resistance, breakdown voltage, and dynamic resistance stability, making it particularly suitable for power electronics applications in high-radiation environments such as aerospace and nuclear energy exploration. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of a conventional enhancement-mode P-GaNHEMT device;

[0028] Figure 2 This is a schematic diagram of the structure of the radiation-resistant, high-performance, enhanced gallium nitride-based power device provided in the embodiments of the present invention;

[0029] Figure 3 This is a schematic diagram of the epitaxial layer structure in an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of the structure of etching and depositing an ohmic metal layer in an embodiment of the present invention;

[0031] Figure 5This is a schematic diagram of the structure of etching strip-shaped P-GaN gate layer, island-shaped P-GaN layer and depositing Schottky metal layer in an embodiment of the present invention;

[0032] Figure 6 This is a flowchart of the manufacturing method provided in the embodiments of the present invention.

[0033] In the figure: 1-substrate layer; 2-nucleation layer; 3-high-resistivity buffer layer; 4-P-type In a Ga 1-a N-back barrier layer; 5-In b Ga 1-b 6-N / GaN superlattice layer; 7-Low-temperature GaN layer; 8-Channel layer; 9-Barrier layer; 10-Strip P-GaN gate layer; 11-Dielectric layer; 12-Source metal layer; 13-Drain metal layer; 14-Island P-GaN layer; 15-Schottky metal layer; 16-Gate Schottky metal layer; 17-Drain metal field plate; 51-In b Ga 1-b N-layer; 52-GaN layer; 100-Conventional substrate layer; 200-Conventional nucleation layer; 300-Conventional buffer layer; 400-Conventional channel layer; 500-Conventional barrier layer; 600-Conventional strip-shaped P-GaN layer; 700-Conventional strip-shaped Schottky gate metal; 800-Conventional drain ohmic contact layer; 900-Conventional source ohmic contact layer. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0035] Figure 1 This is a schematic diagram of a conventional enhancement-mode P-GaNHEMT device. (Example:) Figure 1As shown, existing P-GaN HEMT devices mainly include, from bottom to top, a conventional substrate layer 100, a conventional nucleation layer 200, a conventional buffer layer 300, a conventional channel layer 400, and a conventional barrier layer 500. A conventional strip-shaped P-GaN layer 600 is placed above the conventional barrier layer 500 to deplete the two-dimensional electron gas of the channel layer, achieving a normally-off function. A conventional strip-shaped Schottky gate metal 700 is placed above the conventional strip-shaped P-GaN layer 600 to enhance gate control capability. A conventional drain ohmic contact layer 800 is placed to the right of the conventional strip-shaped P-GaN layer 600, and a conventional source ohmic contact layer 900 is placed to the left. However, under high-voltage bias, hot electrons in the channel of current P-GaN power devices are trapped. These traps originate from deep-level defects in the conventional buffer layer 300, interface states in the conventional barrier layer 500 and passivation layer, and bulk traps. The trapped charges form a "virtual gate," which depletes the two-dimensional electron gas in the channel, leading to a sharp increase in dynamic on-resistance and severely limiting the reliability of the device in high-efficiency power conversion systems. Furthermore, electric field concentration exists near the gate edge and drain of P-GaN devices. When high-energy heavy ions are incident on these high-field regions, they ionize to generate dense electron-hole pairs, triggering a fatal discharge current that causes instantaneous or permanent device failure.

[0036] Therefore, to enable the application of enhancement-mode P-GaNHEMT devices in irradiated environments, it is crucial to address the issue of increased interface state trapped electrons and induced carrier accumulation in the gate region after irradiation. This requires efficiently separating trapped negative charges and carriers to improve the device's radiation resistance and reliability. Simultaneously, the high threshold voltage capability of enhancement-mode devices must be fully considered to avoid increased leakage current and power consumption due to low threshold voltage.

[0037] Figure 2 This is a schematic diagram of the structure of the radiation-resistant, high-performance, enhanced gallium nitride-based power device provided in the embodiments of the present invention; Figure 3 This is a schematic diagram of the epitaxial layer structure in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of etching and depositing an ohmic metal layer in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the etched strip-shaped P-GaN gate layer, island-shaped P-GaN layer, and deposited Schottky metal layer in an embodiment of the present invention. Figures 2 to 5 As shown, based on the above-mentioned deficiencies, this embodiment of the invention provides a radiation-resistant, high-performance enhanced gallium nitride-based power device. The device's layer structure, from bottom to top, includes: a substrate layer 1, a nucleation layer 2, a high-resistivity buffer layer 3, and a P-type In... a Ga 1-a N-back barrier layer 4, In b Ga 1-b 5. N / GaN superlattice layer, 6. Low-temperature GaN layer, 7. Channel layer, 8. Barrier layer, and 9. Strip-shaped P-GaN gate layer.

[0038] The P-GaN gate layer 9 is provided with a dielectric layer 10 and a gate Schottky metal layer 15 in sequence. The P-GaN gate layer 9 is provided with a source metal layer 11 and a drain metal layer 12 connected to the channel layer 7 on both sides. A source metal field plate 16 is provided above the source metal layer 11 and a drain metal field plate 17 is provided above the drain metal layer 12. Multiple island-shaped P-GaN layers 13 are provided on the barrier layer 8 on the side of the drain metal layer 12 closest to the P-GaN gate layer 9. A Schottky metal layer 14 is provided above the island-shaped P-GaN layers 13.

[0039] The following is combined Figure 2 and Figure 5 This invention provides a detailed description of the fabrication method of the radiation-resistant, high-performance enhanced gallium nitride-based power device and the specific implementation of each layer structure.

[0040] Step 1: Growth of the epitaxial layer:

[0041] On the epitaxial wafer, from bottom to top, the following layers are grown sequentially: substrate layer 1, nucleation layer 2, high-resistivity buffer layer 3, and P-type In... a Ga 1-a N-back barrier layer 4, In b Ga 1-b 5. N / GaN superlattice layer, 6. Low-temperature GaN layer, 7. Channel layer, 8. Barrier layer, and 9. P-GaN gate layer.

[0042] In this embodiment of the invention, substrate 1 can be selected from sapphire or silicon substrates, with sapphire substrates being preferred due to their good lattice matching and thermal stability, providing a good substrate for the subsequent growth of epitaxial layers. Nucleation layer 2 is grown on top of substrate 1, typically using AlN or low-temperature GaN as the nucleation layer, with a thickness ranging from 10-50 nm. Its main function is to improve the lattice mismatch between the epitaxial layer and the substrate, and reduce the dislocation density.

[0043] A high-resistivity buffer layer 3 is grown above the nucleation layer 2, using intrinsic GaN or iron-doped GaN material, with a thickness ranging from 1 to 3 μm and a growth temperature of 1000-1100℃. The main function of the high-resistivity buffer layer 3 is to block the leakage of two-dimensional electron gas to the substrate, thereby improving the device's breakdown voltage and leakage current resistance. By using a high-resistivity material, the free carrier concentration in the buffer layer can be effectively reduced, lowering the off-state leakage current of the device and improving the switching performance of the power device.

[0044] P-type In a Ga 1-a The N-back barrier layer 4 is grown above the high-resistivity buffer layer 3, which is one of the key innovative structures of this invention. P-type In a Ga 1-aThe thickness of the N-back barrier layer 4 ranges from 10 to 50 nm, where a ranges from 0.1 to 0.35 and the Mg doping concentration ranges from 1 × 10¹. 7 cm - ³ to 5×10¹ 9 cm - ³. P-type In a Ga 1-a The growth temperature of the N-back barrier layer 4 is 800-850°C, which is lower than the growth temperature of the high-resistivity buffer layer 3 (1000-1100°C) and higher than that of In. b Ga 1-b The growth temperature of the N / GaN superlattice layer 5 is 700-800°C. The precursor ratio of NH3 / TMIn+TMGa is 2000-5000, which is higher than that of In. b Ga 1-b The N / GaN superlattice layer 5 (1000-2000) has a lower precursor ratio than the high-resistivity buffer layer 3 (5000-10000).

[0045] In the width direction of the P-GaN gate layer 9, P-type In a Ga 1-a The length of the N-back barrier layer 4 is greater than the length of the P-GaN gate layer 9, and less than or equal to the length of the high-resistivity buffer layer 3. P-type In a Ga 1-a The distance between the edge of the N-back barrier layer 4 near the drain metal layer 12 and the drain metal layer 12 is smaller than the distance between the P-GaN gate layer 9 and the drain metal layer 12. This design makes the P-type In a Ga 1- a The N-back barrier layer 4 can extend to the gate-drain region, enabling it to perform better carrier collection in the high electric field region.

[0046] P-type In a Ga 1-a The technical advantages of the N-back barrier layer 4 are mainly reflected in the following aspects: First, by utilizing the elevation of its valence band top, a hole barrier is formed. Simultaneously, due to the band shift between InGaN and GaN, a certain barrier is also formed at the conduction band bottom. This structure can better confine the two-dimensional electron gas within the channel layer, reducing electron leakage to the buffer layer, especially under irradiation conditions, thereby reducing leakage current and increasing the device's breakdown voltage; Second, P-type In... a Ga 1-aThe N-back barrier layer 4 can effectively collect holes generated by radiation, preventing holes from accumulating in the buffer layer or under the gate and causing device performance degradation. Due to the hole collection effect of P-InGaN, the influence of radiation-induced trap charges on the channel can be reduced, thereby improving the device's radiation resistance. Third, by adjusting the In composition and doping concentration in InGaN, the height and width of the barrier can be precisely controlled, thereby optimizing the electrical characteristics of the device and meeting the needs of different applications.

[0047] In b Ga 1-b N / GaN superlattice layer 5 is grown on P-type In a Ga 1-a Above the N-back barrier layer 4, this is another key innovative structure of the present invention. b Ga 1-b The N / GaN superlattice layer 5 includes multiple groups of GaN layers 52 and In layers arranged in a periodic cycle from bottom to top. b Ga 1-b Nth floor 51, In b Ga 1-b The thickness ratio of the N layer 51 to the GaN layer 52 ranges from 1:1 to 3:1, and b ranges from 0.05 to 0.25, with b being less than a. b Ga 1-b The N / GaN superlattice layer 5 has 3-50 cycle counts and a growth temperature of 700-800℃, which is lower than that of P-type In. a Ga 1-a The growth temperature of the N-back barrier layer 4.

[0048] In the periodic arrangement b Ga 1-b In layer N, b in the In composition can remain constant to achieve a uniform superlattice structure; alternatively, b can satisfy the gradient variation formula: In x =In b +[(In a -In b )×Z x / (Z-1)] c Where Z is the number of cycles, c>0, Z x This is the xth cycle. Through this gradient design, the In component can gradually transition from a lower value at the bottom to a value approaching that of P-type In at the top. a Ga 1-a The value of N-back barrier layer 4 forms a smooth band transition.

[0049] In b Ga 1-bThe technical advantages of the N / GaN superlattice layer 5 are mainly reflected in the following aspects: First, the multi-interface structure can promote the bending and mutual annihilation of dislocations at the interface, preventing dislocations from extending upward to the active region, thereby reducing the dislocation density in the active region and improving the reliability and lifetime of the device; Second, the gradient superlattice can modulate the longitudinal electric field distribution, avoiding excessive concentration of the electric field in a certain region, thereby improving the breakdown voltage; Third, the numerous interfaces in the superlattice can become "traps" for radiation-induced defects, preventing defects from extending to the active region. At the same time, the polarization electric field of the superlattice can promote the accelerated movement of irradiation-generated holes towards the substrate, avoiding their accumulation below the barrier layer, thereby improving the device's radiation resistance, especially its resistance to single-particle burn-off.

[0050] Low-temperature GaN layer 6 is grown on In b Ga 1-b Above the N / GaN superlattice layer 5, the thickness ranges from 5-30 nm, and the growth temperature is 700-850℃, which is greater than that of In. b Ga 1-b The growth temperature of the N / GaN superlattice layer 5 is 1000-2000, the V / III ratio is 1000-2000, and the growth rate is 0.1-0.3 nm / s. The main function of the low-temperature GaN layer 6 is to form a smooth transition between the superlattice layer and the channel layer, reduce the interface roughness, and at the same time, act as a barrier layer to prevent the In composition in the superlattice layer from diffusing upward to the channel layer.

[0051] The channel layer 7 is grown on top of the low-temperature GaN layer 6, using intrinsic GaN or lightly doped GaN material, with a thickness ranging from 50 to 200 nm. Channel layer 7 is the core functional layer of the device, and a two-dimensional electron gas forms at the interface between channel layer 7 and barrier layer 8. Channel layer 7 needs to have high crystal quality and low defect density to ensure high electron mobility and good conductivity.

[0052] The barrier layer 8 is grown above the channel layer 7, typically made of AlGaN material, with a thickness ranging from 15-30 nm and an Al composition ranging from 0.15-0.30. At the heterojunction interface between the barrier layer 8 and the channel layer 7, a high-density two-dimensional electron gas is generated due to the polarization effect, forming the conductive channel of the device. The Al composition and thickness of the barrier layer 8 directly affect the concentration of the two-dimensional electron gas and the threshold voltage of the device.

[0053] The p-GaN gate layer 9 is grown above the barrier layer 8, using p-type doped GaN material, with a thickness ranging from 80 to 150 nm and a Mg doping concentration ranging from 1 × 10⁻⁶. 18 cm - ³ to 5×10 19 cm -³. The P-GaN gate layer 9 has a strip-shaped structure, and its main function is to deplete the two-dimensional electron gas below it, thereby achieving the normally-off characteristic of the enhancement-mode device. The width of the P-GaN gate layer 9 is determined according to the device design requirements, and is typically in the range of 1-3 μm.

[0054] Step 2: Fabrication of the dielectric layer and source / drain metal layers:

[0055] After the epitaxial layer growth is completed, a dielectric layer 10 is grown on the entire epitaxial wafer. The dielectric layer 10 can be a single dielectric layer formed from any one of SiN, Al2O3, SiO2, and HfO2, or a composite dielectric layer of any combination of several. The thickness of a single dielectric layer ranges from 10 to 50 nm, the thickness of each layer of the composite dielectric layer ranges from 5 to 15 nm, and the total thickness is ≤60 nm.

[0056] When the dielectric layer 10 is a composite dielectric layer, the preferred growth sequence is as follows: first, grow an interface layer (such as AlN or Al2O3) to passivate the surface, with a thickness of 5-10 nm; then, grow a high-k layer (such as HfO2) with a thickness of 5-15 nm; and finally, grow a capping layer (such as SiN) with a thickness of 5-15 nm. Al2O3 and HfO2 are preferably grown using atomic layer deposition (ALD) technology, which can obtain high-quality films and precise thickness control; SiN and SiO2 are preferably grown using plasma-enhanced chemical vapor deposition (PECVD) technology; and AlN is preferably grown using metal-organic chemical vapor deposition (MOCVD) technology.

[0057] The dielectric layer 10 is located above the P-GaN gate layer 9, forming a composite gate structure in conjunction with the gate Schottky metal layer 15. This composite gate, composed of Schottky gate metal, dielectric layer, and P-GaN, improves the threshold voltage and reliability of the device, and optimizes interface characteristics by combining the advantages of different dielectric materials. Carrier transport is improved by adjusting band alignment. The fabrication method is simple, compatible with existing processes, and enhances the overall radiation resistance of the device.

[0058] In the source and drain regions, the dielectric layer 10 is removed using photolithography and etching processes to expose the surface of the barrier layer 8, and then the source metal layer 11 and drain metal layer 12 are deposited. The source metal layer 11 and drain metal layer 12 employ ohmic contact metals, typically a Ti / Al / Ni / Au multilayer metal structure with a total thickness of 100-300 nm. The source metal layer 11 and drain metal layer 12 form a good ohmic contact with the channel layer 7, ensuring low contact resistance.

[0059] refer to Figure 5In this embodiment of the invention, the source metal layer 11 is located to the left of the P-GaN gate layer 9, and the drain metal layer 12 is located to the right of the P-GaN gate layer 9. The spacing between the source metal layer 11 and the drain metal layer 12, i.e., the gate-drain spacing and the gate-source spacing, is designed according to the voltage withstand requirements of the device, and the gate-drain spacing is usually larger than the gate-source spacing. For high-voltage devices, the gate-drain spacing can reach 10-30 μm.

[0060] After the source metal layer 11 and drain metal layer 12 are fabricated, the active region is isolated by ion implantation or mesa etching. Nitrogen ion or argon ion implantation is preferred, with an implantation energy of 50-200 keV and an implantation dose of 1×10⁻⁶. 14 -1×10 15 cm - ², can form a high-resistivity region around the active region of a device, achieving electrical isolation between devices. Mesa etching, on the other hand, uses dry etching technology to etch to the buffer layer, forming physical isolation.

[0061] Step 3: Etching of P-GaN gate layer and island-shaped P-GaN layer, and deposition of Schottky metal:

[0062] refer to Figure 1 and Figure 5 The gate region and island P-GaN region are patterned using photolithography, and then the P-GaN gate layer 9 and island P-GaN layer 13 are etched. Dry etching, such as inductively coupled plasma (ICP) etching or reactive ion etching (RIE), is preferred. The etching gas can be a Cl2 / BCl3 or Cl2 / Ar mixture, which offers good etching selectivity and allows for precise control of the etching depth.

[0063] The P-GaN gate layer 9 and the island-shaped P-GaN layer 13 are etched simultaneously, meaning they are completed in the same photolithography and etching steps. The etching depth needs to penetrate the P-GaN gate layer 9 and reach the surface of the barrier layer 8 to form the etching holes for the gate Schottky metal layer 15 and the Schottky metal layer 14. After etching, the P-GaN gate layer 9 retains its strip-shaped structure, while the island-shaped P-GaN layer 13 forms multiple independent island-shaped structures.

[0064] The island-shaped P-GaN layers 13 are located on the barrier layer 8 on the side of the drain metal layer 12 closest to the P-GaN gate layer 9, and are spaced apart along the length of the P-GaN gate layer 9. The thickness of the island-shaped P-GaN layers 13 is the same as that of the P-GaN gate layer 9, ranging from 80 to 150 nm. The shape of the island-shaped P-GaN layers 13 can be square, circular, or elliptical, depending on the device design requirements.

[0065] In the width direction of the P-GaN gate layer 9, the length of the island-shaped P-GaN layer 13 is 1-3 μm; in the length direction of the P-GaN gate layer 9, the width of the island-shaped P-GaN layer 13 exhibits a gradient change, satisfying the formula: W i =W1×[1+α×(i-1) / (N-1)] β Among them, W i W1 is the width of the i-th island, which is the width of the first island and ranges from 2 to 5 μm. α is the size expansion coefficient, which ranges from 0.2 to 0.5. β is the nonlinear factor, which ranges from 1.0 to 1.5. i is the island number and N is the total number of islands.

[0066] The spacing between multiple island-shaped P-GaN layers 13 also exhibits a gradient change, satisfying the formula: S i =S1×exp[γ×(i-1) / (N-1)], where S i S1 represents the spacing between the i-th island P-GaN layer 13 and the (i+1)-th island P-GaN layer 13, where S1 is the minimum spacing, ranging from 1 to 2 μm, γ is the spacing expansion factor, ranging from 0.4 to 0.8, and i is the spacing index. The spacing between the island P-GaN layer 13 and the P-GaN gate layer 9 is greater than 3 μm.

[0067] This gradient-variable island-shaped P-GaN layer 13 design is one of the key innovations of this invention. Its technical effects are mainly reflected in the following aspects: First, in traditional GaNHEMTs, high electric fields are concentrated at the gate edge and drain side, especially under high drain voltage conditions, where electric field peaks can easily lead to breakdown. After inserting P-GaN islands, the PN junction formed by P-type GaN and two-dimensional electron gas (2DEG) depletes the 2DEG below the P-GaN island, thereby changing the electric field distribution and dispersing the electric field peak to multiple locations (such as the edge of the P-GaN island), reducing the maximum electric field strength and thus improving the breakdown voltage. Second, P-GaN islands can suppress the charging effect of buffer layer traps because the depletion region below the P-GaN island reduces the number of electrons injected into the buffer layer, thereby reducing the chance of trap capture and making the dynamic resistance more stable. Third, through gradient design, the islands near the gate are smaller and more densely spaced, while the islands far from the gate are larger and more sparsely spaced, enabling stepwise modulation of the electric field, optimizing the electric field distribution, and further improving the device's breakdown voltage and radiation resistance.

[0068] After etching the P-GaN gate layer 9 and the island-shaped P-GaN layer 13, a gate Schottky metal layer 15 and a Schottky metal layer 14 are deposited in the etched holes, respectively. The gate Schottky metal layer 15 and the Schottky metal layer 14 use the same metal material and the same deposition process, typically Ni, Pt, or Au, or a Ni / Pt / Au multilayer metal structure, with a total thickness of 150-300 nm. Specifically, a Ni (30-50 nm) / Pt (20-50 nm) / Au (100-200 nm) multilayer structure can be used.

[0069] The gate Schottky metal layer 15 is located above the P-GaN gate layer 9 and works together with the dielectric layer 10 to form a composite gate structure, controlling the opening and closing of the channel. The Schottky metal layer 14 is located above the island-shaped P-GaN layer 13 and forms a Schottky contact with the island-shaped P-GaN layer 13, playing a role in electric field modulation.

[0070] The Schottky metal layer 14 can be square, circular, or elliptical. The spacing between the island-shaped P-GaN layer 13 and the P-GaN gate layer 9 is greater than 3 μm, while the spacing between the Schottky metal layer 14 and the P-GaN gate layer 9 is greater than 2.5 μm. The shapes of the Schottky metal layer 14 and the island-shaped P-GaN layer 13 are consistent or slightly larger to better suppress the spike electric field below the drain metal layer 12. The Schottky metal layer 14 does not contact the barrier layer 8, ensuring that the Schottky metal layer 14 only contacts the island-shaped P-GaN layer 13 and does not directly contact the two-dimensional electron gas, thus avoiding affecting the normal conductivity of the channel. The spacing between the Schottky metal layer 14 and the P-GaN gate layer 9 is greater than 2.5 μm, ensuring sufficient isolation between the gate and the Schottky metal layer 14.

[0071] Step 4: Preparation of passivation layer and field plate metal:

[0072] like Figure 5 As shown, after the deposition of the gate Schottky metal layer 15 and the Schottky metal layer 14, a passivation layer is grown or deposited on the entire wafer to protect the device surface. The passivation layer is typically made of SiN material, with a thickness of 50-200 nm, and is deposited using PECVD technology. The main function of the passivation layer is to passivate the device surface, reduce surface states, suppress surface leakage current, and protect the device from environmental influences.

[0073] After the passivation layer is deposited, the patterned regions of the source metal field plate 16 and the drain metal field plate 17 are defined by photolithography and etching processes. Then, the passivation layer is etched to form contact holes for the field plate metal. The source metal field plate 16, the drain metal field plate 17, and the interconnect metals of the source, drain, and gate are deposited in the contact holes. Typically, a Ti / Au or Ti / Pt / Au multilayer metal structure is used, with a total thickness of 300-500 nm.

[0074] The source metal field plate 16 is located above the source metal layer 11 and interconnects with it to form an electrical connection. The source metal field plate 16 extends towards the gate and is suspended above the dielectric layer 10 and the passivation layer. The source metal field plate 16 does not contact the gate Schottky metal layer 15; the two are kept insulated from each other. The spacing between the source metal field plate 16 and the drain metal field plate 17 ranges from 2.5 to 5 μm.

[0075] The drain metal field plate 17 is located above and interconnected with the drain metal layer 12. The drain metal field plate 17 is also interconnected with the Schottky metal layer 14, electrically connecting the Schottky metal layers 14 on all island-shaped P-GaN layers 13 to the drain metal layer 12. The drain metal field plate 17 extends towards the gate, suspended above the dielectric layer 10 and the passivation layer. The spacing between the drain metal field plate 17 and the P-GaN gate layer 9 is smaller than the spacing between the Schottky metal layer 14 and the P-GaN gate layer 9, allowing the drain metal field plate 17 to perform electric field modulation near the gate.

[0076] The main function of the source metal field plate 16 and the drain metal field plate 17 is to modulate the electric field distribution on the device surface, reduce the electric field peak at the gate edge and near the drain, and improve the breakdown voltage of the device. By changing the surface potential distribution, the field plate structure makes the electric field more uniform on the device surface, reduces local electric field concentration, and thus improves the reliability and withstand voltage of the device.

[0077] Step 5: Annealing treatment:

[0078] After all metal layers have been deposited, annealing is performed in an N2 atmosphere at a temperature of 400-600℃ for 30-300 seconds. The main purpose of annealing is to optimize ohmic contacts and stabilize device performance. Annealing promotes the interfacial reaction between the metal and semiconductor, reduces contact resistance, and repairs defects generated during metal deposition, thereby improving device stability and reliability.

[0079] After annealing, the fabrication of the radiation-resistant, high-performance, enhanced gallium nitride-based power device is complete.

[0080] Figure 6 This is a flowchart of the manufacturing method provided in an embodiment of the present invention. Figure 6 As shown, this embodiment of the invention also provides a manufacturing method for manufacturing such as Figures 2 to 5 The radiation-resistant, high-performance, enhanced gallium nitride-based power device shown in the method includes the following steps:

[0081] S1. On the epitaxial wafer, from bottom to top, grow substrate layer 1, nucleation layer 2, high-resistivity buffer layer 3, and P-type In... a Ga 1-a N-back barrier layer 4, Inb Ga 1-b 5. N / GaN superlattice layer, 6. Low-temperature GaN layer, 7. Channel layer, 8. Barrier layer, and 9. P-GaN gate layer.

[0082] S2. A dielectric layer 10 is grown on the entire epitaxial wafer. A source metal layer 11 and a drain metal layer 12 are etched and deposited in the source and drain regions. An active region isolation is formed by ion implantation or mesa etching.

[0083] S3. Etch the P-GaN gate layer 9 and island P-GaN layer 13 in the patterned area to form etch holes for the gate Schottky metal layer 15 and the Schottky metal layer 14 and deposit Schottky metal respectively.

[0084] S4. Grow or deposit a passivation layer on the entire surface to protect the device surface, etch the source metal field plate 16 and drain metal field plate 17 of the patterned area and deposit the interconnect metal of the source, drain and gate.

[0085] S5. Annealing is performed in an N2 atmosphere to optimize ohmic contacts and stabilize device performance.

[0086] The radiation-resistant, high-performance, enhanced gallium nitride-based power device provided in the embodiments of the present invention, fabricated using the above-described method, incorporates P-type In... a Ga 1-a The N-back barrier layer 4 utilizes the elevation of its valence band top to form a hole barrier, while simultaneously creating a barrier at the conduction band bottom. This better confines the two-dimensional electron gas within the channel layer 7, reducing electron leakage to the buffer layer, especially under irradiation conditions. This, in turn, lowers leakage current and increases the device's breakdown voltage. (P-type In) a Ga 1-a The N-back barrier layer 4 can effectively collect holes generated by radiation, prevent holes from accumulating in the buffer layer or under the gate and causing device performance degradation, reduce the impact of radiation-induced trapped charges on the channel, and thus improve the device's radiation resistance.

[0087] By introducing In b Ga 1-b The N / GaN superlattice layer 5 utilizes its multi-interface structure to induce dislocation bending and mutual annihilation at the interfaces, preventing dislocations from extending upwards into the active region, reducing the dislocation density in the active region, and improving device reliability and lifetime. The graded superlattice can modulate the longitudinal electric field distribution, preventing excessive concentration of the electric field in a certain region, thereby increasing the breakdown voltage. The numerous interfaces in the superlattice can act as "traps" for radiation-induced defects, preventing defects from extending into the active region. Simultaneously, the polarization electric field of the superlattice can accelerate the movement of irradiation-generated holes towards the substrate, preventing their accumulation below the barrier layer 8, thus improving the device's radiation resistance, especially its resistance to single-event burn-out.

[0088] By placing a dielectric layer 10 above the P-GaN gate layer 9 and forming a composite gate structure in conjunction with the gate Schottky metal layer 15, the threshold voltage and reliability of the device are improved. Combining the advantages of different dielectric materials and optimizing interface characteristics, carrier transport is improved by adjusting band alignment. The fabrication method is simple, compatible with existing processes, and enhances the overall radiation resistance of the device.

[0089] By setting multiple gradient-varying island-shaped P-GaN layers 13 on the side of the drain metal layer 12 near the P-GaN gate layer 9, and utilizing the PN junction formed by P-type GaN and two-dimensional electron gas, the 2DEG is depleted below the P-GaN islands, changing the electric field distribution and dispersing the electric field peak to multiple locations, thus reducing the maximum electric field strength and improving the breakdown voltage. The P-GaN islands can suppress the charging effect of buffer layer traps, reducing the number of electrons injected into the buffer layer, thereby reducing the chance of trap capture and making the dynamic resistance more stable. The gradient design achieves step-by-step modulation of the electric field, optimizing the electric field distribution and further improving the device's breakdown voltage and radiation resistance.

[0090] By setting the source metal field plate 16 and the drain metal field plate 17, the electric field distribution on the device surface is modulated, the electric field peak value near the gate edge and the drain is reduced, the electric field on the device surface is made more uniform, the local electric field concentration is reduced, and the reliability and withstand voltage of the device are improved.

[0091] In summary, this invention innovatively introduces P-type In into the traditional enhancement-mode P-GaNHEMT device structure. a Ga 1-a N-back barrier layer 4, In b Ga 1-b The N / GaN superlattice layer 5, the composite gate structure (dielectric layer 10 and gate Schottky metal layer 15), and the gradient-varying island-like P-GaN layer 13 synergistically solve the combined challenges of dynamic resistance instability and radiation sensitivity. This device not only maintains the normally-off characteristics and high threshold voltage of enhancement-mode devices, but also significantly improves radiation resistance, breakdown voltage, and dynamic resistance stability, making it particularly suitable for power electronics applications in high-radiation environments such as aerospace and nuclear energy exploration.

[0092] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0093] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A radiation-resistant, high-performance, enhanced gallium nitride-based power device, characterized in that, It includes, from bottom to top, a substrate layer (1), a nucleation layer (2), a high-resistivity buffer layer (3), and a P-type In layer. a Ga 1-a N-back barrier layer (4), In b Ga 1-b N / GaN superlattice layer (5), low-temperature GaN layer (6), channel layer (7), barrier layer (8) and strip P-GaN gate layer (9). A dielectric layer (10) and a gate Schottky metal layer (15) are sequentially disposed above the P-GaN gate layer (9). A source metal layer (11) and a drain metal layer (12) connected to the channel layer (7) are disposed on both sides of the P-GaN gate layer (9). A source metal field plate (16) is disposed above the source metal layer (11), and a drain metal field plate (17) is disposed above the drain metal layer (12). Multiple island-shaped P-GaN layers (13) are arranged at intervals along the length direction of the P-GaN gate layer (9) on the barrier layer (8) of the drain metal layer (12) near the P-GaN gate layer (9). A Schottky metal layer (14) is disposed above the island-shaped P-GaN layers (13).

2. The radiation-resistant, high-performance, enhanced gallium nitride-based power device according to claim 1, characterized in that, The P-type In a Ga 1-a The thickness of the N-back barrier layer (4) ranges from 10 to 50 nm, where a ranges from 0.1 to 0.35 nm. a Ga 1-a The Mg doping concentration in the N-back barrier layer (4) ranges from 1×10⁻⁶. 17 cm -3 ~5×10 19 cm -3 ; In the width direction of the P-GaN gate layer (9), the P-type In a Ga 1-a The length of the N-back barrier layer (4) is greater than the length of the P-GaN gate layer (9) and less than or equal to the length of the high-resistivity buffer layer (3). a Ga 1-a The distance between the edge of the N-back barrier layer (4) near the drain metal layer (12) and the drain metal layer (12) is less than the distance between the P-GaN gate layer (9) and the drain metal layer (12).

3. The radiation-resistant, high-performance, enhanced gallium nitride-based power device according to claim 1, characterized in that, The In b Ga 1-b The N / GaN superlattice layer (5) includes multiple sets of GaN layers (52) and In layers arranged in a periodic cycle from bottom to top. b Ga 1-b N-layer (51), the In b Ga 1-b The thickness ratio of the N layer (51) to the GaN layer (52) is in the range of 1:1 to 3:1, b is in the range of 0.05 to 0.25, and b is less than a; The In b Ga 1-b The N / GaN superlattice layer (5) has 3 to 50 cycle periods, in which In is arranged in a cyclic pattern. b Ga 1-b In layer N (51), b in the In component remains unchanged; or b satisfies the following change formula: In x =In b +[(In a -In b )×Z x / (Z-1)] c Where Z is the number of cycles, Z x For the xth period, c>0.

4. The radiation-resistant, high-performance, enhanced gallium nitride-based power device according to claim 1, characterized in that, The dielectric layer (10) is a single dielectric layer formed from any one of SiN, Al2O3, SiO2 and HfO2, or a composite dielectric layer formed from any combination of several of them; The thickness of the single dielectric layer ranges from 10 to 50 nm, the thickness of each layer of the composite dielectric layer ranges from 5 to 15 nm, and the total thickness is ≤60 nm.

5. The radiation-resistant, high-performance enhanced gallium nitride-based power device according to claim 1, characterized in that, The island-shaped P-GaN layer (13) has the same thickness as the P-GaN gate layer (9), ranging from 80 to 150 nm; the island-shaped P-GaN layer (13) is square, circular, or elliptical in shape; the length of the island-shaped P-GaN layer (13) in the width direction of the P-GaN gate layer (9) is 1 to 3 micrometers, and the width W in the length direction of the P-GaN gate layer (9) is... i Gradient change, satisfying W i =W1×[1+α×(i-1) / (N-1)] β Among them, W i W1 is the width of the i-th island, and W1 is the width of the first island, with a width range of 2~5μm. α is the size expansion coefficient, with a value range of 0.2~0.

5. β is the nonlinear factor, with a value range of 1.0~1.

5. i is the island number, and N is the total number of islands. The spacing S between the multiple island-shaped P-GaN layers (13) is... i =S1×exp[γ×(i-1) / (N-1)], where S i S1 is the spacing between the i-th island P-GaN layer (13) and the (i+1)-th island P-GaN layer (13), where S1 is the minimum spacing ranging from 1 to 2 μm, γ is the spacing expansion coefficient ranging from 0.4 to 0.8, and i is the spacing number; the spacing between the island P-GaN layer (13) and the P-GaN gate layer (9) is greater than 3 μm.

6. The radiation-resistant, high-performance, enhanced gallium nitride-based power device according to claim 1, characterized in that, The Schottky metal layer (14) above the island-shaped P-GaN layer (13) is interconnected with the drain metal layer (12); the Schottky metal layer (14) is made of Ni, Pt or Au; the Schottky metal layer (14) is not in contact with the barrier layer (8); the shape of the Schottky metal layer (14) is one of square, round or elliptical; the spacing between the Schottky metal layer (14) and the P-GaN gate layer (9) is greater than 2.5 μm.

7. The radiation-resistant, high-performance enhanced gallium nitride-based power device according to claim 1, characterized in that, The source metal field plate (16) is interconnected with the source metal layer (11), and the distance between the source metal field plate (16) and the drain metal field plate (17) is in the range of 2.5 to 5 μm. The source metal field plate (16) is not in contact with the gate Schottky metal layer (15). The drain metal field plate (17) is interconnected with the Schottky metal layer (14), and the distance between the drain metal field plate (17) and the P-GaN gate layer (9) is smaller than the distance between the Schottky metal layer (14) and the P-GaN gate layer (9).

8. The radiation-resistant, high-performance enhanced gallium nitride-based power device according to any one of claims 1 to 7, characterized in that, The P-type In a Ga 1-a The growth temperature of the N-back barrier layer (4) is 800-850°C, which is lower than the growth temperature of the high-resistivity buffer layer (3) and higher than the growth temperature of the In layer. b Ga 1-b The growth temperature of the N / GaN superlattice layer (5).

9. The radiation-resistant, high-performance, enhanced gallium nitride-based power device according to claim 8, characterized in that, The P-type In a Ga 1-a The precursor ratio of the N-back barrier layer (4), NH3 / TMIn+TMGa, is 2000-5000, which is higher than that of the In. b Ga 1- b The N / GaN superlattice layer (5) has a lower precursor ratio than the high-resistivity buffer layer (3).

10. A method for fabricating a radiation-resistant, high-performance, enhanced gallium nitride-based power device, used to fabricate the radiation-resistant, high-performance, enhanced gallium nitride-based power device as described in any one of claims 1 to 9, characterized in that, include: Step 1: The substrate layer (1), the nucleation layer (2), the high-resistivity buffer layer (3), and the P-type In are grown sequentially from bottom to top on the epitaxial wafer. a Ga 1-a N-back barrier layer (4), the In b Ga 1-b The N / GaN superlattice layer (5), the low-temperature GaN layer (6), the channel layer (7), the barrier layer (8), and the P-GaN gate layer (9). Step 2: A dielectric layer (10) is grown on the entire epitaxial wafer. The source metal layer (11) and the drain metal layer (12) are etched and deposited in the source and drain regions. Active region isolation is formed by ion implantation or mesa etching. Step 3: Etch the P-GaN gate layer (9) and the island-shaped P-GaN layer (13) in the patterned area to form etch holes in the gate Schottky metal layer (15) and the Schottky metal layer (14) and deposit Schottky metal respectively; Step 4: Grow or deposit a passivation layer on the entire surface to protect the device surface, etch the source metal field plate (16) and the drain metal field plate (17) of the patterned area and deposit the interconnect metal of the source, drain and gate; Step 5: Annealing is performed in an N2 atmosphere to optimize ohmic contacts and stabilize device performance.

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