Anti-radiation SOI MOSFET device structure capable of defining gate width based on ion implantation and preparation method of anti-radiation SOI MOSFET device structure

Abstract

The invention discloses an anti-radiation SOI MOSFET device structure capable of defining gate width based on ion implantation and a preparation method thereof, and belongs to the field of semiconductor device preparation and anti-radiation reinforcement. The top layer silicon, the buried oxide layer and the supporting layer jointly form an SOI substrate material; the channel region is located in the top layer silicon and located below the grid electrode and between the grid width defining regions; the insulating dielectric layer is located above the exterior of the top silicon; the grid electrode is positioned above the insulating dielectric layer; the source and drain ends are arranged in the top layer silicon and are connected with the channel region; the potential control region is arranged in the top layer silicon and is connected with the source-drain end and the gate width definition region; the doping type of the channel region is the same as that of the gate width defining region, and the doping type of the channel region is different from that of the source drain region. Through device edge ion implantation, the device edge channel doping concentration is improved, an electric leakage channel caused by accumulation of positive charges in isolation silicon dioxide in a radiation environment is eliminated, the gate width is defined through ion implantation, the device channel edge effect is reduced, and the electrical characteristic consistency of devices with different widths is improved.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor device fabrication and radiation hardening technology, and in particular to a radiation-hardened SOI MOSFET device structure and its fabrication method based on ion implantation to define the gate width. Background Technology

[0002] With the continuous development of aerospace and nuclear fields, the requirements for the radiation resistance of devices are constantly increasing. Through design hardening or process hardening, and by continuously optimizing device structure, materials, and processes, the number of radiation-resistant device design schemes is increasing, but it is still impossible to fully meet the requirements of the radiation environment.

[0003] Currently, radiation-hardened device structures are mainly based on strip-gate MOSFET structures on bulk silicon or SOI substrates. T-shaped and H-shaped gates are designed to improve the total dose resistance and reduce edge leakage current. Compared to strip-shaped gates, T-shaped and H-shaped gates can suppress edge leakage current to some extent, but the device area is significantly increased, increasing the complexity of device and circuit design and raising the final product cost. Summary of the Invention

[0004] The purpose of this invention is to provide a radiation-resistant SOI MOSFET device structure and its fabrication method based on ion implantation to define the gate width, so as to solve the problems in the background art.

[0005] To address the aforementioned technical problems, this invention provides a radiation-resistant SOI MOSFET device structure based on ion implantation to define the gate width, comprising: a top silicon layer, a buried oxide layer, a support layer, a channel region, a gate width definition region, an insulating dielectric layer, a gate, source / drain terminals, and a potential control region; wherein,

[0006] The top silicon layer, buried oxide layer, and support layer together constitute the SOI substrate material;

[0007] The channel region is located in the top silicon layer, below the gate and between the gate width definition regions;

[0008] The insulating dielectric layer is located above the outer surface of the top silicon layer; the gate is located above the insulating dielectric layer;

[0009] The source and drain terminals are located in the top silicon layer and connected to the channel region;

[0010] The potential control region is located in the top silicon layer and is connected to the source / drain terminals and the gate width definition region.

[0011] The doping type of the channel region is the same as that of the gate width definition region, but the doping type of the channel region is different from that of the source / drain region.

[0012] In one embodiment, the thickness of the top silicon layer is 1 to 5000 nanometers, and the thickness of the buried oxide layer is 5 to 10000 nanometers.

[0013] In one embodiment, the channel region is formed by ion implantation or diffusion of impurity ions, with the doping type being P-type or N-type, and the doping element being phosphorus, boron, indium, or arsenic or other group III-V elements, with a doping concentration of 0-1E20 / cm³. -3 .

[0014] In one embodiment, the gate width definition region is formed by ion implantation or diffusion of impurity ions, with the doping type being P-type or N-type, and the doping element being phosphorus, boron, indium, or arsenic or other group III-V elements, with a doping concentration of 0-1E20 / cm. -3 .

[0015] In one embodiment, the insulating dielectric layer is SiO2, oxynitride, TiO2, HfO2, Si3N4, ZrO2, Ta2O5, barium strontium titanate (BST), lead zirconate titanate piezoelectric ceramic (PZT), or Al2O3, with a thickness of 0.1–20 nanometers.

[0016] In one embodiment, the gate is made of polysilicon, tantalum, tungsten, tantalum nitride, or titanium nitride, and has a thickness of 2 to 5000 nanometers.

[0017] In one embodiment, the source / drain region is formed by ion implantation or diffusion of impurity ions, with the doping type being P-type or N-type, and the doping element being phosphorus, boron, indium, arsenic, or other group III-V elements, with a doping concentration of 0-1E20 / cm³. -3 .

[0018] This invention also provides a method for fabricating a radiation-resistant SOI MOSFET device structure based on ion implantation to define the gate width, comprising the following steps:

[0019] An SOI substrate is provided, which includes a top silicon layer, a buried oxide layer, and a support layer;

[0020] In the top silicon layer, the channel region and gate width definition region are formed by ion implantation or diffusion;

[0021] An insulating dielectric layer is formed on the outer surface of the top silicon layer by deposition or oxidation; gate material is deposited on the insulating dielectric layer and anisotropic etching is performed to form the gate.

[0022] Source and drain terminals are fabricated on the top silicon layer using self-aligned metal silicide formation or epitaxial processes, thus completing the structure fabrication.

[0023] The present invention provides a radiation-resistant SOI MOSFET device structure and its fabrication method based on ion implantation defining the gate width, which has the following beneficial effects:

[0024] (1) By implanting ions at the device edge, the doping concentration of the device edge channel is increased, the leakage channel caused by the accumulation of positive charge in the isolation silicon dioxide under radiation environment is eliminated, and the radiation resistance is improved.

[0025] (2) By defining the gate width through ion implantation, the device channel edge effect is reduced, and the consistency of electrical characteristics of devices with different widths is improved. Compared with other radiation hardening processes, it is more applicable to narrow channel devices.

[0026] (2) By adopting a PN junction-free structure, the number of process steps and process complexity can be significantly reduced. For example, lightly doped source / drain and sidewall process modules can be eliminated, thereby reducing the manufacturing cost.

[0027] (3) The structure is suitable for bulk silicon and SOI substrates of different thicknesses, especially thin silicon film SOI substrates, and has a certain range of applications. Attached Figure Description

[0028] Figure 1 This invention provides a radiation-resistant SOI MOSFET device structure based on ion implantation to define the gate width.

[0029] Figure 2 This is a schematic diagram of the SOI substrate structure;

[0030] Figure 3 This is a schematic diagram after the gate width definition region has been prepared (along...). Figure 1 A (tangential direction);

[0031] Figure 4 This is a schematic diagram of the device structure after the gate fabrication is completed (along...). Figure 1 (B tangent direction);

[0032] Figure 5 This is a schematic diagram of the device structure after the gate fabrication is completed (along...). Figure 1 A (tangent direction). Detailed Implementation

[0033] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed account of the radiation-resistant SOI MOSFET device structure and its fabrication method based on ion implantation to define the gate width, as proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0034] This invention provides a radiation-resistant SOI MOSFET device structure based on ion implantation to define the gate width, the structure of which is as follows: Figure 1As shown, the substrate includes a top silicon layer 1, a buried oxide layer 2, a support layer 3, a channel region 4, a gate width definition region 5, an insulating dielectric layer 6, a gate 7, a source / drain terminal 8, and a potential control region 9. The top silicon layer 1, the buried oxide layer 2, and the support layer 3 together constitute the SOI substrate material. The channel region 4 is located in the top silicon layer 1, below the gate 7 and between the gate width definition region 5. The insulating dielectric layer 6 is located above and outside the top silicon layer 1. The gate 7 is located above the insulating dielectric layer 6. The source / drain terminal 8 is in the top silicon layer 1 and is connected to the channel region 4. The potential control region 9 is in the top silicon layer 1 and is connected to the source / drain terminal 8 and the gate width definition region 5.

[0035] The thickness of the top silicon layer 1 is 1 to 5000 nanometers, and the thickness of the buried oxide layer 2 is 5 to 10000 nanometers. The channel region 4 is formed by ion implantation or diffusion of impurity ions, with p-type or n-type doping and doping elements such as phosphorus, boron, indium, or arsenic (group III-V elements) at a doping concentration of 0-1E20 / cm³. -3 The gate width definition region 5 is formed by ion implantation or diffusion of impurity ions. The doping type is P-type or N-type, and the doping element is a group III-V element such as phosphorus, boron, indium, or arsenic, with a doping concentration of 0-1E20 / cm. -3 The doping type is the same as that of channel region 4. The insulating dielectric layer 6 is made of SiO2, oxides of nitride, TiO2, HfO2, Si3N4, ZrO2, Ta2O5, barium strontium titanate (BST), lead zirconate titanate piezoelectric ceramic (PZT), or Al2O3, with a thickness of 0.1–20 nm. The gate 7 is made of polysilicon, tantalum, tungsten, tantalum nitride, or titanium nitride, with a thickness of 2–5000 nm. The source / drain regions 8 are formed by ion implantation or diffusion of impurity ions, with a doping type of P-type or N-type, and the doping elements are group III-V elements such as phosphorus, boron, indium, or arsenic, with a doping concentration of 0–1 E20 / cm³. -3 The doping type is different from that of channel region 4.

[0036] The radiation-resistant SOI MOSFET device structure based on ion implantation defining the gate width of the present invention is fabricated by the following method:

[0037] like Figure 2 As shown, an SOI substrate is provided, which includes a top silicon layer 1, a buried oxide layer 2, and a support layer 3;

[0038] like Figure 3 As shown, a channel region 4 and a gate width definition region 5 are formed in the top silicon layer 1 by ion implantation or diffusion;

[0039] like Figure 4 , 5 As shown, an insulating dielectric layer 6 is formed on the outer surface of the top silicon layer 1 by deposition or oxidation; a gate material is deposited on the insulating dielectric layer 6 and anisotropic etching is performed to form a gate 7;

[0040] Source and drain terminals 8 are fabricated on top silicon 1 by self-aligned metal silicide formation or epitaxial process, thus completing the structure fabrication.

[0041] This invention improves radiation resistance by increasing the doping concentration of the device edge channel through ion implantation at the device edge, eliminating leakage channels caused by the accumulation of positive charges in the isolation silicon dioxide under radiation conditions, and defining the gate width through ion implantation. This reduces the edge effect of the device channel and improves the consistency of electrical characteristics of devices with different widths. Compared with other radiation hardening processes, it is more applicable to narrow-channel devices. By adopting a PN junction-free structure, it significantly reduces process steps and process complexity. For example, it can eliminate process modules such as lightly doped source / drain and sidewalls, reducing manufacturing costs. The structure is applicable to bulk silicon and SOI substrates of different thicknesses, especially thin silicon film SOI substrates.

[0042] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An ion implantation based anti-radiation SOI MOSFET device structure defining gate width, characterized by, Comprise: Top layer silicon (1), buried oxygen layer (2), support layer (3), channel region (4), gate width definition area (5), insulating dielectric layer (6), gate (7), source and drain (8), potential control area (9); wherein, The top layer silicon (1), buried oxygen layer (2), support layer (3) together constitute SOI substrate material; The channel region (4) is located in the top layer silicon (1), located below the gate (7), between the gate width definition area (5); The insulating dielectric layer (6) is located above the top layer silicon (1) outside; The gate (7) is located above the insulating dielectric layer (6); The source and drain (8) in the top layer silicon (1), connected with the channel region (4); The potential control area (9) in the top layer silicon (1), connected with the source and drain (8) and gate width definition area (5); The channel region (4) and the gate width definition area (5) are the same, and the channel region (4) and the source and drain region (8) are different.

2. The radiation-hardened SOI MOSFET device structure based on ion implantation defined gate width of claim 1, wherein, The thickness of the top layer silicon (1) is 1 to 5000 nanometers, and the thickness of the buried oxygen layer (2) is 5 to 10000 nanometers.

3. The radiation hard SOI MOSFET device structure based on ion implantation defined gate width as claimed in claim 1, wherein, The channel region (4) is formed by ion implantation or diffusion of impurity ions, the doping type is P type or N type, the doping element is phosphorus, boron, indium or arsenic or other three-five elements, and the doping concentration is 0-1E20 / cm -3 .

4. The radiation-hardened SOI MOSFET device structure based on ion implantation defined gate width of claim 1, wherein, The gate width definition region (5) is formed by ion implantation or diffusion of impurity ions, the doping type is P type or N type, the doping element is phosphorus, boron, indium or arsenic or other group III-V elements, and the doping concentration is 0-1E20 / cm -3 .

5. The radiation-hardened SOI MOSFET device structure based on ion implantation defined gate width of claim 1, wherein, The insulating dielectric layer (6) is SiO2, nitride, TiO2, HfO2, Si3N4, ZrO2, Ta2O5, barium strontium titanate BST, lead zirconate titanate piezoelectric ceramic PZT or Al2O3, thickness is 0.1~20 nanometer.

6. The radiation-hardened SOI MOSFET device structure based on ion implantation defined gate width of claim 1, wherein, The gate (7) is polysilicon, tantalum, tungsten, tantalum nitride or titanium nitride, thickness is 2~5000 nanometer.

7. The radiation-hardened SOI MOSFET device structure based on ion implantation defined gate width of claim 1, wherein, The source-drain region (8) is formed by ion implantation or diffusion of impurity ions, and the doping type is P type or N type, the doping element is phosphorus, boron, indium or arsenic or other three-five elements, and the doping concentration is 0-1E20 / cm -3 .

8. A method of fabricating a radiation-hardened SOI MOSFET device structure based on ion implantation-defined gate width according to any one of claims 1-7, characterized in that, Comprise the following steps: Providing SOI substrate, SOI substrate comprises top layer silicon, buried oxygen layer and support layer; Forming channel region, gate width definition area by ion implantation or diffusion in top layer silicon; Forming insulating dielectric layer on the external surface of the top layer silicon by deposition or oxidation; Deposition of gate material on the insulating dielectric layer, and anisotropic etching, forming gate; Preparation of source and drain by self-aligned metal silicide formation or epitaxial process on the top layer silicon, complete structure preparation.

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