Trench gate electrode self-alignment forming method

Abstract

The invention discloses a trench gate electrode self-alignment forming method. The method comprises the following steps: forming a trench on a drift region of a semiconductor epitaxial layer; a gate medium and a gate electrode are sequentially formed on the drift region of the semiconductor epitaxial layer and on the side wall and the upper portion of the groove, and the gate electrode forms a small groove in the middle of the groove; growing a first mask material on the gate electrode and etching the first mask material, wherein a first mask is left at a small groove in the middle of the groove; etching the gate electrode by using a first mask, and forming a local step at the edge of the first mask remained at the small groove; and growing a second mask material on the gate electrode on the groove, etching, forming a second mask side wall at the local step, further etching the gate electrode by using the first mask and the second mask side wall formed twice, and removing the gate electrode on the table board outside the groove. According to the invention, through the growth and etching of the first mask and the second mask side wall and the utilization of the self-alignment advantage of the side wall technology, the effective protection of the gate electrode in the groove and the full etching of the gate electrode at the mesa are realized.

Description

Technical Field

[0001] This invention relates to the field of MOSFET chip technology, and more particularly to a method for forming a trench gate electrode with self-alignment. Background Technology

[0002] Trench gate power MOSFETs are widely used in modern power electronic systems due to their advantages such as high channel density, low on-resistance, and good switching performance. In the traditional manufacturing process of trench gate MOSFETs, the formation of the gate electrode typically includes the following steps: etching a trench on a substrate, growing a gate oxide layer in the trench and depositing a polysilicon gate electrode to fill the trench, and then defining the gate electrode pattern on the surface area through a gate electrode etching process.

[0003] However, the etching process presents significant technical challenges: when etching the polysilicon in the mesa region, limitations in the etching process can easily lead to two types of defects. First, if over-etching is performed, it can easily result in excessive etching, which will partially remove the polysilicon of the gate electrode within the trench, leading to gate thickness loss, increased gate resistance, and even damage to the gate oxide layer, severely affecting the uniformity of the device's threshold voltage and long-term reliability. Second, if etching is insufficient, excess polysilicon will remain in the mesa region, causing an electrical short circuit between the gate and source, resulting in gate-source leakage or breakdown, significantly reducing device yield. Although an additional photolithography step can be added before etching to cover and protect the trench and part of the mesa region, achieving good etching of other areas of the mesa, the limitations of photolithography overlay precision require a large gate-source spacing to account for process deviations, affecting the reduction of the device's unit cell size. Summary of the Invention

[0004] Technical Objective: To address the defects of over-etching or under-etching that easily occur in the gate electrode etching process of trench gate power devices in the prior art, this invention provides a self-aligned trench gate electrode formation method. By growing and etching the sidewalls of the first and second masks, and utilizing the self-alignment advantage of the sidewall process, effective protection of the gate electrode in the trench, especially near the trench sidewall channel, and sufficient etching of the gate electrode at the mesa can be achieved.

[0005] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution.

[0006] A method for forming a self-aligned trench gate electrode includes the following steps: S1. A trench is formed in the drift region of the semiconductor epitaxial layer; S2. A gate dielectric and a gate electrode are sequentially formed on the drift region of the semiconductor epitaxial layer, on the trench sidewall and above, wherein the gate electrode forms a small groove in the middle of the trench. S3. A first mask material is grown and etched on the gate electrode, and the first mask remains in the small groove in the middle of the trench. S4. Using the first mask remaining in the small groove as a mask, etch the gate electrode so that the gate electrode forms a local step at the edge of the first mask; S5. Grow and etch a second mask material to form a second mask sidewall at the local step. S6. The gate electrode is further etched using the first and second mask sidewalls formed twice to remove the gate electrode on the mesa outside the trench.

[0007] Preferably, the growth thickness L1 of the gate electrode ranges from 0.5W to 0.6W, where W is the width of the trench.

[0008] Preferably, the thickness L2 of the first mask material is 0.4W~0.8W, where W is the width of the trench.

[0009] Preferably, the etch depth E1 of the first mask material ranges from L2 to 1.2L2, where L2 is the thickness of the first mask material.

[0010] Preferably, the etching depth E2 of the gate electrode ranges from 0.5L1 to 0.9L1, where L1 is the gate electrode growth thickness.

[0011] Preferably, the thickness L3 of the second mask sidewall ranges from 0.3W to 0.6W, where W is the width of the trench.

[0012] Preferably, the etch depth E3 of the second mask material ranges from L3 to 1.2L3, where L3 is the thickness of the second mask sidewall.

[0013] Preferably, the etching depth E4 in S6 ranges from 0.2L1 to 0.5L1, where L1 is the gate electrode growth thickness.

[0014] Preferably, the etching selectivity ratio of the first mask and the gate electrode in S3 is greater than 20:1, and the etching selectivity ratio of the second mask sidewall and the gate electrode in S5 is greater than 20:1.

[0015] Preferably, in S6, the etching selectivity ratio of the gate electrode and the sidewall of the first mask or the second mask is greater than 50:1.

[0016] Beneficial effects: This invention, through the growth and etching of the sidewalls of the first and second masks, leverages the self-alignment advantage of sidewall processes to effectively protect the gate electrodes within the trenches, especially near the trench sidewall channels, and to fully etch the gate electrodes at the mesa, avoiding the impact of photolithography precision and thus meeting the requirements of unit cell shrinkage. Furthermore, this invention eliminates the need for additional photolithography to etch the trench gate electrodes, simplifying the process and making it suitable for mass production applications on large-scale production lines. Attached Figure Description

[0017] Figure 1This is a flowchart of a trench gate electrode self-alignment formation method according to an embodiment of the present invention; Figure 2 This is a process diagram of a trench gate electrode self-alignment formation method according to an embodiment of the present invention; Among them, 100 is the drift region of the semiconductor epitaxial layer; 101 is the trench; 200 is the gate dielectric; 300 is the gate electrode; 301 is the local step; 401 is the first mask; and 501 is the sidewall of the second mask. Detailed Implementation

[0018] The following description, in conjunction with the accompanying drawings and embodiments, further explains and illustrates a trench gate electrode self-alignment formation method of the present invention.

[0019] The embodiments are for illustrative purposes only and do not constitute a limitation on the scope of the claims. Other alternative means that can be conceived by those skilled in the art are all within the scope of the claims of this invention.

[0020] Furthermore, in the description of this invention, it should be noted that the terms "central," "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] Example: As attached Figure 1 and attached Figure 2 As shown, a trench gate electrode self-alignment formation method of the present invention includes the following steps: S1. A trench 101 is formed on the drift region 100 of the semiconductor epitaxial layer; In this embodiment, as shown in the appendix Figure 2 As shown in Figure A, a trench 101 is formed on the drift region 100 of the semiconductor epitaxial layer by photolithography and etching; the semiconductor material is SiC; the width W of the trench 101 is 0.8μm and the depth D of the trench 101 is 1.2μm; in some other embodiments, the semiconductor material can be Si.

[0022] S2. A gate dielectric 200 and a gate electrode 300 are sequentially formed on the drift region 100 of the semiconductor epitaxial layer, on the sidewall of the trench 101 and above it. The gate electrode 300 forms a small groove in the middle of the trench. The growth thickness L1 of the gate electrode 300 is in the range of 0.5W~0.6W, where W is the width of the trench 101. In this embodiment, as shown in the appendix Figure 2As shown in Figure B, the gate dielectric is silicon oxide with a thickness of 50 nm, and the gate electrode is doped polysilicon with a growth thickness L1 of 420 nm. Both growth methods are conformal LPCVD growth, meaning that the mesa outside the trench, the bottom surface inside the trench, and the sidewalls of the trench all have the same growth thickness during the growth process. At this point, the trench is completely filled by the polysilicon gate electrode, and a small recess is formed in the middle of the trench.

[0023] S3. A first mask material is grown and etched on the gate electrode 300, and the first mask 401 remains in the small groove in the middle of the trench. In this embodiment, as shown in the appendix Figure 2 As shown in Figure C, the thickness L2 of the first mask material is 0.4W~0.8W, where W is the width of the trench 101. After the first mask material is grown, a large-area etch-back is performed, with an etch-back depth E1 ranging from L2 to 1.2L2. The first mask 401 remains in the small recess in the middle of the trench. In this example, the first mask material is silicon oxide, with a growth thickness L2 of 400nm. The etching depth E1 of the first mask is 450nm. At this point, the first mask on the flat area is completely etched, leaving only the first mask in the small recess in the middle of the trench, with a width of approximately 250nm.

[0024] S4. Using the first mask 401 remaining in the small groove as a mask, the gate electrode is etched so that the gate electrode forms a local step 301 at the edge of the first mask 401. In this embodiment, as shown in the appendix Figure 2 As shown in Figure D, the etching depth E2 of the gate electrode ranges from 0.5L1 to 0.9L1, where L1 is the gate electrode growth thickness; in this example, the etching depth E2 is 350 nm. At this time, the remaining gate electrode thickness in the mesa region is about 70 nm. Meanwhile, due to the first mask remaining at the small trench, a local step 301 is formed at the edge of the polysilicon electrode on the first mask 401. The step height is close to the etching depth E2, about 350 nm.

[0025] S5. Grow and etch a second mask material to form a second mask sidewall 501 at the local step 301; In this embodiment, as shown in the appendix Figure 2 As shown in Figure E, the thickness L3 of the second mask sidewall 501 ranges from 0.3W to 0.6W, where W is the width of the trench 101. After the second mask material is grown, a large-area etch-back is performed, with an etch-back depth E3 ranging from L3 to 1.2L3. The second mask material is silicon oxide, and in this example, the growth thickness L3 is 400 nm, and the etch-back depth E3 is 420 nm. The width of the second mask sidewall 501 formed at this time is approximately 400 nm. Simultaneously, the first mask 401 at the original small trench will be appropriately over-etched due to the etching in this step.

[0026] S6. The gate electrode is further etched using the first mask 401 and the second mask sidewall 501 formed twice to remove the gate electrode on the mesa outside the trench.

[0027] In this embodiment, as shown in the appendix Figure 2 As shown in Figure F, the etching depth E4 in S6 ranges from 0.2L1 to 0.5L1, where L1 is the gate electrode growth thickness; this corresponds to an etching amount >200% of the residual gate electrode thickness at the mesa. In this example, the etching depth E4 is 350nm, ensuring complete etching of the gate electrode at the mesa. At this point, the width of the gate electrode outside the trench is only about 70nm.

[0028] After S6, a micro-oxidation treatment at 800℃~1000℃ is performed, such as 10 minutes of oxygen oxidation at 900℃, to remove any possible slight residues or polysilicon burrs caused by etching, in order to facilitate the subsequent fabrication of the gate-source isolation dielectric.

[0029] In S3, the etching selectivity ratio between the first mask and the gate electrode is greater than 20:1. In S5, the etching selectivity ratio between the second mask sidewall and the gate electrode is greater than 20:1. In S6, the etching selectivity ratio between the gate electrode and either the first mask or the second mask sidewall is greater than 50:1.

[0030] This invention utilizes the self-alignment advantage of the sidewall process to grow and etch the first and second mask sidewalls, thereby achieving effective protection of the gate electrode in the trench, especially near the trench sidewall channel, and sufficient etching of the gate electrode at the mesa, avoiding the influence of photolithography precision and thus meeting the requirements of cell shrinkage.

[0031] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming a self-aligned trench gate electrode, characterized in that, Includes the following steps: S1. A trench (101) is formed on the drift region (100) of the semiconductor epitaxial layer. S2. On the drift region (100) of the semiconductor epitaxial layer, on the sidewall of the trench (101) and above, a gate dielectric (200) and a gate electrode (300) are formed sequentially, wherein the gate electrode (300) forms a small groove in the middle of the trench. S3. A first mask material is grown and etched on the gate electrode (300), and the first mask (401) remains in the small groove in the middle of the trench. S4. Using the first mask (401) remaining in the small groove as a mask, the gate electrode is etched so that the gate electrode forms a local step (301) at the edge of the first mask (401). S5. Grow and etch a second mask material to form a second mask sidewall (501) at a local step (301). S6. The gate electrode is further etched using the first mask (401) and the second mask sidewall (501) formed twice to remove the gate electrode on the mesa outside the trench.

2. The method for forming a self-aligned trench gate electrode according to claim 1, characterized in that: The growth thickness L1 of the gate electrode (300) ranges from 0.5W to 0.6W, where W is the width of the trench (101).

3. The method for forming a self-aligned trench gate electrode according to claim 1, characterized in that: The thickness L2 of the first mask material is 0.4W~0.8W, where W is the width of the trench (101).

4. The method for forming a self-aligned trench gate electrode according to claim 1, characterized in that: The etching depth E1 of the first mask material ranges from L2 to 1.2L2, where L2 is the thickness of the first mask material.

5. The method for forming a self-aligned trench gate electrode according to claim 1, characterized in that: The etching depth E2 of the gate electrode ranges from 0.5L1 to 0.9L1, where L1 is the gate electrode growth thickness.

6. The method for forming a self-aligned trench gate electrode according to claim 1, characterized in that: The thickness L3 of the second mask sidewall (501) ranges from 0.3W to 0.6W, where W is the width of the trench (101).

7. The method for forming a self-aligned trench gate electrode according to claim 1, characterized in that: The etch depth E3 of the second mask material ranges from L3 to 1.2L3, where L3 is the thickness of the second mask sidewall (501).

8. The method for forming a self-aligned trench gate electrode according to claim 1, characterized in that: In S6, the etching depth E4 ranges from 0.2L1 to 0.5L1, where L1 is the gate electrode growth thickness.

9. The method for forming a self-aligned trench gate electrode according to claim 1, characterized in that: In S3, the etching selectivity ratio of the first mask and the gate electrode is greater than 20:1, and in S5, the etching selectivity ratio of the second mask sidewall and the gate electrode is greater than 20:

1.

10. The method for forming a self-aligned trench gate electrode according to claim 1, characterized in that: In S6, the etching selectivity ratio between the gate electrode and the sidewall of the first or second mask is greater than 50:1.

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